Semiconductor device, manufacturing method therefor and electronic device

Abstract

The present application relates to the technical field of semiconductors. Provided are a semiconductor device, a manufacturing method therefor and an electronic device, which are used for reducing contact resistances of semiconductor devices and increasing drive currents of semiconductor devices. The semiconductor device comprises a first electrode, a first inducing layer located on the first electrode, a channel layer located on the side of the first inducing layer away from the first electrode, a gate arranged at the periphery of the channel layer, and a second electrode connected to the channel layer. The first electrode and the second electrode are located on two opposite sides of the channel layer; the channel layer comprises a first portion, a second portion and a third portion, the first portion being located on the surface of the first inducing layer away from the first electrode, the second portion being located on the side of the first portion away from the first inducing layer, the third portion being located on the side of the second portion away from the first portion, and the third portion enclosing to form a ring shape; the thickness of the first portion is greater than the thickness of the third portion.

Description

Semiconductor devices and their fabrication methods, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510489741.9, filed on April 17, 2025, entitled "Semiconductor Device and Preparation Method Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and an electronic device. Background Technology

[0003] With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices such as dynamic random access memory (DRAM) are gradually shrinking. In order to meet the continuous miniaturization of the above semiconductor devices, saddle bulky fin transistors and buried channel array transistors are widely used in DRAM.

[0004] However, due to limitations in transistor structural design and process integration, DRAM size miniaturization has reached its limit. Summary of the Invention

[0005] This application provides a semiconductor device and its fabrication method, as well as an electronic device, for reducing the contact resistance of the semiconductor device and increasing the driving current of the semiconductor device.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] A first aspect of this application provides a semiconductor device including a first electrode, a first inducing layer on the first electrode, a channel layer located on the side of the first inducing layer away from the first electrode, a gate disposed on the periphery of the channel layer, and a second electrode connected to the channel layer. The first electrode and the second electrode are located on opposite sides of the channel layer. The channel layer includes a first portion, a second portion, and a third portion. The first portion is located on the surface of the first inducing layer away from the first electrode, the second portion is located on the side of the first portion away from the first inducing layer, and the third portion is located on the side of the second portion away from the first portion, forming a ring. The sum of the thickness of the first portion and the thickness of the second portion is greater than the thickness of the third portion.

[0008] The semiconductor device provided in this application embodiment has a first part and a second part of the channel layer stacked sequentially on a first inducing layer. The sum of the thickness of the first part and the thickness of the second part of the channel layer is greater than the thickness of the third part. This can increase the carrier concentration of the channel layer, thereby reducing the parasitic resistance of the semiconductor device. At the same time, it can also reduce the contact resistance between the channel layer and the first inducing layer, thereby increasing the driving current of the semiconductor device.

[0009] In one possible implementation, the first portion is located between the surface of the gate near the first electrode and the surface of the first inducing layer near the first electrode. In this way, the thickness of the first portion is greater than the thickness of the third portion, and the carrier concentration of the first portion is greater than the carrier concentration of the third portion.

[0010] In one possible implementation, the material of the first portion has the same crystalline structure as the material of the first inducing layer. This increases the carrier concentration of the first portion.

[0011] In one possible implementation, the channel layer material includes metallic elements; the metallic element content in the first part of the material is greater than that in the third part. This results in a higher carrier concentration in the first part compared to the third part.

[0012] In one possible implementation, the metal element content in the first part of the material is greater than or equal to 30%. This increases the carrier concentration in the first part of the channel layer, thereby reducing the parasitic resistance of the semiconductor device and increasing the drive current of the semiconductor device.

[0013] In one possible implementation, the metallic element includes at least one of zinc and indium. This facilitates a crystalline structure in which the material of the first portion of the channel layer has the same orientation as the material of the first inducing layer.

[0014] In one possible implementation, the materials of the first inducing layer and the channel layer contain at least some of the same metallic elements. This facilitates the formation of a crystalline structure with the same orientation in the first portion of the channel layer as the material of the first inducing layer.

[0015] In one possible implementation, the material of the first inducing layer includes one or more of indium tin oxide, indium gallium oxide, indium oxide, indium gallium zinc oxide, indium gallium zinc oxide, and indium zinc oxide. This facilitates having the same oriented crystal structure as the material of the first portion of the channel layer.

[0016] In one possible implementation, the channel layer material includes one or more of indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium tin gallium zinc oxide, and indium magnesium zinc oxide. This facilitates having the same oriented crystal structure as the material of the first portion of the channel layer and the material of the first inducing layer.

[0017] In one possible implementation, the first electrode has a recess, and the first induction layer is located within the recess of the first electrode. This provides an embodiment of the semiconductor device that further reduces the parasitic resistance of the semiconductor device, further reduces the contact resistance between the channel layer and the first induction layer, and increases the drive current of the semiconductor device.

[0018] In one possible implementation, the semiconductor device further includes a second inducing layer located on the side of the second electrode near the channel layer, and the second inducing layer is in contact with the channel layer. This reduces the contact resistance between the channel layer and the second inducing layer, thereby increasing the drive current of the semiconductor device.

[0019] In one possible implementation, the second electrode is located within the third portion; the semiconductor device further includes a second inducing layer located between the channel layer and the second electrode. This provides an embodiment of the semiconductor device that can further reduce the contact resistance between the channel layer and the second inducing layer, thereby increasing the drive current of the semiconductor device.

[0020] In one possible implementation, the semiconductor device further includes a dielectric layer; the dielectric layer is disposed around a third portion of the channel layer and between the channel layer and the gate. In this way, the dielectric layer can serve as a gate sidewall of the semiconductor device.

[0021] In one possible implementation, the surface of the first portion furthest from the first electrode is higher than the surface of the dielectric layer closest to the first electrode. This ensures that the thickness of the first portion is greater than the thickness of the third portion, increasing the carrier concentration of the channel layer, reducing the parasitic resistance of the semiconductor device, reducing the contact resistance between the channel layer and the first electrode, and increasing the drive current of the semiconductor device.

[0022] In one possible implementation, the dielectric layer extends to the surface of the second portion near the first electrode along a direction parallel to the plane of the first electrode, and the dielectric layer extends to the side of the first portion. In this way, the dielectric layer extends into the channel layer along a direction parallel to the plane of the first electrode, and the first, second, and third portions of the channel layer can be divided based on the portion of the dielectric layer extending into the channel layer.

[0023] In one possible implementation, the area of ​​the first portion is smaller than the area of ​​the second portion along a direction parallel to the plane containing the first electrode. In this way, the dielectric layer is located on the surface of the second portion near the first electrode, and also on the side of the first portion.

[0024] In one possible implementation, the semiconductor device may include a dual-gate vertical transistor, a single-gate vertical transistor, or a ring-gate vertical transistor. In this way, the semiconductor device provided in this application embodiment can be applied to vertical transistors, thereby increasing the drive current of the vertical transistor.

[0025] In one possible implementation, the first portion of the channel layer further extends into the first induced layer. That is, the first induced layer also covers at least a portion of the sidewalls of the channel layer. This allows for a further increase in the carrier concentration of the channel layer.

[0026] A second aspect of this application provides a semiconductor device, comprising: a first electrode, a first inducing layer on the first electrode, a channel layer on the side of the first inducing layer away from the first electrode, a gate electrode disposed on the periphery of the channel layer, and a second electrode connected to the channel layer. The first electrode and the second electrode are located on opposite sides of the channel layer. The content of metal elements in the material of the channel layer decreases along the direction from the first electrode to the second electrode.

[0027] The semiconductor device provided in this application embodiment has a greater carrier concentration on the side of the channel layer closer to the first electrode than on the side farther from the first electrode. This can reduce the parasitic resistance of the semiconductor device and also reduce the contact resistance between the channel layer and the first induction layer, thereby increasing the driving current of the semiconductor device.

[0028] In one possible implementation, the channel layer includes a first portion and a third portion; the first portion is located between the surface of the gate near the first electrode and the first inductive layer, and the third portion is located between the surface of the gate near the first electrode and the second electrode; the metal element content in the material of the first portion is greater than the metal element content in the material of the third portion. Thus, the carrier concentration in the first portion is greater than the carrier concentration in the third portion.

[0029] A third aspect of this application provides a method for fabricating a semiconductor device, comprising: providing a first electrode and a first inducing layer, the first inducing layer being located on the first electrode; forming a first isolation film, a gate film, and a second isolation film on the side of the first inducing layer away from the first electrode; the gate film being located between the first isolation film and the second isolation film, and the second isolation film being located on the side of the first isolation film away from the first inducing layer; forming a groove to form the second isolation layer, the gate film, and the first isolation layer; the groove penetrating the second isolation film, the gate film, and the first isolation film; forming a channel layer in the groove; the channel layer being formed on the sidewall of the groove and the surface of the first inducing layer; the thickness of a portion of the channel layer formed on the surface of the first inducing layer being greater than the thickness of a portion of the channel layer formed on the sidewall of the groove; and forming a second electrode, the second electrode being located on the side of the channel layer away from the first electrode.

[0030] The semiconductor device fabrication method provided in this application embodiment involves forming a channel layer on a first inducing layer. Under the influence of the first inducing layer, the deposition rate of a portion of the channel layer deposited on the surface of the first inducing layer is increased, causing a difference in thickness between the portion of the channel layer in contact with the first inducing layer and the other portion. Consequently, the portion of the channel layer in contact with the first inducing layer is thicker, resulting in a higher content of metal elements in the material of this portion, thus increasing the carrier concentration of the channel layer. Furthermore, due to the influence of the first inducing layer, the channel layer can form a crystalline structure with the same orientation as the material of the first inducing layer, thereby reducing the parasitic resistance of the semiconductor device. Simultaneously, it also reduces the contact resistance between the channel layer and the first inducing layer, increasing the drive current of the semiconductor device. Moreover, the channel layer in the semiconductor device provided in this application embodiment is formed through a deposition process, eliminating the need for etching-back processes and avoiding process defects caused by etching-back processes.

[0031] In one possible implementation, after creating the trench and before forming the channel layer, the method further includes: forming a dielectric film within the trench, the dielectric film being located on the sidewalls and bottom of the trench; removing a portion of the dielectric film located at the bottom of the trench to expose a first induction layer, thereby forming the dielectric layer. In this way, the dielectric layer, located between the gate and the channel layer, can serve as the gate sidewall of the semiconductor device.

[0032] In one possible implementation, after forming the channel layer and before forming the second electrode, the fabrication method further includes: forming a second inducing layer on the side of the channel layer away from the first electrode; and forming the second electrode, which includes forming the second electrode on the side of the second inducing layer away from the first electrode. This reduces the contact resistance between the channel layer and the second inducing layer, thereby increasing the drive current of the semiconductor device.

[0033] In one possible implementation, forming the channel layer includes: the channel layer comprising a first portion, a second portion, and a third portion; the first portion is formed on the surface of the first inducing layer away from the first electrode, the second portion is formed on the side of the first portion away from the first inducing layer, and the third portion is formed on the side of the second portion away from the first portion, with the third portion forming a ring; after forming the channel layer and before forming the second electrode, the fabrication method further includes: forming an insulating layer within the third portion, the surface of the insulating layer away from the first electrode being lower than the surface of the second insulating layer away from the first electrode; forming a second inducing layer on the side of the insulating layer away from the first electrode; the second inducing layer also covering the sidewalls of the trench; and forming the second electrode on the side of the second inducing layer away from the first electrode. This provides an embodiment of a semiconductor device that can reduce the contact resistance between the channel layer and the second inducing layer, thereby increasing the drive current of the semiconductor device.

[0034] A fourth aspect of the embodiments of this application provides an electronic device, including a semiconductor device and a printed circuit board according to either the first aspect or the second aspect, wherein the semiconductor device and the printed circuit board are electrically connected.

[0035] The electronic device provided in the fourth aspect of the embodiments of this application includes the semiconductor device of either the first aspect or the second aspect, and its beneficial effects are the same as those of the semiconductor device, which will not be repeated here. Attached Figure Description

[0036] Figure 1 is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0037] Figure 2 is a schematic diagram of a vertical field-effect transistor according to an embodiment of this application;

[0038] Figure 3A is a schematic diagram of the structure of a semiconductor device according to an embodiment of this application;

[0039] Figure 3B is a schematic diagram of another semiconductor device according to an embodiment of this application;

[0040] Figure 3C is a schematic diagram illustrating the structure of another semiconductor device according to an embodiment of this application;

[0041] Figure 4 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0042] Figure 5 is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0043] Figures 6A-6M are schematic diagrams illustrating a method for fabricating a semiconductor device according to an embodiment of this application;

[0044] Figure 7 is a schematic flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application;

[0045] Figures 8A-8G are schematic diagrams illustrating another method for fabricating a semiconductor device according to an embodiment of this application;

[0046] Figure 9 is a schematic flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application;

[0047] Figures 10A-10E are schematic diagrams illustrating the process of fabricating another semiconductor device according to an embodiment of this application;

[0048] Figure 11 is a schematic diagram of another semiconductor device provided in an embodiment of this application;

[0049] Figure 12A is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0050] Figure 12B is a cross-sectional view of Figure 12A along the A1A2 direction;

[0051] Figure 13A is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0052] Figure 13B is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0053] Figure 14 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0054] Figure 15 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0055] Figure 16A is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0056] Figure 16B is a cross-sectional view of Figure 16A along the B1B2 direction;

[0057] Figure 17 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application.

[0058] Reference numerals in the attached figures: 1-Electronic device; 2-Display module; 3-Middle frame; 4-Housing; 5-Cover plate; 10-Semiconductor device; 100-Substrate; 110-First electrode; 111-Recess; 120-Second electrode; 130-Gate; 130'-Gate film; 210-First induction layer; 220-Second induction layer; 310-Channel layer; 310'-Channel film; 311-First portion; 312-Second portion; 313-Third portion; 302-Receiving cavity; 320-Dielectric layer; 320'-Dielectric film; 330-Insulating layer; 301'-Sacrificial film; 301-Sacrificial layer; 410'-First isolation film; 410-First isolation layer; 420'-Second isolation film; 420-Second isolation layer; 510-Groove. Detailed Implementation

[0059] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0060] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "second," "first," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0061] Furthermore, in the embodiments of this application, directional terms such as "upper," "lower," "left," and "right" may be defined relative to the orientation in which the components are schematically placed in the accompanying drawings. It should be understood that these directional terms can be relative concepts, used for relative description and clarification, and can change accordingly based on the orientation of the components in the accompanying drawings.

[0062] In the embodiments of this application, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. Furthermore, the term "coupled connection" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be direct contact or indirect contact through an intermediate medium.

[0063] In this embodiment of the application, "and / or" describes the relationship between associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following associated objects have an "or" relationship.

[0064] This application provides an electronic device. This electronic device can be, for example, a consumer electronics product, a home electronics product, an in-vehicle electronics product, or a financial terminal product. Consumer electronics products include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronics products include smart door locks, televisions, remote controls, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. In-vehicle electronics products include in-vehicle navigation systems, in-vehicle DVDs, etc. Financial terminal products include ATMs, self-service terminals, etc. This application does not impose special limitations on the specific form of the above-mentioned electronic device. For ease of explanation, the following embodiments all use mobile phones as an example for illustration.

[0065] An example of the structure of an electronic device is shown in Figure 1. The electronic device 1 mainly includes a display module 2, a middle frame 3, a housing (or battery cover, back cover) 4, and a cover plate 5.

[0066] The display module 2 has a light-emitting side that allows the display image to be seen and a non-light-emitting side that is opposite to the light-emitting side. The back of the display module 2 is close to the middle frame 3, and the cover plate 5 is disposed on the light-emitting side of the display module 2.

[0067] The cover plate 5 is located on the side of the display module 2 away from the middle frame 3. The cover plate 5 can be, for example, a cover glass (CG), which can have a certain degree of toughness.

[0068] The middle frame 3 is located between the display module 2 and the housing 4. The surface of the middle frame 3 away from the display module 2 is used to mount internal components such as batteries, printed circuit boards (PCBs), cameras, and antennas. After the housing 4 is closed with the middle frame 3, the aforementioned internal components are located between the housing 4 and the middle frame 3.

[0069] The aforementioned display module 2 includes a display panel (DP).

[0070] The aforementioned electronic device 1 may further include an integrated circuit disposed on a printed circuit board. The printed circuit board is used to carry the integrated circuit and is electrically connected to the integrated circuit to enable signal communication.

[0071] An integrated circuit may include circuit modules for implementing a single function, or it may include multiple circuit modules for implementing different functions. A circuit module can be a circuit with any function, such as a driver circuit, pixel circuit, amplifier circuit, power management circuit, charging protection circuit, control circuit, and image sensor circuit. This application does not limit this. After packaging, the integrated circuit can be used in electronic devices in chip form. Alternatively, it can be used directly in electronic devices without packaging.

[0072] For example, an integrated circuit may include a circuit module for implementing a single function, or it may include multiple circuit modules for implementing different functions. The circuit module may be a circuit with any function, such as a driver circuit, pixel circuit, amplifier circuit, power management circuit, charging protection circuit, control circuit (e.g., a central processing unit (CPU)), image sensor circuit, and storage device circuit, etc.

[0073] In some embodiments, the integrated circuit described above may include at least one transistor, such as a field-effect transistor (FET).

[0074] It is clarified here that field-effect transistors can include planar transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) or junction field-effect transistors (JFETs), and can also include three-dimensional transistors such as fin field-effect transistors (FinFETs), gate-all-around field-effect transistors (GAAFETs), or forksheet field-effect transistors (forksheet FETs or FSFETs). Field-effect transistors can also include vertical field-effect transistors (VFETs). This application does not limit the scope of these categories. The multiple semiconductor devices included in the integrated circuit can be the same or different; the comparison in this application is not limited, and the appropriate configuration can be made according to actual needs.

[0075] In some embodiments, a storage device (e.g., internal memory) may include random access memory (RAM), read-only memory (ROM), etc. Based on their operating principles, RAM can also include ferroelectric random access memory (FeRAM), dynamic random access memory (DRAM), phase-change random access memory (PCRAM), resistive random access memory (ReRAM), or magnetic random access memory (MRAM). Based on whether the stored information persists after the external power supply is removed, memory can be classified as volatile memory (RAM) and non-volatile memory (NVM). Volatile memory, represented by static random access memory (SRAM) or dynamic random access memory, requires a continuous external power supply for information storage. When no external power is applied, the stored information is lost. Non-volatile memories are represented by traditional read-only memory (ROM), flash memory, ferroelectric memory, magnetic random access memory, resistive random access memory (RRAM), and phase-change memory. These non-volatile memories all achieve the characteristic of not losing information when power is off through their unique physical principles. For ease of illustration, the memory provided in the embodiments of this application is a dynamic random access memory as an example for the following illustrative explanation.

[0076] With the development of semiconductor technology, the technical requirements for DRAM are constantly increasing as DRAM size shrinks. For example, the cell structure of DRAM can be 6F2. Here, F represents the feature size, which is the smallest physical size feature that can be realized on the chip, also known as the critical dimension (CD). 6F2 means that the cell area of ​​the DRAM is six times the feature size F.

[0077] To achieve continuous miniaturization of DRAM, transistors within DRAM can include saddle bulky fin transistors and buried channel array transistors. The material for the buried wordline gate of transistors in DRAM has also evolved from tungsten to a double-function layer comprising polysilicon and tungsten, or a titanium nitride layer. For example, the gate material of transistors in low-power double-data-rate synchronous dynamic random access memory (LP-DDR SDRAM) includes a high-dielectric-constant material; that is, a high-k metal gate (HKMG) is used in LP-DDR SDRAM.

[0078] For example, DRAM fabrication includes transistors such as saddle-fin transistors and buried-channel array transistors, capacitors such as cylindrical or quasi-cylindrical capacitors and capacitors on bit lines (COB), and process integration such as bit line air gaps (BL air gaps). However, based on the above device structure and process integration, the 6F2 DRAM cell structure will reach the miniaturization limit at the 10nm node.

[0079] To continue the development of DRAM technology and achieve continuous miniaturization of DRAM size, a 4F2 DRAM cell structure can be used to replace the 6F2 DRAM cell structure. In the 4F2 DRAM cell structure, the saddle-fin transistors in the 6F2 DRAM cell structure are replaced with vertical field-effect transistors (VFETs).

[0080] Figure 2 illustrates a vertical field-effect transistor (VFET). The VFET includes a first electrode, a second electrode, a channel layer connecting the first and second electrodes, and a gate electrode disposed around the channel layer. One of the first and second electrodes is the source, and the other is the drain.

[0081] As shown in Figure 2, an isolation layer is provided between the first electrode and the gate, and between the gate and the second electrode.

[0082] For example, the channel material of a vertical field-effect transistor (VFET) can include an oxide semiconductor (OS) material. That is, the channel layer material includes an oxide semiconductor material. Oxide semiconductors are N-type channel materials with good uniformity, low fabrication temperature, high mobility, and no doping required. Since back-end processes in silicon-based complementary metal-oxide-semiconductor (CMOS) require low thermal loads, the ability of oxide semiconductors to be fabricated below 400°C makes them compatible with CMOS back-end processes. Therefore, OS VFETs can be integrated into the CMOS back-end process to achieve a high-density 4F2 DRAM cell structure. Furthermore, OS VFETs can be placed on the silicon-based CMOS peripheral circuitry, further saving DRAM chip area.

[0083] Furthermore, due to its extremely low off-state current characteristics, OS VFET can replace silicon transistors to improve hold time. For example, OS VFET-based DRAM can achieve hold time several orders of magnitude longer compared to the 6F2 DRAM cell structure. Additionally, the low thermal budget of OS VFETs allows for lower-cost application in silicon-based CMOS, enabling the implementation of 3D DRAM in the back-end processes of silicon-based CMOS.

[0084] For example, an OS VFET-based DRAM chip can achieve a feature size of 26nm and a typical electrical performance of 15μA / cell. However, optimizing the electrical performance of OS VFETs is quite challenging. Firstly, during the design and manufacturing of OS VFETs, it is impossible to simultaneously optimize both the electrical performance of the OS VFET and the stability of subsequent processes; a balance must be found to meet the overall performance requirements of the device. Secondly, the thickness of the isolation layer determines the leakage current and drive current of the OS VFET. Thirdly, the contact between the channel layer and the first electrode or the second electrode—that is, the contact electrode—determines the symmetry characteristics of the OS VFET, and the contact resistance and barrier modulation between the channel layer and the contact electrode affect the transistor's drive current.

[0085] Based on this, given the structural characteristics of OS VFETs, in order to further improve the device's drive current, improvements can be made in three aspects: the composition of the channel layer material, the thickness of the isolation layer, and the contact barrier, in order to achieve an increase in the device's drive current.

[0086] However, on the one hand, the thickness of the isolation layer is limited by the leakage current requirements of OS VFETs in DRAM, necessitating a certain thickness. Reducing the isolation layer thickness has a physical limit, making it difficult to further reduce the gate-controlled channel resistance. On the other hand, increasing the carrier concentration in the channel layer can lead to the device's off-state current and threshold voltage failing to meet practical application requirements, impacting device reliability and thermal stability. Furthermore, the channel layer and isolation layer can be partitioned by doping to alter the channel layer material composition. However, due to the positional relationship between the channel and isolation layers, partitioning doping is difficult and challenging to implement.

[0087] Based on this, to improve the drive current of the device, a semiconductor device is illustrated in Figure 3A. This semiconductor device can be a vertical field-effect transistor. The semiconductor device includes a channel layer and a bottom electrode layer, an isolation layer, a gate layer, and a top electrode layer stacked together. The channel layer penetrates the isolation layer and the gate layer, and is in contact with the bottom electrode layer and the top electrode layer.

[0088] However, the relatively thick isolation layer of the aforementioned semiconductor devices results in a large parasitic resistance, affecting the drive current capability of the semiconductor devices. A significant Schottky barrier forms at the contact between the bottom electrode layer and the channel layer, leading to a decrease in electrical performance. Furthermore, etching damage to the bottom electrode layer after etching easily forms an oxide layer upon contact with the channel layer, resulting in poor conductivity and impacting device performance. Simultaneously, a significant Schottky barrier also forms at the contact between the top electrode layer and the channel layer, and subsequent oxide layer formation during processing causes contact damage, affecting device performance.

[0089] Based on this, the embodiments of this application also illustrate a semiconductor device, as shown in FIG3B. This semiconductor device can be a sidewall single-gate structure or a sidewall dual-gate structure. The semiconductor device includes a top electrode layer, a bottom electrode layer, a channel layer located between the top electrode layer and the bottom electrode layer, and a gate located on the side of the channel layer. As shown in FIG3B, buffer layers are further disposed between the top electrode layer and the channel layer, and between the bottom electrode layer and the channel layer.

[0090] For example, the buffer layer may be made of a metallic material or indium tin oxide (ITO). Alternatively, for example, the buffer layer may be made of the same material as the channel layer. This prevents the formation of Schottky barriers between the top electrode layer and the channel layer, and between the bottom electrode layer and the channel layer.

[0091] However, a relatively thick isolation layer (not shown in Figure 3B) still exists in the aforementioned semiconductor devices. This isolation layer is located between the top electrode layer and the gate, and between the bottom electrode layer and the gate, resulting in a high resistance in the channel layer and a decrease in the device's turn-on current. Furthermore, since the buffer layer is mainly made of oxide, although the conductivity of oxides can reduce or eliminate the Schottky barrier at the contact, a relatively large contact resistance still exists in the semiconductor device.

[0092] Based on this, this application also illustrates a semiconductor device, as shown in FIG3C, which can be a GAAFET. The semiconductor device includes a top electrode layer, a bottom electrode layer, a channel layer located between the top and bottom electrode layers, and a gate located on the side of the channel layer. The semiconductor device also includes a buffer layer surrounding the channel layer. The oxygen dissociation of the buffer layer material is greater than that of the channel layer material.

[0093] However, the aforementioned semiconductor devices still contain relatively thick isolation layers (not shown in Figure 3C). These isolation layers are located between the top electrode layer and the gate, as well as between the bottom electrode layer and the gate, resulting in a high resistance in the channel layer and a decrease in the device's turn-on current. Furthermore, due to the poor conductivity of the buffer layer, the contact resistance between the bottom electrode layer and the channel layer, as well as between the top electrode layer and the channel layer, increases, leading to a decrease in device current.

[0094] Based on this, in order to reduce the contact resistance of the semiconductor device and thus increase the driving current of the semiconductor device, this application embodiment also provides a semiconductor device. As shown in FIG4, the semiconductor device 10 includes a first electrode 110 and a first induction layer 210 stacked together, a channel layer 310 located on the side of the first induction layer 210 away from the first electrode 110, a gate 130 disposed on the periphery of the channel layer 310, and a second electrode 120 located on the side of the channel layer 310 away from the first electrode 110 and connected to the channel layer 310. The channel layer 310 includes a first portion 311, a second portion 312, and a third portion 313. The first portion 311 is located on the surface of the first induction layer 210 away from the first electrode 110, the second portion 312 is located on the side of the first portion 211 away from the first induction layer 210, and the third portion 313 is located on the side of the second portion 312 away from the first portion 311, forming a ring shape. The sum of the thickness of the first portion 311 and the thickness of the second portion 312 is greater than the thickness of the third portion 313.

[0095] For ease of illustration, the following description uses a vertical field-effect transistor (VFET) as an example of the semiconductor device provided in this application embodiment. It is clarified here that the semiconductor device provided in this application embodiment can be integrated into the aforementioned integrated circuit or into any of the aforementioned memory devices. This application embodiment does not impose any limitations on this; appropriate configuration can be made according to actual circumstances.

[0096] Based on this, this application also provides a method for fabricating a semiconductor device, as shown in Figure 5, including:

[0097] S11, providing a first pole 110 and a first induction layer 210.

[0098] In some embodiments, as shown in FIG6A, step S11 may include:

[0099] S111, Provide substrate 100.

[0100] Regarding the substrate 100, the material of the substrate 100 is not limited in this embodiment. Exemplarily, the material of the substrate 100 can be a semiconductor. For example, it can be one of bulk silicon, bulk germanium, silicon germanium, silicon carbide, silicon-on-insulator (SOI), or silicon germanium-on-insulator (SiGe-on-insulator, SGOI). The substrate 100 can also be doped (e.g., P-type doped, N-type doped) or undoped.

[0101] The semiconductor material of the substrate 100 may include any one or a combination of silicon, germanium, compound semiconductors, and alloy semiconductors. Compound semiconductors may include, for example, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide. Alloy semiconductors may include, for example, silicon-germanium (SiGe), germanium-tin (GeSn), silicon-germanium-tin (SiGeSn), gallium arsenide-phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), or gallium indium arsenide-phosphide (GaInAsP).

[0102] SOI comprises a semiconductor material layer formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on a substrate 100, which is typically a silicon substrate or a glass substrate. Other substrates can also be used, such as multilayer or gradient substrates.

[0103] Alternatively, for example, substrate 100 is a wafer, such as a silicon wafer.

[0104] It should be noted that the thickness of the substrate 100 is not limited in the embodiments of this application. Depending on actual needs, the substrate 100 may also be removed after fabrication.

[0105] S112. A first electrode 110 is formed on the substrate 100.

[0106] That is, a first electrode 110 is formed on the surface of the substrate 100.

[0107] For example, the material of the first electrode 110 may include a metallic material. For instance, the material of the first electrode 110 may include metallic materials such as titanium nitride (TiN), aluminum nitride (TiAl), gold (Au), nickel (Ni), or tungsten (W). The first electrode 110 may be a single layer or multiple layers.

[0108] S113, A first induction layer 210 is formed on the first pole 110.

[0109] For example, a first induction layer 210 is formed on the side of the first electrode 110 away from the substrate 100.

[0110] That is, the first induction layer 210 is formed on the side of the first electrode 110 away from the substrate 100. For example, the first induction layer 210 is formed on the surface of the first electrode 110 away from the substrate 100.

[0111] For example, the material of the first inducing layer 210 may include a material with a high degree of crystallinity.

[0112] In this way, it can have a crystalline structure with the same orientation as the adjacent material film layer.

[0113] The material of the first inducing layer 210 may include a metallic element. For example, the metallic element may include at least one of zinc (Zn) and indium (In). For example, the material of the first inducing layer 210 may include one or more of indium tin oxide (ITO), indium gallium oxide (IGO), indium oxide (In2O3), indium gallium zinc oxide (CAAC IGZO), indium gallium zinc oxide (spinel IGZO), and indium zinc oxide (IZO).

[0114] In some embodiments, forming the first electrode 110 and the first inducing layer 210 further includes: patterning the first electrode 110 and the first inducing layer 210. For example, the first electrode 110 and the first inducing layer 210 can be patterned by photolithography (not shown in FIG6A) to form a bit line (BL) or storage node (SN) of the semiconductor device to be formed.

[0115] In other embodiments, after forming the first electrode 110, the method further includes:

[0116] As shown in Figure 6B, a recess 111 is formed on the first electrode 110. Then, a first induction layer 210 is formed in the recess 111.

[0117] In this embodiment, the positional relationship between the first electrode 110 and the first induction layer 210 is not limited; it can be set more reasonably according to the actual situation. For ease of illustration, the following description uses the first electrode 110 and the first induction layer 210 shown in Figure 6A.

[0118] S12, forming the gate film.

[0119] In some embodiments, as shown in FIG6C, step S12 includes:

[0120] S121, Form the first isolation membrane 410'.

[0121] For example, a first isolation membrane 410' is formed on the side of the first induction layer 210 away from the first electrode 110. That is, the first isolation membrane 410' is formed on the side of the first induction layer 210 away from the first electrode 110. For example, the first isolation membrane 410' is formed on the surface of the first induction layer 210 away from the first electrode 110.

[0122] The first isolation film 410' serves as the first isolation layer between the subsequently formed gate film and the first electrode 110.

[0123] For example, the material of the first separator 410' may include a low-dielectric-constant (low-K) material. For instance, the material of the first separator 410' may include silicon oxycarbonate (SiOCH), silicon oxynitride (SiON), silicon carbide (SiC), silicon nitride (SiN), silicon oxide (SiO2), undoped silicon glass (USG), phosphor silicate glass (PSG), fluorinated silica glass (FSG), or boron phosphor silicate glass (BPSG), etc. It is clarified here that the material of the first separator 410' may also be other silicon glass (*SG) materials; this application embodiment does not limit this, and appropriate settings can be made according to actual conditions.

[0124] S122, Forming a gate film 130'.

[0125] For example, a gate film 130' is formed on the side of the first isolation film 410' away from the first induction layer 210. That is, the gate film 130' is formed on the side of the first isolation film 410' away from the first induction layer 210. For example, the gate film 130' is formed on the surface of the first isolation film 410' away from the first induction layer 210.

[0126] For example, the material of the gate film 130' may include a metallic material. For instance, the material of the gate film 130' may include metallic materials such as titanium nitride, aluminum nitride, or tungsten. The gate film 130' may be a single layer or multiple layers. It is noted here that in some embodiments, the gate film 130' may also include a pad electrode layer or a work function adjustment layer. For ease of illustration, this embodiment uses the gate film 130' as an example and does not illustrate the multiple metal layers included in the gate film 130'.

[0127] In some embodiments, forming the gate film 130' further includes: patterning the gate film 130' (not shown in FIG6C). For example, the gate film 130' can be patterned by photolithography to form word lines (WL) of the semiconductor device to be formed.

[0128] S123, Form the second isolation membrane 420'.

[0129] For example, a second isolation film 420' is formed on the side of the gate film 130' away from the first isolation film 410'. That is, the second isolation film 420' is formed on the side of the gate film 130' away from the first isolation film 410'. For example, the second isolation film 420' is formed on the surface of the gate film 130' away from the first isolation film 410'.

[0130] The second isolation film 420' serves as a second isolation layer between the gate film 130' and the subsequently formed second electrode.

[0131] For example, the material of the second separator 420' may include a low dielectric constant material. For instance, the material of the second separator 420' may include silicon oxide, silicon oxynitride, silicon carbide, silicon nitride, silicon oxide, undoped silicon oxide glass, phosphosilicate glass, silicon fluoride glass, or borosilicate glass, etc. It is clarified here that the material of the second separator 420' may also be other silicon glass materials; this application embodiment does not limit this, and it can be reasonably set according to the actual situation. The material of the second separator 420' and the material of the first separator 410' may be the same or different; this application embodiment does not limit this.

[0132] In this embodiment, the thickness of the second separator 420' and the thickness of the first separator 410' are not limited. The thickness of the second separator 420' and the thickness of the first separator 410' can be the same or different, and can be reasonably set according to the actual situation.

[0133] S13. As shown in Figure 6D, a groove 510 is formed.

[0134] At this point, the groove 510 penetrates the second isolation film 420', the gate film 130', and the first isolation film 410', forming the first isolation layer 410, the gate 130, and the second isolation layer 420.

[0135] In other words, the groove 510 extends from the surface of the second isolation film 420' away from the first electrode 110, through the second isolation film 420' and the gate film 130', and into the first isolation film 410'.

[0136] For example, the opening size of the groove 510 gradually increases in the direction away from the first pole 110. Alternatively, for example, the opening size of the groove 510 is the same in the direction away from the first pole 110.

[0137] For example, the included angle between the groove wall and the bottom of the groove 510 is 90° to 110°. That is, the included angle between the groove wall and the bottom of the groove 510 can be 90°, 95°, 100°, 105°, or 110°, etc.

[0138] In some embodiments, as shown in FIG6D, the bottom of the groove 510 is located within the first isolation membrane 410'. That is, the groove 510 does not penetrate the first isolation membrane 410'.

[0139] In other embodiments, as shown in FIG6E, the groove 510 penetrates the first isolation membrane 410'. That is, the bottom of the groove 510 exposes the first induction layer 210.

[0140] That is, the groove 510 extends from the surface of the second isolation film 420' away from the first electrode 110, and passes through the second isolation film 420', the gate film 130', and the first isolation film 410'.

[0141] At this point, after the groove 510 is formed, the remaining portion of the first isolation film 410' serves as the first isolation layer 410, the remaining portion of the gate film 130' serves as the gate 130, and the remaining portion of the second isolation film 420' serves as the second isolation layer 420.

[0142] It is clarified here that the bottom of the groove 510 can also be located within the first induction layer 210. That is, the groove 510 can extend into the first induction layer 210, and the groove 510 can also extend to the surface of the first induction layer 210. This embodiment of the application does not limit this, and can be reasonably set according to the actual situation. For ease of illustration, the groove 510 shown in Figure 6D is used for illustration below.

[0143] S14, as shown in Figure 6F, forms a dielectric layer 320.

[0144] As shown in Figure 6F, the dielectric layer 320 is formed on the groove wall of the groove 510.

[0145] For example, step S14 may include:

[0146] S141, Form a dielectric film 320'.

[0147] As shown in Figure 6F, the dielectric film 320' is formed on the surface of the second insulating layer 420 away from the first electrode 110 and on the surface of the groove 510. For example, the dielectric film 320' covers the bottom and walls of the groove 510.

[0148] The process for forming the dielectric film at 320' can be atomic layer deposition (ALD).

[0149] For example, the material of dielectric film 320' may include a high-k dielectric material. For instance, the material of dielectric film 320' may include one or more of silicon oxide, hafnium dioxide (HfO2), hafnium aluminum oxide (HfAlO), and aluminum oxide (Al2O3). Dielectric film 320' may be a single-layer or multi-layer structure.

[0150] Alternatively, for example, the dielectric film 320' may also include a dipole layer. For instance, the material of the dielectric film 320' may include rare earth metal oxides (LnO), and rare earth metals include lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), etc.

[0151] The thickness of the dielectric film 320' is 0.1 nm to 10 nm. For example, the thickness of the dielectric film 320' can be 0.1 nm, 1 nm, 3 nm, 5 nm, 7 nm, 9 nm, or 10 nm, etc.

[0152] S142, forming a sacrificial membrane 301'.

[0153] As shown in Figure 6F, the sacrificial film 301' is formed on the side of the dielectric film 320' away from the first electrode 110. That is, the sacrificial film 301' covers the surface of the dielectric film 320'.

[0154] In the subsequent process of removing part of the dielectric membrane 320', the sacrificial membrane 301' is used to protect the portion of the dielectric membrane 320' that needs to be retained.

[0155] S143. Remove part of the sacrificial membrane 301' and part of the dielectric membrane 320' located at the bottom of the groove 510.

[0156] At this point, a portion of the sacrificial film 301' and a portion of the dielectric film 320' located on the second isolation layer 420 away from the surface of the first electrode 110 are removed, while a portion of the sacrificial film 301' and a portion of the dielectric film 320' located on the groove wall of the groove 510 are retained. The remaining portion of the dielectric film 320' serves as the dielectric layer 320. The remaining portion of the sacrificial film 301' serves as the sacrificial layer 301.

[0157] For example, part of the sacrificial film 301' and part of the dielectric film 320' at the bottom of the groove 510 can be removed by an anisotropic etching process.

[0158] It should be clarified here that, in step S13, when the groove 510 is located within the first isolation layer 410, after removing the portion of the dielectric film 320' located at the bottom of the groove 510, the exposed portion of the first isolation layer 410 is also removed to expose the first induction layer 210. At this time, as shown in FIG6E, the dielectric layer 320 is located above the first induction layer 210.

[0159] S144, Remove sacrificial layer 301.

[0160] In other words, the remaining portion of the sacrificial membrane 301' is removed, exposing the dielectric layer 320.

[0161] At this point, as shown in Figure 6F, after removing the sacrificial layer 301, the exposed dielectric layer 320 extends to the surface of the first isolation layer 410 away from the first electrode 110.

[0162] In some embodiments, as shown in FIG6G, a portion of the dielectric layer 320 on the side of the second isolation layer 420 away from the first electrode 110 is also removed. It is noted here that the removal of the portion of the dielectric layer 320 on the side of the second isolation layer 420 away from the first electrode 110 can be completed in step S14 or in a subsequent process step, and this application embodiment does not limit this.

[0163] For example, as shown in FIG6G, when removing part of the dielectric layer 320 at the bottom of the groove 510, part of the first induction layer 210 can also be removed. In this way, after the trench layer is formed subsequently, the contact area between the subsequently formed trench layer and the first induction layer 210 can be increased.

[0164] S15, as shown in Figure 6H, forms the channel layer 310.

[0165] For example, a channel layer 310 is formed on the bottom and walls of the groove 510. For instance, the channel layer 310 covers the surface of the dielectric layer 320. The channel layer 310 also covers the surface of the first induction layer 210 away from the first electrode 110.

[0166] At this point, since the portion of the dielectric film 320' located at the bottom of the groove 510 was removed in step S14 above, exposing the first induction layer 210, the thickness of the portion of the channel layer 310 located on the surface of the first induction layer 210 is thicker, that is, the thickness of the portion of the channel layer 310 located on the surface of the first induction layer 210 is greater than the thickness of the portion of the channel layer 310 located on the surface of the dielectric layer 320. As shown in FIG6H, the portion of the channel layer 310 located on the surface of the dielectric layer 320 forms a receiving cavity 302.

[0167] For ease of illustration, the portion of the dielectric layer 320 extending to the surface of the first insulating layer 410 away from the first electrode 110 is referred to as the first portion 311, bounded by the portion of the dielectric layer 320 formed at the bottom of the groove 510 that does not extend beyond the surface of the dielectric layer 320 away from the first electrode 110. In other words, the dielectric layer 320 also extends to the side of the first portion 311. The portion of the channel layer 310 located above the surface of the dielectric layer 320 away from the first electrode 110 is referred to as the second portion 312, and the portion of the channel layer 310 formed on the wall of the groove 510 is referred to as the third portion 313. That is, the second portion 312 and the third portion 313 form a receiving cavity 302. The second portion 312 is located on the side of the first portion 311 away from the first electrode 110, and the third portion 313 is located on the side of the second portion 312 away from the first portion 311, forming a ring. The opening of the receiving cavity 302 faces the side away from the first electrode 110.

[0168] At this time, as shown in Figure 6H, the dielectric layer 320 is also located on the side of the first part 311 and on the surface of the second part 312 near the first electrode 110.

[0169] The material of the channel layer 310 may, for example, include an oxide semiconductor material. Exemplarily, the material of the channel layer 310 may include metal elements, and the metal elements included in the channel layer 310 may be the same as at least some of the metal elements included in the first inducing layer 210. For example, the material of the channel layer 310 may include at least one metal element selected from zinc and indium. For example, the material of the channel layer 310 may include one or more of indium gallium zinc oxide (InGaZnO), indium aluminum zinc oxide (InAlZnO), indium tin zinc oxide (InSnZnO), indium tin gallium zinc oxide (InSnGaZnO), and indium magnesium zinc oxide (InMgZnO).

[0170] In this way, the material of the channel layer 310 can have the same oriented crystalline structure as the material of the first induction layer 210.

[0171] During the deposition of the channel layer 310 material, the deposition rate of metal elements in the part of the channel layer 310 material deposited on the first induction layer 210 changes. For example, the deposition rate of metal elements in the part of the channel layer 310 in contact with the first induction layer 210 is faster, resulting in a thicker part of the channel layer 310 in contact with the first induction layer 210.

[0172] For example, the surface of the portion of the channel layer 310 that contacts the first induction layer 210, away from the first induction layer 210, extends beyond the surface of the first isolation layer 410 that is away from the first induction layer 210. Alternatively, the surface of the portion of the channel layer 310 that contacts the first induction layer 210, away from the first induction layer 210, is lower than the surface of the gate 130 that is close to the first induction layer 210, or the surface of the portion of the channel layer 310 that contacts the first induction layer 210, away from the first induction layer 210, is flush with the surface of the gate 130 that is close to the first induction layer 210. In other words, the surface of the portion of the channel layer 310 that contacts the first induction layer 210, away from the first induction layer 210, is located within the first isolation layers 410.

[0173] Because the deposition rate of metal elements in the channel layer 310 material changes and the deposition rate is faster, the metal element content in the part of the channel layer 310 material that is in contact with the first induction layer 210 is higher.

[0174] For example, the content of metal elements in the material of the portion of the channel layer 310 in contact with the first inducing layer 210 is greater than or equal to 30%. For instance, the content of zinc in the material of the portion of the channel layer 310 in contact with the first inducing layer 210 is greater than or equal to 30%, or the content of indium in the material of the portion of the channel layer 310 in contact with the first inducing layer 210 is greater than or equal to 30%.

[0175] In this way, under the action of the first inducing layer 210, the deposition rate of the partial channel layer 310 deposited on the surface of the first inducing layer 210 can be increased, so that the thickness of the partial channel layer 310 in contact with the first inducing layer 210 and the thickness of the other part of the channel layer 310 are different. This results in the partial channel layer 310 in contact with the first inducing layer 210 being thicker, and thus the metal element content in the material of the partial channel layer 310 in contact with the first inducing layer 210 is higher. This can increase the carrier concentration of the channel layer to be formed, thereby reducing the parasitic resistance and contact resistance of the semiconductor device to be formed, and increasing the driving current of the semiconductor device to be formed.

[0176] S16. As shown in Figure 6I, an insulating layer 330 is formed within the channel layer 310.

[0177] For example, a portion of the channel layer 310 located on the surface of the dielectric layer 320 has a receiving cavity 302, and the insulating layer 330 fills the receiving cavity 302 of the channel layer 310.

[0178] In other words, the insulating layer 330 fills the third part 313 of the channel layer 310.

[0179] The material of the insulating layer 330 may include, for example, silicon oxide or aluminum oxide.

[0180] For example, the surface of the insulating layer 330 away from the first electrode 110 is flush with the surface of the second insulating layer 420 away from the first electrode 110.

[0181] For example, the insulating layer 330 can be formed by: firstly forming an insulating material in the channel layer 310, the insulating material also covering the surface of the second isolation layer 420 away from the first electrode 110, and then using a chemical mechanical polishing (CMP) process to remove the insulating material located in the second isolation layer 420, retaining the insulating material located in the channel layer 310, thus forming the insulating layer 330.

[0182] It should be noted that when removing part of the trench membrane 310' located on the surface of the second insulating layer 420 in step S15, the removal can also be performed when removing part of the insulating material located on the surface of the second insulating layer 420 in step S16.

[0183] In some implementations, when silicon oxide is used as the material of the insulating layer 330, an aluminum oxide layer can also be formed first to cover the surface of the channel layer 310 to block the material of the dielectric layer 320.

[0184] For example, the insulating layer 330 can be one or more layers.

[0185] S17, as shown in Figure 6J, forms the second pole 120.

[0186] For example, as shown in FIG6J, the second electrode 120 covers the surface of the second isolation layer 420 and the insulating layer 330, and the second electrode 120 is also in direct contact with the channel layer 310.

[0187] The material of the second electrode 120 can be the same as or different from the material of the first electrode 110. This application does not limit this. For example, the material of the second electrode 120 may include a metallic material. For instance, the material of the second electrode 120 may include metallic materials such as titanium nitride, aluminum nitride, gold, nickel, or tungsten. The second electrode 120 can be a single layer or multiple layers.

[0188] In some embodiments, before forming the second electrode 120, the method further includes forming a second induction layer.

[0189] For example, as shown in FIG6K, step S17 may include:

[0190] S171, Formation of the second induction layer 220.

[0191] As shown in Figure 6K, the second induction layer 220 covers the surface of the second isolation layer 420 and the insulating layer 330, and the second induction layer 220 is also in direct contact with the channel layer 310.

[0192] The material of the second inducing layer 220 can be the same as or different from the material of the first inducing layer 210. For example, the material of the second inducing layer 220 may include a material with a high degree of crystallinity. The material of the second inducing layer 220 may include a metallic element. For example, the metallic element may include at least one of zinc and indium. For example, the material of the second inducing layer 220 may include one or more of indium tin oxide, indium gallium oxide, indium oxide, indium gallium zinc oxide, indium gallium zinc oxide, and indium zinc oxide.

[0193] S172, forming the second pole 120.

[0194] As shown in Figure 6K, the second electrode 120 is formed on the surface of the second induction layer 220 away from the first electrode 110.

[0195] In some embodiments, after forming the second electrode 120 and the second inducing layer 220, the fabrication method further includes: as shown in FIG6L, patterning the second electrode 120 and the second inducing layer 220, for example, by photolithography. At this time, as shown in FIG6L, the channel layer 310 can also be patterned. That is, the patterning of the second electrode 120, the second inducing layer 220, and the channel layer 310 can be performed in the same process step.

[0196] In this embodiment, one of the first electrode 110 and the second electrode 120 is the drain, and the other is the source. For example, the first electrode 110 is the source, and the second electrode 120 is the drain. Alternatively, for example, the first electrode 110 is the drain, and the second electrode 120 is the source. This embodiment does not limit the specific configuration; it can be set appropriately according to actual circumstances.

[0197] In some embodiments, the preparation method further includes:

[0198] S18, as shown in Figure 6M, forms an insulating material.

[0199] For example, an insulating material is formed on the surface of the second electrode 120 away from the first electrode 110 and within the blank pattern of the patterned second electrode 120. Then, the surface of the insulating material is subjected to a CMP polishing process to retain the insulating material in the same layer as the second electrode 120 and the second induction layer 220.

[0200] Insulating materials may include, for example, silicon oxide.

[0201] It should be noted that the semiconductor device fabrication method provided in this application is not limited to the above steps. Other steps may be added or some of the above steps may be omitted as needed. It is not limited to including every step, nor is it limited to including only the above steps. In addition, the order of steps in the above fabrication method is only illustrative and does not impose any restrictions on the order of steps. It can be adjusted and changed as needed.

[0202] In some embodiments, this application also provides another method for fabricating a semiconductor device, as shown in FIG7, including:

[0203] S21, providing a first pole 110 and a first induction layer 210.

[0204] S22, Form gate film 130'.

[0205] S23, Create a groove 510.

[0206] S24, Forming a dielectric layer 320.

[0207] Steps S21-S24 are the same as steps S11-S14 above, and you can refer to the relevant descriptions of S11-S14 in the above embodiments.

[0208] S25, as shown in Figure 8A, a channel membrane 310' is formed.

[0209] For example, a channel membrane 310' is formed on the bottom and walls of the groove 510. For instance, the channel membrane 310' covers the surface of the dielectric layer 320. The channel membrane 310' also covers the surface of the first induction layer 210 away from the first electrode 110. A portion of the channel membrane 310' located on the surface of the dielectric layer 320 forms a receiving cavity 302.

[0210] At this point, the thickness of the portion of the channel membrane 310' in contact with the first induction layer 210 is different from the thickness of the other portion of the channel membrane 310', and the portion of the channel membrane 310' in contact with the first induction layer 210 is thicker.

[0211] For a detailed description of the thickness difference of the channel membrane 310', please refer to the description of the channel layer 310 in step S15.

[0212] In some embodiments, as shown in FIG8B, step S25 further includes:

[0213] Remove a portion of the channel membrane 310' located on the surface of the second isolation layer 420 away from the first electrode 110. At this point, the remaining portion of the channel membrane 310' serves as the channel layer 310.

[0214] In other words, the channel layer 310 is located on the wall of the groove 510 and the surface of the first induction layer 210, and the thickness of the portion of the channel layer 310 located on the surface of the first induction layer 210 is greater than the thickness of the portion of the channel layer 310 located on the wall of the groove 510.

[0215] In this embodiment of the application, the trench layer 310 is formed by removing a portion of the trench membrane 310' on the surface of the second isolation layer 420. This can be formed in step S25 or in a subsequent process step. This embodiment of the application does not limit this. For ease of illustration, the trench membrane 310' will be used for the following description.

[0216] S26. As shown in Figure 8C, an insulating layer 330 is formed within the channel membrane 310'.

[0217] In other words, an insulating layer 330 is formed within the receiving cavity 302. For example, the surface of the insulating layer 330 away from the first electrode 110 is lower than the surface of the second insulating layer 420 away from the first electrode 110. Alternatively, the thickness of the insulating layer 330 can be considered less than the depth of the receiving cavity 302.

[0218] As a result, the insulating layer 330 does not completely fill the receiving cavity 302.

[0219] For example, the method of forming the insulating layer 330 may be as follows: first, an insulating material is formed in the channel membrane 310', the insulating material also covers the surface of the second isolation layer 420 away from the first electrode 110, then the insulating material located in the second isolation layer 420 is removed by chemical mechanical polishing process, then a portion of the insulating material located in the channel membrane 310' is etched back, and the remaining portion of the insulating material forms the insulating layer 330.

[0220] In this embodiment, the thickness of the insulating layer 330 is not limited. For example, the surface of the insulating layer 330 away from the first electrode 110 may be higher than the upper surface of the gate 130 (the surface of the gate 130 away from the first electrode 110), or it may be located between the upper surface and the lower surface of the gate 130 (the surface of the gate 130 near the first electrode 110). Alternatively, it may be lower than the lower surface of the gate 130. The thickness can be set reasonably according to the actual situation.

[0221] The specific description of the insulating layer 330 is the same as in step S16 above, and you can refer to the relevant description of the insulating layer 330 in the above embodiments.

[0222] S27, forming the second pole 120.

[0223] For example, step S27 may include:

[0224] S271, Formation of the second induction layer 220.

[0225] As shown in Figure 8D, a second induction layer 220 is formed on the side of the insulating layer 330 away from the first electrode 110.

[0226] As exemplarily shown in FIG8D, the second induction layer 220 covers the sidewalls of the receiving cavity 302 and the surface of the insulating layer 330.

[0227] S272, as shown in Figure 8E, forms the second electrode 120.

[0228] As shown in Figure 8E, a second electrode 120 is formed on the side of the second induction layer 220 away from the first electrode 110.

[0229] At this point, the second electrode 120 covers the surface of the second induction layer 220.

[0230] As shown in Figure 8E, a portion of the channel membrane 310', a portion of the second induction layer 220, and a portion of the second electrode 120 located on the side of the second isolation layer 420 away from the first electrode 110 are also removed to form a channel layer 310 and a second induction layer 220 and a second electrode 120 located on the side of the channel layer 310 away from the first electrode 110.

[0231] In some embodiments, as shown in FIG8F, the second induction layer 220 may also completely fill the receiving cavity 302. In this case, a portion of the channel membrane 310' located on the side of the second isolation layer 420 away from the first electrode 110 is first removed to form the channel layer 310, and then the second electrode 120 is formed. The second electrode 120 is located on the side of the second induction layer 220 away from the first electrode 110 and also covers the surface of the second isolation layer 420 away from the first electrode 110.

[0232] The specific description of the second electrode 120 and the second induction layer 220 is the same as in step S17 above. You can refer to the relevant description of the second electrode 120 and the second induction layer 220 in the above embodiments.

[0233] S28, as shown in Figure 8G, forms an insulating material.

[0234] Step S28 is the same as step S18 above, and you can refer to the relevant description of S18 in the above embodiments.

[0235] The preparation method provided in this application does not impose any restrictions on the order of steps and can be reasonably adjusted as needed.

[0236] Furthermore, steps S21-S28 above can be omitted as needed, and are not required to be included in every step. Alternatively, steps can be added as needed, and are not limited to only the steps described above.

[0237] In some embodiments, this application also provides another method for fabricating a semiconductor device, as shown in FIG9, including:

[0238] S31, providing a first pole 110 and a first induction layer 210.

[0239] S32, Form gate film 130'.

[0240] S33, create a groove 510.

[0241] S34, Forming a dielectric layer 320.

[0242] Steps S31-S4 are the same as steps S11-S14 above, and you can refer to the relevant descriptions of S11-S14 in the above embodiments.

[0243] S35, as shown in Figure 10A, forms a channel layer 310.

[0244] The difference from forming the channel layer 310 in step S15 is that, as shown in Figure 10A, the channel layer 310 fills the channel 310.

[0245] For example, the trench layer 310 can be formed by: firstly forming a trench layer material in the groove 510, the trench layer material also covering the surface of the second isolation layer 420 away from the first electrode 110, and then using a chemical mechanical polishing process to remove the trench layer material located in the second isolation layer 420, leaving the trench layer material located in the groove 510, thus forming the trench layer 310.

[0246] At this point, as shown in Figure 10A, the channel layer 310 can be divided into a first part 311 and a third part 313. The first part 311 and the third part 313 are stacked, and the first part 311 is located on the side of the third part 313 closer to the first induction layer 210, and the first part 311 is in contact with the first induction layer 210.

[0247] For example, the surface of the first portion 311 away from the first electrode 110 does not protrude above the surface of the gate 130 near the first electrode 110.

[0248] The content of metallic elements in the material of Part 1, 311 is greater than the content of metallic elements in the material of Part 3, 313.

[0249] It is clarified here that during the deposition process of the channel layer 310, the metal elements in the channel layer 310 material are affected by the first inducing layer 210. The deposition rate of metal elements in the channel layer 310 material in contact with the first inducing layer 210 is faster, and the content of metal elements in the channel layer 310 material in contact with the first inducing layer 210 is higher. Therefore, the content of metal elements in the material of the channel layer 310 closer to the first inducing layer 210 is greater than the content of metal elements in the material of the channel layer 310 farther away from the first inducing layer 210. In other words, the content of metal elements in the material of the channel layer 310 gradually decreases along the direction away from the first inducing layer 210. Therefore, in the formed semiconductor device, there is no clear boundary between the first portion 311 and the third portion 313.

[0250] Furthermore, since the material of the channel layer 310 that is far from the first induction layer 210 is not affected by the first induction layer 210, the content of metal elements in the third part 313 is the same, while the content of metal elements in the first part 311 gradually decreases in the direction away from the first induction layer 210.

[0251] For example, the content of a metallic element in the material of the first part 311 is greater than or equal to 30%. For instance, the content of zinc in the material of the first part 311 is greater than or equal to 30%, or the content of indium in the material of the first part 311 is greater than or equal to 30%.

[0252] The specific description of the channel layer 310 is the same as in step S17 above, and you can refer to the relevant description of the channel layer 310 in the above embodiments.

[0253] S36, as shown in Figures 10B and 10C, forms the second electrode 120.

[0254] For example, step S36 may include:

[0255] S361, Formation of the second induction layer 220.

[0256] As shown in Figure 10B, a second induction layer 220 is formed on the side of the channel layer 310 away from the first electrode 110.

[0257] The second induction layer 220 covers the surfaces of the second isolation layer 420 and the insulating layer 330.

[0258] S362, as shown in Figure 10C, forms the second pole 120.

[0259] As shown in Figure 10C, the second electrode 120 is formed on the surface of the second induction layer 220 away from the first electrode 110.

[0260] The specific description of the second electrode 120 and the second induction layer 220 is the same as in step S17 above. You can refer to the relevant description of the second electrode 120 and the second induction layer 220 in the above embodiments.

[0261] In some embodiments, as shown in FIG10D, the second electrode 120 and the second induction layer 220 may also be formed in the annular structure surrounded by the dielectric layer 320, and the second electrode 120 and the second induction layer 220 are disposed on the side of the channel layer 310 away from the first electrode 110.

[0262] In other words, the second pole 120 and the second induction layer 220 are formed on the side of the third part 313 of the channel layer 310 away from the first part 311.

[0263] At this point, the method for forming the second electrode 120 and the second induction layer 220 is the same as in step S27 above, and the relevant description of S27 in the above embodiments can be referred to.

[0264] S37, As shown in Figure 10E, an insulating material is formed.

[0265] Step S37 is the same as step S18 above, and you can refer to the relevant description of S18 in the above embodiments.

[0266] The preparation method provided in this application does not impose any restrictions on the order of steps and can be reasonably adjusted as needed.

[0267] Furthermore, steps S31-S37 above can be omitted as needed, and are not required to be included in every step. Steps can also be added as needed, and are not limited to only the steps described above.

[0268] The semiconductor device fabrication method provided in this application embodiment involves forming a channel layer 310 on a first inducing layer 210. Under the action of the first inducing layer 210, the deposition rate of a portion of the channel layer 310 (first portion 311) deposited on the surface of the first inducing layer 210 can be increased, causing a difference in thickness between the portion of the channel layer 310 in contact with the first inducing layer 210 and the other portion of the channel layer 310 (third portion 313). Consequently, the first portion 311 of the channel layer 310 is thicker, resulting in a higher content of metal elements in the material of the first portion 311. This increases the carrier concentration of the channel layer 310. Furthermore, influenced by the first inducing layer 210, the channel layer 310 can form a crystalline structure with the same orientation as the material of the first inducing layer 210, thereby reducing the parasitic resistance of the semiconductor device 10. It also reduces the contact resistance between the channel layer 310 and the first inducing layer 210, increases the driving current of the semiconductor device 10, and thus improves the performance of the semiconductor device 10. Furthermore, the channel layer 310 in the semiconductor device 10 provided in this application embodiment is formed by a deposition process, without the need for a back-etching process, thus avoiding process defects caused by the back-etching process.

[0269] Based on this, this application also provides a semiconductor device, which can be fabricated by the above-described semiconductor device fabrication method. As shown in FIG11, the semiconductor device includes a first electrode 110, a first inducing layer 210 located on the first electrode 110, a channel layer 310 located on the side of the first inducing layer 210 away from the first electrode 110, a gate 130 disposed on the periphery of the channel layer 310, and a second electrode 120 connected to the channel layer 310. The first electrode 110 and the second electrode 120 are located on opposite sides of the channel layer 310.

[0270] In this application, one of the first electrode 110 and the second electrode 120 is the source and the other is the drain. For example, the first electrode 110 is the source and the second electrode 120 is the drain. Alternatively, for example, the first electrode 110 is the drain and the second electrode 120 is the source. This application does not impose any limitations on this; it can be reasonably configured according to the actual situation.

[0271] When the first electrode 110 is the drain electrode, the first electrode 110 can also be used as a bit line or a storage point.

[0272] For example, the first electrode 110 and the second electrode 120 are located at opposite ends of the channel layer 310, and both the first electrode 110 and the second electrode 120 are connected to the channel layer 310.

[0273] For example, the material of the first electrode 110 may include a metallic material. For instance, the material of the first electrode 110 may include metallic materials such as titanium nitride, aluminum nitride, gold, nickel, or tungsten. The first electrode 110 may be a single layer or multiple layers.

[0274] For example, the material of the second electrode 120 may include a metallic material. For instance, the material of the second electrode 120 may include metallic materials such as titanium nitride, aluminum nitride, gold, nickel, or tungsten. The second electrode 120 may be a single layer or multiple layers.

[0275] The materials of the first electrode 110 and the second electrode 120 can be the same or different. This application does not impose any limitations on this; the materials can be reasonably set according to the actual situation.

[0276] Referring again to Figure 11, the gate 130 is located between the first electrode 110 and the second electrode 120, and the gate 130 is disposed around the channel layer 310.

[0277] For example, the material of gate 130 may include a metallic material. For instance, the material of gate 130 may include metallic materials such as titanium nitride, aluminum nitride, or tungsten. Gate 130 may be a single layer or multiple layers. It is noted here that in some embodiments, gate 130 may also include a pad electrode layer or a work function adjustment layer. For ease of illustration, this embodiment uses gate 130 as the illustration and does not illustrate the multiple metal layers included in gate 130.

[0278] In some embodiments, as shown in FIG11, a first isolation layer 410 is further provided between the gate 130 and the first electrode 110. The first isolation layer 410 is used to separate the gate 130 and the first electrode 110 so as to insulate the gate 130 and the first electrode 110.

[0279] For example, the material of the first isolation layer 410 may include a low dielectric constant material. For instance, the material of the first isolation layer 410 may include silicon oxycarbonate, silicon oxynitride, silicon carbide, silicon nitride, silicon oxide, undoped silicon oxide glass, phosphosilicate glass, silicon fluoride glass, or borosilicate glass, etc. It is clarified here that the material of the first isolation layer 410 may also be other silicon glass materials; this application embodiment does not limit this, and it can be reasonably set according to the actual situation.

[0280] In some embodiments, as shown in FIG11, a second isolation layer 420 is further provided between the gate 130 and the second electrode 120. The second isolation layer 420 is used to separate the gate 130 and the second electrode 120 so as to insulate the gate 130 and the second electrode 120.

[0281] For example, the material of the second isolation layer 420 may include a low dielectric constant material. For instance, the material of the second isolation layer 420 may include silicon oxycarbonate, silicon oxynitride, silicon carbide, silicon nitride, silicon oxide, undoped silicon oxide glass, phosphosilicate glass, silicon fluoride glass, or borosilicate glass, etc. It is clarified here that the material of the second isolation layer 420 may also be other silicon glass materials; this application embodiment does not limit this, and it can be reasonably set according to the actual situation. The material of the second isolation layer 420 and the material of the first isolation layer 410 may be the same or different; this application embodiment does not limit this.

[0282] Regarding the first induction layer 210, as exemplarily shown in FIG11, the first induction layer 210 may be located on the surface of the first electrode 110.

[0283] At this point, the first induction layer 210 and the first electrode 110 are stacked.

[0284] Alternatively, as exemplarily shown in FIG12A, the first electrode 110 has a recess 111, and the first induction layer 210 is located within the recess 111 of the first electrode 110.

[0285] In other words, the first induction layer 210 is located inside the first pole 110.

[0286] In this embodiment, the positional relationship between the first induction layer 210 and the first electrode 110 is not limited. It is sufficient that the first induction layer 210 is in contact with the first electrode 110 and the first induction layer 210 is also in contact with the channel layer 310.

[0287] For example, the material of the first inducing layer 210 may include one or more of indium tin oxide, indium gallium oxide, indium oxide, indium gallium zinc oxide, indium gallium zinc oxide, and indium zinc oxide.

[0288] Regarding the channel layer 310, in some embodiments, as shown in FIG12A, the channel layer 310 includes a first portion 311, a second portion 312, and a third portion 313. The first portion 311 is located on the surface of the first induction layer 210 away from the first electrode 110. The second portion 312 is located on the side of the first portion 211 away from the first induction layer 210, and the third portion 313 is located one layer away from the second portion 312 and the first portion 311. As shown in FIG12B, which is a cross-sectional view of FIG12A along the A1A2 direction, the third portion 313 forms a ring. The sum of the thickness of the first portion 311 and the thickness of the second portion 312 is greater than the thickness of the third portion 313.

[0289] Regarding the thickness of the first part 311 and the second part 312, as shown in Figure 12A, it can be understood that along the thickness direction of the first electrode 110, the sum of the dimensions of the first part 311 and the second part 312 is the thickness d1 of the first part 311 and the second part 312. Regarding the thickness of the third part 313, as shown in Figure 12A, it can be understood that along the direction perpendicular to the thickness direction of the first electrode 110, the dimension of the third part 313 is the thickness d2 of the third part 313.

[0290] For example, the thickness of the second part 312 can be the same as the thickness of the third part 313.

[0291] For example, as shown in FIG12A, the first portion 311 of the channel layer 310 is located between the surface of the gate 130 near the first electrode 110 and the surface of the first induction layer 210 near the first electrode 110.

[0292] In other words, the surface of the first portion 311 of the channel layer 310 that is away from the first induction layer 210 is not higher than the surface of the gate 130 that is close to the first induction layer 210.

[0293] In other words, the surface of the first portion 311 of the channel layer 310 does not exceed the gate 130.

[0294] In this way, the first part 311 is thicker and has a higher carrier concentration, and the channel layer 310 has a higher carrier concentration, which can reduce the parasitic resistance and contact resistance of the semiconductor device 10.

[0295] In some embodiments, continuing to refer to FIG11, the first portion 311 of the channel layer 310 may also be located within the first induction layer 210.

[0296] In other words, the first portion 311 of the channel layer 310 extends from the surface of the first induction layer 210 away from the first electrode 110 into the first induction layer 210.

[0297] In some embodiments, as shown in FIG13A, the first portion 311 of the channel layer 310 may be located on the surface of the first induction layer 210 away from the first electrode 110. This embodiment is not limited in this respect; it can be reasonably configured according to actual circumstances.

[0298] In this embodiment, the material of the first portion 311 of the channel layer 310 has the same crystalline structure as the material of the first inducing layer 210. Exemplarily, the material of the channel layer 310 may include a metal element, and the metal element included in the channel layer 310 may be the same as at least some of the metal elements included in the first inducing layer 210. For example, the material of the channel layer 310 may include at least one metal element selected from zinc and indium. Exemplarily, the material of the first inducing layer 210 may include a metal element. For example, the metal element may include at least one metal element selected from zinc and indium.

[0299] For example, the material of the channel layer 310 may include one or more of indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium tin gallium zinc oxide, and indium magnesium zinc oxide.

[0300] For example, the content of a metal element in the material of the first portion 311 of the channel layer 310 is greater than or equal to 30%. For example, the content of zinc in the material of the first portion 311 is greater than or equal to 30%, or the content of indium in the material of the first portion 311 is greater than or equal to 30%.

[0301] In this way, since the material of the first part 311 of the channel layer 310 has a high content of metal elements, the carrier concentration of the channel layer 310 can be increased, thereby reducing the parasitic resistance of the semiconductor device 10. At the same time, the contact resistance between the channel layer 310 and the first induction layer 210 can also be reduced, thereby increasing the driving current of the semiconductor device 10.

[0302] In some embodiments, as shown in FIG13A, the semiconductor device 10 further includes a dielectric layer 320.

[0303] For example, as shown in FIG13A, the dielectric layer 320 is disposed around the third portion 313 of the channel layer 310, and the dielectric layer 320 is disposed between the channel layer 310 and the gate 130.

[0304] In other words, the dielectric layer 320 is located between the first isolation layer 410 and the channel layer 310, between the gate 130 and the channel layer 310, and between the second isolation layer 420 and the channel layer 310.

[0305] As shown in Figure 13A, the dielectric layer 320 extends from the surface of the second isolation layer 420 away from the first electrode 110, through the gate 130, and to the first isolation layer 410. For example, the dielectric layer 320 may be located within the first isolation layer 410, or the dielectric layer 320 may also penetrate the first isolation layer 410, i.e., the dielectric layer 320 is in contact with the first induction layer 210. This embodiment of the application does not impose any limitations on this.

[0306] At this point, the third portion 313 of the channel layer 310 can be considered as the annular portion of the channel layer 310, and the first portion 311 and the second portion 312 of the channel layer 310 are the portions located on the side of the first induction layer 210 away from the first electrode 110. Regarding the first portion 311 and the second portion 312, for ease of distinction, it can be assumed that the thickness of the second portion 312 is the same as the thickness of the third portion 313. For example, the portion of the channel layer 310 with the same thickness as the third portion 313 can be selected as the second portion 312, and the remaining portion of the channel layer 310 can be considered as the first portion 311. Alternatively, in this case, it can be assumed that there is no clear boundary between the first portion 311 and the second portion 312, in which case the sum of the thicknesses of the first portion 311 and the second portion 312 is greater than the thickness of the third portion 313.

[0307] In this embodiment, there is no limitation on this, as long as the thickness of the portion of the channel layer 310 located on the side of the first induction layer 210 away from the first electrode 110 is greater than the thickness of the portion of the channel layer 310 located on the surface of the dielectric layer 320.

[0308] For example, as shown in FIG13B, the dielectric layer 320 can also extend towards the channel layer 310 in a direction parallel to the plane where the first electrode 110 is located. That is, the dielectric layer 320 also extends to the surface of the second portion 312 of the channel layer 310 near the first electrode 110. At this time, the dielectric layer 320 also extends to the side of the first portion 311 of the channel layer 310. That is, the dielectric layer 320 is L-shaped.

[0309] For ease of illustration, as shown in Figure 13B, the portion of the dielectric layer 320 extending into the channel layer 310 along a direction parallel to the plane of the first electrode 110 is designated as the first portion 311, meaning the dielectric layer 320 extends beyond the surface of the dielectric layer 320 on the side of the first induction layer 210 away from the first electrode 110. The portion of the channel layer 310 above the surface of the dielectric layer 320 away from the first electrode 110 is designated as the second portion 312, meaning the dielectric layer 320 extends to the surface of the second portion 312 near the first electrode 110. The portion of the channel layer 310 on the side of the dielectric layer 320 away from the gate 130 is designated as the third portion 313.

[0310] For example, along the direction parallel to the plane where the first pole 110 is located, the area of ​​the first portion 311 of the channel layer 310 is smaller than the area of ​​the second portion 312 of the channel layer 310.

[0311] In other words, when the dielectric layer 320 extends into the first isolation layer 410, the dielectric layer 320 also extends to the side of the first isolation layer 410 away from the first induction layer 210. Alternatively, when the dielectric layer 320 contacts the first induction layer 210, the dielectric layer 320 also extends to the surface of the first induction layer 210.

[0312] For example, the surface of the first portion 311 of the channel layer 310 away from the first electrode 110 is higher than the surface of the dielectric layer 320 near the first electrode 110. That is, the first portion 311 of the channel layer 310 extends beyond the dielectric layer 320.

[0313] This ensures that the thickness of the first part 311 is greater than the thickness of the third part 313, thereby increasing the carrier concentration of the channel layer 310, reducing the parasitic resistance of the semiconductor device 10, reducing the contact resistance between the channel layer 310 and the first electrode 110, and increasing the driving current of the semiconductor device 10.

[0314] Regarding the material of the dielectric layer 320, for example, the material of the dielectric layer 320 may include a high dielectric constant material. For instance, the material of the dielectric layer 320 may include one or more of silicon oxide, hafnium dioxide, hafnium aluminum oxide, and aluminum oxide. The dielectric layer 320 may be a single layer or a multilayer structure.

[0315] Alternatively, for example, the dielectric layer 320 may also include a dipole layer. For instance, the material of the dielectric layer 320 may include rare earth metal oxides, and rare earth metals include lanthanum, cerium, praseodymium, neodymium, etc.

[0316] The thickness of the dielectric layer 320 is 0.1 nm to 10 nm. For example, the thickness of the dielectric layer 320 can be 0.1 nm, 1 nm, 3 nm, 5 nm, 7 nm, 9 nm or 10 nm, etc.

[0317] In some embodiments, as shown in FIG14, the semiconductor device 10 further includes a second inducing layer 220.

[0318] The second induction layer 220 is located on the side of the second electrode 120 near the channel layer 310, and the second induction layer 220 is also in contact with the channel layer 310.

[0319] For example, the material of the second inducing layer 220 may include a material with a high degree of crystallinity. The material of the second inducing layer 220 may include a metallic element. For example, the metallic element may include at least one of zinc and indium. For example, the material of the second inducing layer 220 may include one or more of indium tin oxide, indium gallium oxide, indium oxide, indium gallium zinc oxide, indium gallium zinc oxide, and indium zinc oxide. The material of the second inducing layer 220 may be the same as or different from the material of the first inducing layer 210.

[0320] In this way, the second induction layer 220 disposed between the channel layer 310 and the second electrode 120 can reduce the contact resistance between the channel layer 310 and the second electrode 120, thereby increasing the driving current of the semiconductor device 10.

[0321] In some embodiments, as shown in FIG14, the semiconductor device 10 further includes an insulating layer 330. The insulating layer 330 is located within a third portion 313 of the channel layer 310.

[0322] In other words, the insulating layer 330 fills the third part 313 of the channel layer 310.

[0323] The insulating layer 330 may be made of silicon oxide or aluminum oxide. The insulating layer 330 may be a single layer or multiple layers.

[0324] For example, as shown in FIG14, the surface of the insulating layer 330 away from the first electrode 110 can be flush with the surface of the second insulating layer 420 away from the first electrode 110. In this case, the second induction layer 220 is located on the side of the second insulating layer 420 away from the first electrode 110, and the second electrode 120 is located on the side of the second induction layer 220 away from the first electrode 110.

[0325] At this point, the channel layer 310 can also extend between the second isolation layer 420 and the second induction layer 220.

[0326] Alternatively, as exemplarily shown in FIG15, the surface of the insulating layer 330 away from the first electrode 110 is lower than the surface of the second insulating layer 420 away from the first electrode 110.

[0327] At this point, as shown in Figure 15, the second electrode 120 is located on the side of the insulating layer 330 away from the first electrode 110. That is, the second electrode 120 is located within the third part 313 of the channel layer 310.

[0328] As exemplarily shown in FIG15, the second induction layer 220 is located between the channel layer 310 and the second electrode 120. The second induction layer 220 may also extend between the second electrode 120 and the insulating layer 330.

[0329] In other words, the second induction layer 220 can be located on the side of the third part 313 of the channel layer 310 away from the dielectric layer 320, and the second induction layer 220 can also extend to the side of the insulating layer 330 away from the first electrode 110.

[0330] In this embodiment, the thickness of the insulating layer 330 is not limited. For example, the surface of the insulating layer 330 away from the first electrode 110 can be higher than the upper surface of the gate 130 (the surface of the gate 130 away from the first electrode 110), or it can be located between the upper surface of the gate 130 (the surface of the gate 130 away from the first electrode 110) and the lower surface of the gate 130 (the surface of the gate 130 close to the first electrode 110). Alternatively, it can be lower than the lower surface of the gate 130 (the surface of the gate 130 close to the first electrode 110). The thickness can be set reasonably according to the actual situation.

[0331] In other words, the surface of the second induction layer 220 near the first electrode 110 can be higher than the upper surface of the gate 130 (the surface of the gate 130 away from the first electrode 110), or it can be located between the upper surface of the gate 130 (the surface of the gate 130 away from the first electrode 110) and the lower surface of the gate 130 (the surface of the gate 130 near the first electrode 110). Alternatively, it can be lower than the lower surface of the gate 130 (the surface of the gate 130 near the first electrode 110).

[0332] In other embodiments, as shown in Figures 16A and 16B, the channel layer 310 can be divided into a first portion 311 and a third portion 313. The first portion 311 and the third portion 313 are stacked, and the first portion 311 is located on the side of the third portion 313 closer to the first induction layer 210, and the first portion 311 is in contact with the first induction layer 210.

[0333] The difference between the third part 313 and the above-mentioned channel layer 310 is that the structure of the third part 313 is different, that is, there is no insulating layer filling the third part 313.

[0334] For example, the content of metal elements in the material of the first part 311 is greater than the content of metal elements in the material of the third part 313. For instance, the content of metal elements in the material of the first part 311 gradually decreases in the direction away from the first inducing layer 210, while the content of metal elements in the material of the third part 313 is the same.

[0335] Since the third part 313 is far from the first inducing layer 210, the content of metal elements in the material of the third part 313 is less affected by the first inducing layer 210.

[0336] It is clarified here that the metal element content in the material of the channel layer 310 near the first inducing layer 210 is greater than the metal element content in the material of the channel layer 310 farther away from the first inducing layer 210. That is, the metal element content in the material of the channel layer 310 gradually decreases along the direction away from the first inducing layer 210. Therefore, in the semiconductor device 10, there is no clear boundary between the first portion 311 and the third portion 313.

[0337] For example, the content of a metallic element in the material of the first part 311 is greater than or equal to 30%. For instance, the content of zinc in the material of the first part 311 is greater than or equal to 30%, or the content of indium in the material of the first part 311 is greater than or equal to 30%.

[0338] For example, the surface of the first portion 311 away from the first electrode 110 is not higher than the surface of the gate 130 near the first electrode 110. That is, taking the surface of the gate 130 near the first electrode 110 as the interface, the content of metal elements in the channel layer 310 material below the interface is greater than or equal to 30%, and the content of metal elements in the channel layer 310 material above the interface is less than 30%.

[0339] In some embodiments, as shown in FIG17, the semiconductor device 10 further includes a substrate 100. All of the above structures are disposed on the substrate 100.

[0340] For example, the material of substrate 100 may be semiconductor. Substrate 100 may also be doped (e.g., P-type doped, N-type doped) or undoped.

[0341] Alternatively, by way of example, substrate 100 is a wafer, such as a silicon wafer. This application embodiment does not limit the material of substrate 100.

[0342] In this embodiment, the semiconductor device 10 may include a dual-gate vertical transistor, a single-gate vertical transistor, or a ring-gate vertical transistor. This embodiment does not limit the type of vertical transistor; it can be set appropriately according to actual conditions.

[0343] The semiconductor device 10 provided in this application embodiment has a first portion 311 and a second portion 312 of a channel layer 310 sequentially stacked on a first inducing layer 210. The sum of the thickness of the first portion 311 and the thickness of the second portion 312 of the channel layer 310 is greater than the thickness of the third portion 313. This can increase the carrier concentration of the channel layer 310, thereby reducing the parasitic resistance of the semiconductor device 10. At the same time, it can also reduce the contact resistance between the channel layer 310 and the first inducing layer 210, thereby increasing the driving current of the semiconductor device 10.

[0344] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: First pole; The first induction layer is located on the first electrode; A channel layer is located on the side of the first induction layer away from the first electrode; the channel layer includes a first part, a second part, and a third part; the first part is located on the surface of the first induction layer away from the first electrode, and the second part is located on the side of the first part away from the first induction layer. The third part is located on the side of the second part away from the first part, and the third part forms a ring; the sum of the thickness of the first part and the thickness of the second part is greater than the thickness of the third part; The gate is disposed on the periphery of the channel layer; The second electrode is connected to the channel layer; the second electrode and the first electrode are located on opposite sides of the channel layer.

2. The semiconductor device according to claim 1, characterized in that, The first portion is located between the surface of the gate near the first electrode and the surface of the first induction layer near the first electrode.

3. The semiconductor device according to claim 1 or 2, characterized in that, The material of the first part has the same crystalline structure as the material of the first inducing layer.

4. The semiconductor device according to any one of claims 1-3, characterized in that, The material of the channel layer includes metallic elements; the content of the metallic elements in the material of the first part is greater than the content of the metallic elements in the material of the third part.

5. The semiconductor device according to claim 4, characterized in that, The content of the metal element in the material of the first part is greater than or equal to 30%.

6. The semiconductor device according to claim 4 or 5, characterized in that, The metallic element includes at least one of zinc and indium.

7. The semiconductor device according to any one of claims 1-6, characterized in that, The materials of the first induction layer and the channel layer contain at least some of the same metallic elements.

8. The semiconductor device according to any one of claims 1-7, characterized in that, The material of the first induction layer includes one or more of indium tin oxide, indium gallium oxide, indium oxide, indium gallium zinc oxide, indium gallium zinc oxide, and indium zinc oxide.

9. The semiconductor device according to any one of claims 1-8, characterized in that, The material of the channel layer includes one or more of indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, indium tin gallium zinc oxide, and indium magnesium zinc oxide.

10. The semiconductor device according to any one of claims 1-9, characterized in that, The first electrode has a recess, and the first induction layer is located within the recess of the first electrode.

11. The semiconductor device according to any one of claims 1-10, characterized in that, The semiconductor device further includes a second induction layer, which is located on the side of the second electrode near the channel layer and is in contact with the channel layer.

12. The semiconductor device according to any one of claims 1-11, characterized in that, The second pole is located within the third portion; The semiconductor device further includes a second induction layer, which is located between the channel layer and the second electrode.

13. The semiconductor device according to any one of claims 1-12, characterized in that, The semiconductor device further includes a dielectric layer; the dielectric layer is disposed around the third portion of the channel layer and is disposed between the channel layer and the gate.

14. The semiconductor device according to claim 13, characterized in that, The surface of the first portion away from the first electrode is higher than the surface of the dielectric layer near the first electrode.

15. The semiconductor device according to claim 13 or 14, characterized in that, Along a direction parallel to the plane where the first electrode is located, the dielectric layer also extends to the surface of the second portion near the first electrode, and the dielectric layer extends to the side of the first portion.

16. The semiconductor device according to any one of claims 1-15, characterized in that, The semiconductor device may include a dual-gate vertical transistor, a single-gate vertical transistor, or a ring-gate vertical transistor.

17. A semiconductor device, characterized in that, include: First pole; The first induction layer is located on the first electrode; The channel layer is located on the side of the first induction layer away from the first electrode; The gate is disposed on the periphery of the channel layer; The second electrode is connected to the channel layer; the second electrode and the first electrode are located on opposite sides of the channel layer; along the direction from the first electrode to the second electrode, the content of metal elements in the material of the channel layer decreases.

18. The semiconductor device according to claim 17, characterized in that, The channel layer includes a first portion and a third portion; the first portion is located between the surface of the gate near the first electrode and the first induction layer, and the third portion is located between the surface of the gate near the first electrode and the second electrode; the content of the metal element in the material of the first portion is greater than the content of the metal element in the material of the third portion.

19. A method for fabricating a semiconductor device, characterized in that, include: A first electrode and a first induction layer are provided, wherein the first induction layer is located on the first electrode; A first isolation film, a gate film, and a second isolation film are formed on the side of the first induction layer away from the first electrode; the gate film is located between the first isolation film and the second isolation film, and the second isolation film is located on the side of the first isolation film away from the first induction layer. A groove is formed to create a second isolation layer, a gate film, and a first isolation layer; the groove extends through the second isolation film, the gate film, and the first isolation film. A channel layer is formed within the groove; the channel layer is formed on the sidewall of the groove and on the surface of the first induction layer; The thickness of the portion of the channel layer formed on the surface of the first induction layer is greater than the thickness of the portion of the channel layer formed on the sidewall of the groove; A second electrode is formed, which is located on the side of the channel layer away from the first electrode.

20. The method for fabricating a semiconductor device according to claim 19, characterized in that, After creating the grooves and before forming the channel layer, the method further includes: A dielectric film is formed within the groove, the dielectric film being located on the sidewalls and bottom of the groove; The portion of the dielectric film located at the bottom of the tank is removed to expose the first induction layer, thereby forming a dielectric layer.

21. The method for fabricating a semiconductor device according to claim 19 or 20, characterized in that, After the channel layer is formed and before the second electrode is formed, the preparation method further includes: A second induction layer is formed on the side of the channel layer away from the first electrode; Forming the second electrode includes: forming the second electrode on the side of the second induction layer away from the first electrode.

22. The method for fabricating a semiconductor device according to claim 19 or 20, characterized in that, The formation of the channel layer includes: the channel layer comprising a first portion and a third portion; the first portion being formed on the surface of the first induction layer away from the first electrode, the second portion being formed on the side of the first portion away from the first induction layer; the third portion being formed on the side of the second portion away from the first portion, and the third portion forming a ring shape; After the channel layer is formed and before the second electrode is formed, the preparation method further includes: An insulating layer is formed within the third portion, wherein the surface of the insulating layer away from the first electrode is lower than the surface of the second insulating layer away from the first electrode; A second induction layer is formed on the side of the insulating layer away from the first electrode; the second induction layer also covers the sidewall of the groove; A second electrode is formed on the side of the second induction layer away from the first electrode.

23. An electronic device, characterized in that, Includes the semiconductor device and printed circuit board according to any one of claims 1-18; the semiconductor device and the printed circuit board are electrically connected.

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