Semiconductor device and manufacturing method therefor, power module, power conversion circuit, and vehicle

Abstract

A semiconductor device and a manufacturing method therefor, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises: a first semiconductor body (1), wherein a first region (14) is arranged on a first surface (101), a well region (15) is arranged on the side of the first region (14) distant from the first surface (101), and the first region (14) and the well region (15) have opposite conductivity types; a second semiconductor body (2) covering part of the first region (14) and part of the well region (15); a gate structure (3) located on the first surface (101) or extending from the first surface (101) into the first semiconductor body (1), the gate structure (3) comprising a gate oxide layer (30) and a gate (31), wherein the gate oxide layer (30) is located on the side of the second semiconductor body (2) distant from the first semiconductor body (1) and covers the side surface of the second semiconductor body (2), and the gate electrode (31) is located on the side of the gate oxide layer (30) distant from the second semiconductor body (2); a source (4) located on the first surface (101); and a drain (5) located on a second surface (102).

Description

Semiconductor devices and their fabrication methods, power modules, power conversion circuits, and vehicles

[0001] This application claims priority to Chinese Patent Application No. 202510458855.7, filed with the Chinese Patent Office on April 14, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, such as a semiconductor device and its fabrication method, a power module, a power conversion circuit, and a vehicle. Background Technology

[0003] Silicon carbide devices are constantly evolving towards smaller cell size, lower on-resistance, lower switching losses, and higher reliability. For example, silicon carbide metal-oxide field-effect transistors (MOSFETs) with planar gate structure have the advantages of simple process, good crystal orientation consistency of conduction channel, and relatively high avalanche energy, and have always been the mainstream.

[0004] The planar gate structure of silicon carbide metal-oxide field-effect transistors has a first region and a well region. Since the first region is a heavily doped region, the silicon carbide oxidation rate on the surface of the first region is fast during the gate oxidation process. The well region is a lightly doped region, and the silicon carbide oxidation rate on the surface of the well region is slow. This results in an inconsistency in the height of the surface of the first region and the surface of the well region, poor channel flatness, and affects the electrical performance of the silicon carbide MOSFET. Summary of the Invention

[0005] This application provides semiconductor devices and their fabrication methods, power modules, power conversion circuits, and vehicles to improve the flatness of the channel surface and enhance the conductivity of the semiconductor devices.

[0006] This application provides a semiconductor device, including:

[0007] A first semiconductor body includes a first surface and a second surface disposed opposite to each other. The first semiconductor body also includes a well region and a first region, the first region being disposed on the first surface and the well region being disposed on the side of the first region away from the first surface; the first region and the well region have opposite conductivity types; a second semiconductor body covers a portion of the first region and the well region.

[0008] A gate structure is located on or extends from a first surface into a first semiconductor body; the gate structure includes a gate oxide layer and a gate, the gate oxide layer is located on the side of the second semiconductor body away from the first semiconductor body and covers the side of the second semiconductor body, and the gate is located on the side of the gate oxide layer away from the second semiconductor body.

[0009] The source electrode is located on the first surface;

[0010] The drain electrode is located on the second surface.

[0011] Optionally, the second semiconductor body is located on the first surface;

[0012] The gate structure is located on the side of the second semiconductor body away from the first surface.

[0013] Optionally, a gate trench is provided on the first surface, and the gate trench extends from the first surface into the first semiconductor body;

[0014] The second semiconductor body is located on the sidewalls and bottom surface of the gate trench;

[0015] The gate structure is located in the gate trench, wherein the gate oxide layer is located on the side of the second semiconductor body away from the first semiconductor body and the bottom surface of the gate trench, and the gate is located on the side of the gate oxide layer away from the first semiconductor body in the gate trench.

[0016] Optionally, the first semiconductor body includes a silicon carbide semiconductor body, and the second semiconductor body includes a silicon carbide semiconductor body.

[0017] Optionally, the doping concentration of the second semiconductor body is lower than the doping concentration of the first region;

[0018] The doping type of the second semiconductor body is the same as that of the well region.

[0019] This application provides a method for fabricating a semiconductor device, including:

[0020] A first semiconductor body is provided; wherein the first semiconductor body includes a first surface and a second surface disposed opposite to each other, the first semiconductor body further includes a well region and a first region, the first region is disposed on the first surface, and the well region is disposed on the side of the first region away from the first surface; the first region and the well region have opposite conductivity types;

[0021] A second semiconductor body is formed, which covers a portion of the first region and the well region;

[0022] A gate structure is formed on a first surface, the gate structure being located on the first surface or extending from the first surface into the semiconductor body; the gate structure includes a gate oxide layer and a gate, the gate oxide layer being located on the side of the second semiconductor body away from the first semiconductor body and covering the side of the second semiconductor body, and the gate being located on the side of the gate oxide layer away from the second semiconductor body.

[0023] A source electrode is formed on one side of the first surface;

[0024] A drain electrode is formed on one side of the second surface.

[0025] Optionally, forming the second semiconductor body and forming the gate structure on the first surface includes: forming the second semiconductor body on the first surface, the second semiconductor body covering a portion of the first region and the well region;

[0026] A gate oxide layer is formed on the side of the second semiconductor body away from the first semiconductor body and on the side surface of the second semiconductor body;

[0027] A gate is formed on the side of the gate oxide layer away from the second semiconductor body.

[0028] Optionally, forming the second semiconductor body and forming the gate structure on the first surface includes:

[0029] A gate trench is formed on the first surface, and the gate trench extends from the first surface into the first semiconductor body;

[0030] A second semiconductor body is formed on the sidewall of the gate trench;

[0031] A gate oxide layer is formed on the side of the second semiconductor body away from the first semiconductor body and on the bottom surface of the gate trench.

[0032] A gate is formed on the side of the gate oxide layer in the gate trench away from the first semiconductor body.

[0033] Optionally, the first semiconductor body includes:

[0034] Provides silicon carbide semiconductor body;

[0035] Forming the second semiconductor body includes:

[0036] Forming the silicon carbide semiconductor body.

[0037] Optionally, forming the second semiconductor body includes:

[0038] A second semiconductor body is formed with a doping concentration lower than that of the first region and the same doping type as that of the well region.

[0039] This application provides a power module including a substrate and at least one semiconductor device as provided in this application, wherein the substrate is used to support the semiconductor device.

[0040] This application provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction.

[0041] The power conversion circuit includes a circuit board and at least one semiconductor device as provided in the embodiments of this application, the semiconductor device being electrically connected to the circuit board. Attached Figure Description

[0042] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0043] Figure 2 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application;

[0044] Figure 3 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0045] Figure 4 is a structural schematic diagram of step S110 in Figure 3;

[0046] Figure 5 is a schematic diagram of the structure of the well region formed on the first surface of the first semiconductor according to an embodiment of this application;

[0047] Figure 6 is a schematic diagram of the structure of the first region formed on the first surface of the first semiconductor according to an embodiment of this application;

[0048] Figure 7 is a schematic diagram of the structure of forming a third mask plate on the first region according to an embodiment of this application;

[0049] Figure 8 is a structural schematic diagram corresponding to step S120 in Figure 3;

[0050] Figure 9 is a schematic diagram of the structure for removing the third mask plate provided in an embodiment of this application;

[0051] Figure 10 is a schematic diagram of a structure in which a gate oxide layer is formed on the side of the first region away from the first surface, according to an embodiment of this application.

[0052] Figure 11 is a structural schematic diagram corresponding to step S130 in Figure 3;

[0053] Figure 12 is a schematic diagram of a structure in which an interlayer insulating layer is formed on the side of the gate away from the first surface, according to an embodiment of this application;

[0054] Figure 13 is a structural schematic diagram corresponding to step S140 in Figure 3;

[0055] Figure 14 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0056] Figure 15 is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application;

[0057] Figure 16 is a flowchart of another method for fabricating a semiconductor device provided in an embodiment of this application. Detailed Implementation

[0058] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort should fall within the scope of protection of this application.

[0059] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, any variations of the terms "comprising" and "having" are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0060] Figure 1 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application, and Figure 2 is a schematic diagram of the structure of another semiconductor device provided in an embodiment of this application. Figure 1 shows a planar gate structure of a semiconductor device, and Figure 2 shows a trench gate structure of a semiconductor device. Referring to Figures 1 and 2, the semiconductor device includes: a first semiconductor body 1, including a first surface 101 and a second surface 102 disposed opposite to each other. The first semiconductor body 1 also includes a well region 15 and a first region 14. The first region 14 is disposed on the first surface 101, and the well region 15 is disposed on the side of the first region 14 away from the first surface 101. The first region 14 and the well region 15 have opposite conductivity types; a second semiconductor body 2 covers a portion of the first region 14 and the well region 15; a gate structure 3 is located on or extends from the first surface 101 into the first semiconductor body 1; the gate structure 3 includes a gate oxide layer 30 and a gate 31, the gate oxide layer 30 is located on the side of the second semiconductor body 2 away from the first semiconductor body 1 and covers the side of the second semiconductor body 2, and the gate 31 is located on the side of the gate oxide layer 30 away from the second semiconductor body 2; a source 4 is located on the first surface 101; and a drain 5 is located on the second surface 102.

[0061] The first semiconductor body 1 includes a substrate 11 and an epitaxial layer 12. In some embodiments of this application, the first semiconductor body 1 may also include only the epitaxial layer 12. In other embodiments of this application, the first semiconductor body 1 may also include a substrate 11 and a semiconductor layer formed by other processes. The epitaxial layer 12 is a semiconductor layer formed on the substrate 11 by a single epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE). The second semiconductor body 2 includes an epitaxial layer, which is a semiconductor layer formed on the first semiconductor body 1 by a single epitaxial process.

[0062] In the embodiments of this application, the MOSFET semiconductor device includes an N-type MOSFET semiconductor device or a P-type MOSFET semiconductor device. Taking an N-type MOSFET semiconductor device as an example, the first semiconductor body 1 is an N-type semiconductor body, the first region 14 is an N+ doped region, the second region 13 is a P+ doped region, and the well region 15 is a P-well region. In other optional embodiments of this application, the first semiconductor body 1 further includes a second region 13, which is connected to the first region 14. The second region 13 and the well region 15 have the same conductivity type, the doping concentration of the second region 13 is greater than the doping concentration of the well region 15, and the second region 13 is located on the first surface 101, which can form a better ohmic contact with the first semiconductor body 1. Taking an N-type MOSFET semiconductor device as an example, the second region 13 includes a P+ doped region.

[0063] In other optional embodiments of this application, an interlayer insulating layer 32 is also provided to insulate the gate 31 and the source 4.

[0064] In Figure 1, the gate structure 3 is located on the first surface 101. The second semiconductor body 2 covers a portion of the first region 14 and the well region 15. The gate oxide layer 30 is located on the side of the second semiconductor body 2 away from the first semiconductor body 1 and covers the side surface of the second semiconductor body 2, improving the flatness of the planar channel on the surface of the well region 15. In Figure 2, the gate structure 3 extends from the first surface 101 into the first semiconductor body 1. The second semiconductor body 2 covers a portion of the first region 14 and the well region 15. The gate oxide layer 30 is located on the side of the second semiconductor body 2 away from the first semiconductor body 1 and covers the side surface of the second semiconductor body 2, improving the flatness of the vertical channel on the surface of the well region 15.

[0065] The semiconductor device provided in this application embodiment has a second semiconductor body 2 located on one side of the first surface 101 and covering the well region 15 and part of the first region 14, so that the well region 15 and part of the first region 14 are protected by the second semiconductor body 2. During the formation of the gate oxide layer 30, the silicon in the second semiconductor body 2 is consumed by the thermal oxidation process to form the gate oxide layer 30, without consuming the silicon in the first region 14 and the well region 15. This ensures that the silicon carbide oxidation rate on the surface of the first region 14 and the well region 15 is consistent, and avoids the inconsistency in height between the surface of the first region 14 and the surface of the well region 15 due to the different doping concentrations of the first region 14 and the well region 15. This improves the flatness of the channel on the surface of the well region 15, thereby reducing the on-resistance of the semiconductor device.

[0066] Referring to Figure 1, optionally, based on the above embodiment, the second semiconductor body 2 is located on the first surface 101; the gate structure 3 is located on the side of the second semiconductor body 2 away from the first surface 101.

[0067] In Figure 1, the gate structure 3 is located on the first surface 101, the second semiconductor body 2 covers part of the first region 14 and the well region 15, and the gate oxide layer 30 is located on the side of the second semiconductor body 2 away from the first semiconductor body 1 and covers the side of the second semiconductor body 2, which improves the flatness of the planar channel on the surface of the well region 15.

[0068] Referring to Figure 2, optionally, based on the above embodiment, a gate trench 19 is provided on the first surface 101, and the gate trench 19 extends from the first surface 101 into the first semiconductor body 1; the second semiconductor body 2 covers the first region 14 and the well region 15 located on the sidewall of the gate trench 19; the gate structure 3 is located in the gate trench 19, wherein the gate oxide layer 30 is located on the side of the second semiconductor body 2 in the gate trench 19 away from the first semiconductor body 1 and on the bottom surface of the gate trench 19, and the gate 31 is located on the side of the gate oxide layer 30 in the gate trench 19 away from the first semiconductor body 1.

[0069] In Figure 2, the gate structure 3 extends from the first surface 101 into the first semiconductor body 1. The second semiconductor body 2 covers the first region 14 and the well region 15 located on the sidewall of the gate trench 19. The gate oxide layer 30 is located on the side of the second semiconductor body 2 away from the first semiconductor body 1 and covers the side of the second semiconductor body 2, which improves the flatness of the vertical channel on the surface of the well region 15.

[0070] Referring to Figure 1 or Figure 2, optionally, based on the above embodiments, the first semiconductor body 1 includes a silicon carbide semiconductor body, and the second semiconductor body 2 includes a silicon carbide semiconductor body.

[0071] The first semiconductor body 1 includes a silicon carbide semiconductor body, and the second semiconductor body 2 includes a silicon carbide semiconductor body. The silicon carbide metal-oxide field-effect transistor semiconductor device formed by the silicon carbide semiconductor body has a wide bandgap, high critical breakdown field strength, high thermal conductivity and high carrier saturation velocity characteristics, and the silicon carbide metal-oxide field-effect transistor semiconductor device has high voltage withstand performance, low on-resistance and high stability.

[0072] Referring to Figure 1 or Figure 2, optionally, based on the above embodiments, the doping concentration of the second semiconductor body 2 is less than the doping concentration of the first region 14; the doping type of the second semiconductor body 2 is the same as the doping type of the well region 15.

[0073] In this embodiment of the application, by setting the doping concentration of the second semiconductor body 2 to be less than the doping concentration of the first region 14, the slow switching state transition of the semiconductor device due to the excessively high doping concentration of the second semiconductor body 2 is avoided, thereby improving the instantaneous switching response of the semiconductor device.

[0074] Figure 3 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application. Referring to Figure 3, the specific steps of the method for fabricating a semiconductor device according to an embodiment of this application are as follows:

[0075] S110, providing the first semiconductor body.

[0076] Referring to Figure 4, an epitaxial layer 12 is formed on the substrate 11 by an epitaxial process, the first surface 101 is patterned, and a second region 13 is formed on the first surface 101 by an ion implantation process. Referring to Figure 5, a first mask 16 is formed on the first surface 101 by a physical vapor deposition process or a chemical vapor deposition process, the first surface 101 is patterned, and a well region 15 is formed on the first surface 101 by an ion implantation process.

[0077] Referring to Figure 6, a second mask 17 is formed on both sides of the first mask 16 and on the side of the second region 13 away from the first surface 101 using physical vapor deposition or chemical vapor deposition. A first region 14 is formed on the side of the well region 15 near the first surface 101 using ion implantation. The first region 14 and the well region 15 have opposite conductivity types. The first mask 16 and the second mask 17 are removed using wet etching or etching processes, followed by high-temperature annealing. The high-temperature annealing is used to activate the implanted ions and repair the crystal lattice.

[0078] S120, forming the second semiconductor body.

[0079] The process by which the second semiconductor body 2 covers the first region 14 and the well region 15 is as follows:

[0080] Referring to Figure 7, a third mask 18 is formed on a portion of the first region 14 using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process. Referring to Figure 8, a second semiconductor body 2 is formed in the region of the third mask 18 that is not covered by the first surface 101 using an epitaxial process. Referring to Figure 9, the third mask 18 is removed using a wet etching or etching process.

[0081] S130, A gate structure is formed on the first surface.

[0082] Referring to Figure 10, a gate oxide layer 30 is formed on the side of the second semiconductor body 2 and the first region 14 away from the first surface 101 by a thermal oxidation process. Referring to Figure 11, a gate 31 is formed on the side of the gate oxide layer 30 away from the second semiconductor body 2 by a physical vapor deposition process or a chemical vapor deposition process, and the gate 31 is patterned. Referring to Figure 12, an interlayer insulating layer 32 is formed on the side of the gate 31 away from the first surface 101, wherein the interlayer insulating layer 32 covers the gate 31.

[0083] S140, a source electrode is formed on one side of the first surface.

[0084] Referring to Figure 12, a portion of the gate oxide layer 30 located in the first region 14 is etched by an etching process, and the source ohmic contact region is exposed on the first surface 101. Referring to Figure 13, the source 4 is formed on one side of the first surface 101 and on the side of the gate structure 3 away from the first surface 101 by a metal sputtering or metal stripping process.

[0085] S150, a drain electrode is formed on one side of the second surface.

[0086] Referring to Figure 1, the drain electrode 5 is formed on one side of the second surface 102 by a metal sputtering process.

[0087] In this embodiment, the second semiconductor body is located on the first surface, and the first semiconductor body covers a portion of the first region and the well region. During the oxidation process, the second semiconductor body is used to oxidize a portion of the second semiconductor body through a thermal oxidation process, while also forming a gate oxide layer on the side of the second semiconductor body away from the first surface. This eliminates the need to consume the first region and the well region, ensuring that the silicon carbide oxidation rate of the first region and the well region surfaces is consistent. It also avoids the inconsistency in height between the surface of the first region and the well region due to different doping concentrations, improving the flatness of the channel surface and enhancing the conductivity of the semiconductor device.

[0088] Optionally, based on the above embodiments, providing the first semiconductor body includes: providing a silicon carbide semiconductor body; forming the second semiconductor body includes: forming a silicon carbide semiconductor body.

[0089] Figure 14 is a flowchart of another semiconductor device fabrication method provided in this application embodiment. Based on the semiconductor device fabrication method shown in Figure 3, a second semiconductor body is formed on the first surface. As shown in Figure 14, the steps of this semiconductor device fabrication method are as follows:

[0090] S210, providing the first semiconductor body.

[0091] S220, A second semiconductor body is formed on the first surface.

[0092] S230, a gate oxide layer is formed on the side of the second semiconductor body away from the first semiconductor body and on the side surface of the second semiconductor body.

[0093] S240, A gate is formed on the side of the gate oxide layer away from the second semiconductor body.

[0094] S250, a source electrode is formed on one side of the first surface.

[0095] S260, a drain electrode is formed on one side of the second surface.

[0096] The preparation process and effects of S210-S260 are the same as those of S110-S150, and will not be repeated here.

[0097] Figure 15 is a flowchart of another semiconductor device fabrication method provided in this application embodiment. Based on the semiconductor device fabrication method shown in Figure 14, a second semiconductor body is formed on the first surface and the sidewalls and bottom of the gate trench. As shown in Figure 15, the steps of this semiconductor device fabrication method are as follows:

[0098] S310 provides the first semiconductor body.

[0099] The preparation process and effects of S310 are the same as those of S210, and will not be repeated here.

[0100] S320, forming a gate trench on the first surface.

[0101] Referring to Figure 2, a gate trench 19 is formed on the first surface 101 by an etching process, and the gate trench 19 extends from the first surface 101 into the first semiconductor body 1.

[0102] S330, A second semiconductor body is formed on the sidewalls and bottom of the gate trench.

[0103] Referring to Figure 2, a third mask is formed on a portion of the first region 14 by physical vapor deposition or chemical vapor deposition. A second semiconductor body 2 is formed in the gate trench 19 and in the region where the third mask does not cover the first surface 101. The third mask is removed by wet etching or etching process.

[0104] S340, A gate oxide layer is formed on the side of the second semiconductor body away from the first semiconductor body and on the bottom surface of the gate trench.

[0105] Referring to Figure 2, a gate oxide layer 30 is formed in the gate trench 19 and on the side of the first region 14 away from the substrate 11 by a thermal oxidation process.

[0106] S350, A gate is formed on the side of the gate oxide layer in the gate trench away from the first semiconductor body.

[0107] Referring to Figure 2, a gate 31 is formed on the side of the gate oxide layer 30 in the gate trench 19 away from the first semiconductor body 1. The gate 31 may be a polysilicon gate.

[0108] S360, a source electrode is formed on one side of the first surface.

[0109] S370, a drain electrode is formed on one side of the second surface.

[0110] The preparation process and effects of S360-S370 are the same as those of S250-S260, and will not be repeated here.

[0111] Figure 16 is a flowchart of a semiconductor device fabrication method provided in an embodiment of this application. Based on the semiconductor device fabrication method shown in Figure 14, a second semiconductor body is formed with a doping concentration lower than that of the first region and the same doping type as that of the well region. As shown in Figure 16, the steps of the semiconductor device fabrication method are as follows:

[0112] S210, providing the first semiconductor body.

[0113] S2101, forming a second semiconductor body with a doping concentration less than that of the first region and the same doping type as that of the well region.

[0114] S130, A gate structure is formed on the first surface.

[0115] S140, a source electrode is formed on one side of the first surface.

[0116] S150, a drain electrode is formed on one side of the second surface.

[0117] The semiconductor device fabrication method of this application embodiment belongs to the same inventive concept as the semiconductor device provided in any embodiment of this application. For technical details not detailed in this embodiment, please refer to the semiconductor device provided in any embodiment of this application.

[0118] This application provides a power module including a substrate and at least one semiconductor device as described in any embodiment of this application, wherein the substrate is used to support the semiconductor device. Therefore, this power module includes the functions of the semiconductor device as described in any embodiment of this application, which will not be elaborated further here.

[0119] This application provides a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction. The power conversion circuit includes a circuit board and at least one semiconductor device as described in any embodiment of this application, and the semiconductor device is electrically connected to the circuit board.

[0120] Therefore, this power conversion circuit includes the functions of any semiconductor device described in any embodiment of this application, and will not be repeated here.

[0121] This application also provides a vehicle, including a load and any power conversion circuit as described in any embodiment of this application. The power conversion circuit is used to convert AC and / or DC power into AC and / or DC power and then input it to the load.

[0122] Therefore, the vehicle includes the power conversion circuit of any embodiment of this application, and thus the vehicle includes the function of the power conversion circuit described in any embodiment of this application, which will not be repeated here.

[0123] It should be understood that the various processes shown above can be used to rearrange, add, or delete steps. For example, the multiple steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

Claims

1. A semiconductor device, comprising: A first semiconductor body includes a first surface and a second surface disposed opposite to each other. The first semiconductor body also includes a well region and a first region. The first region is disposed on the first surface, and the well region is disposed on the side of the first region away from the first surface. The first region and the well region have opposite conductivity types. A second semiconductor body, the second semiconductor body covering a portion of the first region and the well region; A gate structure is located on or extends from the first surface into the first semiconductor body; the gate structure includes a gate oxide layer and a gate, the gate oxide layer is located on the side of the second semiconductor body away from the first semiconductor body and covers the side of the second semiconductor body, and the gate is located on the side of the gate oxide layer away from the second semiconductor body; The source electrode is located on the first surface; The drain electrode is located on the second surface.

2. The semiconductor device of claim 1, wherein, The second semiconductor body is located on the first surface; The gate structure is located on the side of the second semiconductor body away from the first surface.

3. The semiconductor device of claim 1, wherein, The first surface is provided with a gate trench, which extends from the first surface into the first semiconductor body; The second semiconductor body covers the first region located on the sidewall of the gate trench and the well region; The gate structure is located within the gate trench, wherein the gate oxide layer is located on the side of the second semiconductor body away from the first semiconductor body and the bottom surface of the gate trench within the gate trench, and the gate is located on the side of the gate oxide layer away from the first semiconductor body within the gate trench.

4. The semiconductor device of claim 1, wherein, The first semiconductor body includes a silicon carbide semiconductor body, and the second semiconductor body includes a silicon carbide semiconductor body.

5. The semiconductor device of claim 1, wherein, The doping concentration of the second semiconductor body is lower than that of the first region; The doping type of the second semiconductor body is the same as the doping type of the well region.

6. A method for fabricating a semiconductor device, comprising: A first semiconductor body is provided; wherein the first semiconductor body includes a first surface and a second surface disposed opposite to each other, the first semiconductor body further includes a well region and a first region, the first region is disposed on the first surface, and the well region is disposed on the side of the first region away from the first surface; the first region and the well region have opposite conductivity types; A second semiconductor body is formed, the second semiconductor body covering a portion of the first region and the well region; A gate structure is formed on the first surface, the gate structure being located on or extending from the first surface into the semiconductor body; the gate structure includes a gate oxide layer and a gate, the gate oxide layer being located on the side of the second semiconductor body away from the first semiconductor body and covering the side of the second semiconductor body, and the gate being located on the side of the gate oxide layer away from the second semiconductor body; A source electrode is formed on one side of the first surface; A drain electrode is formed on one side of the second surface.

7. The method of producing a semiconductor device according to claim 6, wherein Forming a second semiconductor body and forming a gate structure on the first surface includes: forming a second semiconductor body on the first surface, the second semiconductor body covering a portion of the first region and the well region; A gate oxide layer is formed on the side of the second semiconductor body away from the first semiconductor body and on the side surface of the second semiconductor body; A gate is formed on the side of the gate oxide layer away from the second semiconductor body.

8. The method of producing a semiconductor device according to Claim 6, wherein Forming the second semiconductor body and forming the gate structure on the first surface includes: A gate trench is formed on the first surface, the gate trench extending from the first surface into the first semiconductor body; A second semiconductor body is formed on the sidewall of the gate trench, the second semiconductor body covering the first region and the well region located on the sidewall of the gate trench; A gate oxide layer is formed on the side of the second semiconductor body away from the first semiconductor body within the gate trench and on the bottom surface of the gate trench; A gate is formed on the side of the gate oxide layer in the gate trench away from the first semiconductor body.

9. The method of producing a semiconductor device according to Claim 6, wherein The first semiconductor body includes: Provides silicon carbide semiconductor body; Forming the second semiconductor body includes: Forming the silicon carbide semiconductor body.

10. The method of producing a semiconductor device according to Claim 6, wherein Forming the second semiconductor body includes: A second semiconductor body is formed with a doping concentration lower than that of the first region and the same doping type as that of the well region.

11. A power module comprising a substrate and a semiconductor device as claimed in any one of claims 1-5, wherein the substrate is used to support the semiconductor device.

12. A power conversion circuit, The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as described in any one of claims 1-5, wherein the semiconductor device is electrically connected to the circuit board.

13. A vehicle comprising a load and a power conversion circuit as claimed in claim 12, the power conversion circuit being configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input the converted direct current to the load.

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