Packaging module

Abstract

A packaging module, relating to the technical field of chip packaging, comprising: a substrate having a first surface and a second surface opposite to each other, wherein the substrate is provided with chip through-slots arranged in an array, and functional chips are arranged in the chip through-slots; a first wiring layer that is arranged on a first surface and comprises at least one layer of first metal wirings, a first target metal wiring among the first metal wirings being electrically connected to the functional chips, wherein the first target metal wiring is the first metal wiring closest to pins of the functional chips; a second wiring layer that is arranged on a second surface and comprises at least one layer of second metal wirings, a second target metal wiring among the second metal wirings being electrically connected to the functional chips, wherein the second target metal wiring is the second metal wiring closest to the pins of the functional chips; and at least one functional device arranged in the first wiring layer and electrically connected to the first metal wirings, and / or arranged in the second wiring layer and electrically connected to the second metal wirings. The present application has the beneficial effects of significantly improving the integration level of the packaging module and effectively reducing the packaging size of the packaging module, thereby meeting the miniaturization requirements of devices such as communication terminals.

Description

A packaging module Technical Field

[0001] This application relates to the field of chip packaging technology, and in particular to a packaging module. Background Technology

[0002] The development of multi-mode wireless communication has facilitated the functional expansion of communication terminals. More and more functional components are being integrated into a single package module, forming communication terminals that support multi-mode wireless communication to provide communication services to users. In RF front-end architecture, different functional components typically employ different substrates and packaging processes, making it difficult to integrate these components into a single chip. Therefore, conventional packaging modules often use multi-chip packaging to implement their respective communication functions. However, with the evolution of communication terminals towards smaller sizes, multi-chip packaging has led to a significant increase in the size of the packaging module, making it difficult for the module to meet increasingly stringent size requirements. Therefore, there is an urgent need to propose a miniaturized packaging method for high-density multi-chip packaging to meet the miniaturization requirements of the packaging module. Summary of the Invention

[0003] This application provides a packaging module that embeds functional chips in chip slots of a substrate and forms electronic devices on the substrate surface using metal wiring and functional components. This significantly improves the integration of the packaging module and effectively reduces the packaging size of the packaging module, thereby meeting the miniaturization requirements of communication terminals and other devices.

[0004] To achieve the above objectives, the main technical solutions adopted in this application include:

[0005] This application provides a packaging module, including:

[0006] A substrate having opposing first and second surfaces, wherein chip slots are arranged in an array and functional chips are disposed within the chip slots;

[0007] A first wiring layer is disposed on the first surface, and the first wiring layer includes at least one first metal wiring layer. A first target metal wiring layer in the at least one first metal wiring layer is electrically connected to the functional chip. The first target metal wiring layer is the first metal wiring layer closest to the pin of the functional chip.

[0008] A second wiring layer is disposed on the second surface. The second wiring layer includes at least one layer of second metal wiring. A second target metal wiring in the at least one layer of second metal wiring is electrically connected to the functional chip. The second target metal wiring is the second metal wiring closest to the pin of the functional chip.

[0009] At least one functional device, wherein the functional device is disposed within the first wiring layer and electrically connected to the first metal wiring; and / or the functional device is disposed within the second wiring layer and electrically connected to the second metal wiring.

[0010] The packaging module proposed in this application has chip slots in the substrate for embedding functional chips, allowing the functional chips to be hidden within the substrate without occupying additional packaging module height, thus effectively reducing the packaging thickness of the packaging module. This application also forms metal wiring on the substrate surface to connect functional devices and functional chips, thereby forming electronic devices with corresponding functions on the substrate surface. This reduces the processing steps for mounting electronic devices, improves the integration of the packaging module, and further reduces the size of the packaging module. Compared with related technologies, this application achieves the integration of multiple chips and multifunctional devices through the arrayed chip slots in the substrate and multiple wiring layers on the substrate surface, improving the integration of the packaging module. Therefore, based on high-density integration, it effectively reduces the packaging size of the packaging module, thereby meeting the thinner and lighter application requirements of communication terminals and other devices.

[0011] Optionally, the number of layers of the at least one first metal wiring is two or more, and the first metal wirings of different layers are electrically connected by interconnect wiring.

[0012] Optionally, the number of layers of the at least one layer of second metal wiring is two or more, and the second metal wirings of different layers are electrically connected by interconnecting wiring.

[0013] Optionally, the substrate is provided with wiring vias, through which the first metal wiring and the second metal wiring are electrically connected.

[0014] Optionally, the packaging module further includes an external interface, which is located on the side of the first wiring layer or the second wiring layer away from the substrate, and is electrically connected to the wiring layer that is closest to the first wiring layer or the second wiring layer.

[0015] Optionally, the packaging module further includes a protective layer, which is disposed on the side of the first wiring layer or the second wiring layer away from the substrate, and the protective layer and the external interface are respectively disposed on both sides relative to the substrate.

[0016] Optionally, the thickness of the packaging module is the sum of the thicknesses of the substrate, the first wiring layer, the second wiring layer, and the protective layer.

[0017] Optionally, the thickness of the substrate is matched with the height of the functional chip.

[0018] Optionally, the functional chip includes a first chip with pins facing the first wiring layer and the first chip being electrically connected to the first target metal wiring.

[0019] Optionally, the functional chip includes a second chip with pins facing the second wiring layer, and the second chip is electrically connected to the second target metal wiring. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1a is a schematic diagram of the module structure of conventional packaging technology in an embodiment of this application;

[0022] Figure 1b is a schematic diagram of the module structure of the conventional packaging technology in the embodiments of this application;

[0023] Figure 2 is a schematic diagram of the packaging module provided in an embodiment of this application;

[0024] Figure 3 is a schematic diagram of the arrangement of chip through-slots on the substrate surface in an embodiment of this application;

[0025] Figure 4 is a schematic diagram of the wiring structure of the first wiring layer in an embodiment of this application;

[0026] Figure 5 is a schematic diagram of the wiring structure of the second wiring layer in an embodiment of this application;

[0027] Figure 6 is a schematic diagram of the indirect connection between the first chip and the functional devices in the second wiring layer in an embodiment of this application;

[0028] Figure 7 is a schematic diagram of the indirect connection between the second chip and the functional devices in the first wiring layer in an embodiment of this application.

[0029] The reference numerals in the accompanying drawings are as follows: 100. Substrate, 110. Chip through-hole, 120. Functional chip, 121. First chip, 122. Second chip, 130. Wiring via, 200. First wiring layer, 210. First metal wiring, 211. First target metal wiring, 220. Interconnect wiring, 300. Second wiring layer, 310. Second metal wiring, 311. Second target metal wiring, 320. Interconnect wiring, 400. Functional device, 500. External interface, 510. Solder mask layer, 600. Protective layer, 101. First surface, 102. Second surface. Detailed Implementation

[0030] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0032] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, doping type, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0033] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0035] The development of multi-mode wireless communication has promoted the functional expansion of communication terminals. More and more functional devices are being integrated into a single package module to form communication terminals that support multi-mode wireless communication and provide communication services to users. In the RF front-end architecture, devices with different functions usually use different substrates and packaging processes, making it difficult to integrate these devices into a single chip. Therefore, conventional packaging modules often adopt a multi-chip packaging approach to implement their respective communication functions.

[0036] However, with the evolution of communication terminals towards smaller sizes, multi-chip packaging methods have led to a significant increase in the size of packaging modules, making it difficult for them to meet increasingly stringent size requirements. Referring to Figures 1a and 1b, traditional multi-chip miniaturization packaging technologies typically utilize chip stacking packaging or double-sided substrate packaging.

[0037] The chip stacking packaging method is shown in Figure 1a, which uses four chips as an example, each with different functions. During the packaging process, chips 2 and 4 are first mounted on the substrate surface according to the chip layout design. Then, chips 1 and 2 are interconnected using bump solder joints or TSV transfer boards, and chips 3 and 4 are interconnected, thus completing the packaging. This method, by vertically stacking the chips, greatly saves space on the substrate surface. It also shortens the communication distance between chips by using bump solder joints or TSV transfer boards to interconnect them. However, it is clear from Figure 1a that as the number of chips increases, the overall thickness of the packaged module obtained by this method increases significantly, affecting its application in scenarios with strict requirements for package size.

[0038] The double-sided packaging method is shown in Figure 1b, which also uses four chips as an example, each with different functions. During the packaging process, according to the pre-designed chip layout, chips 1 and 2 are mounted on the surface of the substrate away from the solder balls, while chips 3 and 4 are mounted on the surface of the substrate closer to the solder balls. The chips are interconnected through vias in the substrate, thus completing the packaging. This method mounts the chips on different surfaces of the substrate, maximizing the use of the substrate surface space and reducing the thickness of the packaging module. However, when there are a large number of chips, this method still faces limitations due to the substrate surface space, and the height of the chips themselves also increases the thickness of the packaging module, failing to effectively reduce the package size.

[0039] To address the aforementioned issues, this application provides a packaging module comprising: a substrate having opposing first and second surfaces, wherein an array of chip slots are arranged in the substrate, and a functional chip is disposed within the chip slots; a first wiring layer disposed on the first surface, including at least one first metal wiring layer, wherein the first target metal wiring is electrically connected to the functional chip; a second wiring layer disposed on the second surface, including at least one second metal wiring layer, wherein the second target metal wiring is electrically connected to the functional chip; at least one functional device disposed within the first wiring layer and electrically connected to the first metal wiring; and / or disposed within the second wiring layer and electrically connected to the second metal wiring.

[0040] The packaging module provided in this application has a chip through-slot in the substrate for embedding functional chips, allowing the functional chips to be hidden in the substrate without occupying additional packaging module height, thus effectively reducing the packaging thickness of the packaging module. This application also forms metal wiring on the substrate surface, using the metal wiring to connect functional devices and functional chips, thereby forming electronic devices with corresponding functions on the substrate surface, improving the integration of the packaging module, and further reducing the size of the packaging module.

[0041] Compared with related technologies, this application achieves the integration of multiple chips and multifunctional devices through the chip through slots arranged in an array in the substrate and multiple wiring layers on the substrate surface, thereby improving the integration of the packaging module. On the basis of high-density integration, the packaging size of the packaging module is effectively reduced, thus meeting the application requirements of thin and light communication terminals and other devices.

[0042] The packaging module provided in this specification can be applied to terminal devices with miniaturization requirements, including but not limited to laptops, desktop computers, smartphones, smart wearable devices (virtual reality glasses, smartwatches, etc.), and tablet computers. It is understood that, with adaptive modifications, this application can also be used in fields requiring high space utilization of the packaging module, such as data center servers and edge computing devices.

[0043] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0044] This embodiment provides a packaging module that can be used in the aforementioned terminal devices with miniaturization requirements. Referring to FIG2, the packaging module includes a substrate, a first wiring layer, a second wiring layer, and at least one functional device. The substrate has opposing first and second surfaces, and an array of chip slots are provided in the substrate, with functional chips disposed within the chip slots. The first wiring layer is disposed on the first surface and includes at least one layer of first metal wiring, with a first target metal wiring in the at least one layer of first metal wiring electrically connected to the functional chip; wherein the first target metal wiring is the first metal wiring closest to the pin of the functional chip. The second wiring layer is disposed on the second surface and includes at least one layer of second metal wiring, with a second target metal wiring in the at least one layer of second metal wiring electrically connected to the functional chip; wherein the second target metal wiring is the second metal wiring closest to the pin of the functional chip. The functional device is disposed within the first wiring layer and electrically connected to the first metal wiring; and / or the functional device is disposed within the second wiring layer and electrically connected to the second metal wiring.

[0045] Specifically, the packaging module includes a substrate 100, a first wiring layer 200, a second wiring layer 300, and at least one functional device 400. The substrate 100 supports the functional chip 120, providing physical support for it using its own structure. The substrate 100 can be made of materials such as glass, quartz, or ceramic. The substrate 100 has multiple chip slots 110 for mounting the functional chip 120. The depth direction of the chip slots 110 is aligned with the thickness direction of the substrate 100, and the opening size of the chip slots 110 matches the size of the functional chip 120. The chip slots 110 can be processed by grinding or polishing, and their dimensional accuracy can be controlled within ±5μm.

[0046] Furthermore, the functional chip 120 is fixed in the chip slot 110. The position of the functional chip 120 in the thickness direction of the substrate 100 does not exceed the first surface 101 and the second surface 102, so that the functional chip 120 can be completely hidden in the substrate 100. The functional chip 120 can be fixed by conductive silver paste or thermally conductive adhesive, etc., to ensure that the functional chip 120 will not move in the packaging module and to ensure that the functional chip 120 is in the correct position. It should be noted that compared with the method of setting the functional chip 120 using a groove, setting the chip slot 110 can effectively eliminate the influence of blind slot depth error on the packaging module. When there is an error in the blind slot depth, the inconsistency of the groove depth will lead to inconsistent height of the functional chip 120, which will cause the electrical connection between the functional chip 120 and the first metal wiring 210 or the second metal wiring 310 to fail, affecting the operation of the packaging module. It is understandable that when the functional chip 120 is disposed in the chip through slot 110, the chip through slot 110 is also filled with an insulating medium, so that the functional chip 120 is electrically connected to the first wiring layer 200 or the second wiring layer 300 only through the pins, thereby reducing the probability of electrical connection errors of the functional chip 120.

[0047] Referring to Figure 3, taking an example with six chip slots 110, the chip slots 110 in the substrate 100 are arranged in an array, thereby maximizing the use of the space on the surface of the substrate 100 and realizing the integration of multiple chips in the substrate 100. In other embodiments, the arrangement of the chip slots 110 can also be other forms. The spacing between the chip slots 110 can be determined according to the actual needs of the scenario. For example, when there are many functional chips 120, the distance between the chip slots 110 can be appropriately reduced to increase the number of chip slots 110, thereby accommodating more functional chips 120 in the packaging module; or, for example, when there are high requirements for the overall yield of the packaging module processing, the distance between the chip slots 110 can be appropriately increased to improve the mechanical strength of the substrate 100, thereby improving the mechanical strength of the packaging module, reducing the breakage rate and warpage rate during the packaging module processing, and improving the overall yield.

[0048] Furthermore, the packaging module has wiring layers on different surfaces of the substrate 100, including a first wiring layer 200 and a second wiring layer 300. The first wiring layer 200 is disposed on the first surface 101 of the substrate 100, and the second wiring layer 300 is disposed on the second surface 102 of the substrate 100. The first surface 101 and the second surface 102 are two opposite surfaces on the substrate 100. The first wiring layer 200 includes at least one first metal wiring 210, which is formed using a rewiring layer technique. The layers of the first metal wiring 210 can be distributed along the thickness direction of the first wiring layer 200. For any functional chip 120, the metal wiring in the first metal wiring 210 that is closest to the pin of the functional chip 120 is designated as the first target metal wiring 211. The functional chip 120 is electrically connected to the first target metal wiring 211 through its pin, thereby achieving an electrical connection between the functional chip 120 and the first wiring layer 200.

[0049] Similarly, the second wiring layer 300 includes at least one layer of second metal wiring 310, which is formed using a rewiring layer technique. The layers of the second metal wiring 310 can be distributed along the thickness direction of the second wiring layer 300. For any functional chip 120, the metal wiring in the second metal wiring 310 that is closest to a pin of that functional chip 120 is designated as the second target metal wiring 311. The functional chip 120 is electrically connected to the second target metal wiring 311 through its pins, thereby achieving an electrical connection between the functional chip 120 and the second wiring layer 300.

[0050] Furthermore, the packaging module includes at least one functional device 400. The functional device 400 can be a resistor or a metal-insulator-metal capacitor (MIM capacitor), etc. The functional device 400 can be disposed within the first wiring layer 200 or the second wiring layer 300. When the functional device 400 is disposed within the first wiring layer 200, it is electrically connected to the first metal wiring 210; when the functional device 400 is disposed within the second wiring layer 300, it is electrically connected to the second metal wiring 310. It should be noted that the electrical connection between the functional device 400 and the first metal wiring 210 or the second metal wiring 310 can form electronic devices with corresponding functions on the surface of the substrate 100, such as passive devices like resistor-capacitor-inductor devices or electrical filters, thereby improving the integration of the packaging module and further reducing its size. Among them, electrical filters are mainly in contrast to acoustic filters (such as SAW / BAW). They are usually formed by capacitors, inductors, dielectrics, cavities, etc., such as IPD filters or ceramic filters.

[0051] It is understandable that when the functional chip 120 is electrically connected to the first metal wiring 210 or the second metal wiring 310, the functional device 400 can also be electrically connected to the functional chip 120 through the first metal wiring 210 or the second metal wiring 310, thereby forming an electronic system capable of performing complex functions.

[0052] The packaging module provided in this embodiment has a chip through-slot in the substrate for embedding the functional chip, allowing the functional chip to be hidden in the substrate without occupying additional packaging module height, thus effectively reducing the packaging thickness of the packaging module. This application also forms metal wiring on the substrate surface, using the metal wiring to connect the functional device and the functional chip, thereby forming an electronic device with corresponding functions on the substrate surface. This reduces the processing steps for mounting the electronic device, improves the integration of the packaging module, and further reduces the size of the packaging module.

[0053] Compared with related technologies, this application achieves the integration of multiple chips and multifunctional devices through the chip through slots arranged in an array in the substrate and multiple wiring layers on the substrate surface, thereby improving the integration of the packaging module. On the basis of high-density integration, the packaging size of the packaging module is effectively reduced, thus meeting the application requirements of thin and light communication terminals and other devices.

[0054] As one embodiment of this application, the number of layers of the first metal wiring is two or more, and the first metal wirings of different layers are electrically connected by interconnect wiring.

[0055] Specifically, when it is necessary to form an electronic device with complex functions on the surface of the substrate 100, the first wiring layer 200 may be provided with more than one layer of multilayer first metal wiring 210, and the different layers of the first metal wiring 210 are distributed along the thickness direction of the first wiring layer 200.

[0056] Referring to Figure 4, the first wiring layer 200 is further filled with an insulating medium. This insulating medium fills the spaces between the first metal wirings 210, isolating the first metal wirings 210 at different levels and between different first metal wirings 210 at the same level, thus reducing the possibility of short circuits or mutual interference between the first metal wirings 210. It should be noted that vias are provided in the insulating medium filling the spaces between the first metal wirings 210 at different levels. Interconnecting wirings 220 are provided in these vias. These interconnecting wirings 220 can be made of metal and are used to achieve electrical connections between the first metal wirings 210 at different levels along the thickness direction of the first wiring layer 200.

[0057] Furthermore, when it is necessary to form electronic devices within the first wiring layer 200, one or more functional devices 400 may be disposed in the first wiring layer 200 and connected to any of the first metal wirings 210 in the first wiring layer 200. It is understood that the position of the functional device 400 may be determined according to the layout design of the package module.

[0058] As one embodiment of this application, the number of layers of at least one layer of second metal wiring is two or more, and the second metal wirings of different layers are electrically connected by interconnect wiring.

[0059] Specifically, when it is necessary to form an electronic device with complex functions on the surface of the substrate 100, the second wiring layer 300 may be provided with more than one layer of multilayer second metal wiring 310, and the different layers of the second metal wiring 310 are distributed along the thickness direction of the second wiring layer 300.

[0060] Referring to Figure 5, the second wiring layer 300 is further filled with an insulating medium. This insulating medium fills the spaces between the second metal wirings 310, isolating the second metal wirings 310 at different levels and between different second metal wirings 310 at the same level, thus reducing the possibility of short circuits or mutual interference between the second metal wirings 310. It should be noted that vias are provided in the insulating medium filling the spaces between the second metal wirings 310 at different levels. Interconnecting wirings 320 are provided in these vias. These interconnecting wirings 320 can be made of metal and are used to achieve electrical connections between the second metal wirings 310 at different levels along the thickness direction of the second wiring layer 300.

[0061] Furthermore, when electronic devices need to be formed within the second wiring layer 300, one or more functional devices 400 may be disposed in the second wiring layer 300 and connected to any of the second metal wirings 310 in the second wiring layer 300. It is understood that the position of the functional device 400 may be determined according to the layout design of the package module.

[0062] As one embodiment of this application, the substrate is provided with wiring vias, and the first metal wiring and the second metal wiring are electrically connected through the wiring vias.

[0063] Specifically, the wiring vias 130 in the substrate 100 are filled with conductive material to achieve electrical connections between the wiring layers on both sides of the substrate 100. For example, when the substrate 100 is made of glass, the wiring vias 130 in the glass substrate can be obtained using through-glass via (TGV) technology. It is understood that when any functional chip 120 is electrically connected to the first wiring layer 200, and another functional chip 120 is electrically connected to the second wiring layer 300, the wiring vias 130 can also be used to achieve electrical connections between the functional chip 120 and the other functional chip 120, improving the flexibility of electrical connections in the packaging module.

[0064] As one embodiment of this application, the packaging module further includes an external interface, which is located on the side of the first wiring layer or the second wiring layer away from the substrate, and is electrically connected to the wiring layer that is closest to the first wiring layer or the second wiring layer.

[0065] Specifically, the external interface 500 can take the form of I / O pads or balls, used to connect the package module to the outside world for integration into the terminal device. The external interface 500 can be located on the side of the first wiring layer 200 away from the substrate 100 and electrically connected to the first metal wiring 210 in the first wiring layer 200 for electrical connection to electronic devices formed in the package module. Similarly, the external interface 500 can also be located on the side of the second wiring layer 300 away from the substrate 100 and electrically connected to the second metal wiring 310 in the second wiring layer 300 for electrical connection to electronic devices formed in the package module.

[0066] Furthermore, a solder resist layer 510 is provided on the surface with the external interface 500. The solder resist layer 510 is used to protect the packaging module and reduce the impact of the soldering process on the packaging module when the packaging module is connected to the external device by soldering, thereby improving the reliability of the packaging module.

[0067] As one embodiment of this application, the packaging module further includes a protective layer, which is disposed on the side of the first wiring layer or the second wiring layer away from the substrate, and the protective layer and the external interface are respectively disposed on both sides relative to the substrate.

[0068] Specifically, the protective layer 600 in the packaging module is disposed on the side of the first wiring layer 200 or the second wiring layer 300 away from the substrate 100, and the protective layer 600 and the external interface 500 are respectively located on opposite sides of the substrate 100. That is, when the external interface 500 is disposed on the side of the first wiring layer 200 away from the substrate 100, the protective layer 600 is disposed on the side of the second wiring layer 300 away from the substrate 100, or when the external interface 500 is disposed on the side of the second wiring layer 300 away from the substrate 100, the protective layer 600 is disposed on the side of the first wiring layer 200 away from the substrate 100. The protective layer 600 is used to protect the packaging module and reduce the interference of the external environment on the structure or operation of the packaging module. By setting the protective layer 600, the packaging steps in the packaging module production process can be reduced, significantly reducing the production cost of the packaging module.

[0069] As one embodiment of this application, the thickness of the packaging module is the sum of the thicknesses of the substrate, the first wiring layer, the second wiring layer, and the protective layer.

[0070] Referring to Figure 2, the functional chip 120 is fixed in the chip slot 110, and the position of the functional chip 120 in the thickness direction of the substrate 100 does not exceed the first surface 101 and the second surface 102, so that the functional chip 120 is completely hidden in the substrate 100. Furthermore, the functional device 400 is disposed within the first wiring layer 200 or the second wiring layer 300, and the functional device 400 does not occupy additional height in the packaging module, effectively reducing the thickness of the packaging module. It can be understood that the thickness of the packaging module is the sum of the thicknesses of the substrate 100, the first wiring layer 200, the second wiring layer 300, and the protective layer 600, and is not affected by the number or thickness of the functional chip 120 or the functional device 400, effectively ensuring the miniaturization and thinning of the packaging module.

[0071] As one embodiment of this application, the thickness of the substrate is matched with the height of the functional chip.

[0072] Specifically, the functional chip 120 in the chip slot 110 is positioned no more than the first surface 101 and the second surface 102 in the thickness direction of the substrate 100, so that the functional chip 120 is completely hidden in the substrate 100. Therefore, the height of the functional chip 120 can be less than the thickness of the substrate 100. In order to maximize the utilization of the space in the thickness direction of the substrate 100, the thickness of the substrate 100 can be matched with the height of the functional chip 120, so that the functional chip 120 makes full use of the space in the chip slot 110, thereby improving the space utilization rate of the substrate 100.

[0073] The thickness of the substrate 100 can be matched with the height of the functional chip 120, meaning the height of the functional chip 120 is slightly less than the thickness of the substrate 100. In practical applications, thermally conductive adhesive is typically used to fix the functional chip 120 along its height. To completely conceal the functional chip 120 within the substrate 100, the thickness of the thermally conductive adhesive needs to be considered. This thickness can be determined based on the specific material and is not an absolute value.

[0074] As one embodiment of this application, the functional chip includes a first chip with pins facing a first wiring layer and the first chip being electrically connected to a first target metal wiring.

[0075] Specifically, the functional chip 120 disposed in the chip through slot 110 can be electrically connected to the first wiring layer 200 or the second wiring layer 300 respectively. When the functional chip 120 is electrically connected to the first wiring layer 200, it is used as the first chip 121, with its pins facing the first wiring layer 200, and electrically connected to the first target metal wiring 211 in the first wiring layer 200 through the pins.

[0076] Referring to Figure 6, for the first chip 121, when the functional device 400 is disposed in the second wiring layer 300, the first chip 121 can also be connected to the functional device 400 through the first target metal wiring 211, the wiring via 130 and the second metal wiring 310, thereby improving the flexibility of electrical connections in the packaging module.

[0077] As one embodiment of this application, the functional chip includes a second chip with pins facing a second wiring layer and the second chip being electrically connected to a second target metal wiring layer.

[0078] Specifically, the functional chip 120 disposed in the chip through slot 110 can be electrically connected to the first wiring layer 200 or the second wiring layer 300 respectively. When the functional chip 120 is electrically connected to the second wiring layer 300, it is used as the second chip 122, with its pins facing the second wiring layer 300, and electrically connected to the second target metal wiring 311 in the second wiring layer 300 through the pins.

[0079] Referring to FIG7, for the second chip 122, when the functional device 400 is disposed in the first wiring layer 200, the second chip 122 can also be connected to the functional device 400 through the second target metal wiring 311, the wiring via 130 and the first metal wiring 210, thereby improving the flexibility of electrical connections in the packaging module.

[0080] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0081] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0082] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

[0083] Although embodiments of this application have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of this application, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A packaging module, characterized in that, include: A substrate having opposing first and second surfaces, wherein chip slots are arranged in an array and functional chips are disposed within the chip slots; A first wiring layer is disposed on the first surface, and the first wiring layer includes at least one first metal wiring layer. A first target metal wiring layer in the at least one first metal wiring layer is electrically connected to the functional chip. The first target metal wiring layer is the first metal wiring layer closest to the pin of the functional chip. A second wiring layer is disposed on the second surface. The second wiring layer includes at least one layer of second metal wiring. A second target metal wiring in the at least one layer of second metal wiring is electrically connected to the functional chip. The second target metal wiring is the second metal wiring closest to the pin of the functional chip. At least one functional device, wherein the functional device is disposed within the first wiring layer and electrically connected to the first metal wiring; and / or the functional device is disposed within the second wiring layer and electrically connected to the second metal wiring.

2. The packaging module according to claim 1, characterized in that, The number of layers of the first metal wiring is two or more, and the first metal wirings at different layers are electrically connected by interconnecting wiring.

3. The packaging module according to claim 1, characterized in that, The number of layers of the at least one layer of second metal wiring is two or more, and the second metal wirings at different layers are electrically connected by interconnect wiring.

4. The packaging module according to claim 1, characterized in that, The substrate has wiring vias, and the first metal wiring and the second metal wiring are electrically connected through the wiring vias.

5. The packaging module according to claim 1, characterized in that, The packaging module further includes an external interface, which is located on the side of the first wiring layer or the second wiring layer away from the substrate, and is electrically connected to the wiring layer that is closest to the first wiring layer or the second wiring layer.

6. The packaging module according to claim 5, characterized in that, The packaging module further includes a protective layer, which is disposed on the side of the first wiring layer or the second wiring layer away from the substrate. The protective layer and the external interface are respectively disposed on both sides relative to the substrate.

7. The packaging module according to claim 6, characterized in that, The thickness of the packaging module is the sum of the thicknesses of the substrate, the first wiring layer, the second wiring layer, and the protective layer.

8. The packaging module according to claim 1, characterized in that, The thickness of the substrate is matched to the height of the functional chip.

9. The packaging module according to claim 1, characterized in that, The functional chip includes a first chip with pins facing the first wiring layer and the first chip being electrically connected to the first target metal wiring.

10. The packaging module according to claim 1, characterized in that, The functional chip includes a second chip with pins facing the second wiring layer and the second chip being electrically connected to the second target metal wiring.

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