Array substrate and charging method therefor, and display panel

Abstract

The present application relates to the technical field of display, and provides an array substrate and a charging method therefor, and a display panel. The array substrate comprises a display area and a first peripheral area located on one side of the display area. The display area comprises a plurality of sub-pixels arranged in an array and a plurality of data signal lines extending in a first direction; and the data signal lines are arranged between two adjacent columns of the sub-pixels. The plurality of sub-pixels comprise first sub-pixel columns; and display colors of sub-pixels in the first sub-pixel columns are not all the same. The same data signal line is separately electrically connected to sub-pixels having the same display color in the at least two first sub-pixel columns. The first direction is a direction from the display area to the first peripheral area. The array substrate has low energy consumption and good display effect.

Description

Array substrate and its charging method, display panel

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510478135.7, filed on April 16, 2025, entitled “Array Substrate and Charging Method Thereof, Display Panel”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of display technology, and in particular to an array substrate and its charging method, and a display panel. Background Technology

[0004] With the rapid development of OLED (Organic Light-Emitting Diode) display technology, people have increasingly higher requirements for the characteristics of OLED display products. Based on the advantages of OLED display products, their diverse display refresh rates, and the successive development of multi-frequency display products, OLED display technology is also constantly being updated and iterated.

[0005] However, in actual use, the power consumption of the screen, signal transmission (such as MIPI transmission), and terminal image rendering are all relatively high. As the requirements for the battery life of display products increase, it is urgent to improve the power consumption of display products in order to reduce power consumption. Summary of the Invention

[0006] The embodiments of this application adopt the following technical solutions:

[0007] In a first aspect, embodiments of this application provide an array substrate, including a display area and a first peripheral area located on one side of the display area. The display area includes a plurality of sub-pixels arranged in an array and a plurality of data signal lines extending along a first direction. The data signal lines are disposed between two adjacent columns of the sub-pixels.

[0008] The plurality of sub-pixels includes a first sub-pixel column, wherein the display colors of the sub-pixels in the first sub-pixel column are not completely the same; the same data signal line is electrically connected to at least two sub-pixels in the first sub-pixel column that have the same display color; the first direction is the direction from the display area to the first peripheral area.

[0009] In some array substrates provided in embodiments of this application, the first peripheral area includes a multiplexing circuit, multiple bonding terminals, and multiple source signal lines. The data signal lines are electrically connected to the bonding terminals through the multiplexing circuit. The multiplexing circuit is configured to control the conduction and cutoff between the bonding terminals and the data signal lines.

[0010] Wherein, two data signal lines with the same display color as the connected sub-pixels are connected together and then electrically connected to the bonding terminal through the same source signal line.

[0011] In some array substrates provided in the embodiments of this application, the multiplexing circuit includes a first multiplexing unit and a second multiplexing unit. One of the two data signal lines connected by the same source signal line is electrically connected to the first multiplexing unit, and the other data signal line is electrically connected to the second multiplexing unit.

[0012] In some array substrates provided in the embodiments of this application, the same data signal line is electrically connected to the sub-pixels with the same display color in two adjacent first sub-pixel columns.

[0013] In some array substrates provided in embodiments of this application, the plurality of sub-pixels further includes a second sub-pixel column, the second sub-pixel column is located between two adjacent first sub-pixel columns, the display color of each sub-pixel in the second sub-pixel column is the same, and each sub-pixel in the second sub-pixel column is electrically connected to the same data signal line.

[0014] In some array substrates provided in the embodiments of this application, the first sub-pixel column includes alternately arranged first color sub-pixels and second color sub-pixels, and the second sub-pixel column includes third color sub-pixels; one second sub-pixel column is provided in any two adjacent first sub-pixel columns;

[0015] The first color sub-pixel in the first sub-pixel column of the first column and the first color sub-pixel in the second column of the first column are electrically connected to the first data signal line, the third color sub-pixel in the second sub-pixel column of the first column is electrically connected to the second data signal line, the second color sub-pixel in the first sub-pixel column of the first column and the second color sub-pixel in the first sub-pixel column of the second column are electrically connected to the third data signal line, and the third color sub-pixel in the second sub-pixel column of the second column is electrically connected to the fourth data signal line.

[0016] The first color sub-pixel in the first sub-pixel column of the third column and the first color sub-pixel in the first sub-pixel column of the fourth column are electrically connected to the fifth data signal line, the third color sub-pixel in the second sub-pixel column of the third column is electrically connected to the sixth data signal line, the second color sub-pixel in the first sub-pixel column of the third column and the second color sub-pixel in the first sub-pixel column of the fourth column are electrically connected to the seventh data signal line, and the third color sub-pixel in the second sub-pixel column of the fourth column is electrically connected to the eighth data signal line.

[0017] In some array substrates provided in the embodiments of this application, the first multiplexing unit includes a first multiplexing signal line, a first switch, a second switch, a third switch and a sixth switch, and the second multiplexing unit includes a second multiplexing signal line, a fourth switch, a fifth switch, a seventh switch and an eighth switch;

[0018] The gates of the first switch, the second switch, the third switch, and the sixth switch are all electrically connected to the first multiplexed signal line, and the gates of the fourth switch, the fifth switch, the seventh switch, and the eighth switch are all electrically connected to the second multiplexed signal line.

[0019] The source of the first switching transistor is connected to the portion of the first data signal line located in the display area, and the drain of the first switching transistor is connected to the portion of the first data signal line located in the first peripheral area; the source of the second switching transistor is connected to the portion of the second data signal line located in the display area, and the drain of the second switching transistor is connected to the portion of the second data signal line located in the first peripheral area; the source of the third switching transistor is connected to the portion of the third data signal line located in the display area, and the drain of the third switching transistor is connected to the portion of the third data signal line located in the first peripheral area; the source of the fourth switching transistor is connected to the portion of the fourth data signal line located in the display area, and the drain of the fourth switching transistor is connected to the portion of the fourth data signal line located in the first peripheral area. The source of the fifth switch is connected to the portion of the fifth data signal line located in the display area, and the drain of the fifth switch is connected to the portion of the fifth data signal line located in the first peripheral area; the source of the sixth switch is connected to the portion of the sixth data signal line located in the display area, and the drain of the sixth switch is connected to the portion of the sixth data signal line located in the first peripheral area; the source of the seventh switch is connected to the portion of the seventh data signal line located in the display area, and the drain of the seventh switch is connected to the portion of the seventh data signal line located in the first peripheral area; the source of the eighth switch is connected to the portion of the eighth data signal line located in the display area, and the drain of the eighth switch is connected to the portion of the eighth data signal line located in the first peripheral area.

[0020] In some array substrates provided in the embodiments of this application, the first color sub-pixel is a red sub-pixel, the second color sub-pixel is a blue sub-pixel, and the third color sub-pixel is a green sub-pixel.

[0021] In some array substrates provided in the embodiments of this application, the first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a green sub-pixel.

[0022] In some array substrates provided in the embodiments of this application, the same data signal line is electrically connected to the sub-pixels of the same color in three columns of the first sub-pixels.

[0023] In some array substrates provided in the embodiments of this application, the first sub-pixel column includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged repeatedly along the first direction. In the same row of sub-pixels, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are arranged repeatedly along a direction perpendicular to the first direction.

[0024] In some array substrates provided in embodiments of this application, the first color sub-pixels in the first sub-pixel columns of the first column, the second column, and the third column are electrically connected to the first data signal line, the second color sub-pixels in the first sub-pixel columns of the first column, the second column, and the third column are electrically connected to the second data signal line, and the third color sub-pixels in the first sub-pixel columns of the first column, the second column, and the third column are electrically connected to the third data signal line.

[0025] The first color sub-pixels in the first sub-pixel columns of columns 4, 5, and 6 are electrically connected to the fourth data signal line, the second color sub-pixels in the first sub-pixel columns of columns 4, 5, and 6 are electrically connected to the fifth data signal line, and the third color sub-pixels in the first sub-pixel columns of columns 4, 5, and 6 are electrically connected to the sixth data signal line.

[0026] In some array substrates provided in the embodiments of this application, the first multiplexing unit includes a first multiplexing signal line, a first switch, a second switch and a third switch, and the second multiplexing unit includes a second multiplexing signal line, a fourth switch, a fifth switch and a sixth switch;

[0027] The gates of the first, second, and third switching transistors are electrically connected to the first multiplexed signal line. The source of the first switching transistor is connected to the portion of the first data signal line located in the display area, and the drain of the first switching transistor is connected to the portion of the first data signal line located in the first peripheral area. The source of the second switching transistor is connected to the portion of the second data signal line located in the display area, and the drain of the second switching transistor is connected to the portion of the second data signal line located in the first peripheral area. The source of the third switching transistor is connected to the portion of the third data signal line located in the display area, and the drain of the third switching transistor is connected to the portion of the third data signal line located in the first peripheral area.

[0028] The gates of the fourth, fifth, and sixth switching transistors are electrically connected to the second multiplexed signal line. The source of the fourth switching transistor is connected to the portion of the fourth data signal line located in the display area, and the drain of the fourth switching transistor is connected to the portion of the fourth data signal line located in the first peripheral area. The source of the fifth switching transistor is connected to the portion of the fifth data signal line located in the display area, and the drain of the fifth switching transistor is connected to the portion of the fifth data signal line located in the first peripheral area. The source of the sixth switching transistor is connected to the portion of the sixth data signal line located in the display area, and the drain of the sixth switching transistor is connected to the portion of the sixth data signal line located in the first peripheral area.

[0029] In some array substrates provided in the embodiments of this application, one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is a red sub-pixel, another is a green sub-pixel, and the third is a blue sub-pixel.

[0030] In some array substrates provided in embodiments of this application, the first multiplexed signal line is configured to transmit a first multiplexed signal, and the second multiplexed signal line is configured to transmit a second multiplexed signal;

[0031] The transistors electrically connected to the first multiplexed signal line and the transistors electrically connected to the second multiplexed signal line do not conduct simultaneously.

[0032] In some array substrates provided in embodiments of this application, the display area further includes multiple gate lines extending perpendicular to the first direction, with the same gate line connecting the same row of sub-pixels, the gate line being configured to transmit a gate control signal to the sub-pixel, and the gate control signal being configured to control the charging time of the sub-pixel;

[0033] After each transistor electrically connected to the first multiplexed signal line is turned on and then turned off, each transistor electrically connected to the second multiplexed signal line is turned on.

[0034] After each transistor electrically connected to the second multiplexed signal line is turned on, the gate control signal is configured to control the sub-pixel to begin charging.

[0035] In some array substrates provided in the embodiments of this application, each transistor electrically connected to the first multiplexed signal line and each transistor electrically connected to the second multiplexed signal line are P-type transistors.

[0036] Secondly, embodiments of this application provide a charging method for an array substrate, applied to an array substrate as described in any one of the first aspects, the charging method comprising:

[0037] A first multiplexed signal of a first level is input to the first multiplexed signal line, and a second multiplexed signal of a second level is input to the second multiplexed signal line;

[0038] A first multiplexed signal of the second level is input to the first multiplexed signal line, and a second multiplexed signal of the first level is input to the second multiplexed signal line; wherein, the first level is less than the second level;

[0039] A gate control signal is input to the gate line, and the gate control signal overlaps with a portion of the second multiplexed signal.

[0040] Thirdly, embodiments of this application provide a display panel including a driver chip and an array substrate as described in the first aspect, wherein the driver chip and bonding terminals on the array substrate are electrically connected.

[0041] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 is a schematic diagram of the structure of the driving circuit of the first array substrate provided in the embodiment of this application;

[0044] Figure 2 is a schematic diagram of the driving circuit of the second array substrate provided in the embodiment of this application;

[0045] Figure 3 is a schematic diagram of the driving circuit of the third array substrate provided in the embodiment of this application;

[0046] Figure 4 is a timing signal diagram of a multiplexing circuit provided in an embodiment of this application;

[0047] Figure 5 is a timing diagram illustrating a multiplexed signal and a gate control signal provided in an embodiment of this application;

[0048] Figure 6 is a schematic diagram of the driving circuit of the fourth array substrate provided in the embodiments of this application. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0051] In the embodiments of this application, the use of terms such as "first" and "second" to describe the same or similar items with essentially the same function and effect is only for the purpose of clearly describing the technical solution of the embodiments of this application, and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0052] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this application include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include a certain degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (e.g., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of said value. "At least one" refers to one or more, and "more than one" refers to at least two.

[0053] In this application, "same layer" refers to the relationship between multiple film layers formed from the same material after undergoing the same step (e.g., a patterning process). "Same layer" here does not always mean that multiple film layers have the same thickness or the same height in a cross-sectional view. The polygons used in this specification are not strictly defined; they can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances.

[0054] In this specification, "electrical connection" and "coupling" include situations where components are connected together by elements that have some electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0055] With the continuous development of display technology, Organic Light-Emitting Diode (OLED) displays have become a research hotspot and technological development direction for major manufacturers due to their advantages such as wide color gamut, high contrast, thin and light design, self-emissive nature, and wide viewing angle. Currently, OLED displays are widely used in various electronic products, from small items like smart bracelets, smartwatches, smartphones, and tablets to large items like laptops, desktop computers, and televisions. Therefore, the market demand for active-matrix OLED displays is increasingly strong.

[0056] However, OLED technology still faces a power consumption bottleneck. In actual use of OLED display terminals, the power consumption of the screen, signal transmission (such as MIPI transmission), and terminal image rendering are all relatively high. As the requirements for the battery life of display products increase, it is urgent to improve the power consumption of display products in order to reduce power consumption.

[0057] Based on this, embodiments of this application provide an array substrate and its charging method, and a display panel. The array substrate includes a display area and a first peripheral area located on one side of the display area. The display area includes a plurality of sub-pixels arranged in an array and a plurality of data signal lines extending along a first direction. The data signal lines are disposed between two adjacent columns of sub-pixels. The plurality of sub-pixels include a first sub-pixel column, and the display colors of each sub-pixel in the first sub-pixel column are not completely the same. The same data signal line is electrically connected to at least two sub-pixels in the first sub-pixel column that have the same display color. The first direction is the direction from the display area to the first peripheral area.

[0058] This application, based on the need to reduce the power consumption of the driver IC, optimizes the driving design of sub-pixels in the array substrate so that the same data signal line is electrically connected to at least two sub-pixels of the same color in the first sub-pixel column. This ensures that the sub-pixels electrically connected to each source channel of the driver chip are all of the same color, for example, all red sub-pixels; or all green sub-pixels; or all blue sub-pixels. When the display panel displays a solid color image, the difference in the toggle voltage (or transition voltage) of each source channel of the driver chip is very small, thus avoiding large voltage jumps in the source signal line when displaying solid colors, effectively reducing the power consumption of the driver chip. The estimated effective power consumption reduction is approximately 20%, significantly increasing the lifespan of the display product.

[0059] The array substrate, its charging method, and the display panel provided in the embodiments of this application will now be described and explained in detail with reference to the accompanying drawings.

[0060] An embodiment of this application provides an array substrate, as shown in Figures 1 to 3, including a display area AA and a first peripheral area B1 located on one side of the display area AA. The display area AA includes a plurality of sub-pixels PX arranged in an array and a plurality of data signal lines Data extending along a first direction (e.g., the OA direction). The data signal lines Data are disposed between two adjacent columns of sub-pixels PX.

[0061] Multiple sub-pixels PX include a first sub-pixel column PXX1, and the display colors of each sub-pixel PX in the first sub-pixel column PXX1 are not completely the same; the same data signal line Data is electrically connected to at least two sub-pixels PX in the first sub-pixel column PXX1 that have the same display color; the first direction (e.g., the OA direction) is the direction from the display area AA to the first peripheral area B1.

[0062] The aforementioned display area AA refers to the area in the array substrate used for displaying images. The first peripheral area B1 may include at least a fan-out area (e.g., a fan-out area, or a fan-out area and a bonding area). The fan-out area is used to set up various traces to connect the signal lines in the display area AA to the bonding terminals (pins) in the bonding area BD. The bonding area BD is used to set up multiple bonding terminals, which can be bonded together with the driver chip, allowing the signals transmitted by the driver chip to be input into the traces of the fan-out area through the bonding terminals.

[0063] For example, the aforementioned "first direction" can be the direction in which the display area AA points to the fan-out area.

[0064] It should be noted that the first sub-pixel column PXX1 refers to a column of sub-pixels where the display colors of each sub-pixel PX are not completely identical. Multiple sub-pixels PX including the first sub-pixel column PXX1 can include the following situations:

[0065] First, the multiple sub-pixels PX include the first sub-pixel column PXX1, and also include sub-pixel columns with other sub-pixel arrangement rules;

[0066] Second, multiple sub-pixels in the array substrate are arranged in the manner of first sub-pixel column PXX1. It can be understood that each column of sub-pixels can be called the first sub-pixel column PXX1.

[0067] Additionally, "display colors are not completely identical" means that some sub-pixels in the same column of sub-pixels display the same color, while others display different colors.

[0068] In some embodiments, the array substrate may include multiple sub-pixels that display different colors. For example, the array substrate may simultaneously include three sub-pixels that display red, blue, and green; or, for another example, the array substrate may simultaneously include four sub-pixels that display red, blue, green, and white.

[0069] In this case, the display colors of each sub-pixel PX in the first sub-pixel column PXX1 are not completely the same, and the number of sub-pixels with different display colors in the sub-pixel column is not limited. In this case, the first sub-pixel column PXX1 includes at least two sub-pixels with different display colors. For example, the first sub-pixel column PXX1 includes two sub-pixels with different display colors; for another example, the first sub-pixel column PXX1 includes three sub-pixels with different display colors; and for yet another example, the first sub-pixel column PXX1 includes three sub-pixels with different display colors. Of course, in some array substrates, the first sub-pixel column PXX1 may include four sub-pixels with different display colors.

[0070] In the embodiments of this application, unlike the driving method in related technologies that electrically connects a data signal line Data to the same column of sub-pixels, this application uses the same data signal line Data to electrically connect at least two sub-pixels PX in the first sub-pixel column PXX1 that display the same color. Since the sub-pixels PX electrically connected to the same data signal line Data display the same color, when the source channel in the driver chip transmits signals to the data signal line Data through the bonding terminal, the voltage jump in the same source channel is small at different display stages, and the difference in voltage change of the signal in the same data signal line Data is relatively small, thus avoiding power loss caused by large voltage jumps.

[0071] The electrical connection of the same data signal line Data to at least two sub-pixels PX in the first sub-pixel column PXX1 that display the same color can include the following situations:

[0072] First, the same data signal line Data is electrically connected to the sub-pixels PX in the two first sub-pixel columns PXX1 that display the same color.

[0073] For example, the same data signal line Data is electrically connected to the first color sub-pixel in the first first sub-pixel column PXX1 and the first color sub-pixel in the second first sub-pixel column PXX1, respectively.

[0074] For example, the same data signal line Data is electrically connected to the second color sub-pixel in the first first sub-pixel column PXX1 and the second color sub-pixel in the second first sub-pixel column PXX1 respectively;

[0075] For example, the same data signal line Data is electrically connected to the third color sub-pixel in the first first sub-pixel column PXX1 and the third color sub-pixel in the second first sub-pixel column PXX1, respectively.

[0076] Second, the same data signal line Data is electrically connected to the sub-pixels PX in the three first sub-pixel columns PXX1 that display the same color.

[0077] For example, the same data signal line Data is electrically connected to the first color sub-pixel in the first first sub-pixel column PXX1, the first color sub-pixel in the second first sub-pixel column PXX1, and the first color sub-pixel in the third first sub-pixel column PXX1, respectively.

[0078] For example, the same data signal line Data is electrically connected to the second color sub-pixel in the first first sub-pixel column PXX1, the second color sub-pixel in the second first sub-pixel column PXX1, and the second color sub-pixel in the third first sub-pixel column PXX1, respectively.

[0079] For example, the same data signal line Data is electrically connected to the third color sub-pixel in the first first sub-pixel column PXX1, the third color sub-pixel in the second first sub-pixel column PXX1, and the third color sub-pixel in the third first sub-pixel column PXX1.

[0080] In the embodiments of this application, by setting multiple sub-pixels PX including a first sub-pixel column PXX1, the display colors of each sub-pixel PX in the first sub-pixel column PXX1 are not completely the same; the same data signal line Data is electrically connected to at least two sub-pixel PXs in the first sub-pixel column PXX1 that have the same display color; in this way, it can be ensured that the sub-pixels electrically connected to each source channel of the driver chip are all sub-pixels of the same color, for example, all red sub-pixels; or all green sub-pixels; or all blue sub-pixels; when the display panel displays a solid color image, the difference in the switching voltage (toggle voltage, or jump voltage) of each source channel of the driver chip is very small, thereby avoiding the large jump of the voltage signal transmitted by the source signal line when displaying solid color images of different colors, thus effectively reducing the power consumption of the driver chip. It is estimated that the effective power consumption can be reduced by about 20%, which greatly improves the service life of the display product.

[0081] In some array substrates provided in the embodiments of this application, as shown in Figures 1 to 3, the first peripheral region B1 includes a multiplexing circuit MUX, multiple bonding terminals Pin, and multiple source signal lines. The data signal line Data is electrically connected to the bonding terminals Pin through the multiplexing circuit MUX. The multiplexing circuit MUX is configured to control the conduction and cutoff between the bonding terminals Pin and the data signal line Data.

[0082] Among them, the two data signal lines with the same display color of the connected sub-pixels are connected together and then electrically connected to the bonding terminal pin through the same source signal line.

[0083] The multiplexing circuit MUX is located at the lower end of the display area AA. One end of the multiplexing circuit MUX is electrically connected to each data signal line Data in the display area AA, and the other end is electrically connected to multiple source signal lines Source Line in the first peripheral area B1. The number of source signal lines Source Line is usually less than or equal to the number of data signal lines Data, and the two numbers can satisfy a certain proportional relationship.

[0084] For example, when two data signal lines (Data) with the same display color of the connected sub-pixels are connected together, they are electrically connected to the bonding terminal (Pin) through the same source signal line (Source Line). In this case, the number of data signal lines (Data) is twice the number of source signal lines (Source Line).

[0085] The multiplexing circuit MUX has multiple switching transistors, each of which controls whether or not signal transmission occurs between at least one data signal line (Data) and a bonding terminal (Pin).

[0086] The number of bonding terminal pins (e.g., also known as COP Pads) and their arrangement in the first peripheral area B1 are not limited here. Since the bonding terminal pins will be electrically connected to the driver IC, the arrangement of the bonding terminal pins is related to the pin settings and arrangement in the selected driver IC.

[0087] For example, multiple bonding terminals (Pins) can be arranged in at least one row, as shown in Figure 1. Bonding terminals S1, S2, S3, S4, S5, S6, S7, and S8 are arranged in the same row along a direction perpendicular to the display area AA and pointing towards the first peripheral area B1. The Driver IC bonding area marked by the dashed rectangle in the figure is the area for subsequent bonding of the driver chip.

[0088] In some embodiments, the plurality of bonding terminal pins also include a dummy bonding terminal, wherein the dummy bonding terminal may not be electrically connected to the data signal line Data in the display area AA, but is mainly used to improve the terrain flatness in the first peripheral area B1 and avoid the problem of increased bonding process difficulty caused by local unevenness.

[0089] In the embodiments of this application, two data signal lines Data with the same display color for connected sub-pixels are connected together in the array substrate and electrically connected to the bonding terminal Pin through the same source signal line Source Line. On the one hand, this can reduce the number of traces in the first peripheral area B1 and reduce the space occupied by the design. On the other hand, since the two data signal lines Data that are electrically connected to the same source signal line Source Line are connected to sub-pixels with the same display color in the display area AA, the voltage signal transmitted by the source signal transmission channel in the driver chip is less different when the driver chip transmits signals to the source signal line Source Line, thereby greatly reducing the power consumption of the driver chip.

[0090] In some array substrates provided in the embodiments of this application, the multiplexing circuit MUX includes a first multiplexing unit MUX1 and a second multiplexing unit MUX2. Among the two data signal lines Data connected by the same source signal line, one data signal line Data is electrically connected to the first multiplexing unit MUX1, and the other data signal line Data is electrically connected to the second multiplexing unit MUX2.

[0091] Since one of the two data signal lines Data connected to the same source signal line is electrically connected to the first multiplexing unit MUX1 and the other data signal line Data is electrically connected to the second multiplexing unit MUX2, the first multiplexing unit MUX1 can control whether or not signal transmission occurs between one of the two data signal lines Data connected to the same source signal line and the source signal line. The second multiplexing unit MUX1 can control whether or not signal transmission occurs between the other data signal line Data connected to the same source signal line and the source signal line. This allows control over the transmission of signals between the two data signal lines Data connected to the same source signal line at different time periods (e.g., writing new signals or charging at different time periods).

[0092] In some array substrates provided in the embodiments of this application, as shown in Figures 1 and 2, the same data signal line Data is electrically connected to the sub-pixels with the same display color in two adjacent first sub-pixel columns PXX1.

[0093] In some array substrates provided in the embodiments of this application, as shown in Figures 1 and 2, the multiple sub-pixels PX further include a second sub-pixel column PXX2. The second sub-pixel column PXX2 (e.g., a green sub-pixel column) is located between two adjacent first sub-pixel columns PXX1. The display color of each sub-pixel in the second sub-pixel column PXX2 is the same, and each sub-pixel in the second sub-pixel column PXX2 is electrically connected to the same data signal line Data.

[0094] In some array substrates provided in the embodiments of this application, as shown in Figures 1 and 2, the first sub-pixel column PXX1 includes alternating first color sub-pixels and second color sub-pixels, and the second sub-pixel column PXX2 includes third color sub-pixels; a second sub-pixel column PXX2 is provided in any two adjacent first sub-pixel columns PXX1.

[0095] Among them, one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is a red sub-pixel, another is a green sub-pixel, and the last is a blue sub-pixel.

[0096] As shown in Figures 1 and 2, the first color sub-pixel in the first sub-pixel column PXX1 of the first column and the first color sub-pixel in the second column PXX1 are electrically connected to the first data signal line Data, the third color sub-pixel in the second sub-pixel column PXX2 of the first column is electrically connected to the second data signal line Data, the second color sub-pixel in the first sub-pixel column PXX1 of the first column and the second color sub-pixel in the second column PXX1 are electrically connected to the third data signal line Data, and the third color sub-pixel in the second sub-pixel column PXX2 of the second column is electrically connected to the fourth data signal line Data.

[0097] As shown in Figures 1 and 2, the first color sub-pixel in the first sub-pixel column PXX1 of the third column and the first color sub-pixel in the first sub-pixel column PXX1 of the fourth column are electrically connected to the fifth data signal line Data, the third color sub-pixel in the second sub-pixel column PXX2 of the third column is electrically connected to the sixth data signal line Data, the second color sub-pixel in the first sub-pixel column PXX1 of the third column and the second color sub-pixel in the first sub-pixel column PXX1 of the fourth column are electrically connected to the seventh data signal line Data, and the third color sub-pixel in the second sub-pixel column PXX2 of the fourth column is electrically connected to the eighth data signal line Data.

[0098] As shown in Figures 1 and 2, the electrical connection between each subsequent column of sub-pixels and the data signal line Data is the same as the connection of the eight columns of sub-pixels mentioned above, and the connection is repeated cyclically in eight columns as a repeating unit.

[0099] For example, the first color sub-pixel in the first sub-pixel column PXX1 of the nth column and the first color sub-pixel in the (n+1)th column PXX1 are electrically connected to the nth data signal line Data, the third color sub-pixel in the second sub-pixel column PXX2 of the nth column is electrically connected to the (n+1)th data signal line Data, the second color sub-pixel in the first sub-pixel column PXX1 of the nth column and the second color sub-pixel in the (n+1)th column PXX1 are electrically connected to the (n+2)th data signal line Data, and the third color sub-pixel in the second sub-pixel column PXX2 of the (n+1)th column is electrically connected to the (n+3)th data signal line Data. The first color sub-pixel in the first sub-pixel column PXX1 of column n+2 and the first color sub-pixel in the first sub-pixel column PXX1 of column n+3 are electrically connected to the (n+4)th data signal line Data, respectively. The third color sub-pixel in the second sub-pixel column PXX2 of column n+2 is electrically connected to the (n+5)th data signal line Data, respectively. The second color sub-pixel in the first sub-pixel column PXX1 of column n+2 and the second color sub-pixel in the first sub-pixel column PXX1 of column n+3 are electrically connected to the (n+6)th data signal line Data, respectively. The third color sub-pixel in the second sub-pixel column PXX2 of column n+3 is electrically connected to the (n+7)th data signal line Data, respectively. Wherein, n is a positive integer.

[0100] In some array substrates provided in the embodiments of this application, as shown in Figures 1 and 2, the first multiplexing unit MUX1 includes a first multiplexing signal line ML1, a first switch T1, a second switch T2, a third switch T3, and a sixth switch T6; the second multiplexing unit MUX2 includes a second multiplexing signal line ML2, a fourth switch T4, a fifth switch T5, a seventh switch T7, and an eighth switch T8; the gates of the first switch T1, the second switch T2, the third switch T3, and the sixth switch T6 are all electrically connected to the first multiplexing signal line ML1, and the gates of the fourth switch T4, the fifth switch T5, the seventh switch T7, and the eighth switch T8 are all electrically connected to the second multiplexing signal line ML2.

[0101] The source of the first switching transistor T1 is connected to the first data signal line Data located in the display area AA, and the drain of the first switching transistor T1 is connected to the first data signal line Data located in the first peripheral area B1; the source of the second switching transistor T2 is connected to the second data signal line Data located in the display area AA, and the drain of the second switching transistor T2 is connected to the second data signal line Data located in the first peripheral area B1; the source of the third switching transistor T3 is connected to the third data signal line Data located in the display area AA, and the drain of the third switching transistor T4 is connected to the third data signal line Data located in the first peripheral area B1; the source of the fourth switching transistor T4 is connected to the fourth data signal line Data located in the display area AA, and the drain of the fourth switching transistor T4 is connected to the fourth data signal line Data located in the first peripheral area B1. The source of the fifth switch transistor T5 is connected to the portion of the fifth data signal line Data located in the display area AA, and the drain of the fifth switch transistor T5 is connected to the portion of the fifth data signal line Data located in the first peripheral area B1; the source of the sixth switch transistor T6 is connected to the portion of the sixth data signal line Data located in the display area AA, and the drain of the sixth switch transistor T6 is connected to the portion of the sixth data signal line Data located in the first peripheral area B1; the source of the seventh switch transistor T7 is connected to the portion of the seventh data signal line Data located in the display area AA, and the drain of the seventh switch transistor T7 is connected to the portion of the seventh data signal line Data located in the first peripheral area B1; the source of the eighth switch transistor T8 is connected to the portion of the eighth data signal line Data located in the display area AA, and the drain of the eighth switch transistor T8 is connected to the portion of the eighth data signal line Data located in the first peripheral area B1.

[0102] The types of the first switch T1, the second switch T2, the third switch T3 and the sixth switch T6, as well as the fourth switch T4, the fifth switch T5, the seventh switch T7 and the eighth switch T8, are not limited here.

[0103] For example, the first switch T1, the second switch T2, the third switch T3 and the sixth switch T6 are of the same transistor type, for example, all of them are N-type switches; or, all of them are P-type switches.

[0104] For example, the fourth switch T4, the fifth switch T5, the seventh switch T7, and the eighth switch T8 mentioned above are of the same type, for example, all of them are N-type switches; or, all of them are P-type switches.

[0105] For example, all of the above-mentioned switching transistors can be P-type thin-film transistors; or, all of the above-mentioned switching transistors can be N-type thin-film transistors.

[0106] Of course, all of the above-mentioned switching transistors can be P-type MOS transistors; or, all of the above-mentioned switching transistors can be N-type MOS transistors.

[0107] For N-type transistors, the operating voltage level is high, and the non-operating voltage level is low. For P-type transistors, the operating voltage level is low, and the non-operating voltage level is high. The operating voltage level refers to the voltage level that enables the source and drain of the transistor to conduct, while the non-operating voltage level refers to the voltage level that enables the source and drain of the transistor to disconnect.

[0108] In some array substrates provided in the embodiments of this application, as shown in FIG1, the first color sub-pixel is a red sub-pixel R, the second color sub-pixel is a blue sub-pixel B, and the third color sub-pixel is a green sub-pixel G.

[0109] In some array substrates provided in the embodiments of this application, as shown in FIG2, the first color sub-pixel is blue sub-pixel B, the second color sub-pixel is red sub-pixel R, and the third color sub-pixel is green sub-pixel B.

[0110] In the embodiments of this application, as shown in Figure 1 or Figure 2, the same data signal line (Data) is electrically connected to sub-pixels of the same color in two first sub-pixel columns (PXX1). This ensures that the sub-pixels electrically connected to each source channel of the driver chip are all sub-pixels of the same color, for example, all red sub-pixels; or all green sub-pixels; or all blue sub-pixels. When the display panel displays a solid color image, the difference in the toggle voltage (or transition voltage) of each source channel of the driver chip is very small, thereby avoiding large jumps in the voltage signal transmitted by the source signal line when displaying solid color images of different colors. This effectively reduces the power consumption of the driver chip, with an estimated effective power consumption reduction of approximately 20%, significantly increasing the lifespan of the display product.

[0111] The array substrates in Figures 1 and 2 can be configured with sub-pixels of two colors, RG and GB, as one pixel unit. This is beneficial for manufacturing high PPI display products and improving display performance.

[0112] In some other embodiments, as shown in Figure 1 or Figure 2, the four sub-pixels RGBG can be set to the same pixel unit.

[0113] In an exemplary embodiment, the second multiplexed signal line ML2 may be located on the side of the first multiplexed signal line ML1 away from the display area AA, and the distance from each transistor electrically connected to the first multiplexed signal line ML1 (e.g., the first switch T1, the second switch T2, the third switch T3, and the sixth switch T6) to the display area AA may be less than the distance from each transistor electrically connected to the second multiplexed signal line ML2 (e.g., the fourth switch T4, the fifth switch T5, the seventh switch T7, and the eighth switch T8).

[0114] It should be noted that the embodiments of this application do not limit the shape of the sub-pixels. The shape of each sub-pixel may include polygons, arcs, or a combination of polygons and arcs. Among them, polygons include quadrilaterals, pentagons, hexagons, etc.; arcs include circles, semicircles, ellipses, and semi-ellipses; the combination of polygons and arcs refers to the graphic formed by the combination of polygons and / or arcs, or the graphic formed by removing part of the area based on polygons and arcs; the shapes of sub-pixels with different display colors may be the same, or the shapes of sub-pixels with different display colors may be different.

[0115] For convenience, the accompanying drawings provided in the embodiments of this application are drawn with each sub-pixel being a circle as an example, which does not represent a limitation on the shape of the sub-pixels in this application.

[0116] The embodiments of this application do not limit the shape and size of the sub-pixels. For example, when sub-pixels of different colors have the same shape, their side length, diameter, or diagonal length may not be exactly the same. In the accompanying drawings of this application, for the sake of simplicity and clarity in showing the electrical connection method, each sub-pixel is drawn as an example where all sub-pixels are circular and of the same size.

[0117] In some array substrates provided in the embodiments of this application, as shown in FIG3, the same data signal line Data is electrically connected to the sub-pixels with the same display color in the three first sub-pixel columns PXX1.

[0118] In some array substrates provided in the embodiments of this application, as shown in FIG3, the first sub-pixel column PXX1 includes a first color sub-pixel, a second color sub-pixel and a third color sub-pixel. The first color sub-pixel, the second color sub-pixel and the third color sub-pixel are repeatedly arranged in sequence along a first direction (e.g., the OA direction). In the same row of sub-pixels PX, the first color sub-pixel, the second color sub-pixel and the third color sub-pixel are repeatedly arranged in sequence along a direction perpendicular to the first direction (e.g., the OA direction).

[0119] In the embodiments of this application, by connecting sub-pixels that are all R sub-pixels, all G sub-pixels, and all B sub-pixels in series on the same source channel, and finally driving them with the same source of the same driver IC, the power consumption of the driver chip Diver IC caused by the source voltage jump of the driver chip can be effectively reduced, thereby achieving the effect of reducing screen power consumption and increasing the overall usage time of the device.

[0120] In some array substrates provided in the embodiments of this application, as shown in FIG3, the first color sub-pixels in the first sub-pixel columns PXX1 of the first, second, and third columns are electrically connected to the first data signal line Data, the second color sub-pixels in the first, second, and third columns PXX1 are electrically connected to the second data signal line Data, and the third color sub-pixels in the first, second, and third columns PXX1 are electrically connected to the third data signal line Data; the first color sub-pixels in the first, fifth, and sixth columns PXX1 are electrically connected to the fourth data signal line Data, the second color sub-pixels in the first, fifth, and sixth columns PXX1 are electrically connected to the fifth data signal line Data, and the third color sub-pixels in the first, fifth, and sixth columns PXX1 are electrically connected to the sixth data signal line Data.

[0121] As shown in Figure 3, the electrical connection between each subsequent column of sub-pixels and the data signal line Data is the same as the connection of the above six columns of sub-pixels, and the connection is repeated cyclically in six columns as a repeating unit.

[0122] In some array substrates provided in embodiments of this application, as shown in FIG3, the first color sub-pixels in the first sub-pixel columns PXX1 of the nth, n+1th, and n+2th columns are electrically connected to the nth data signal line Data, the second color sub-pixels in the first sub-pixel columns PXX1 of the nth, n+1th, and n+2th columns are electrically connected to the n+1th data signal line Data, and the third color sub-pixels in the first sub-pixel columns PXX1 of the nth, n+1th, and n+2th columns are electrically connected to the n+2th data signal line Data. The first color subpixels in the first subpixel columns PXX1 of columns n+3, n+4, and n+5 are electrically connected to the (n+3)th data signal line Data, the second color subpixels in the first subpixel columns PXX1 of columns n+3, n+4, and n+5 are electrically connected to the (n+4)th data signal line Data, and the third color subpixels in the first subpixel columns PXX1 of columns 4, 5, and 6 are electrically connected to the (n+5)th data signal line Data; where n is a positive integer.

[0123] In some array substrates provided in the embodiments of this application, as shown in FIG3, the first multiplexing unit MUX1 includes a first multiplexing signal line ML1, a first switch T1, a second switch T2 and a third switch T3, and the second multiplexing unit MUX2 includes a second multiplexing signal line ML2, a fourth switch T4, a fifth switch T5 and a sixth switch T6.

[0124] The gates of the first switch transistor T1, the second switch transistor T2, and the third switch transistor T3 are electrically connected to the first multiplexed signal line ML1. The source of the first switch transistor T1 is connected to the portion of the first data signal line Data located in the display area AA, and the drain of the first switch transistor T1 is connected to the portion of the first data signal line Data located in the first peripheral area B1. The source of the second switch transistor T1 is connected to the portion of the second data signal line Data located in the display area AA, and the drain of the second switch transistor T2 is connected to the portion of the second data signal line Data located in the first peripheral area B1. The source of the third switch transistor T3 is connected to the portion of the third data signal line Data located in the display area AA, and the drain of the third switch transistor T3 is connected to the portion of the third data signal line Data located in the first peripheral area B1.

[0125] The gates of the fourth switch transistor T4, the fifth switch transistor T5, and the sixth switch transistor T6 are electrically connected to the second multiplexed signal line ML2. The source of the fourth switch transistor T4 is connected to the portion of the fourth data signal line Data located in the display area AA, and the drain of the fourth switch transistor T4 is connected to the portion of the fourth data signal line Data located in the first peripheral area B1. The source of the fifth switch transistor T5 is connected to the portion of the fifth data signal line Data located in the display area AA, and the drain of the fifth switch transistor T5 is connected to the portion of the fifth data signal line Data located in the first peripheral area B1. The source of the sixth switch transistor T6 is connected to the portion of the sixth data signal line Data located in the display area AA, and the drain of the sixth switch transistor T6 is connected to the portion of the sixth data signal line Data located in the first peripheral area B1.

[0126] The types of the first switch T1, the second switch T2, the third switch T3, the fourth switch T4, the fifth switch T5, and the sixth switch T6 are not limited here.

[0127] For example, the first switch T1, the second switch T2, and the third switch T3 mentioned above have the same transistor type, for example, all of them are N-type switches; or, all of them are P-type switches.

[0128] For example, the fourth switch T4, the fifth switch T5, and the sixth switch T6 mentioned above are of the same type, for example, all of them are N-type switches; or, all of them are P-type switches.

[0129] For example, all of the above-mentioned switching transistors can be P-type thin-film transistors; or, all of the above-mentioned switching transistors can be N-type thin-film transistors.

[0130] Of course, all of the above-mentioned switching transistors can be P-type MOS transistors; or, all of the above-mentioned switching transistors can be N-type MOS transistors.

[0131] The timing diagram shown in FIG4 provided in the embodiments of this application is provided as an example where each transistor is a P-type transistor.

[0132] In some array substrates provided in the embodiments of this application, as shown in FIG3, one of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is a red sub-pixel, another is a green sub-pixel, and the third is a blue sub-pixel.

[0133] For example, as shown in Figure 3, the first color sub-pixel can be a red sub-pixel, the second color sub-pixel can be a green sub-pixel, and the third color sub-pixel can be a blue sub-pixel.

[0134] In some array substrates provided in the embodiments of this application, in Figures 1 to 3, a first multiplexed signal line ML1 is configured to transmit a first multiplexed signal, and a second multiplexed signal line ML2 is configured to transmit a second multiplexed signal; the transistors electrically connected to the first multiplexed signal line and the transistors electrically connected to the second multiplexed signal line are not turned on simultaneously.

[0135] The first multiplexed signal and the second multiplexed signal are not simultaneously at the first level signal; wherein, the first level signal is the effective signal for each transistor in the MUX circuit to be turned on. For example, when all the above-mentioned transistors are P-type transistors, the first multiplexed signal and the second multiplexed signal are not simultaneously at the low level signal, so that the transistors electrically connected to the first multiplexed signal line ML1 and the transistors electrically connected to the second multiplexed signal line ML2 are not simultaneously turned on.

[0136] In the embodiments of this application, by setting the transistors electrically connected to the first multiplexed signal line ML1 and the transistors electrically connected to the second multiplexed signal line ML2 to not be turned on at the same time, for two data signal lines Data connected to the same source signal line Source, the MUX circuit can control the driver chip to transmit signals to the two data signal lines Data connected to the same source signal line Source at different time periods, thereby transmitting different signals to these two data signal lines Data.

[0137] In some array substrates provided in the embodiments of this application, as shown in FIG6, the display area AA further includes multiple gate lines GL (including GL1, GL2, GL3...) extending along a direction perpendicular to the first direction (e.g., the first direction OA). The same gate line GL connects to the same row of sub-pixels PX. The gate line GL is configured to transmit a gate control signal (also known as the gate signal Gout) to the sub-pixel PX. The gate control signal is configured to control the charging time of the sub-pixel PX.

[0138] Based on the timing signals shown in Figure 5, after each transistor connected to the first multiplexed signal line ML1 is turned on and off, each transistor connected to the second multiplexed signal line ML1 is turned on; after each transistor connected to the second multiplexed signal line ML2 is turned on, the gate control signal is configured to control the sub-pixel PX to start charging.

[0139] In an exemplary embodiment, when the second multiplexed signal line ML2 is located on the side of the first multiplexed signal line ML1 away from the display area AA, and the distance from each transistor electrically connected to the first multiplexed signal line ML1 (e.g., the first switch T1, the second switch T2, the third switch T3, and the sixth switch T6) to the display area AA is less than the distance from each transistor electrically connected to the second multiplexed signal line ML2 (e.g., the fourth switch T4, the fifth switch T5, the seventh switch T7, and the eighth switch T8), when the four sub-pixels RGBG belong to the same pixel unit, as shown in FIG1 or FIG2, taking the first column pixel unit as an example, since the first multiplexed signal line ML1 controls the first switch T1, the second switch T2, the third switch T3, and the sixth switch T6 to turn on, the data signal lines Data corresponding to the first column sub-pixels (R and B), the second column sub-pixels (G), and the third column sub-pixels (R and B) in the first column pixel unit are charged first. However, the data signal line Data corresponding to the fourth sub-pixel (G) in the first column pixel unit is not charged. After the transistors connected to the first multiplexed signal line ML1 are turned off, the transistors connected to the second multiplexed signal line ML2 are turned on, and the data signal line Data corresponding to the fourth sub-pixel (G) in the first column pixel unit begins to charge. In this way, even if the gate control signal controls each data signal line to be turned on simultaneously to charge the sub-pixel, the charging time of the data signal line Data corresponding to the fourth sub-pixel (G) is shorter, and the actual charging degree of the fourth sub-pixel (G) is lower than that of the first column sub-pixels (R and B), the second column sub-pixels (G), and the third column sub-pixels (R and B). This makes the actual display brightness of the fourth sub-pixel (G) lower than that of the second column sub-pixel (G). Thus, for this RGBG four-sub-pixel pixel unit, it can largely improve the problem of the display screen being greenish due to the excessive brightness of the green sub-pixel.

[0140] Similarly, for the second column pixel unit, the two green sub-pixels are controlled by the sixth transistor and the eighth transistor respectively, as shown in Figure 1 or Figure 2. In the second column pixel unit, the two green sub-pixels are controlled by the first multiplexed signal line ML1 and the second multiplexed signal line ML2 respectively. Due to the timing difference, the actual charging rate of one of the green sub-pixels is lower, which can greatly improve the problem of the display screen being too green due to the excessive brightness of the green sub-pixels.

[0141] In some array substrates provided in the embodiments of this application, each transistor electrically connected to the first multiplexed signal line ML1 and each transistor electrically connected to the second multiplexed signal line ML2 are P-type transistors.

[0142] It should be noted that the array substrate described above may also include other structures and components. This specification only describes the structures and components related to the inventive point. Other structures and components can be referred to the descriptions in related technologies.

[0143] Embodiments of this application provide a charging method for an array substrate, applied to an array substrate as described in any of the preceding descriptions. Referring to Figures 4 and 5, the charging method includes:

[0144] S01. First step: Input a first multiplexed signal of the first level to the first multiplexed signal line ML1, and input a second multiplexed signal of the second level to the second multiplexed signal line ML2;

[0145] S02. Second step: Input a first multiplexed signal with a second level to the first multiplexed signal line ML1, and input a second multiplexed signal with a first level to the second multiplexed signal line ML2; wherein, the first level is lower than the second level;

[0146] S03. Third step: Input gate control signal to gate line GL. Gate control signal Gout partially overlaps with second multiplexed signal Mux2.

[0147] It should be noted that during the charging process described above, the second step begins after the first step is completed, and the third step can begin before the second step has started and ended.

[0148] The following example, charging the first row of sub-pixels, illustrates the charging method for the array substrate:

[0149] Step 1: Input a first multiplexed signal with a first level (e.g., low level) to the first multiplexed signal line ML1, and input a second multiplexed signal with a second level (e.g., high level) to the second multiplexed signal line ML2; The first multiplexed signal line ML1 controls the transistor electrically connected to it to turn on, and the second multiplexed signal line ML2 controls the transistor electrically connected to it to turn off, so as to charge the signal provided by the source channel of the driver chip into the corresponding data signal line Data in the first row of sub-pixels;

[0150] Step 2: Input a first multiplexed signal with a second level (e.g., high level) to the first multiplexed signal line ML1, and input a second multiplexed signal with a first level (e.g., low level) to the second multiplexed signal line ML2; the first multiplexed signal line ML1 controls the transistor electrically connected to it to turn off, and the second multiplexed signal line ML2 controls the transistor electrically connected to it to turn on, so as to charge the signal provided by the source channel of the driver chip into the data signal line Data corresponding to the first row of sub-pixels;

[0151] Step 3: Input a gate control signal (e.g., low level) to the gate line GL. The gate line GL, which is electrically connected to the first row of sub-pixels PX, controls the transistors of the pixel driving circuit in the first row of sub-pixels PX to turn on. The data signal line Data controlled by the first multiplexed signal line ML1 and the data signal line Data controlled by the second multiplexed signal line ML2 respectively start charging the sub-pixels electrically connected to them.

[0152] As can be seen from the timing diagram in Figure 5, the falling edge of the Gout1 signal appears after the falling edge of the Mux2 signal, and there is a time overlap between the two signals. Therefore, step 3 can start before the end of step 2.

[0153] The charging process for the other rows of sub-pixels is the same as that for the first row. By controlling the gate control signals of different rows, the array substrate can complete the charging process row by row.

[0154] For example, taking the refresh time of a row as H, the opening time t of each mux (e.g., the first multiplexing unit MUX1 or the second multiplexing unit MUX2) is approximately in the range of 0.1*H to 0.45*H. The specific time can be determined according to the product design.

[0155] Since the charging time of the sub-pixels is controlled by the gate control signal provided by the gate line GL, the charging time of the sub-pixels electrically connected by the first multiplexed signal line ML1 and the sub-pixels electrically connected by the second multiplexed signal line ML2 is consistent, resulting in good brightness uniformity and thus enabling the display panel to have a good display effect.

[0156] In the embodiments of this application, by setting multiple sub-pixels PX including a first sub-pixel column PXX1, the display colors of each sub-pixel PX in the first sub-pixel column PXX1 are not completely the same; the same data signal line Data is electrically connected to at least two sub-pixel PXs in the first sub-pixel column PXX1 that have the same display color; in this way, it can be ensured that during the charging process of the sub-pixels of the driving substrate, the sub-pixels electrically connected to each source channel of the driving chip are all sub-pixels of the same color, for example, all red sub-pixels; or all green sub-pixels; or all blue sub-pixels; when the display panel displays a solid color image, the difference in the switching voltage (toggle voltage, or jump voltage) of each source channel of the driving chip is very small, thereby avoiding the large jump of the voltage signal transmitted by the source signal line when displaying solid color images of different colors, thus effectively reducing the power consumption of the driving chip. It is estimated that the effective power consumption can be reduced by about 20%, which greatly improves the service life of the display product.

[0157] Embodiments of this application provide a display panel including a driver chip and an array substrate as described above, wherein the driver chip and the array substrate are electrically connected to bonding terminals Pin.

[0158] In an exemplary embodiment, the display panel can be a light-emitting diode (LED), organic light-emitting diode (OLED), micro LED (micro light-emitting diode), or mini LED (mini light-emitting diode) display panel.

[0159] The aforementioned display panel can be a silicon-based display panel or a glass-based display panel. A silicon-based display panel refers to a display panel whose driving circuit is disposed on a silicon substrate and fabricated using MOS technology. A glass-based display panel refers to a display panel whose driving circuit is disposed on a glass substrate and fabricated using TFT technology.

[0160] For example, the above-mentioned display panel can be a Touch and Display Driver Integration (TDDI) display panel.

[0161] The size of the aforementioned display panel is not limited. It can be used in large or extra-large (e.g., 86 inches) UHD (Ultra High Definition) or HD (High Definition) display devices, or it can be used in small (e.g., 23.6 inches) UHD or HD display devices.

[0162] In an exemplary embodiment, the display panel of this application can also be used in virtual reality devices or augmented display devices, etc. The display panel may include, but is not limited to: mobile phones, tablets, televisions, monitors, laptops, digital photo frames, navigators, or any product or component with display function.

[0163] In the display panel provided in the embodiments of this application, multiple sub-pixels PX are set, including a first sub-pixel column PXX1, and the display colors of each sub-pixel PX in the first sub-pixel column PXX1 are not completely the same; the same data signal line Data is electrically connected to at least two sub-pixel PXs in the first sub-pixel column PXX1 with the same display color; in this way, it can be ensured that the sub-pixels electrically connected to each source channel of the driver chip are all sub-pixels of the same color, for example, all red sub-pixels; or all green sub-pixels; or all blue sub-pixels; when the display panel displays a solid color image, the difference in the switching voltage (toggle voltage, or jump voltage) of each source channel of the driver chip is very small, thereby avoiding the large jump of the voltage signal transmitted by the source signal line when displaying solid color images of different colors, thereby effectively reducing the power consumption of the driver chip. It is estimated that the effective power consumption can be reduced by about 20%, which greatly improves the service life of the display product.

[0164] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An array substrate, wherein, It includes a display area and a first peripheral area located on one side of the display area. The display area includes a plurality of sub-pixels arranged in an array and a plurality of data signal lines extending along a first direction. The data signal lines are disposed between two adjacent columns of the sub-pixels. The plurality of sub-pixels includes a first sub-pixel column, wherein the display colors of the sub-pixels in the first sub-pixel column are not completely the same; the same data signal line is electrically connected to at least two sub-pixels in the first sub-pixel column that have the same display color; the first direction is the direction from the display area to the first peripheral area.

2. The array substrate according to claim 1, wherein, The first peripheral area includes a multiplexing circuit, multiple bonding terminals, and multiple source signal lines. The data signal lines are electrically connected to the bonding terminals through the multiplexing circuit. The multiplexing circuit is configured to control the conduction and cutoff between the bonding terminals and the data signal lines. Wherein, two data signal lines with the same display color as the connected sub-pixels are connected together and then electrically connected to the binding terminal through the same source signal line.

3. The array substrate according to claim 2, wherein, The multiplexing circuit includes a first multiplexing unit and a second multiplexing unit. One of the two data signal lines connected by the same source signal line is electrically connected to the first multiplexing unit, and the other data signal line is electrically connected to the second multiplexing unit.

4. The array substrate according to claim 3, wherein, The same data signal line is electrically connected to the sub-pixels of the same color in two adjacent columns of the first sub-pixel.

5. The array substrate according to claim 4, wherein, The plurality of sub-pixels also includes a second sub-pixel column, which is located between two adjacent first sub-pixel columns. The display color of each sub-pixel in the second sub-pixel column is the same, and each sub-pixel in the second sub-pixel column is electrically connected to the same data signal line.

6. The array substrate according to claim 5, wherein, The first sub-pixel column includes alternating first and second color sub-pixels, and the second sub-pixel column includes a third color sub-pixel; one of the second sub-pixel columns is provided in any two adjacent first sub-pixel columns; The first color sub-pixel in the first sub-pixel column of the first column and the first color sub-pixel in the second column are electrically connected to the first data signal line, the third color sub-pixel in the second sub-pixel column of the first column are electrically connected to the second data signal line, the second color sub-pixel in the first sub-pixel column of the first column and the second color sub-pixel in the first sub-pixel column of the second column are electrically connected to the third data signal line, and the third color sub-pixel in the second sub-pixel column of the second column are electrically connected to the fourth data signal line. The first color sub-pixel in the first sub-pixel column of the third column and the first color sub-pixel in the first sub-pixel column of the fourth column are electrically connected to the fifth data signal line, the third color sub-pixel in the second sub-pixel column of the third column is electrically connected to the sixth data signal line, the second color sub-pixel in the first sub-pixel column of the third column and the second color sub-pixel in the first sub-pixel column of the fourth column are electrically connected to the seventh data signal line, and the third color sub-pixel in the second sub-pixel column of the fourth column is electrically connected to the eighth data signal line.

7. The array substrate according to claim 6, wherein, The first multiplexing unit includes a first multiplexing signal line, a first switch, a second switch, a third switch, and a sixth switch; the second multiplexing unit includes a second multiplexing signal line, a fourth switch, a fifth switch, a seventh switch, and an eighth switch. The gates of the first switch, the second switch, the third switch, and the sixth switch are all electrically connected to the first multiplexed signal line, and the gates of the fourth switch, the fifth switch, the seventh switch, and the eighth switch are all electrically connected to the second multiplexed signal line. The source of the first switching transistor is connected to the portion of the first data signal line located in the display area, and the drain of the first switching transistor is connected to the portion of the first data signal line located in the first peripheral area; the source of the second switching transistor is connected to the portion of the second data signal line located in the display area, and the drain of the second switching transistor is connected to the portion of the second data signal line located in the first peripheral area; the source of the third switching transistor is connected to the portion of the third data signal line located in the display area, and the drain of the third switching transistor is connected to the portion of the third data signal line located in the first peripheral area; the source of the fourth switching transistor is connected to the portion of the fourth data signal line located in the display area, and the drain of the fourth switching transistor is connected to the portion of the fourth data signal line located in the first peripheral area. The source of the fifth switch is connected to the portion of the fifth data signal line located in the display area, and the drain of the fifth switch is connected to the portion of the fifth data signal line located in the first peripheral area; the source of the sixth switch is connected to the portion of the sixth data signal line located in the display area, and the drain of the sixth switch is connected to the portion of the sixth data signal line located in the first peripheral area; the source of the seventh switch is connected to the portion of the seventh data signal line located in the display area, and the drain of the seventh switch is connected to the portion of the seventh data signal line located in the first peripheral area; the source of the eighth switch is connected to the portion of the eighth data signal line located in the display area, and the drain of the eighth switch is connected to the portion of the eighth data signal line located in the first peripheral area.

8. The array substrate according to claim 7, wherein, The first color sub-pixel is a red sub-pixel, the second color sub-pixel is a blue sub-pixel, and the third color sub-pixel is a green sub-pixel.

9. The array substrate according to claim 7, wherein, The first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel is a green sub-pixel.

10. The array substrate according to claim 3, wherein, The same data signal line is electrically connected to the three sub-pixels in the first sub-pixel column that display the same color.

11. The array substrate according to claim 10, wherein, The first sub-pixel column includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel. The first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are sequentially repeated along the first direction. In the same row of sub-pixels, the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel are sequentially repeated along a direction perpendicular to the first direction.

12. The array substrate according to claim 11, wherein, The first color sub-pixels in the first sub-pixel columns of columns 1, 2, and 3 are electrically connected to the first data signal line, the second color sub-pixels in the first sub-pixel columns of columns 1, 2, and 3 are electrically connected to the second data signal line, and the third color sub-pixels in the first sub-pixel columns of columns 1, 2, and 3 are electrically connected to the third data signal line. The first color sub-pixels in the first sub-pixel columns of columns 4, 5, and 6 are electrically connected to the fourth data signal line, the second color sub-pixels in the first sub-pixel columns of columns 4, 5, and 6 are electrically connected to the fifth data signal line, and the third color sub-pixels in the first sub-pixel columns of columns 4, 5, and 6 are electrically connected to the sixth data signal line.

13. The array substrate according to claim 12, wherein, The first multiplexing unit includes a first multiplexing signal line, a first switch, a second switch, and a third switch; the second multiplexing unit includes a second multiplexing signal line, a fourth switch, a fifth switch, and a sixth switch. The gates of the first, second, and third switching transistors are electrically connected to the first multiplexed signal line. The source of the first switching transistor is connected to the portion of the first data signal line located in the display area, and the drain of the first switching transistor is connected to the portion of the first data signal line located in the first peripheral area. The source of the second switching transistor is connected to the portion of the second data signal line located in the display area, and the drain of the second switching transistor is connected to the portion of the second data signal line located in the first peripheral area. The source of the third switching transistor is connected to the portion of the third data signal line located in the display area, and the drain of the third switching transistor is connected to the portion of the third data signal line located in the first peripheral area. The gates of the fourth, fifth, and sixth switching transistors are electrically connected to the second multiplexed signal line. The source of the fourth switching transistor is connected to the portion of the fourth data signal line located in the display area, and the drain of the fourth switching transistor is connected to the portion of the fourth data signal line located in the first peripheral area. The source of the fifth switching transistor is connected to the portion of the fifth data signal line located in the display area, and the drain of the fifth switching transistor is connected to the portion of the fifth data signal line located in the first peripheral area. The source of the sixth switching transistor is connected to the portion of the sixth data signal line located in the display area, and the drain of the sixth switching transistor is connected to the portion of the sixth data signal line located in the first peripheral area.

14. The array substrate according to claim 13, wherein, One of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel is a red sub-pixel, another is a green sub-pixel, and the third is a blue sub-pixel.

15. The array substrate according to any one of claims 7-9 and 13-14, wherein, The first multiplexed signal line is configured to transmit a first multiplexed signal, and the second multiplexed signal line is configured to transmit a second multiplexed signal; The transistors electrically connected to the first multiplexed signal line and the transistors electrically connected to the second multiplexed signal line do not conduct simultaneously.

16. The array substrate according to claim 15, wherein, The display area further includes multiple gate lines extending perpendicular to the first direction, with the same gate line connecting the same row of sub-pixels. The gate line is configured to transmit a gate control signal to the sub-pixel, and the gate control signal is configured to control the charging time of the sub-pixel. After each transistor electrically connected to the first multiplexed signal line is turned on and then turned off, each transistor electrically connected to the second multiplexed signal line is turned on. After each transistor electrically connected to the second multiplexed signal line is turned on, the gate control signal is configured to control the sub-pixel to begin charging.

17. The array substrate according to claim 16, wherein, The transistors electrically connected to the first multiplexed signal line and the transistors electrically connected to the second multiplexed signal line are all P-type transistors.

18. A charging method for an array substrate, wherein, Applied to an array substrate as described in any one of claims 1 to 17, the charging method includes: A first multiplexed signal of a first level is input to the first multiplexed signal line, and a second multiplexed signal of a second level is input to the second multiplexed signal line; A first multiplexed signal of the second level is input to the first multiplexed signal line, and a second multiplexed signal of the first level is input to the second multiplexed signal line; wherein, the first level is less than the second level; A gate control signal is input to the gate line, and the gate control signal overlaps with a portion of the second multiplexed signal.

19. A display panel, wherein, It includes a driver chip and an array substrate as described in any one of claims 2 to 17, wherein the driver chip and the bonding terminals on the array substrate are electrically connected.

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