Encoding method, decoding method, apparatus, and system

Abstract

The present application relates to the technical field of communications, and discloses an encoding method, a decoding method, an apparatus, and a system. The encoding method comprises: determining a check matrix on the basis of shift values corresponding to elements in a base matrix of an LDPC code, and encoding an information bit sequence on the basis of the check matrix, wherein the first value is not an integer multiple of a lifting factor, and the first value is related to the shift values corresponding to at least two non-zero elements in a first region of the base matrix and the shift values corresponding to at least two non-zero elements located in the same row in a second region of the base matrix; the first region comprises first elements in N columns of the base matrix, and the first elements are located in the first M rows of the base matrix; the second region comprises second elements in the N columns of the base matrix, and the second elements are located in the (M+d1)-th row to the (M+d2)-th row of the base matrix. In this way, by optimizing the shift values corresponding to the elements in the second region of the base matrix, the influence of trapping sets (such as the first region) is reduced, thereby facilitating a stable improvement in performance even under high reliability requirements.

Description

A coding and decoding method, apparatus and system

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510484588.0, filed on April 16, 2025, entitled "A coding and decoding method, apparatus and system", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to a coding / decoding method, apparatus, and system. Background Technology

[0004] Low-density parity-check (LDPC) codes are channel coding schemes very close to the Shannon limit and have been chosen as the data channel coding scheme for fifth-generation (5G) systems. Mainstream LDPCs have a quasi-cyclic (QC) structure, i.e., QC-LDPC, which is represented using a base graph (BG). The base graph can also be written in matrix form, called the base matrix. Based on the boost value and the shift values ​​corresponding to the non-empty positions in the base matrix, the base matrix can be expanded into a complete parity-check matrix for encoding or decoding.

[0005] However, LDPC codes have certain limitations when applied to ultra-reliable and low-latency communication (URLLC) scenarios. For example, the basis matrix of LDPC codes contains a trapping set. This special topology can lead to the inability to completely correct certain errors during iterative decoding, resulting in an error floor phenomenon, which makes it difficult to meet the reliability requirements of URLLC scenarios. Summary of the Invention

[0006] This application provides a coding method, apparatus, and system that reduces the impact of trap sets by optimizing the shift values ​​corresponding to the elements in the second region of the basis matrix, which is beneficial for maintaining stable performance improvement under high reliability requirements.

[0007] In a first aspect, embodiments of this application provide an encoding method, which can be executed by a first communication device (or encoding device). Unless otherwise specified, the "first communication device" in this application can refer to a communication device (e.g., a network device, a terminal device, an encoding device, etc.), a component used in the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device but coupled to it. For example, in the method provided in the first aspect, the first communication device determines the shift value corresponding to each element in the base matrix of the LDPC code based on the boosting factor; determines the parity check matrix based on the shift value corresponding to each element in the base matrix; encodes the information bit sequence based on the parity check matrix; and outputs the encoded bit sequence; wherein, the first value is not an integer multiple of the boosting factor, and the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix; the first region includes the first element in the N columns of the base matrix, and the first element is located in the first M rows of the base matrix; the second region includes the second element in the N columns of the base matrix, and the second element is located in the M+d1 to M+d2 rows of the base matrix; the N columns are a part of the information column and the core parity column of the base matrix; M is an integer greater than 2, N is an integer greater than or equal to M, d1 and d2 are integers greater than or equal to 1, and d1 is less than or equal to d2.

[0008] Thus, for the second region in the base matrix, a design scheme for the shift values ​​corresponding to the non-zero elements in the second region is provided, thereby maximizing the speed at which the code distance increases with the number of rows, reducing the impact of the trap set, and ensuring that the code distance in the low-to-medium code rate region meets the requirements, which is beneficial for stable performance improvement under high reliability requirements.

[0009] Based on the first aspect mentioned above, there are one or more possible designs as follows:

[0010] In one possible design, after determining the shift values ​​corresponding to each element in the base matrix based on the method provided in this application, the shift values ​​corresponding to each element in the base matrix are stored on the encoding device side and the decoding device side in a manner specified by protocol or predefined. During encoding or decoding, the encoding device and the decoding device respectively read these shift values ​​and perform cyclic shifting and expansion (expansion based on the lift value) on the elements at the corresponding positions in the base matrix to obtain a parity check matrix for encoding or decoding.

[0011] In one possible design, at least two non-zero elements in the first region of the basis matrix include a first non-zero element and a second non-zero element located in the same row, and at least two non-zero elements in the second region of the basis matrix include a third non-zero element and a fourth non-zero element located in the same row. The first non-zero element and the third non-zero element are located in the same column, and the second non-zero element and the fourth non-zero element are located in the same column. The first value is related to the shift value corresponding to the first non-zero element, the second non-zero element, the third non-zero element, and the fourth non-zero element.

[0012] In one possible design, the first value satisfies the following formula: Q = V3 - V4 + V2 - V1

[0013] Where Q represents the first value, V1 represents the shift value corresponding to the first non-zero element, V2 represents the shift value corresponding to the second non-zero element, V3 represents the shift value corresponding to the third non-zero element, and V4 represents the shift value corresponding to the fourth non-zero element.

[0014] In one possible design, the first element is located in the first M rows of the base matrix, including: the first element is located in row M1 of the first M rows of the base matrix, where M1 is an integer greater than 2 and less than or equal to M; and N = M1 + 1.

[0015] In one possible design, M1 = 3, N = 4; the first non-zero element and the third non-zero element are located in the 3rd column of the N columns, the second non-zero element and the fourth non-zero element are located in the 4th column of the N columns, and the first non-zero element and the second non-zero element are located in the 3rd row of the M1 rows.

[0016] In one possible design, M1 = 3, N = 4; the first non-zero element and the third non-zero element are located in the first column of the N columns, the second non-zero element and the fourth non-zero element are located in the second column of the N columns, and the first non-zero element and the second non-zero element are located in the second row of the M1 rows.

[0017] In one possible design, the first region is any of the following:

[0018] or

[0019] In one possible design, M1 = 4, N = 5; the first non-zero element and the third non-zero element are located in the first column of the N columns, the second non-zero element and the fourth non-zero element are located in the second column of the N columns, and the first non-zero element and the second non-zero element are located in the second row of the M1 rows.

[0020] In one possible design, M1 = 4, N = 5; the first non-zero element and the third non-zero element are located in the 4th column of the N columns, the second non-zero element and the fourth non-zero element are located in the 5th column of the N columns, and the first non-zero element and the second non-zero element are located in the 4th row of the M1 rows.

[0021] In one possible design, the first region is any of the following:

[0022] or

[0023] In one possible design, in the first region is When one row of the second region is [1, 1, 0, 0], the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix, including at least one of the following: Q = SV1 - SV2 + (x22 - x21); Q = SV1 - SV2 + (x13 - x14 + x22 - x21 + x34 - x33); Q = SV1 - SV2 + (x14 - x13 + x22 - x21 + x33 - x34);

[0024] Where Q represents the first value, SV1 represents the non-zero element in the first column of one row of the second region, SV2 represents the non-zero element in the second column of one row of the second region, xuv represents the shift value corresponding to the element in the u-th row and v-th column of the first region, u = 1, 2, 3, v = 1, 2, 3, 4, and mod represents the modulo operation.

[0025] In one possible design, in the first region is When one row of the second region is [1, 1, 1, 0], the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix, including at least one of the following: Q = SV1 - SV2 + (x22 - x21); Q = SV1 - SV2 + (x13 - x14 + x22 - x21 + x34 - x33); Q = SV1 - SV2 + (x14 - x13 + x22 - x21 + x33 - x34); Q = SV1 - SV3 + (x13 - x11); Q = SV1 - SV3 + (x13 - x12 + x22 - x21); Q = SV1 - SV3 + (x14 - x11 + x33 - x34); Q=SV1-SV3+(x14-x12+x22-x21+x33-x34); Q=SV2-SV3+(x13-x11+x21-x22); Q=SV2-SV3+(x13-x12); Q=SV2-SV3+(x14-x11+x21-x22+x33-x34); Q=SV2-SV3+(x14-x12+x33-x34);

[0026] Where Q represents the first value, SV1 represents the non-zero element in the first column of one row of the second region, SV2 represents the non-zero element in the second column of one row of the second region, SV3 represents the non-zero element in the third column of one row of the second region, xuv represents the shift value corresponding to the element in the u-th row and v-th column of the first region, u = 1, 2, 3, v = 1, 2, 3, 4, and mod represents the modulo operation.

[0027] Secondly, embodiments of this application provide a decoding method, which can be executed by a second communication device (or decoding device). Unless otherwise specified, the "second communication device" in this application can refer to a communication device (e.g., a terminal device, a network device, a decoding device, etc.), a component used in the communication device (e.g., a processor, a chip, or a chip system, etc.), or a logic module or software capable of implementing all or part of the functions of the communication device. The component used in the communication device can be a component in the communication device, or it can be independent of the communication device but coupled to it. For example, in the method provided in the second aspect, the second communication device determines the shift value corresponding to each element in the base matrix of the LDPC code based on the boosting factor; determines the parity check matrix based on the shift value corresponding to each element in the base matrix; and decodes the bit sequence to be decoded based on the parity check matrix; wherein, the first value is not an integer multiple of the boosting factor, and the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix; the first region includes the first element in the N columns of the base matrix, and the first element is located in the first M rows of the base matrix; the second region includes the second element in the N columns of the base matrix, and the second element is located in rows M+d1 to M+d2 of the base matrix; the N columns are a part of the information column and the core parity column of the base matrix; M is an integer greater than 2, N is an integer greater than or equal to M, d1 and d2 are integers greater than or equal to 1, and d1 is less than or equal to d2.

[0028] Based on the second aspect mentioned above, there are one or more possible designs as follows:

[0029] In one possible design, after determining the shift values ​​corresponding to each element in the base matrix based on the method provided in this application, the shift values ​​corresponding to each element in the base matrix are stored on the encoding device side and the decoding device side in a manner specified by protocol or predefined. During encoding or decoding, the encoding device and the decoding device respectively read these shift values ​​and perform cyclic shifting and expansion (expansion based on the lift value) on the elements at the corresponding positions in the base matrix to obtain a parity check matrix for encoding or decoding.

[0030] In one possible design, at least two non-zero elements in the first region of the basis matrix include a first non-zero element and a second non-zero element located in the same row, and at least two non-zero elements in the second region of the basis matrix include a third non-zero element and a fourth non-zero element located in the same row. The first non-zero element and the third non-zero element are located in the same column, and the second non-zero element and the fourth non-zero element are located in the same column. The first value is related to the shift value corresponding to the first non-zero element, the second non-zero element, the third non-zero element, and the fourth non-zero element.

[0031] In one possible design, the first value satisfies the following formula: Q = V3 - V4 + V2 - V1

[0032] Where Q represents the first value, V1 represents the shift value corresponding to the first non-zero element, V2 represents the shift value corresponding to the second non-zero element, V3 represents the shift value corresponding to the third non-zero element, and V4 represents the shift value corresponding to the fourth non-zero element.

[0033] In one possible design, the first element is located in the first M rows of the base matrix, including: the first element is located in row M1 of the first M rows of the base matrix, where M1 is an integer greater than 2 and less than or equal to M; and N = M1 + 1.

[0034] In one possible design, M1 = 3, N = 4; the first non-zero element and the third non-zero element are located in the 3rd column of the N columns, the second non-zero element and the fourth non-zero element are located in the 4th column of the N columns, and the first non-zero element and the second non-zero element are located in the 3rd row of the M1 rows.

[0035] In one possible design, M1 = 3, N = 4; the first non-zero element and the third non-zero element are located in the first column of the N columns, the second non-zero element and the fourth non-zero element are located in the second column of the N columns, and the first non-zero element and the second non-zero element are located in the second row of the M1 rows.

[0036] In one possible design, the first region is any of the following:

[0037] or

[0038] In one possible design, M1 = 4, N = 5; the first non-zero element and the third non-zero element are located in the first column of the N columns, the second non-zero element and the fourth non-zero element are located in the second column of the N columns, and the first non-zero element and the second non-zero element are located in the second row of the M1 rows.

[0039] In one possible design, M1 = 4, N = 5; the first non-zero element and the third non-zero element are located in the 4th column of the N columns, the second non-zero element and the fourth non-zero element are located in the 5th column of the N columns, and the first non-zero element and the second non-zero element are located in the 4th row of the M1 rows.

[0040] In one possible design, the first region is any of the following:

[0041] or

[0042] In one possible design, in the first region is When one row of the second region is [1, 1, 0, 0], the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix, including at least one of the following: Q = SV1 - SV2 + (x22 - x21); Q = SV1 - SV2 + (x13 - x14 + x22 - x21 + x34 - x33); Q = SV1 - SV2 + (x14 - x13 + x22 - x21 + x33 - x34);

[0043] Where Q represents the first value, SV1 represents the non-zero element in the first column of one row of the second region, SV2 represents the non-zero element in the second column of one row of the second region, xuv represents the shift value corresponding to the element in the u-th row and v-th column of the first region, u = 1, 2, 3, v = 1, 2, 3, 4, and mod represents the modulo operation.

[0044] In one possible design, in the first region is When one row of the second region is [1, 1, 1, 0], the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix, including at least one of the following: Q = SV1 - SV2 + (x22 - x21); Q = SV1 - SV2 + (x13 - x14 + x22 - x21 + x34 - x33); Q = SV1 - SV2 + (x14 - x13 + x22 - x21 + x33 - x34); Q = SV1 - SV3 + (x13 - x11); Q = SV1 - SV3 + (x13 - x12 + x22 - x21); Q = SV1 - SV3 + (x14 - x11 + x33 - x34); Q=SV1-SV3+(x14-x12+x22-x21+x33-x34); Q=SV2-SV3+(x13-x11+x21-x22); Q=SV2-SV3+(x13-x12); Q=SV2-SV3+(x14-x11+x21-x22+x33-x34); Q=SV2-SV3+(x14-x12+x33-x34);

[0045] Where Q represents the first value, SV1 represents the non-zero element in the first column of one row of the second region, SV2 represents the non-zero element in the second column of one row of the second region, SV3 represents the non-zero element in the third column of one row of the second region, xuv represents the shift value corresponding to the element in the u-th row and v-th column of the first region, u = 1, 2, 3, v = 1, 2, 3, 4, and mod represents the modulo operation.

[0046] Thirdly, this application provides a communication device that performs the functions described in the first or second aspect above. For example, the communication device includes modules, units, or means corresponding to the operations described in the first or second aspect above. The functions, units, or means can be implemented by software, hardware, or hardware executing corresponding software.

[0047] In one possible design, the communication device includes a processing unit and a communication unit, wherein the communication unit can be used to transmit and receive signals to enable communication between the communication device and other devices; the processing unit can be used to perform some internal operations of the communication device. The functions performed by the processing unit and the communication unit can correspond to the operations involved in the first or second aspect described above.

[0048] In one possible design, the communication device includes a processor that can be coupled to a memory. The memory can store necessary computer programs or instructions for implementing the functions described in the first or second aspect above. The processor can execute the computer programs or instructions stored in the memory, causing the communication device to implement the methods in any possible design or implementation of the first or second aspect above, when the computer programs or instructions are executed.

[0049] In one possible design, the communication device includes a processor and a memory, the memory of which may store necessary computer programs or instructions for implementing the functions involved in the first or second aspect described above. The processor may execute the computer programs or instructions stored in the memory, and when the computer programs or instructions are executed, cause the communication device to implement the methods in any possible design or implementation of the first or second aspect described above.

[0050] In one possible design, the communication device includes a processor and an interface circuit, wherein the processor is configured to communicate with other devices via the interface circuit and to perform the methods in any possible design or implementation of the first or second aspect described above.

[0051] Understandably, in the third aspect described above, the processor can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc.; when implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. Furthermore, there can be one or more processors, and one or more memories. The memory can be integrated with the processor or separated from it. In specific implementations, the memory can be integrated with the processor on the same chip or disposed on different chips. This application does not limit the type of memory or the arrangement of the memory and processor.

[0052] Fourthly, this application provides a communication system, which may include a first communication device and a second communication device; wherein the first communication device is used to perform the method described in the first aspect, and the second communication device is used to perform the method described in the second aspect.

[0053] Fifthly, this application provides a computer-readable storage medium storing a computer program or computer-readable instructions, wherein when a computer reads and executes part or all of the computer program or instructions, the method in any of the possible designs in the first or second aspect described above is executed.

[0054] For example, a computer-readable storage medium can be any available medium that a computer can access. This includes, but is not limited to, non-transient computer-readable media, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), CD-ROM or other optical disc storage, magnetic disk storage media, or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer.

[0055] Sixthly, this application provides a computer program product including instructions that, when executed, cause the method in any of the possible designs of the first or second aspect described above to be performed.

[0056] In a seventh aspect, this application provides a chip (or chip system) including a processor coupled to a memory storing a computer program; the processor is configured to invoke part or all of the computer program in the memory, such that the method in any of the possible designs in the first or second aspect described above is executed. Attached Figure Description

[0057] Figure 1 is a schematic diagram of the architecture of the communication system applicable to the embodiments of this application;

[0058] Figure 2 is a schematic diagram of the information transmission process provided in an embodiment of this application;

[0059] Figures 3A and 3B are schematic diagrams of the matrix structure of the base graph of LDPC codes;

[0060] Figure 4 is a flowchart corresponding to the method provided in the embodiment of this application;

[0061] Figure 5 is a schematic diagram of the first and second regions provided in an embodiment of this application;

[0062] Figures 6A to 6I are schematic diagrams of simulation results provided in the embodiments of this application;

[0063] Figure 7 is an exemplary block diagram of the apparatus involved in the embodiments of this application;

[0064] Figure 8 is a schematic diagram of the structure of a communication device provided in an embodiment of this application. Detailed Implementation

[0065] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. This application will focus on various aspects, embodiments, or features of a system that may include multiple devices, components, modules, etc. It should be understood and appreciated that each system may include additional devices, components, modules, etc., and / or may not include all the devices, components, modules, etc. discussed in conjunction with the accompanying drawings. Furthermore, combinations of these solutions may also be used.

[0066] The technical solutions of this application can be applied to various wireless communication systems, such as Universal Mobile Telecommunications System (UMTS), Wireless Local Area Network (WLAN), short-range wireless communication systems (such as sidelink, wireless fidelity, Wi-Fi, Bluetooth, etc.), wired networks, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, vehicle-to-everything (V2X) communication systems, 4th generation (4G) mobile communication systems (such as Long Term Evolution (LTE) systems), LTE Frequency Division Duplex (FDD) systems, LTE Time Division Duplex (TDD) systems, Worldwide Interoperability for Microwave Access (WiMAX) communication systems, 5G mobile communication systems (such as New Radio (NR) systems), Future Communications systems, or other similar communication systems, without limitation. This application describes the communication system shown in Figure 1 as an example. When applying the technical solution of this application to other communication systems, the devices, components, modules, etc. in the embodiment can be replaced with corresponding devices, components, modules in other communication systems without limitation.

[0067] Figure 1 is a schematic diagram of the architecture of the communication system applied in the embodiments of this application. As shown in Figure 1, the communication system includes an access network 100, and optionally, the communication system may also include a core network 200 and an Internet 300. The access network 100 may include at least one network device, such as 110a and 110b in Figure 1, and may also include at least one terminal device, such as 120a-120j in Figure 1. Specifically, 110a is a base station, 110b is a micro-station, 120a, 120e, 120f, and 120j are mobile phones, 120b is a car, 120c is a fuel dispenser, 120d is a home access point (HAP) deployed indoors or outdoors, 120g is a laptop computer, 120h is a printer, and 120i is a drone. The same terminal device or network device can provide different functions in different application scenarios. For example, the mobile phones in Figure 1 are 120a, 120e, 120f and 120j. Mobile phone 120a can access base station 110a, connect to car 120b, communicate directly with mobile phone 120e and access HAP. Car 120b can access HAP and communicate directly with mobile phone 120a. Mobile phone 120f can access micro-station 110b, connect to laptop 120g and printer 120h. Mobile phone 120j can control drone 120i.

[0068] (1) Network equipment

[0069] A network device is a network-side device with wireless transceiver capabilities. A network device can be a device in a radio access network (RAN) that provides wireless communication capabilities to terminal devices; this is called RAN equipment. The RAN can be an access network within the 3rd Generation Partnership Project (3GPP), such as 4G, 5G, or future networks. The RAN can also be an open RAN (O-RAN or ORAN), a cloud radio access network (CRAN), or a communication network combining two or more of these.

[0070] Network equipment can also be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next-generation NodeB (gNB) in a 5G mobile communication system, a base station in a future mobile communication system, or an access node in a WiFi system, etc.

[0071] Network equipment can also be modules or units that perform some of the functions of a base station. For example, it can be a central unit (CU), a distributed unit (DU), or a radio unit (RU). The CU performs the functions of the radio resource control (RRC) and packet data convergence protocol (PDCP) layers of the base station, and can also perform the functions of the service data adaptation protocol (SDAP). The CU can be further divided into a CU control plane (CP) (i.e., CU-CP) and a CU user plane (UP) (i.e., CU-UP). The DU performs the functions of the radio link control (RLC) and media access control (MAC) layers of the base station, and can also perform some or all of the physical layer functions. For specific descriptions of the above protocol layers, please refer to the relevant 3GPP technical specifications. The CU and DU can be set up separately, or they can be included in the same network element, such as in a baseband unit (BBU). The RU can be included in radio frequency equipment or radio frequency units, such as in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, CU, DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an ORAN system, CU can also be called O-CU (open CU), DU can also be called O-DU, and RU can also be called O-RU. Any of the CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software and hardware modules. The RAN equipment can be a macro base station (as shown in Figure 1, 110a), a micro base station or an indoor station (as shown in Figure 1, 110b), or a relay node or donor node, etc. The embodiments of this application do not limit the specific technology or specific equipment form used in the network equipment. The functions of the network equipment can also be executed by modules (such as chips) within the network equipment, or by a control subsystem containing the functions of the network equipment. The control subsystem here, which includes network device functionality, can be the control center in the aforementioned application scenarios such as smart grids, industrial control, intelligent transportation, and smart cities.

[0072] (2) Terminal equipment

[0073] A terminal device is a user-side device with wireless transceiver capabilities. Terminal devices can also be called terminals, user equipment (UE), mobile stations, mobile terminals, etc. They can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), the Internet of Things (IoT), virtual reality, augmented reality, industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables, intelligent transportation, and smart cities.

[0074] Terminal devices can be: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices (such as smartwatches, smart bracelets, pedometers, smart glasses, etc.), in-vehicle equipment (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed trains, etc.), satellite terminals, virtual reality (VR) devices, augmented reality (AR) devices, smart point of sale (POS) machines, customer-premises equipment (CPE), light user equipment (UE), reduced capability user equipment (REDCAP UE), wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electricity meters, etc.), smart robots, robotic arms, workshop equipment, wireless terminals in autonomous driving, wireless terminals in telemedicine, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, and flying equipment (such as smart robots, hot air balloons, drones, airplanes), etc. The terminal device can also be a vehicle device (such as a complete vehicle device, vehicle module, vehicle chip, on-board unit (OBU), or telematics box (T-BOX), etc.). In the embodiments of this application, the device used to implement the function of the terminal device can be the terminal device itself, or it can be a device that supports the terminal device in implementing the function, such as a chip system or a combination of devices or components that can implement the function of the terminal device. This device can be installed in the terminal device. The embodiments of this application do not limit the specific technology or specific device form adopted by the terminal device. The function of the terminal device can also be executed by a module (such as a chip or modem) in the terminal device, or it can be executed by a device that includes the function of the terminal device.

[0075] Network devices and terminal devices can be fixed or mobile. They can be deployed on land, including indoors or outdoors, handheld or vehicle-mounted; on water; or in the air on airplanes, balloons, and satellites. The embodiments of this application do not limit the application scenarios of the network devices and terminal devices. The roles of network devices and terminal devices can be relative. For example, the helicopter or drone 120i in Figure 1 can be configured as a mobile network device. For terminal devices 120j that access the wireless access network 100 via 120i, terminal device 120i is a network device; however, for network device 110a, 120i is a terminal device, meaning that 110a and 120i communicate via a wireless air interface protocol. Of course, 110a and 120i can also communicate via a network device-to-network device interface protocol; in this case, relative to 110a, 120i is also a network device. Therefore, both network devices and terminal devices can be collectively referred to as communication devices. 110a and 110b in Figure 1 can be called communication devices with network device functions, and 120a-120j in Figure 1 can be called communication devices with terminal device functions.

[0076] The network architecture and business scenarios described in this application are intended to more clearly illustrate the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0077] Based on the communication system shown in Figure 1, Figure 2 illustrates an information transmission process. As shown in Figure 2, the sending end (i.e., the source) obtains the bit sequence to be encoded (i.e., the information bit sequence) through source coding, and then performs channel coding on the information bit sequence to obtain the encoded bit sequence. Correspondingly, the receiving end (i.e., the sink) obtains the symbol sequence to be decoded, performs channel decoding on the symbol sequence to be decoded to obtain the information bit sequence, and then performs source recovery on the information bit sequence to obtain useful information. Here, the sending end is a network device, and the receiving end is a terminal device, or the sending end is a terminal device and the receiving end is a network device; the specific configuration is not limited.

[0078] Since source coding does not consider interference resistance, if the bit sequence output by source coding is directly transmitted through the channel, noise interference in the channel will cause bit errors, reducing communication reliability. Therefore, channel coding, which encodes the bit sequence output by source coding again, can improve communication reliability. There are various channel coding methods, such as LDPC codes. LDPC codes are linear block codes with sparse parity-check matrices, which not only have good performance approaching the Shannon limit but also have low decoding complexity and flexible structure. Channel decoding is the inverse process of channel coding. For example, the main decoding algorithms for LDPC codes are the min-sum (MS) algorithm and the belief propagation (BP) decoding algorithm. The BP algorithm has better decoding performance than the MS algorithm, but because the BP algorithm requires a large amount of information storage and has a complex calculation method, it is not conducive to hardware implementation. Therefore, in practical communication systems, the offset-MS decoding algorithm and the normalized-MS decoding algorithm are used.

[0079] In 5G communication systems, LDPC codes have become the core channel coding scheme for enhanced mobile broadband (eMBB) scenarios due to their high throughput and excellent decoding performance. Mainstream LDPC codes have a quasi-cyclic structure and can be called quasi-cyclic low-density parity check (QC-LDPC) codes. The basis diagram of a QC-LDPC code can be expressed in matrix form, denoted as the basis matrix H. BG The parity-check matrix of the QC-LDPC code is obtained by comparing the basis matrix H. BG It is obtained by lifting and shifting.

[0080] The 3GPP TS 38.212 protocol defines the base diagram of 5G LDPC codes as BG1 and BG2, which have a common matrix structure, as shown in Figures 3A and 3B below.

[0081] Figures 3A and 3B are schematic diagrams of the matrix structure of the LDPC code base map. As shown in Figure 3B, the LDPC code base map can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region can include parts A and B as shown in Figure 3A. Part A corresponds to information bits (or information digits, system bits, etc.), and part B is a square matrix corresponding to the core parity bits (or core parity bits). The core parity can be the parity corresponding to the highest code rate, or it can be a parity with a degree greater than or equal to 2, or it can be the parity node corresponding to the row set with the largest row weight (row weight significantly higher than other rows). The all-zero region can correspond to part C in Figure 3A and is an all-zero matrix. The incremental redundancy region can correspond to part D in Figure 3A. The raptor-like region can correspond to part E in Figure 3A and can be an identity matrix, corresponding to the parity bits of the low-rate extension. Part B and Part E are both verification parts. Part B is defined as the core verification region, and its features can be non-lower triangular coding parts (i.e., values ​​above the diagonal are not all 0) or coding parts with column weight greater than 1. Part E is defined as the extended verification region, and its features can be lower triangular coding parts (i.e., values ​​above the diagonal are all 0) or diagonal matrices.

[0082] However, LDPC codes have certain limitations when applied to URLLC scenarios. For example, the basis matrix of LDPC codes contains trap sets. This special topology can lead to the inability to completely correct certain errors during iterative decoding, resulting in error phasing. Specifically, when channel quality improves (i.e., the signal-to-noise ratio (SNR) increases), the rate of decrease in the block error ratio (BLER) slows down significantly or even stops, making it difficult to meet the requirement of BLER being less than or equal to 10 in URLLC scenarios. -6 The reliability requirements are high. In addition, since the code length and code rate of URLLC are very flexible, different code lengths and code rates correspond to different parity check matrices, and the positions of the trap sets may be different for different parity check matrices. Therefore, it is quite difficult to optimize the trap set for each parity check matrix.

[0083] Based on this, embodiments of this application provide a coding and decoding method and apparatus, which reduces the impact of trap sets by optimizing the shift values ​​corresponding to the elements in the second region of the basis matrix, thereby helping to steadily improve performance under high reliability requirements.

[0084] Here, we will first give a brief introduction to the embodiments of this application:

[0085] The LDPC code basis matrix shown in Figure 3B employs a "raptor-like" structure, which can be gradually extended from a high-rate core matrix to a low-rate matrix. In practical use, as shown in Figure 3B, the first X rows and first Y columns of the basis matrix can be extracted. As the code rate decreases, X and Y gradually increase, and the area of ​​the matrix used also gradually expands. Therefore, as the code rate decreases (a lower code rate means a larger proportion of parity bits), the number of parity check equations (more rows) and the number of variable nodes (more columns) are usually increased to improve error correction capability. This design significantly enhances the minimum Hamming distance (i.e., code distance) of the code, making the differences between codewords greater, thus more reliably distinguishing and correcting errors.

[0086] As the code rate decreases, the requirements for code distance become more stringent in low bit error rate (BER) scenarios. This is because, at low BERs, insufficient code distance can cause error correction performance to easily enter an "error plane," where the BER no longer decreases significantly with improved channel quality, creating a performance bottleneck. Therefore, in this embodiment, the shift values ​​corresponding to the elements in the incremental redundancy region of the base matrix are optimized to maximize the rate at which the code distance increases with the number of rows, reduce the impact of trap sets, and ensure that the code distance in the low-to-medium code rate region meets the requirements. This is beneficial for maintaining stable performance improvement even under high reliability requirements.

[0087] The method provided in this application embodiment will be described in detail below with reference to specific embodiments. The method provided in this application embodiment involves a first communication device and / or a second communication device. The first communication device is a signal transmitting end, and the second communication device is a signal receiving end. Unless otherwise specified, the "first communication device" in this application can refer to a first communication device (e.g., network device, terminal device, encoding device, etc.), a component used in the first communication device (e.g., processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the communication device functions. Similarly, the "second communication device" in this application can refer to a second communication device (e.g., terminal device, network device, decoding device, etc.), a component used in the second communication device (e.g., processor, chip, or chip system, etc.), or a logic module or software capable of implementing all or part of the communication device functions. The component used in the communication device can be a component within the communication device, or it can be independent of the communication device but coupled to it. For example, the first communication device is a network device and the second communication device is a terminal device; or, the first communication device is a terminal device and the second communication device is a network device.

[0088] This application involves code length, information bit sequence length, and code rate, and these terms are explained below. The length of the information bit sequence is the number of information bits to be transmitted. These information bits may or may not include cyclic redundancy check (CRC) bits; there is no restriction. Code length refers to the length of the (to be) transmitted bits, which can be the number of transmitted bits corresponding to the modulated symbol. Code rate is the ratio of the number of information bits to the number of transmitted bits. Code length, information bit length, and code rate can be pre-configured by higher-layer signaling, medium access control (MAC) layer, or downlink physical layer signals, and they can also be directly obtained and calculated by the transceiver. More specifically, the code length can be determined by the frame structure, number of layers, and modulation scheme of the encoded and transmitted information bits; the code rate can be indicated in the above ways or given in the modulation and coding scheme (MCS) table.

[0089] Figure 4 is a flowchart illustrating the method provided in this embodiment. As shown in Figure 4, the process may include:

[0090] S401, the first communication device determines the shift value corresponding to each element in the basis matrix of the LDPC code according to the boosting factor.

[0091] For example, the first communication device determines the base matrix of the LDPC code based on the code length and / or code rate. The specific implementation can refer to existing protocols; for example, the determined base matrix may include the first X rows and first Y columns of BG1, or the first X rows and first Y columns of BG2. Then, the first communication device determines the lifting factor Zc based on the code length and the base matrix, and determines the shift value matrix S = [P] based on the lifting factor Zc. a,b The dimension of the shift value matrix S and the basis matrix H BG Similarly, the element P in the shift value matrix a,b The basis matrix H BG The shift value corresponding to the element in the a-th row and b-th column is the shift value matrix, which includes the shift values ​​corresponding to each element in the base matrix.

[0092] (1) A description of the specific implementation of “determining the shift value corresponding to each element in the basis matrix based on the lifting factor Zc”.

[0093] For example, the first communication device determines the set of lifting factors to which the lifting factor Zc belongs based on the lifting factor list, and then determines the shift value corresponding to each element in the basis matrix based on the shift value list corresponding to the lifting factor set. The lifting factor list and the shift value list can be pre-configured or predefined. Table 1 is an example of a lifting factor list.

[0094] Table 1: List of Enhancement Factors

[0095] Each row of the boosting value list corresponds to a boosting factor set, and the j-th row of the boosting factor list... Where a j ∈{2,3,5,7,9,11,13,15}, max(k j )∈{7,7,6,5,5,5,4,4}. For example, if j=0, the index of the lifting factor set corresponding to the j-th row is 0, a j =2, the promotion factor set includes {2, 4, 8, 16, 32, 64, 128, 256}; for example, j=1, the index of the promotion factor set corresponding to the j-th row is 1, a j =3, the set of boosting factors includes {3, 6, 12, 24, 48, 96, 192, 384}.

[0096] Table 2 is a list of the edges and shift values ​​for a portion of the basis matrix, where the first two columns correspond to the basis matrix of that portion, and the last eight columns correspond to the shift values ​​of that portion.

[0097] Table 2: List of edges and shift values ​​for a portion of the basis matrix

[0098] The row index of the lifting factor list corresponds one-to-one with the column index of the shift value. That is, each row of the lifting factor list corresponds to a set of shift values ​​for each lifting factor, and multiple lifting factors share the same set of shift values.

[0099] As shown in Table 2, set index i LS=0, the promotion factor {2, 4, 8, 16, 32, 64, 128, 256} corresponds to the shift value {250, 69, 226, 159, 100, 10, 59, 229, 110, 191, 9, 195, 23, 190, 35, 239, 31, 1, 0}. The shift values ​​given here are just examples, and the actual shift values ​​set may be different from those here. Assuming Zc = 4, the shift values ​​corresponding to the elements with a value of 1 in the 0th row of the basis matrix are 250 mod 4, 69 mod 4, 226 mod 4, 159 mod 4, 100 mod 4, 10 mod 4, 59 mod 4, 229 mod 4, 110 mod 4, 191 mod 4, 9 mod 4, 195 mod 4, 23 mod 4, 190 mod 4, 35 mod 4, 239 mod 4, 31 mod 4, 1 mod 4, 0 mod 4, which are 2, 1, 2, 3, 0, 2, 3, 1, 2, 3, 1, 3, 3, 2, 3, 3, 3, 1, 0. For each element with a value of 0 in the 0th row (row index 0) of the basis matrix, its corresponding shift value can be recorded as -1. In this way, the shift values ​​corresponding to each element in the 0th row of the basis matrix can be obtained, and the shift values ​​corresponding to each element in the other rows of the basis matrix can be obtained in the same way.

[0100] (2) Describe the shift values ​​corresponding to the elements in the basis matrix.

[0101] In this embodiment, the shift values ​​corresponding to the elements in the basis matrix satisfy preset conditions.

[0102] For example, some or all of the shift values ​​in Table 2 above can be set according to the conditions that need to be met.

[0103] For example, the shift values ​​corresponding to the elements in the basis matrix satisfy a preset condition, including: the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix satisfy the preset condition. For example, the first value is not an integer multiple of the boost factor, and the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix. The first region of the basis matrix can be understood as the trap set of the basis matrix.

[0104] For example, at least two non-zero elements in the first region of the aforementioned basis matrix may include a first non-zero element and a second non-zero element located in the same row, and at least two non-zero elements in the second region of the aforementioned basis matrix may include a third non-zero element and a fourth non-zero element. The first and third non-zero elements are located in the same column, and the second and fourth non-zero elements are located in the same column. In this case, the first value is related to the shift values ​​corresponding to the first, second, third, and fourth non-zero elements. For example, the first value satisfies the following formula: Q = V3 - V4 + V2 - V1

[0105] Where Q represents the first value, V1 represents the shift value corresponding to the first non-zero element, V2 represents the shift value corresponding to the second non-zero element, V3 represents the shift value corresponding to the third non-zero element, and V4 represents the shift value corresponding to the fourth non-zero element. In other words, the first value is the sum of the difference between the shift values ​​corresponding to the first and second non-zero elements and the difference between the shift values ​​corresponding to the third and fourth non-zero elements.

[0106] It is understood that the embodiments of this application do not strictly limit the order of operations for the above formula (i.e., Q = V3 - V4 + V2 - V1). It can be implemented using the default left-to-right continuous arithmetic operations, or it can be implemented using grouped operations, such as Q = (V3 - V4) - (V1 - V2) or Q = (V3 - V1) - (V4 - V2), etc., which are mathematically equivalent transformations. Therefore, any variations that are mathematically equivalent to the above formula, including but not limited to changing the order of operations by adding parentheses, adjusting the arrangement of variables, or introducing intermediate steps, should be considered to fall within the scope of this application. Other formulas involved in the embodiments of this application can be referred to here.

[0107] The first value is not an integer multiple of the promotion factor; it can mean that the remainder when the first value is divided by the promotion factor is greater than 0, for example, expressed as Q mod (Z). C Q > 0, or it can also be expressed as Q > 0 mod (Z) C In this application embodiment, "Q>0mod(Z)" will be used. C In this notation, Q represents the first value and mod represents the modulo operation.

[0108] (2.1) First region and second region

[0109] The first region includes the first element in the N columns of the base matrix. The first element is located in the first M rows of the base matrix, and the first element can be understood as multiple elements. The second region includes the second element in the N columns of the base matrix. The second element is located in rows M+d1 to M+d2 of the base matrix, and the second element can be understood as multiple elements. M is an integer greater than 2, N is an integer greater than or equal to M, d1 and d2 are integers greater than or equal to 1, and d1 is less than or equal to d2.

[0110] For example, it can also be described as follows: the first region includes multiple first elements in the N columns of the base matrix, and the second region includes multiple second elements in the N columns of the base matrix.

[0111] Column N:

[0112] The columns of the basis matrix include information columns and parity columns, or the columns of the basis matrix consist of information columns and parity columns. Information columns: Corresponding to information bits (or information bits, system bits, etc.), these are the columns corresponding to part A (see Figure 3A). Parity columns: Corresponding to parity bits (or parity digits, etc.), these are the columns corresponding to parts B and C (see Figure 3A), and may include core parity columns and extended parity columns. Core parity columns are the columns corresponding to part B, and extended parity columns are the columns corresponding to parts C or E. Extended parity columns can also be called raptor-like columns. Alternatively, core parity columns are the parity columns in part B with a column weight greater than 1 (part B has 1 elements both above and below the diagonal), and extended parity columns are the remaining parity columns excluding the core parity columns.

[0113] Column N represents a portion of the information columns and core check columns of the base matrix. Column N can be continuous, for example, including columns 3 / 4 / 5 / 6 of the information columns and core check columns of the base matrix; or it can be non-contiguous, for example, including columns 3 / 5 / 8 / 10 of the information columns and core check columns of the base matrix. For example, a base matrix (such as BG1) has 22 information columns and 4 core check columns, meaning it has a total of 26 columns, and the aforementioned column N is a portion of these 26 columns. As another example, a base matrix (such as BG2) has 10 information columns and 4 core check columns, meaning it has a total of 14 columns, and the aforementioned column N is a portion of these 14 columns.

[0114] Understandably, assuming columns N include the 3rd, 4th, 5th, and 6th columns of the base matrix, the first region is obtained by sorting the first elements of columns N in ascending order of their indices. For example, the first region's first column includes the first element of the 3rd column, the second column includes the first element of the 4th column, the third column includes the first element of the 5th column, and the fourth column includes the first element of the 6th column. In this case, the second region is obtained by sorting the second elements of columns N in ascending order of their indices. Alternatively, the first region can be obtained by sorting the first elements of columns N in descending order of their indices. For example, the first region's first column includes the first element of the 6th column, the second column includes the first element of the 5th column, the third column includes the first element of the 4th column, and the fourth column includes the first element of the 3rd column. In this case, the second region is obtained by sorting the second elements of columns N in descending order of their indices. Besides the sorting methods described here, such as "sorting by index of N columns from low to high" or "sorting by index of N columns from high to low," there are many other sorting methods. For example, the first column of the first region may include the first element of the fourth column of the base matrix, the second column of the first region may include the first element of the fifth column of the base matrix, the third column of the first region may include the first element of the third column of the base matrix, and the fourth column of the first region may include the first element of the sixth column of the base matrix. The sorting of the N columns in this embodiment is not limited. Therefore, the "x-th column of N columns" mentioned in this embodiment can refer to the x-th column after sorting the N columns by index from low to high, or it can refer to the x-th column after sorting the N columns in other ways; the specific method is not limited.

[0115] First M lines:

[0116] The first M rows of the base matrix are located in the high bitrate region of the base matrix. For example, if the high bitrate region of the base matrix includes 4 rows, then M is greater than 2 and less than or equal to 4. The first element is located in the first M rows of the base matrix. Specifically, the first element can be located in the M1th row of the first M rows of the base matrix. This M1th row can be continuous or non-contiguous. M1 is an integer greater than 2 and less than or equal to M, and N = M1 + 1.

[0117] For example, when M=3, M1=M, and the first element is located in the first 3 rows of the base matrix, that is, the first element is located in the 1st, 2nd, and 3rd rows of the base matrix. As another example, when M=4, the first element is located in the first 4 rows of the base matrix. If M1=M, then the first element is located in the 1st, 2nd, 3rd, and 4th rows of the base matrix. If M1 is less than M, then the first element is located in the 1st, 2nd, and 3rd rows of the base matrix (optionally, the element in the 4th row of the N columns of the base matrix has a value of 0), or the first element is located in the 1st, 2nd, and 4th rows of the base matrix (optionally, the element in the 3rd row of the N columns of the base matrix has a value of 0), or the first element is located in the 2nd, 3rd, and 4th rows of the base matrix (optionally, the element in the 1st row of the N columns of the base matrix has a value of 0). The specific details are not limited and will not be listed individually.

[0118] It is understood that the aforementioned M1 rows can be sorted from low to high according to their index, or they can be sorted from high to low according to their index. The sorting of M1 rows in this embodiment is not limited. Therefore, the "y-th row in M1" mentioned in this embodiment can refer to the y-th row after sorting M1 rows from low to high according to their index, or it can refer to the y-th row after sorting M1 rows in other ways; the specific meaning is not limited.

[0119] Lines M+d1 to M+d2:

[0120] Rows M+d1 to M+d2 of the base matrix are located in the incremental redundancy region of the base matrix. For example, if the incremental redundancy region of the base matrix includes 38 rows, then rows M+d1 to M+d2 of the base matrix are part or all of these 38 rows. The second element is located in rows M+d1 to M+d2 of the base matrix. Specifically, the second element can be located in row M2 of rows M+d1 to M+d2 of the base matrix. These M2 rows can be consecutive or non-consecutive, and M2 is an integer less than or equal to d2-d1.

[0121] For example, if M = 4, d1 = 1, d2 = 42, and the second element is located in rows 5 to 42 of the base matrix, if M2 is less than d2 - d1, then the second element is located in rows 5, 6, 7, and 8 of the base matrix (i.e., M2 = 4, and rows M2 are consecutive), or in rows 5, 6, 9, and 10 of the base matrix (i.e., M2 = 4, and rows M2 are discontinuous), or in rows 5, 6, 7, 8, and 9 of the base matrix (i.e., M2 = 5, and rows M2 are consecutive), or in rows 7, 9, 10, 12, and 15 of the base matrix (i.e., M2 = 5, and rows M2 are discontinuous). Specific possibilities are not limited and will not be listed individually.

[0122] Figure 5 shows several possible examples of the first and second regions:

[0123] As shown in Figure 5(a), N=4, the N columns of the basis matrix are continuous, the first region includes the first element in the N columns of the basis matrix, and the row containing the first element is continuous; the second region includes the second element in the N columns of the basis matrix, and the row containing the second element is continuous.

[0124] As shown in Figure 5(b), N=4, the N columns of the basis matrix are discontinuous, the first region includes the first element in the N columns of the basis matrix, and the row containing the first element is discontinuous; the second region includes the second element in the N columns of the basis matrix, and the row containing the second element is continuous.

[0125] As shown in Figure 5(c), N=4, the N columns of the basis matrix are discontinuous, the first region includes the first element in the N columns of the basis matrix, and the row containing the first element is discontinuous; the second region includes the second element in the N columns of the basis matrix, and the row containing the second element is discontinuous.

[0126] As shown in Figure 5(d), N=5, the N columns of the basis matrix are continuous, the first region includes the first element in the N columns of the basis matrix, and the row containing the first element is continuous; the second region includes the second element in the N columns of the basis matrix, and the row containing the second element is continuous.

[0127] As shown in Figure 5(e), N=5, the N columns of the basis matrix are not continuous, the first region includes the first element in the N columns of the basis matrix, and the row containing the first element is continuous; the second region includes the second element in the N columns of the basis matrix, and the row containing the second element is continuous.

[0128] It is understandable that the first region and the second region mentioned above can be understood as a region pair. The basis matrix can include multiple region pairs, that is, the basis matrix includes multiple first regions and multiple second regions. For example, the basis matrix includes first region A1 and second region A2, and also includes first region B1 and second region B2.

[0129] (2.2) First value (M1=3, N=4)

[0130] For "M1=3, N=4", in one example, the first and third non-zero elements are located in the 3rd column of column N, the second and fourth non-zero elements are located in the 4th column of column N, and the first and second non-zero elements are located in the 3rd row of row M1. The shift value corresponding to the element in the u-th row and v-th column of the first region can be denoted as xuv, where u = 1, 2, 3, and v = 1, 2, 3, 4. The first value is not an integer multiple of the promotion factor; it is related to the shift values ​​corresponding to the first, second, third, and fourth non-zero elements, as shown in Formula 1 below: Q = SV3 – SV4 + (x34 – x33) = (SV3 – SV4) – (x33 – x34) > 0 mod (Z C )

[0131] Where Q represents the first value, x33 represents the shift value corresponding to the first non-zero element (located in the 3rd row of row M1 and the 3rd column of column N), x34 represents the shift value corresponding to the second non-zero element (located in the 3rd row of row M1 and the 4th column of column N), SV3 represents the shift value corresponding to the third non-zero element, and SV4 represents the shift value corresponding to the fourth non-zero element.

[0132] In another example, the first and third non-zero elements are located in column 1 of column N, the second and fourth non-zero elements are located in column 2 of column N, and the first and second non-zero elements are located in row 2 of row M1. The first value is not an integer multiple of the lifting factor; the first value is related to the shift values ​​corresponding to the first, second, third, and fourth non-zero elements, as shown in Formula 2 below: Q = SV1 – SV2 + (x22 – x21) = (SV1 – SV2) – (x21 – x22) > 0 mod (Z C )

[0133] Where Q represents the first value, x21 represents the shift value corresponding to the first non-zero element (located in the 2nd row of row M1 and the 1st column of column N), x22 represents the shift value corresponding to the second non-zero element (located in the 2nd row of row M1 and the 2nd column of column N), SV1 represents the shift value corresponding to the third non-zero element, and SV2 represents the shift value corresponding to the fourth non-zero element.

[0134] Formulas 1 and 2 listed above are merely examples. The specific implementation of these two formulas is described below.

[0135] Assume that N columns correspond to N sets, and the elements in each set are obtained by shifting one or more non-zero elements in the first region. The second region contains at least two non-zero elements in any row, including the non-zero element in column p and the non-zero element in column q of the N columns. Then, the following condition is satisfied: Q = SVp – SVq + (ep – eq) > 0 mod (Z). C )

[0136] Where Q represents the first value, SVp represents the shift value corresponding to the non-zero element in the p-th column of N columns, SVq represents the shift value corresponding to the non-zero element in the q-th column of N columns, ep represents any element in the set corresponding to the p-th column, and eq represents any element in the set corresponding to the q-th column. Formulas 1 and 2 listed above are equivalent to "(SVp–SVq)+(ep–eq)>0mod(Z)". C Two specific examples of ")". Among them, SVp–SVq+(ep–eq)>0mod(Z C It can also be transformed into: SVp–SVq+ep–eq>0mod(Z) C ), or SVp–SVq–(eq–ep)>0mod(Z C (Specifically, no limit is specified.)

[0137] In this embodiment, the shift values ​​corresponding to each non-zero element in the first region can refer to the prior art. That is, the shift values ​​corresponding to each non-zero element in the second region can be optimized to satisfy: (SVp–SVq)+(ep–eq)>0mod(Z) C This maximizes the speed at which the code distance increases with the number of lines, reduces the impact of the trap set (i.e., the first region), ensures that the code distance in the low-to-medium code rate region meets the requirements, and guarantees stable performance improvement even under high reliability requirements.

[0138] (2.3) For the specific case of "M1=3, N=4"

[0139] For example, in scenario 1, the first region is:

[0140] In this case, the first value is not an integer multiple of the boost factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix. Specifically, it includes at least one of the following 24 formulas: Q=SV1-SV2+(x22-x21)>0mod(Z C ); Q=SV1-SV2+(x13-x14+x22-x21+x34-x33)>0mod(ZC ); Q=SV1-SV2+(x14-x13+x22-x21+x33-x34)>0mod(Z C ); Q=SV1-SV2+(x22-x21)>0mod(Z C ); Q=SV1-SV3+(x13-x11)>0mod(Z C ); Q=SV1-SV3+(x13-x12+x22-x21)>0mod(Z C ); Q=SV1-SV3+(x14-x11+x33-x34)>0mod(Z C ); Q=SV1-SV3+(x14-x12+x22-x21+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x13-x11+x21-x22)>0mod(Z C ); Q=SV2-SV3+(x13-x12)>0mod(Z C ); Q=SV2-SV3+(x14-x11+x21-x22+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x14-x12+x33-x34)>0mod(Z C ); Q=SV2-SV4+(x13-x11+x21-x22+x34-x33)>0mod(Z C ); Q=SV2-SV4+(x13-x12+x34-x33)>0mod(Z C ); Q=SV2-SV4+(x14-x11+x21-x22)>0mod(Z C ); Q=SV2-SV4+(x14-x12)>0mod(Z C ); Q=SV1-SV4+(x13-x11+x34-x33)>0mod(Z C ); Q=SV1-SV4+(x13-x12+x22-x21+x34-x33)>0mod(Z C ); Q=SV1-SV4+(x14-x11)>0mod(Z C ); Q=SV1-SV4+(x14-x12+x22-x21)>0mod(Z C ); Q=SV3–SV4+[(x11+x22+x34)–(x11+x22+x33)]=SV3-SV4+(x34-x33)>0mod(Z C); Q=SV3-SV4+(x11-x12+x22-x21+x34-x33)>0mod(Z C ); Q=SV3-SV4+(x12-x11+x21-x22+x34-x33)>0mod(Z C ); Q=SV3–SV4+[(x12+x21+x34)–(x12+x21+x33)]=SV3-SV4+(x34-x33)>0mod(Z C ).

[0141] As one possible implementation, the N columns of the first region correspond to N sets, namely sets S1 to S4 (i.e., N = 4), and then according to the formula Q = SVp – SVq + (ep – eq) > 0 mod (Z C The above 24 formulas can be determined by considering sets S1 to S4. The specific implementation of determining the N sets is not limited in this application embodiment. For example, for the first region in case 1, the N sets are: S1 = [x13 + x22 + x34, x14 + x22 + x33]; S2 = [x13 + x21 + x34, x14 + x21 + x33]; S3 = [x11 + x22 + x34, x12 + x21 + x34]; S4 = [x11 + x22 + x33, x12 + x21 + x33].

[0142] In other words, given the sets S1 to S4 corresponding to the first region, the formula that the first value must satisfy can be determined.

[0143] Furthermore, for example, if the elements of one row (called row h1) in the second region are: 1, 1, 0, 0, then the first value is not an integer multiple of the lifting factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix. Specifically, it includes at least one of the following (since S1 includes two elements, namely x13+x22+x34 and x14+x22+x33, and S2 includes two elements, namely x13+x21+x34 and x14+x21+x33, therefore ep can be any of the two elements included in S1, and eq can be any of the two elements included in S2, for a total of 4 formulas): Q=SV1–SV2+[(x13+x22+x34)–(x13+x21+x34)]=SV1-SV2+(x22-x21)>0mod(Z C ); Q=SV1-SV2+(x13-x14+x22-x21+x34-x33)>0mod(Z C); Q=SV1-SV2+(x14-x13+x22-x21+x33-x34)>0mod(Z C ); Q=SV1–SV2+[(x14+x22+x33)–(x14+x21+x33)]=SV1-SV2+(x22-x21)>0mod(Z C ).

[0144] The first and fourth formulas are essentially the same: Q = SV1 - SV2 + (x22 - x21) > 0 mod (Z) C ).

[0145] If the elements of one row (called row h2) in the second region are 0, 0, 1, 1, then the first value is not an integer multiple of the lifting factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix, specifically including at least one of the following: Q = SV3 – SV4 + [(x11 + x22 + x34) – (x11 + x22 + x33)] = SV3 - SV4 + (x34 - x33) > 0 mod (Z C ); Q=SV3-SV4+(x11-x12+x22-x21+x34-x33)>0mod(Z C ); Q=SV3-SV4+(x12-x11+x21-x22+x34-x33)>0mod(Z C ); Q=SV3–SV4+[(x12+x21+x34)–(x12+x21+x33)]=SV3-SV4+(x34-x33)>0mod(Z C ).

[0146] The first and fourth formulas are essentially the same: Q = SV3 - SV4 + (x34 - x33) > 0 mod (Z) C ).

[0147] If the elements of one row (called row h3) in the second region are 0, 1, 1, 0, then the first value is not an integer multiple of the promotion factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix, specifically including at least one of the following: Q = SV2 - SV3 + (x13 - x11 + x21 - x22) > 0 mod (Z C ); Q=SV2-SV3+(x13-x12)>0mod(Z C); Q=SV2-SV3+(x14-x11+x21-x22+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x14-x12+x33-x34)>0mod(Z C ).

[0148] If the elements of one row (called row h4) in the second region are: 1, 0, 1, 0, then the first value is not an integer multiple of the lifting factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix, specifically including at least one of the following: Q = SV1 - SV3 + (x13 - x11) > 0 mod (Z C ); Q=SV1-SV3+(x13-x12+x22-x21)>0mod(Z C ); Q=SV1-SV3+(x14-x11+x33-x34)>0mod(Z C ); Q=SV1-SV3+(x14-x12+x22-x21+x33-x34)>0mod(Z C ).

[0149] If the elements of one row (called row h5) in the second region are: 0, 1, 0, 1, then the first value is not an integer multiple of the lifting factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix, specifically including at least one of the following: Q = SV2 - SV4 + (x13 - x11 + x21 - x22 + x34 - x33) > 0 mod (Z C ); Q=SV2-SV4+(x13-x12+x34-x33)>0mod(Z C ); Q=SV2-SV4+(x14-x11+x21-x22)>0mod(Z C ); Q=SV2-SV4+(x14-x12)>0mod(Z C ).

[0150] If the elements of one row (called row h6) in the second region are: 1, 0, 0, 1, then the first value is not an integer multiple of the lifting factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix, specifically including at least one of the following: Q = SV1 - SV4 + (x13 - x11 + x34 - x33) > 0 mod (Z C); Q=SV1-SV4+(x13-x12+x22-x21+x34-x33)>0mod(Z C ); Q=SV1-SV4+(x14-x11)>0mod(Z C ); Q=SV1-SV4+(x14-x12+x22-x21)>0mod(Z C ).

[0151] If the elements of one row in the second region (called row h7) are: 1, 1, 1, 0, then the first value is not an integer multiple of the lifting factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix. Specifically, it includes at least one of the following (i.e., at least one of the 12 formulas corresponding to rows h1, h3, and h4 above, where two of the 12 formulas are the same, so it can also be understood as 11 formulas): Q=SV1-SV2+(x22-x21)>0mod(Z C ); Q=SV1-SV2+(x13-x14+x22-x21+x34-x33)>0mod(Z C ); Q=SV1-SV2+(x14-x13+x22-x21+x33-x34)>0mod(Z C ); Q=SV1-SV3+(x13-x11)>0mod(Z C ); Q=SV1-SV3+(x13-x12+x22-x21)>0mod(Z C ); Q=SV1-SV3+(x14-x11+x33-x34)>0mod(Z C ); Q=SV1-SV3+(x14-x12+x22-x21+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x13-x11+x21-x22)>0mod(Z C ); Q=SV2-SV3+(x13-x12)>0mod(Z C ); Q=SV2-SV3+(x14-x11+x21-x22+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x14-x12+x33-x34)>0mod(Z C ).

[0152] If the elements of one row (called row h8) in the second region are 1, 1, 1, 1, then the first value is not an integer multiple of the lifting factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix. Specifically, it includes at least one of the above 24 formulas, which will not be listed here.

[0153] It is understood that the second region may include one or more rows from h1 to h8 mentioned above. The rows h1 to h8 listed above are only some possible examples; other possible examples can be found above and will not be listed again. In other words, for the first region in scenario 1 above, based on the column containing the non-zero elements in the same row of the second region, it is possible to determine which of the 24 formulas mentioned above must be satisfied.

[0154] Scenario 2, the first region is:

[0155] In this case, the first value is not an integer multiple of the boost factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix. Specifically, it includes at least one of the following 24 formulas: Q = SV1 - SV2 + (x12 - x11) > 0 mod (Z C ); Q=SV1-SV2+(x12-x13+x24-x21+x33-x34)>0mod(Z C ); Q=SV1-SV2+(x13-x11+x22-x24+x34-x33)>0mod(Z C ); Q=SV1-SV2+(x22-x21)>0mod(Z C ); Q=SV1-SV3+(x12-x11+x24-x22+x33-x34)>>0mod(Z C ); Q=SV1-SV3+(x24-x21+x33-x34)>0mod(Z C ); Q=SV1-SV3+(x13-x11)>0mod(Z C ); Q=SV1-SV3+(x13-x12+x22-x21)>0mod(Z C ); Q=SV1-SV4+(x12-x11+x24-x22)>0mod(Z C ); Q=SV1-SV4+(x24-x21)>0mod(Z C); Q=SV1-SV4+(x13-x11+x22-x22+x34-x33)>0mod(Z C ); Q=SV1-SV4+(x13-x12+x22-x21+x34-x33)>0mod(Z C ); Q=SV2-SV3+(x11-x11+x24-x22+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x11-x12+x24-x21+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x13-x11+x21-x22)>0mod(Z C ); Q=SV2-SV3+(x13-x12)>0mod(Z C ); Q=SV2-SV4)+(x24-x22)>0mod(Z C ); Q=SV2-SV4+(x11-x12+x24-x21)>0mod(Z C ); Q=(SV2-SV4+(x13-x11+x21-x22+x34-x33)>0mod(Z C ); Q=(SV2-SV4+(x13-x12+x21-x21+x34-x33)>0mod(Z C ); Q=SV3-SV4+(x34-x33)>0mod(Z C ); Q=SV3-SV4+(x11-x12+x22-x21+x34-x33)>0mod(Z C ); Q=SV3-SV4+(x12-x11+x21-x22+x34-x33)>0mod(Z C ); Q=SV3-SV4+(x34-x33)>0mod(Z C );

[0156] As one possible implementation, the N columns of the first region correspond to N sets, namely sets S1 to S4 (i.e., N = 4), and then according to the formula Q = SVp – SVq + (ep – eq) > 0 mod (Z CThe above 24 formulas can be determined by considering sets S1 to S4. The specific implementation of determining the N sets is not limited in this application embodiment. For example, for the first region in case 2, the N sets are: S1 = [x12 + x24 + x33, x13 + x22 + x34]; S2 = [x11 + x24 + x33, x13 + x21 + x34]; S3 = [x11 + x22 + x34, x12 + x21 + x34]; S4 = [x11 + x22 + x33, x12 + x21 + x33].

[0157] Furthermore, for example, based on the columns containing the non-zero elements in the same row of the second region, it can be determined which of the 24 formulas the first value needs to satisfy. For example, if the columns containing the non-zero elements in the same row of the second region are columns 1 and 2, then the first value must satisfy at least one of the first four formulas of the 24 formulas. For details, please refer to the description in Case 1.

[0158] Scenario 3, the first region is:

[0159] In this case, the first value is not an integer multiple of the boost factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix. Specifically, it includes at least one of the following 33 formulas: Q=SV1-SV2+(x12-x11)>0mod(Z C ); Q=SV1-SV2+(x12-x13+x24-x21+x33-x34)>0mod(Z C ); Q=SV1-SV2+(x12-x14+x24-x21)>0mod(Z C ); Q=SV1-SV2+(x13-x11+x22-x24+x34-x33)>0mod(Z C ); Q=SV1-SV2+(x22-x21)>0mod(Z C ); Q=SV1-SV2+(x13-x14+x22-x21+x34-x33)>0mod(Z C ); Q=SV1-SV2+(x14-x11+x22-x24)>0mod(Z C ); Q=SV1-SV2+(x14-x13+x22-x21+x33-x34)>0mod(Z C ); Q=SV1-SV2+(x22-x21)>0mod(Z C); Q=SV1-SV3+(x12-x11+x24-x22+x33-x34)>0mod(Z C ); Q=SV1-SV3+(x24-x21+x33-x34)>0mod(Z C ); Q=SV1-SV3+(x13-x11)>0mod(Z C ); Q=SV1-SV3+(x13-x12+x22-x21)>0mod(Z C ); Q=SV1-SV3+(x14-x11+x33-x34)>0mod(Z C ); Q=SV1-SV3+(x14-x12+x22-x21+x33-x34)>0mod(Z C ); Q=SV1-SV4+(x12-x11+x24-x22)>0mod(Z C ); Q=SV1-SV4+(x24-x21)>0mod(Z C ); Q=SV1-SV4+(x13-x11+x34-x33)>0mod(Z C ); Q=SV1-SV4+(x13-x12+x22-x21+x34-x33)>0mod(Z C ); Q=SV1-SV4+(x14-x11)>0mod(Z C ); Q=SV1-SV4+(x14-x12+x22-x21)>0mod(Z C ); Q=SV2-SV3+(x24-x22+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x11-x12+x24-x21+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x13-x11+x21-x22)>0mod(Z C ); Q=SV2-SV3+(x13-x12)>0mod(Z C ); Q=SV2-SV3+(x14-x11+x21-x22+x33-x34)>0mod(Z C ); Q=SV2-SV3+(x14-x12+x33-x34)>0mod(Z C ); Q=SV2-SV4+(x24-x22)>0mod(Z C ); Q=SV2-SV4+(x11-x12+x24-x21)>0mod(Z C); Q=SV2-SV4+(x13-x11+x21-x22+x34-x33)>0mod(Z C ); Q=SV2-SV4+(x13-x12+x34-x33)>0mod(Z C ); Q=SV2-SV4+(x14-x11+x21-x22)>0mod(Z C ); Q=SV2-SV4+(x14-x12)>0mod(Z C ); Q=SV3-SV4+(x34-x33)>0mod(Z C ); Q=SV3-SV4+(x11-x12+x22-x21+x34-x33)>0mod(Z C ); Q=SV3-SV4+(x12-x11+x21-x22+x34-x33)>0mod(Z C ); Q=SV3-SV4+(x34-x33)>0mod(Z C ).

[0160] As one possible implementation, the N columns of the first region correspond to N sets, namely sets S1 to S4 (i.e., N = 4), and then according to the formula Q = SVp – SVq + (ep – eq) > 0 mod (Z C The above 33 formulas can be determined by considering sets S1 to S4. The specific implementation of determining the N sets is not limited in this application embodiment. For example, for the first region in case 3, the N sets are: S1 = [x12+x24+x33, x13+x22+x34, x14+x22+x33]; S2 = [x11+x24+x33, x13+x21+x34, x14+x21+x33]; S3 = [x11+x22+x34, x12+x21+x34]; S4 = [x11+x22+x33, x12+x21+x33].

[0161] Furthermore, for example, based on the columns containing the non-zero elements in the same row of the second region, it can be determined which of the 33 formulas the first value needs to satisfy. For example, if the columns containing the non-zero elements in the same row of the second region are columns 1 and 2, then the first value must satisfy at least one of the first 9 formulas of the 33 formulas. For details, please refer to the description in Case 1.

[0162] The following will give other possible cases for the first region and N sets (such as cases 4 to 7). The specific formulas will not be listed one by one. Please refer to the descriptions of cases 1 to 3.

[0163] Scenario 4, the first region is:

[0164] Correspondingly, the N sets are: S1 = [x12+x23+x34,x12+x24+x33,x14+x23+x32]; S2 = [x11+x23+x34,x11+x24+x33,x14+x21+x33]; S3 = [x11+x24+x32,x12+x21+x34,x14+x21+x32]; S4 = [x11+x23+x32,x12+x21+x33].

[0165] Scenario 5, the first region is:

[0166] Correspondingly, the N sets are as follows: S1 = [x12+x23+x34,x12+x24+x33,x13+x22+x34,x14+x22+x33]; S2 = [x11+x23+x34,x11+x24+x33,x13+x21+x34,x14+x21+x33]; S3 = [x11+x22+x34,x12+x21+x34]; S4 = [x11+x22+x33,x12+x21+x33].

[0167] Scenario 6, the first region is:

[0168] Correspondingly, the N sets are as follows: S1 = [x12+x23+x34,x12+x24+x33,x13+x24+x32,x14+x23+x32]; S2 = [x11+x23+x34,x11+x24+x33,x13+x21+x34,x14+x21+x33]; S3 = [x11+x24+x32,x12+x21+x34,x14+x21+x32]; S4 = [x11+x23+x32,x12+x21+x33,x13+x21+x32].

[0169] Scenario 7, the first region is:

[0170] Correspondingly, the N sets are as follows: S1 = [x12+x23+x34,x12+x24+x33,x13+x22+x34,x13+x24+x32,x14+x22+x33,x14+x23+x32]; S2 = [x11+x23+x34,x11+x24+x33,x13+x21+x34,x14+x21+x33]; S3 = [x11+x22+x34,x11+x24+x32,x12+x21+x34,x14+x21+x32]; S4 = [x11+x22+x33,x11+x23+x32,x12+x21+x33,x13+x21+x32].

[0171] It is understandable that the basis matrix can include the first region as shown in at least one of the cases 1 to 7 above. When the basis matrix includes the first region as shown in multiple cases 1 to 7 above, the shift values ​​corresponding to each element in the second region can be optimized for some or all of these multiple cases. There is no limit to the number of cases to be optimized, nor is there a limit to which cases among the multiple cases to be optimized; for example, cases with smaller numbers can be prioritized for optimization. For example, if the basis matrix includes the first region as shown in cases 1 to 7 above, and assuming that the shift values ​​corresponding to each element in the second region are optimized for each of these 7 cases, there are a total of W1 formulas for the 7 cases (case 1 corresponds to 24 formulas, case 2 corresponds to 24 formulas, and cases 3-7 have a larger number of formulas due to the increased number of elements in the set), analysis reveals that some formulas appear repeatedly among these W1 formulas, meaning that there are high-frequency formulas among the W1 formulas. For example, SV3–SV4+(x34–x33)>0mod(Z C (i.e., Formula 1 above), appears 14 times, and this formula appears in all 7 of the above cases. Another example is SV1–SV2+(x22–x21)>0mod(Z C (i.e., formula 2 above), repeated 12 times. In addition, there are other high-frequency formulas among W1 formulas, such as SV1–SV2+(x33-x32)>0mod(Z). C ), SV3–SV4+(x33-x32)>0mod(Z C ), SV2–SV3+(x13-x12)>0mod(Z C ), SV2–SV4+(x13-x12)>0mod(Z C Therefore, if it is necessary to simplify the constraints, the high-frequency formulas can be selected first (high-frequency formulas can cover most cases), such as formulas 1 and 2, that is, the shift values ​​corresponding to each non-zero element in the second region can be set according to formulas 1 and 2.

[0172] (2.4) First value (M1=4, N=5)

[0173] For "M1=4, N=5", in one example, the first and third non-zero elements are located in the first column of column N, the second and fourth non-zero elements are located in the second column of column N, and the first and second non-zero elements are located in the second row of row M1. The shift value corresponding to the element in row u and column v of the first region can be denoted as xuv, where u = 1, 2, 3, 4, and v = 1, 2, 3, 4, 5. The first value is not an integer multiple of the promotion factor; it is related to the shift values ​​corresponding to the first, second, third, and fourth non-zero elements, as shown in Formula 3 below: Q = SV1 – SV2 + (x22 – x21) > 0 mod (Z C )

[0174] Where Q represents the first value, x21 represents the shift value corresponding to the first non-zero element (located in the 2nd row of row M1 and the 1st column of column N), x22 represents the shift value corresponding to the second non-zero element (located in the 2nd row of row M1 and the 2nd column of column N), SV1 represents the shift value corresponding to the third non-zero element, and SV2 represents the shift value corresponding to the fourth non-zero element.

[0175] In another example, the first and third non-zero elements are located in column 4 of column N, the second and fourth non-zero elements are located in column 5 of column N, and the first and second non-zero elements are located in row 4 of row M1. The first value is not an integer multiple of the lifting factor; the first value is related to the shift values ​​corresponding to the first, second, third, and fourth non-zero elements, as shown in Formula 4 below: Q = SV4 – SV5 + (x45 – x44) > 0 mod (Z C )

[0176] Where Q represents the first value, x44 represents the shift value corresponding to the first non-zero element (located in the 4th row of M1 and the 4th column of N), x45 represents the shift value corresponding to the second non-zero element (located in the 4th row of M1 and the 5th column of N), SV4 represents the shift value corresponding to the third non-zero element, and SV5 represents the shift value corresponding to the fourth non-zero element.

[0177] Formulas 3 and 4 listed above are merely examples. The specific implementation of these two formulas will be described below.

[0178] Assume that N columns correspond to N sets, and the elements in each set are obtained by shifting one or more non-zero elements in the first region. The second region contains at least two non-zero elements in any row, including the non-zero element in column p and the non-zero element in column q of the N columns. Then, the following condition is satisfied: Q = SVp – SVq + (ep – eq) > 0 mod (Z). C )

[0179] Where Q represents the first value, SVp represents the shift value corresponding to the non-zero element in the p-th column of N columns, SVq represents the shift value corresponding to the non-zero element in the q-th column of N columns, ep represents any element in the set corresponding to the p-th column, and eq represents any element in the set corresponding to the q-th column. Formulas 3 and 4 listed above are equivalent to "SVp – SVq + (ep – eq) > 0 mod (Z)". C Two specific examples of ")".

[0180] In this embodiment, the shift values ​​corresponding to each non-zero element in the first region can refer to the prior art. That is, the shift values ​​corresponding to each non-zero element in the second region can be optimized to satisfy: SVp–SVq+(ep–eq)>0mod(Z) C This allows for maximizing the speed at which the code distance increases with the number of lines, ensuring that the code distance in the low-to-medium code rate range meets the requirements and that performance can still be steadily improved under high reliability requirements.

[0181] (2.5) For the specific case of "M1=4, N=5"

[0182] Assuming scenario 1, the first region is:

[0183] In this case, the first value is not an integer multiple of the boost factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix. Specifically, it includes at least one of the following 40 formulas: Q = SV1 - SV2 + (x22 - x21) > 0 mod (Z C ); Q=SV1-SV2+(x13-x14+x22-x21+x35-x33+x44-x45)>0mod(Z C ); Q=SV1-SV2+(x14-x13+x22-x21+x33-x35+x45-x44)>0mod(Z C ); Q=SV1-SV2+(x22-x21)>0mod(Z C); Q=SV1-SV3+(x13-x11)>0mod(Z C ); Q=SV1-SV3+(x13-x12+x22-x21)>0mod(Z C ); Q=SV1-SV3+(x14-x11+x22-x22+x33-x35+x45-x44)>0mod(Z C ); Q=SV1-SV3+(x14-x12+x22-x21+x33-x35+x45-x44)>0mod(Z C ); Q=SV1-SV4+(x13-x11+x22-x22+x35-x33+x44-x45)>0mod(Z C ); Q=SV1-SV4+(x13-x12+x22-x21+x35-x33+x44-x45)>0mod(Z C ); Q=SV1-SV4+(x14-x11)>0mod(Z C ); Q=SV1-SV4+(x14-x12+x22-x21)>0mod(Z C ); Q=SV2-SV3+(x13-x11+x21-x22)>0mod(Z C ); Q=SV2-SV3+(x13-x12)>0mod(Z C ); Q=SV2-SV3+(x14-x11+x21-x22+x33-x35+x45-x44)>0mod(Z C ); Q=SV2-SV3+(x14-x12+x33-x35+x45-x44)>0mod(Z C ); Q=SV2-SV4+(x13-x11+x21-x22+x35-x33+x44-x45)>0mod(Z C ); Q=SV2-SV4+(x13-x12+x35-x33+x44-x45)>0mod(Z C ); Q=SV2-SV4+(x14-x11+x21-x22)>0mod(Z C ); Q=SV2-SV4+(x14-x12)>0mod(Z C ); Q=SV3-SV4+(x35-x33+x44-x45)>0mod(Z C ); Q=SV3-SV4+(x11-x12+x22-x21+x35-x33+x44-x45)>0mod(Z C); Q=SV3-SV4+(x12-x11+x21-x22+x35-x33+x44-x45)>0mod(Z C ); Q=SV3-SV4+(x35-x33+x44-x45)>0mod(Z C ); Q=SV1-SV5+(x13-x11+x35-x33)>0mod(Z C ); Q=SV1-SV5+(x13-x12+x22-x21+x35-x33)>0mod(Z C ); Q=SV1-SV5+(x14-x11+x45-x44)>0mod(Z C ); Q=SV1-SV5+(x14-x12+x22-x21+x45-x44)>0mod(Z C ); Q=SV2-SV5+(x13-x11+x21-x22+x35-x33)>0mod(Z C ); Q=SV2-SV5+(x13-x12+x35-x33)>0mod(Z C ); Q=SV2-SV5+(x14-x11+x45-x44)>0mod(Z C ); Q=SV2-SV5+(x14-x12+x45-x44)>0mod(Z C ); Q=SV3-SV5+(x35-x33)>0mod(Z C ); Q=SV3-SV5+(x11-x12+x22-x21+x35-x33)>0mod(Z C ); Q=SV3-SV5+(x12-x11+x21-x22+x35-x33)>0mod(Z C ); Q=SV3-SV5+(x35-x33)>0mod(Z C ); Q=SV4-SV5+(x45-x44)>0mod(Z C ); Q=SV4-SV5+(x11-x12+x22-x21+x45-x44)>0mod(Z C ); Q=SV4-SV5+(x12-x11+x21-x22+x45-x44)>0mod(Z C ); Q=SV4-SV5+(x45-x44)>0mod(Z C )。

[0184] As one possible implementation, the N columns of the first region correspond to N sets, namely sets S1 to S5 (i.e., N = 5), and then according to the formula Q = Q = SVp – SVq + (ep – eq) > 0 mod (Z C The above 40 formulas can be determined by considering sets S1 to S5. The specific implementation of determining the N sets is not limited in this application embodiment. For example, for the first region in case 1, the N sets are: S1 = [x13+x22+x35+x44, x14+x22+x33+x45]; S2 = [x13+x21+x35+x44, x14+x21+x33+x45]; S3 = [x11+x22+x35+x44, x12+x21+x35+x44]; S4 = [x11+x22+x33+x45, x12+x21+x33+x45]; S5 = [x11+x22+x33+x44, x12+x21+x33+x44].

[0185] Furthermore, for example, if the elements of one row (called row h1) in the second region are: 1, 1, 0, 0, 0, then the first value is not an integer multiple of the lifting factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix. Specifically, it includes at least one of the following (since S1 includes two elements, namely x13+x22+x35+x44 and x14+x22+x33+x45, and S2 includes two elements, namely x13+x21+x35+x44 and x14+x21+x33+x45, therefore ep can be any of the two elements included in S1, and eq can be any of the two elements included in S2, for a total of 4 formulas): Q=SV1-SV2+(x22-x21)>0mod(Z C ); Q=SV1-SV2+(x13-x14+x22-x21+x35-x33+x44-x45)>0mod(Z C ); Q=SV1-SV2+(x14-x13+x22-x21+x33-x35+x45-x44)>0mod(Z C ); Q=SV1-SV2+(x22-x21)>0mod(Z C ).

[0186] If the elements of one row (called row h2) in the second region are: 0, 0, 0, 1, 1, then the first value is not an integer multiple of the lifting factor. The first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix, specifically including at least one of the following: Q = SV4 - SV5 + (x45 - x44) > 0 mod (Z C ); Q=SV4-SV5+(x11-x12+x22-x21+x45-x44)>0mod(Z C ); Q=SV4-SV5+(x12-x11+x21-x22+x45-x44)>0mod(Z C ); Q=SV4-SV5+(x45-x44)>0mod(Z C ).

[0187] It is understandable that the second region can include multiple possible rows, as detailed in the description when "M1=3, N=4", which will not be listed here. In other words, given the sets S1 to S5 corresponding to the first region, the formula satisfied by the first value can be determined. Therefore, the following text will further provide some cases (i.e., cases 2 to 42) of the first region and its corresponding sets S1 to S5, without listing the specific formulas.

[0188] Scenario 2, the first region is:

[0189] Correspondingly, the N sets are as follows: S1 = [x12+x24+x33+x45, x13+x22+x35+x44]; S2 = [x11+x24+x33+x45, x13+x21+x35+x44]; S3 = [x11+x22+x35+x44, x12+x21+x35+x44]; S4 = [x11+x22+x33+x45, x12+x21+x33+x45]; S5 = [x11+x22+x33+x44, x12+x21+x33+x44].

[0190] Scenario 3, the first region is:

[0191] Correspondingly, the N sets are as follows: S1 = [x12+x25+x34+x43, x13+x24+x32+x45]; S2 = [x11+x25+x34+x43, x13+x21+x34+x45]; S3 = [x11+x24+x32+x45, x12+x21+x34+x45]; S4 = [x11+x25+x32+x43, x13+x21+x32+x45]; S5 = [x11+x24+x32+x43, x12+x21+x34+x43].

[0192] Scenario 4, the first region is:

[0193] Correspondingly, the N sets are as follows: S1 = [x13+x22+x35+x44,x14+x22+x33+x45,x15+x22+x33+x44]; S2 = [x13+x21+x35+x44,x14+x21+x33+x45,x15+x21+x33+x44]; S3 = [x11+x22+x35+x44,x12+x21+x35+x44]; S4 = [x11+x22+x33+x45,x12+x21+x33+x45]; S5 = [x11+x22+x33+x44,x12+x21+x33+x44].

[0194] Scenario 5, the first region is:

[0195] Correspondingly, the N sets are as follows: S1 = [x12+x25+x33+x44,x13+x22+x35+x44,x14+x22+x33+x45]; S2 = [x11+x25+x33+x44,x13+x21+x35+x44,x14+x21+x33+x45]; S3 = [x11+x22+x35+x44,x12+x21+x35+x44]; S4 = [x11+x22+x33+x45,x12+x21+x33+x45]; S5 = [x11+x22+x33+x44,x12+x21+x33+x44].

[0196] Scenario 6, the first region is:

[0197] Correspondingly, the N sets are as follows: S1 = [x12+x24+x33+x45,x13+x22+x35+x44,x15+x22+x33+x44]; S2 = [x11+x24+x33+x45,x13+x21+x35+x44,x15+x21+x33+x44]; S3 = [x11+x22+x35+x44,x12+x21+x35+x44]; S4 = [x11+x22+x33+x45,x12+x21+x33+x45]; S5 = [x11+x22+x33+x44,x12+x21+x33+x44].

[0198] Scenario 7, the first region is:

[0199] Correspondingly, the N sets are as follows: S1 = [x13+x22+x34+x45, x13+x22+x35+x44]; S2 = [x13+x21+x34+x45, x13+x21+x35+x44]; S3 = [x11+x22+x34+x45, x11+x22+x35+x44, x12+x21+x34+x45, x12+x21+x35+x44]; S4 = [x11+x22+x33+x45, x12+x21+x33+x45]; S5 = [x11+x22+x33+x44, x12+x21+x33+x44].

[0200] Scenario 8, the first region is:

[0201] Correspondingly, the N sets are as follows: S1 = [x12+x25+x33+x44,x13+x22+x34+x45,x15+x22+x33+x44]; S2 = [x11+x25+x33+x44,x13+x21+x34+x45,x15+x21+x33+x44]; S3 = [x11+x22+x34+x45,x12+x21+x34+x45]; S4 = [x11+x22+x33+x45,x12+x21+x33+x45]; S5 = [x11+x22+x33+x44,x12+x21+x33+x44].

[0202] Scenario 9, the first region is:

[0203] Correspondingly, the N sets are as follows: S1 = [x12+x25+x34+x43,x13+x24+x32+x45,x15+x24+x32+x43]; S2 = [x11+x25+x34+x43,x13+x21+x34+x45,x15+x21+x34+x43]; S3 = [x11+x24+x32+x45,x12+x21+x34+x45]; S4 = [x11+x25+x32+x43,x13+x21+x32+x45,x15+x21+x32+x43]; S5 = [x11+x24+x32+x43,x12+x21+x34+x43].

[0204] Scenario 10, the first region is:

[0205] Correspondingly, the N sets are as follows: S1 = [x12+x24+x35+x43,x12+x25+x34+x43,x13+x24+x32+x45]; S2 = [x11+x24+x35+x43,x11+x25+x34+x43,x13+x21+x34+x45]; S3 = [x11+x24+x32+x45,x12+x21+x34+x45]; S4 = [x11+x25+x32+x43,x12+x21+x35+x43,x13+x21+x32+x45]; S5 = [x11+x24+x32+x43,x12+x21+x34+x43].

[0206] Scenario 11, the first region is:

[0207] Correspondingly, the N sets are as follows: S1 = [x12+x25+x33+x44, x13+x22+x35+x44, x14+x22+x33+x45, x15+x22+x33+x44]; S2 = [x11+x25+x33+x44, x13+x21+x35+x44, x14+x21+x33+x45, x15+x21+x33+x44]; S3 = [x11+x22+x35+x44, x12+x21+x35+x44]; S4 = [x11+x22+x33+x45, x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0208] Scenario 12, the first region is:

[0209] Correspondingly, the N sets are as follows: S1 = [x12+x24+x33+x45, x12+x25+x33+x44, x13+x22+x35+x44, x15+x22+x33+x44]; S2 = [x11+x24+x33+x45, x11+x25+x33+x44, x13+x21+x35+x44, x15+x21+x33+x44]; S3 = [x11+x22+x35+x44, x12+x21+x35+x44]; S4 = [x11+x22+x33+x45, x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0210] Scenario 13, the first region is:

[0211] Correspondingly, the N sets are as follows: S1 = [x13+x22+x34+x45,x13+x22+x35+x44,x15+x22+x33+x44]; S2 = [x13+x21+x34+x45,x13+x21+x35+x44,x15+x21+x33+x44]; S3 = [x11+x22+x34+x45,x11+x22+x35+x44,x12+x21+x34+x45,x12+x21+x35+x44]; S4 = [x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0212] Scenario 14, the first region is:

[0213] Correspondingly, the N sets are as follows: S1 = [x12+x25+x33+x44,x13+x22+x34+x45,x13+x22+x35+x44]; S2 = [x11+x25+x33+x44,x13+x21+x34+x45,x13+x21+x35+x44]; S3 = [x11+x22+x34+x45,x11+x22+x35+x44,x12+x21+x34+x45,x12+x21+x35+x44]; S4 = [x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0214] Scenario 15, the first region is:

[0215] Correspondingly, the N sets are as follows: S1 = [x12+x24+x33+x45, x13+x22+x35+x44, x14+x22+x33+x45, x15+x22+x33+x44]; S2 = [x11+x24+x33+x45, x13+x21+x35+x44, x14+x21+x33+x45, x15+x21+x33+x44]; S3 = [x11+x22+x35+x44, x12+x21+x35+x44]; S4 = [x11+x22+x33+x45, x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0216] Scenario 16, the first region is:

[0217] Correspondingly, the N sets are as follows: S1 = [x12+x24+x33+x45, x12+x25+x33+x44, x13+x22+x35+x44, x14+x22+x33+x45]; S2 = [x11+x24+x33+x45, x11+x25+x33+x44, x13+x21+x35+x44, x14+x21+x33+x45]; S3 = [x11+x22+x35+x44, x12+x21+x35+x44]; S4 = [x11+x22+x33+x45, x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0218] Scenario 17, the first region is:

[0219] Correspondingly, the N sets are as follows: S1 = [x12+x24+x33+x45, x12+x25+x34+x43, x14+x22+x33+x45, x15+x22+x34+x43]; S2 = [x11+x24+x33+x45, x11+x25+x34+x43, x14+x21+x33+x45, x15+x21+x34+x43]; S3 = [x11+x22+x34+x45, x12+x21+x34+x45]; S4 = [x11+x22+x33+x45, x12+x21+x33+x45]; S5=[x11+x22+x34+x43,x12+x21+x34+x43].

[0220] Scenario 18, the first region is:

[0221] Correspondingly, the N sets are as follows: S1 = [x12+x23+x35+x44, x12+x25+x34+x43, x15+x23+x32+x44]; S2 = [x11+x23+x35+x44, x11+x25+x34+x43, x15+x21+x34+x43]; S3 = [x11+x25+x32+x44, x12+x21+x35+x44, x15+x21+x32+x44]; S4 = [x11+x25+x32+x43, x12+x21+x35+x43, x15+x21+x32+x43]; S5=[x11+x23+x32+x44,x12+x21+x34+x43].

[0222] Scenario 19, the first region is:

[0223] Correspondingly, the N sets are: S1 = [x12+x25+x33+x44,x13+x22+x34+x45,x13+x22+x35+x44,x15+x22+x33+x44]; S2 = [x11+x25+x33+x44,x13+x21+x34+x45,x13+x21+x35+x44,x15+x21+x33+x44]; S3 = [x11+x22+x34+x45,x11+x22+x35+x44,x12+x21+x34+x45,x12+x21+x35+x44]; S4=[x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0224] Scenario 20, the first region is:

[0225] Correspondingly, the N sets are: S1 = [x12+x24+x33+x45,x12+x25+x33+x44,x13+x22+x35+x44,x14+x22+x33+x45,x15+x22+x33+x44]; S2 = [x11+x24+x33+x45,x11+x25+x33+x44,x13+x21+x35+x44,x14+x21+x33+x45,x15+x21+x33+x44]; S3 = [x11+x22+x35+x44,x12+x21+x35+x44]; S4=[x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0226] Scenario 21, the first region is:

[0227] Correspondingly, the N sets are: S1 = [x13+x22+x34+x45,x13+x22+x35+x44,x14+x22+x33+x45,x15+x22+x33+x44]; S2 = [x13+x21+x34+x45,x13+x21+x35+x44,x14+x21+x33+x45,x15+x21+x33+x44]; S3 = [x11+x22+x34+x45,x11+x22+x35+x44,x12+x21+x34+x45,x12+x21+x35+x44]; S4=[x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0228] Scenario 22, the first region is:

[0229] Correspondingly, the N sets are: S1 = [x12+x25+x33+x44,x13+x22+x34+x45,x13+x22+x35+x44,x14+x22+x33+x45]; S2 = [x11+x25+x33+x44,x13+x21+x34+x45,x13+x21+x35+x44,x14+x21+x33+x45]; S3 = [x11+x22+x34+x45,x11+x22+x35+x44,x12+x21+x34+x45,x12+x21+x35+x44]; S4=[x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0230] Scenario 23, the first region is:

[0231] Correspondingly, the N sets are: S1 = [x12+x24+x33+x45,x12+x25+x33+x44,x13+x22+x34+x45,x13+x22+x35+x44]; S2 = [x11+x24+x33+x45,x11+x25+x33+x44,x13+x21+x34+x45,x13+x21+x35+x44]; S3 = [x11+x22+x34+x45,x11+x22+x35+x44,x12+x21+x34+x45,x12+x21+x35+x44]; S4=[x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0232] Case 24, the first region is:

[0233] Correspondingly, the N sets are as follows: S1 = [x12+x25+x33+x44,x12+x25+x34+x43,x15+x22+x33+x44,x15+x22+x34+x43]; S2 = [x11+x25+x33+x44,x11+x25+x34+x43,x15+x21+x33+x44,x15+x21+x34+x43]; S3 = [x11+x22+x35+x44,x12+x21+x35+x44]; S4 = [x11+x22+x35+x43,x12+x21+x35+x43]; S5=[x11+x22+x33+x44,x11+x22+x34+x43,x12+x21+x33+x44,x12+x21+x34+x43].

[0234] Case 25, the first region is:

[0235] Correspondingly, the N sets are: S1 = [x12+x23+x35+x44,x12+x24+x33+x45,x13+x22+x35+x44,x14+x22+x33+x45,x15+x22+x33+x44]; S2 = [x11+x23+x35+x44,x11+x24+x33+x45,x13+x21+x35+x44,x14+x21+x33+x45,x15+x21+x33+x44]; S3 = [x11+x22+x35+x44,x12+x21+x35+x44]; S4=[x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0236] Case 26, the first region is:

[0237] Correspondingly, the N sets are: S1 = [x12+x24+x35+x43,x12+x25+x34+x43,x13+x24+x32+x45,x15+x24+x32+x43]; S2 = [x11+x24+x35+x43,x11+x25+x34+x43,x13+x21+x34+x45,x15+x21+x34+x43]; S3 = [x11+x24+x32+x45,x12+x21+x34+x45]; S4=[x11+x25+x32+x43,x12+x21+x35+x43,x13+x21+x32+x45,x15+x21+x32+x43]; S5=[x11+x24+x32+x43,x12+x21+x34+x43].

[0238] Case 27, the first region is:

[0239] Correspondingly, the N sets are as follows: S1 = [x12+x25+x34+x43,x13+x24+x32+x45,x14+x25+x32+x43,x15+x24+x32+x43]; S2 = [x11+x25+x34+x43,x13+x21+x34+x45,x15+x21+x34+x43]; S3 = [x11+x24+x32+x45,x12+x21+x34+x45,x14+x21+x32+x45]; S4 = [x11+x25+x32+x43,x13+x21+x32+x45,x15+x21+x32+x43]; S5=[x11+x24+x32+x43,x12+x21+x34+x43,x14+x21+x32+x43].

[0240] Case 28, the first region is:

[0241] Correspondingly, the N sets are: S1 = [x12+x24+x33+x45,x12+x25+x33+x44,x14+x23+x32+x45,x15+x23+x32+x44]; S2 = [x11+x24+x33+x45,x11+x25+x33+x44,x14+x21+x33+x45,x15+x21+x33+x44]; S3 = [x11+x24+x32+x45,x11+x25+x32+x44,x14+x21+x32+x45,x15+x21+x32+x44]; S4=[x11+x23+x32+x45,x12+x21+x33+x45]; S5=[x11+x23+x32+x44,x12+x21+x33+x44].

[0242] Case 29, the first region is:

[0243] Correspondingly, the N sets are: S1 = [x12+x23+x35+x44, x12+x24+x33+x45, x14+x23+x32+x45, x15+x23+x32+x44]; S2 = [x11+x23+x35+x44, x11+x24+x33+x45, x14+x21+x33+x45, x15+x21+x33+x44]; S3 = [x11+x24+x32+x45, x12+x21+x35+x44, x14+x21+x32+x45, x15+x21+x32+x44]; S4=[x11+x23+x32+x45,x12+x21+x33+x45]; S5=[x11+x23+x32+x44,x12+x21+x33+x44].

[0244] Case 30, the first region is:

[0245] Correspondingly, the N sets are: S1 = [x12+x24+x35+x43,x12+x25+x34+x43,x13+x24+x32+x45,x14+x25+x32+x43]; S2 = [x11+x24+x35+x43,x11+x25+x34+x43,x13+x21+x34+x45,x14+x21+x35+x43]; S3 = [x11+x24+x32+x45,x12+x21+x34+x45,x14+x21+x32+x45]; S4=[x11+x25+x32+x43,x12+x21+x35+x43,x13+x21+x32+x45]; S5=[x11+x24+x32+x43,x12+x21+x34+x43,x14+x21+x32+x43].

[0246] Case 31, the first region is:

[0247] Correspondingly, the N sets are as follows: S1 = [x12+x23+x34+x45,x12+x25+x34+x43,x14+x23+x32+x45,x14+x25+x32+x43,x15+x24+x32+x43]; S2 = [x11+x23+x34+x45,x11+x25+x34+x43,x15+x21+x34+x43]; S3 = [x11+x24+x32+x45,x12+x21+x34+x45,x14+x21+x32+x45]; S4=[x11+x23+x32+x45,x11+x25+x32+x43,x15+x21+x32+x43]; S5=[x11+x24+x32+x43,x12+x21+x34+x43,x14+x21+x32+x43].

[0248] Case 32, the first region is:

[0249] Correspondingly, the N sets are: S1 = [x12+x23+x34+x45,x12+x24+x35+x43,x14+x23+x32+x45,x15+x24+x32+x43]; S2 = [x11+x23+x34+x45,x11+x24+x35+x43,x14+x21+x35+x43,x15+x21+x34+x43]; S3 = [x11+x24+x32+x45,x12+x21+x34+x45,x14+x21+x32+x45]; S4=[x11+x23+x32+x45,x12+x21+x35+x43,x15+x21+x32+x43]; S5=[x11+x24+x32+x43,x12+x21+x34+x43,x14+x21+x32+x43].

[0250] Case 33, the first region is:

[0251] Correspondingly, the N sets are: S1 = [x12+x25+x33+x44,x13+x22+x34+x45,x13+x22+x35+x44,x14+x22+x33+x45,x15+x22+x33+x44]; S2 = [x11+x25+x33+x44,x13+x21+x34+x45,x13+x21+x35+x44,x14+x21+x33+x45,x15+x21+x33+x44]; S3=[x11+x22+x34+x45,x11+x22+x35+x44,x12+x21+x34+x45,x12+x21+x35+x44]; S4=[x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0252] Case 34, the first region is:

[0253] Correspondingly, the N sets are: S1 = [x12+x24+x33+x45,x12+x25+x33+x44,x13+x22+x34+x45,x13+x22+x35+x44,x15+x22+x33+x44]; S2 = [x11+x24+x33+x45,x11+x25+x33+x44,x13+x21+x34+x45,x13+x21+x35+x44,x15+x21+x33+x44]; S3=[x11+x22+x34+x45,x11+x22+x35+x44,x12+x21+x34+x45,x12+x21+x35+x44]; S4=[x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0254] Case 35, the first region is:

[0255] Correspondingly, the N sets are: S1 = [x12+x24+x33+x45,x12+x24+x35+x43,x14+x22+x33+x45,x14+x22+x35+x43,x15+x22+x34+x43]; S2 = [x11+x24+x33+x45,x11+x24+x35+x43,x14+x21+x33+x45,x14+x21+x35+x43,x15+x21+x34+x43]; S3 = [x11+x22+x34+x45,x12+x21+x34+x45]; S4=[x11+x22+x33+x45,x11+x22+x35+x43,x12+x21+x33+x45,x12+x21+x35+x43]; S5=[x11+x22+x34+x43,x12+x21+x34+x43].

[0256] Case 36, the first region is:

[0257] Correspondingly, the N sets are: S1 = [x12+x23+x35+x44,x12+x24+x33+x45,x12+x25+x33+x44,x13+x22+x35+x44,x14+x22+x33+x45,x15+x22+x33+x44]; S2 = [x11+x23+x35+x44,x11+x24+x33+x45,x11+x25+x33+x44,x13+x21+x35+x44,x14+x21+x33+x45,x15+x21+x33+x44]; S3=[x11+x22+x35+x44,x12+x21+x35+x44]; S4=[x11+x22+x33+x45,x12+x21+x33+x45]; S5=[x11+x22+x33+x44,x12+x21+x33+x44].

[0258] Case 37, the first region is:

[0259] Correspondingly, the N sets are as follows: S1 = [x12+x24+x35+x43,x12+x25+x34+x43,x13+x24+x32+x45,x13+x25+x32+x44]; S2 = [x11+x24+x35+x43,x11+x25+x34+x43,x13+x21+x34+x45,x13+x21+x35+x44]; S3 = [x11+x24+x32+x45,x11+x25+x32+x44,x12+x21+x34+x45,x12+x21+x35+x44]; S4=[x11+x25+x32+x43,x12+x21+x35+x43,x13+x21+x32+x45]; S5=[x11+x24+x32+x43,x12+x21+x34+x43,x13+x21+x32+x44].

[0260] Situation 38:

[0261] Correspondingly, the N sets are: S1 = [x12+x23+x34+x45,x12+x23+x35+x44,x12+x25+x34+x43,x15+x23+x32+x44]; S2 = [x11+x23+x34+x45,x11+x23+x35+x44,x11+x25+x34+x43,x15+x21+x34+x43]; S3 = [x11+x25+x32+x44,x12+x21+x34+x45,x12+x21+x35+x44,x15+x21+x32+x44]; S4=[x11+x23+x32+x45,x11+x25+x32+x43,x12+x21+x35+x43,x15+x21+x32+x43]; S5=[x11+x23+x32+x44,x12+x21+x34+x43].

[0262] Situation 39:

[0263] Correspondingly, the N sets are: S1 = [x12+x23+x34+x45,x12+x24+x35+x43,x12+x25+x34+x43,x14+x23+x32+x45,x14+x25+x32+x43]; S2 = [x11+x23+x34+x45,x11+x24+x35+x43,x11+x25+x34+x43,x14+x21+x35+x43]; S3 = [x11+x24+x32+x45,x12+x21+x34+x45,x14+x21+x32+x45]; S4=[x11+x23+x32+x45,x11+x25+x32+x43,x12+x21+x35+x43]; S5=[x11+x24+x32+x43,x12+x21+x34+x43,x14+x21+x32+x43].

[0264] Case 40, the first region is:

[0265] Correspondingly, the N sets are: S1 = [x12+x23+x34+x45,x12+x23+x35+x44,x14+x23+x32+x45,x15+x23+x32+x44]; S2 = [x11+x23+x34+x45,x11+x23+x35+x44,x14+x21+x35+x43,x15+x21+x34+x43]; S3 = [x12+x21+x34+x45,x12+x21+x35+x44,x14+x21+x32+x45,x15+x21+x32+x44]; S4=[x11+x23+x32+x45,x12+x21+x35+x43,x15+x21+x32+x43]; S5=[x11+x23+x32+x44,x12+x21+x34+x43,x14+x21+x32+x43].

[0266] Case 41, the first region is:

[0267] Correspondingly, the N sets are: S1 = [x12+x23+x35+x44,x12+x24+x33+x45,x12+x25+x33+x44,x14+x23+x32+x45,x15+x23+x32+x44]; S2 = [x11+x23+x35+x44,x11+x24+x33+x45,x11+x25+x33+x44,x14+x21+x33+x45,x15+x21+x33+x44]; S3=[x11+x24+x32+x45,x11+x25+x32+x44,x12+x21+x35+x44,x14+x21+x32+x45,x15+x21+x32+x44]; S4=[x11+x23+x32+x45,x12+x21+x33+x45]; S5=[x11+x23+x32+x44,x12+x21+x33+x44].

[0268] Case 42, the first region is:

[0269] Correspondingly, the N sets are as follows: S1 = [x12+x23+x34+x45,x12+x23+x35+x44,x12+x25+x34+x43,x14+x23+x32+x45,x14+x25+x32+x43]; S2 = [x11+x23+x34+x45,x11+x23+x35+x44,x11+x25+x34+x43,x14+x21+x35+x43]; S3 = [x11+x25+x32+x44,x12+x21+x34+x45,x12+x21+x35+x44,x14+x21+x32+x45]; S4=[x11+x23+x32+x45,x11+x25+x32+x43,x12+x21+x35+x43]; S5=[x11+x23+x32+x44,x12+x21+x34+x43,x14+x21+x32+x43].

[0270] It is understandable that the basis matrix can include the first region as shown in at least one of the cases 1 to 42 above. When the basis matrix includes the first region as shown in multiple cases 1 to 42 above, the shift values ​​corresponding to each element in the second region can be optimized for some or all of these multiple cases. There is no limit to the number of cases to be optimized, nor is there a limit to which cases among these multiple cases to be optimized; for example, cases with smaller numbers can be prioritized for optimization. For example, if the basis matrix includes the first region as shown in cases 1 to 42 above, and assuming that for each of these 42 cases, the shift values ​​corresponding to each element in the second region are optimized, there are a total of W2 formulas for the 42 cases (40 formulas for case 1, 40 formulas for case 2, and more formulas for cases 3-42 due to the increased number of elements in the set), analysis reveals that some formulas appear repeatedly among these W2 formulas, meaning there are high-frequency formulas among the W2 formulas. For example, SV1–SV2+(x22–x21)>0mod(Z C (i.e., formula 3 above), repeated 28 times. For example, SV4–SV5+(x45–x44)>0mod(Z) C (i.e., formula 4 above), repeated 25 times. In addition, there are other high-frequency formulas among the W2 formulas, such as SV3–SV4+(x35-x33)>0mod(Z). C ), SV3–SV4+(x33-x32)>0mod(Z C ), SV1–SV3+(x13-x11)>0mod(Z C ), SV3–SV5+(x35–x32)>0mod(Z CTherefore, if it is necessary to simplify the constraints, the high-frequency formulas can be selected first (high-frequency formulas can cover most cases), such as formulas 3 and 4, that is, the shift values ​​corresponding to each non-zero element in the second region can be set according to formulas 3 and 4.

[0271] The above describes the 7 cases corresponding to "M1=3, N=4" and the 42 cases corresponding to "M1=4, N=5" (49 cases in total). It should be understood that the basis matrix may include the first region represented by at least one of the 49 cases. When the basis matrix includes the first region represented by the 49 cases, the shift values ​​corresponding to each element in the second region can be optimized for some or all of these 49 cases; there is no limitation on how many cases to optimize, nor on which of the 49 cases to optimize. For example, if the basis matrix includes the first region represented by the 49 cases, and assuming that the shift values ​​corresponding to each element in the second region are optimized for each of these 49 cases, there are a total of W1+W2 formulas corresponding to the 49 cases. Some of these W1+W2 formulas appear repeatedly, meaning there are high-frequency formulas among the W1+W2 formulas. Therefore, if it is necessary to simplify the constraints, the high-frequency formulas can be selected first (high-frequency formulas can cover most cases), such as formula 1, formula 2 (formula 2 and formula 3 are the same) and formula 4, that is, the shift values ​​corresponding to each non-zero element in the second region are set according to formula 1, formula 2 and formula 4.

[0272] S402, the first communication device determines the parity check matrix based on the shift values ​​corresponding to each element in the base matrix.

[0273] For example, the first communication device replaces each element in the basis matrix with a Zc×Zc square matrix according to the shift value corresponding to each element in the basis matrix, wherein elements with a value of 0 are replaced with a Zc×Zc 0 matrix, and elements with a value of 1 (the element corresponding to a shift value of P) are replaced with a Zc×Zc 0 matrix. a,b Replace with a Zc×Zc identity matrix (circularly shifted to the right) P a,b The matrix.

[0274] S403, the first communication device encodes the information bit sequence according to the parity check matrix.

[0275] For example, the first communication device can modulate the encoded bit sequence to obtain multiple modulation symbols and output the multiple modulation symbols; correspondingly, the second communication device can acquire the multiple modulation symbols and obtain the bit sequence to be decoded by demodulation.

[0276] Optionally, rate matching and other steps may be performed before the encoded bits are modulated, but this application does not limit this.

[0277] S404, the first communication device outputs the encoded bit sequence; correspondingly, the second communication device acquires the bit sequence to be decoded.

[0278] For example, the first communication device can modulate the encoded bit sequence to obtain multiple modulation symbols and output the multiple modulation symbols; correspondingly, the second communication device can acquire the multiple modulation symbols and obtain the bit sequence to be decoded by demodulation.

[0279] Optionally, rate matching and other steps may be performed before the encoded bits are modulated, but this application does not limit this.

[0280] Optionally, the above method further includes S405 to S407, where S405 to S407 are the contents of the second communication device. S405 to S407 can be implemented in combination with S401 to S404, or S405 to S407 can be implemented independently, and there is no specific limitation.

[0281] S405, the second communication device determines the shift value corresponding to each element in the basis matrix of the LDPC code according to the boosting factor.

[0282] For example, the specific implementation of S405 can be referred to the description of S401.

[0283] S406, the second communication device determines the parity check matrix based on the shift values ​​corresponding to each element in the base matrix.

[0284] For example, the specific implementation of S406 can be referred to the description of S402.

[0285] S407, the second communication device decodes the bit sequence to be decoded according to the parity check matrix to obtain the information bit sequence.

[0286] In the solution provided in the embodiments of this application, a design scheme for the shift value corresponding to the non-zero element in the second region of the base matrix is ​​provided, so as to maximize the speed of the code distance increasing with the number of rows, reduce the influence of the trap set, and make the code distance in the medium and low code rate region meet the requirements, which is conducive to the stable improvement of performance under high reliability requirements.

[0287] Optionally, after determining the shift values ​​corresponding to each element in the base matrix based on the method provided in this application, the shift values ​​corresponding to each element in the base matrix are stored on the encoding device side and the decoding device side in a manner specified by protocol, predefined, or preconfigured. During encoding or decoding, the encoding device and the decoding device respectively read these shift values ​​and perform cyclic shifting and expansion (expansion based on the boost value) on the elements at the corresponding positions in the base matrix to obtain a parity check matrix for encoding or decoding. The shift values ​​corresponding to each element in the base matrix determined based on the scheme of this application can refer to the storage method corresponding to BG1 or BG2 in the 5G communication system. The main difference is that the shift values ​​corresponding to the non-zero elements in the second region of the base matrix designed in this application are different from those in the 5G communication system.

[0288] The decoding performance of Scheme 1 and Scheme 2 is compared below using simulation examples. Scheme 1, as described in this embodiment, optimizes the shift values ​​corresponding to each non-zero element in the second region of the base matrix (e.g., BG2) based on W1+W2 formulas corresponding to 49 cases. Then, based on the shift values ​​corresponding to each non-zero element in the base matrix, the parity check matrix is ​​determined, and encoding / decoding is performed based on the parity check matrix. Scheme 2, according to the definition in the current protocol, determines the shift values ​​corresponding to each non-zero element in the base matrix (e.g., BG2), then determines the parity check matrix of the 5G LDPC code based on the shift values ​​corresponding to each non-zero element in the base matrix, and performs encoding / decoding based on the parity check matrix of the 5G LDPC code.

[0289] Referring to Figures 6A to 6I, the horizontal axis represents SNR and the vertical axis represents BLER. Figures 6A to 6I show the simulation results of Scheme 1 and Scheme 2 for different code lengths and code rates, respectively. Z in Figures 6A to 6I... C The boost factor is represented by a length 10 times the information bit sequence length. As shown in Figures 6A to 6I, in Scheme 2, the presence of trap sets in the base matrix leads to error flattening; that is, as the SNR increases, the BLER decrease rate slows significantly, making it difficult to meet the reliability requirement of BLER less than or equal to 10⁻⁶ in URLLC scenarios. In Scheme 1, by optimizing the shift values ​​corresponding to the non-zero elements in the second region of the base matrix, the speed at which the code distance increases with the number of lines can be improved, reducing the impact of trap sets. Figures 6A to 6I show that Scheme 1, compared to Scheme 2, performs better in the ultra-high reliability range (e.g., BLER = 10⁻⁶). -6 ~10 -7 It has a gain of 0.7 dB to 1.2 dB.

[0290] Regarding the above embodiments, it is understood that:

[0291] (1) In the embodiments of this application, unless otherwise specified or in case of logical conflict, the terms and / or descriptions of different implementations or different examples are consistent and can be referenced or referenced to each other. The technical features of different implementations or different examples can be combined to form new embodiments according to their inherent logical relationship.

[0292] (2) The various numerical designations used in this application are merely for descriptive convenience and are not intended to limit the scope of this application. The step numbers in the above flowcharts are only examples of the execution process and do not constitute a restriction on the order of execution of the steps. That is, the size of each step number does not imply the order of execution; the execution order of each step should be determined by its function and internal logic. Furthermore, not all steps shown in the flowcharts are mandatory steps; some steps may be added or deleted based on actual needs.

[0293] The foregoing mainly describes the solutions provided by the embodiments of this application from the perspective of interaction among multiple devices. It is understood that, in order to achieve the above functions, the multiple devices may include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should readily recognize that, in conjunction with the units and algorithm steps of the various examples described in the embodiments disclosed herein, the embodiments of this application can be implemented in hardware or a combination of hardware and computer software. Whether a function is executed in hardware or by computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0294] This application embodiment can divide multiple devices (such as a first communication device and a second communication device) into functional units according to the above method example. For example, each function can be divided into a separate functional unit, or two or more functions can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0295] In the case of using integrated units, FIG7 shows a possible exemplary block diagram of the device involved in the embodiments of this application. As shown in FIG7, the device 700 may include a processing unit 702 and a communication unit 703. The processing unit 702 is used to control and manage the operation of the device 700. The communication unit 703 is used to support communication between the device 700 and other devices. Optionally, the communication unit 703, also referred to as a communication unit, may include a receiving unit and / or a transmitting unit, respectively used to perform receiving and transmitting operations. The device 700 may also include a storage unit 701 for storing the program code and / or data of the device 700.

[0296] (1) The device 700 can be the first communication device in the above embodiments. The processing unit 702 can support the device 700 in performing the actions of the first communication device in the above method embodiments. Alternatively, the processing unit 702 mainly performs the internal actions of the first communication device in the method embodiments, and the communication unit 703 can support communication between the device 700 and other devices.

[0297] For example, in one embodiment, the processing unit 702 is used to: determine the shift value corresponding to each element in the base matrix of the LDPC code according to the boosting factor; determine the parity check matrix according to the shift value corresponding to each element in the base matrix; and encode the information bit sequence according to the parity check matrix; the communication unit 703 is used to: output the encoded bit sequence; wherein, the first value is not an integer multiple of the boosting factor, and the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix; the first region includes the first element in the N columns of the base matrix, and the first element is located in the first M rows of the base matrix; the second region includes the second element in the N columns of the base matrix, and the second element is located in the M+d1 to M+d2 rows of the base matrix; M is an integer greater than 2, N is an integer greater than or equal to M, d1 and d2 are integers greater than or equal to 1, and d1 is less than or equal to d2.

[0298] Other further technical features can be found in the descriptions in the above method embodiments.

[0299] (2) The device 700 can be the second communication device in the above embodiments. The processing unit 702 can support the device 700 in performing the actions of the second communication device in the above method embodiments. Alternatively, the processing unit 702 mainly performs the internal actions of the second communication device in the method embodiments, and the communication unit 703 can support communication between the device 700 and other devices.

[0300] For example, in one embodiment, the communication unit 703 is used to: determine the shift value corresponding to each element in the base matrix of the LDPC code according to the boosting factor; determine the parity check matrix according to the shift value corresponding to each element in the base matrix; and decode the bit sequence to be decoded according to the parity check matrix; wherein, the first value is not an integer multiple of the boosting factor, and the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix; the first region includes the first element in the N columns of the base matrix, and the first element is located in the first M rows of the base matrix; the second region includes the second element in the N columns of the base matrix, and the second element is located in the M+d1 to M+d2 rows of the base matrix; M is an integer greater than 2, N is an integer greater than or equal to M, d1 and d2 are integers greater than or equal to 1, and d1 is less than or equal to d2.

[0301] Other further technical features can be found in the descriptions in the above method embodiments.

[0302] It should be understood that the division of units in the above device is merely a logical functional division. In actual implementation, they can be fully or partially integrated into a single physical entity, or they can be physically separated. Furthermore, all units in the device can be implemented entirely through software calls from processing elements; all units can be implemented entirely in hardware; or some units can be implemented through software calls from processing elements, while others are implemented in hardware. For example, each unit can be a separate processing element, or it can be integrated into a chip within the device. Alternatively, it can be stored as a program in memory, called and executed by a processing element of the device. Moreover, these units can be fully or partially integrated together, or implemented independently. The processing element here can also be called a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, the operations or units described above can be implemented through integrated logic circuits in the processor element or through software calls from processing elements.

[0303] In one example, a unit in any of the above devices can be one or more integrated circuits configured to implement the methods described above, such as one or more application-specific integrated circuits (ASICs), or one or more digital signal processors (DSPs), or one or more field-programmable gate arrays (FPGAs), or a combination of at least two of these forms of integrated circuits. As another example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a processor, such as a central processing unit (CPU), or other processor capable of calling programs. Furthermore, these units can be integrated together to implement a system-on-chip (SoC).

[0304] The receiving unit described above is an interface circuit of the device, used to receive signals from other devices. For example, when the device is implemented as a chip, the receiving unit is an interface circuit for the chip to receive signals from other chips or devices. The transmitting unit described above is an interface circuit of the device, used to transmit signals to other devices. For example, when the device is implemented as a chip, the transmitting unit is an interface circuit for the chip to transmit signals to other chips or devices.

[0305] Based on the above embodiments, this application also provides a communication device. Referring to FIG8, the communication device 800 may include one or more processors 801. Optionally, the device 800 may also include a memory 802, which may be disposed inside or outside the device 800. It is understood that FIG8 only shows the main components of the communication device, and the communication device may further include a transceiver (not shown in the figure).

[0306] Specifically, processor 801 can be a CPU, a network processor (NP), or a combination of a CPU and an NP. Processor 801 may further include a hardware chip. The aforementioned hardware chip can be an ASIC, a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), an FPGA, generic array logic (GAL), or any combination thereof.

[0307] The processor 801 and memory 802 are interconnected. Optionally, the processor 801 and memory 802 are interconnected via bus 803; bus 803 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is used in Figure 8, but this does not indicate that there is only one bus or one type of bus.

[0308] In one alternative implementation, memory 802 is used to store programs, etc. Specifically, the program may include program code, which includes computer operation instructions. Memory 802 may include RAM, and may also include non-volatile memory, such as one or more disk storage devices. Processor 801 executes the application program stored in memory 802 to implement the above-mentioned functions, thereby realizing the functions of device 800.

[0309] For example, the device 800 may be the first communication device or the second communication device in the above embodiments.

[0310] In one embodiment, when the device 800 implements the function of the first communication device in the above method embodiment, the transceiver can perform the transmit and receive operations executed by the first communication device in the above method embodiment; the processor 801 can perform other operations besides the transmit and receive operations executed by the first communication device in the above method embodiment. Specific details can be found in the relevant descriptions in the above embodiments, and will not be elaborated upon here.

[0311] In one embodiment, when the device 800 implements the function of the second communication device in the above method embodiment, the transceiver can perform the transmit and receive operations executed by the second communication device in the above method embodiment; the processor 801 can perform other operations besides the transmit and receive operations executed by the second communication device in the above method embodiment. Specific details can be found in the relevant descriptions in the above embodiments, and will not be elaborated upon here.

[0312] The terms "system" and "network" in the embodiments of this application are used interchangeably. "At least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single items, plural items, or all items. For example, "at least one of A, B, and C" includes A, B, C, AB, AC, BC, or ABC.

[0313] In the embodiments of this application, "send" and "receive" indicate the direction of signal transmission. For example, "send information to XX" can be understood as the destination of the information being XX, which may include direct transmission via the air interface or indirect transmission by other units or modules via the air interface. "Receive information from YY" can be understood as the source of the information being YY, which may include direct reception from YY via the air interface or indirect reception from YY by other units or modules via the air interface. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface. In other words, sending and receiving can occur between devices, such as between network devices and terminal devices, or within a device, such as between components, modules, chips, software modules, or hardware modules within the device via a bus, wiring, or interface. It is understood that information may undergo necessary processing, such as encoding and modulation, between the source and destination of information transmission, but the destination can understand the valid information from the source. Similar expressions in this application can be understood in a similar way and will not be repeated here.

[0314] The ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the size, content, order, timing, priority, or importance of the multiple objects. For example, the first sequence and the second sequence refer to two different sequences, and do not indicate that the content, priority, or importance of these two sequences are different. Words such as "exemplary" or "for example" are used to indicate that they are examples, illustrations, or explanations. Any embodiment or design scheme described as "exemplary" or "for example" in this application should not be construed as being better or more advantageous than other embodiments or design schemes. Specifically, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0315] Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a list of units is not necessarily limited to those units, but may include other units not expressly listed or inherent to those processes, methods, products, or apparatuses. The methods and apparatuses provided in the embodiments of this application are based on the same or similar technical concepts. Since the principles by which the methods and apparatuses solve the problems are similar, implementations of the apparatus and methods can be referred to mutually, and repeated details will not be elaborated further.

[0316] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0317] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0318] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0319] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

Claims

1. An encoding method characterized by comprising: The method includes: Based on the boosting factor, determine the shift value corresponding to each element in the basis matrix of the LDPC code; The parity check matrix is ​​determined based on the shift values ​​corresponding to each element in the base matrix; The information bit sequence is encoded according to the verification matrix; Output the encoded bit sequence; Wherein, the first value is not an integer multiple of the lifting factor, and the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix; The first region includes the first element in the N columns of the base matrix, and the first element is located in the first M rows of the base matrix; the second region includes the second element in the N columns of the base matrix, and the second element is located in rows M+d1 to M+d2 of the base matrix; M is an integer greater than 2, N is an integer greater than or equal to M, d1 and d2 are integers greater than or equal to 1, and d1 is less than or equal to d2.

2. The method of claim 1, wherein, The first region of the base matrix contains at least two non-zero elements, including a first non-zero element and a second non-zero element located in the same row. The second region of the base matrix contains at least two non-zero elements, including a third non-zero element and a fourth non-zero element located in the same row. The first non-zero element and the third non-zero element are located in the same column, and the second non-zero element and the fourth non-zero element are located in the same column. The first value is related to the shift values ​​corresponding to the first non-zero element, the second non-zero element, the third non-zero element, and the fourth non-zero element.

3. The method according to claim 2, characterized in that, The first value satisfies the following formula: Q = V3 - V4 + V2 - V1 Where Q represents the first value, V1 represents the shift value corresponding to the first non-zero element, V2 represents the shift value corresponding to the second non-zero element, V3 represents the shift value corresponding to the third non-zero element, and V4 represents the shift value corresponding to the fourth non-zero element.

4. The method according to claim 2 or 3, characterized in that, The first element is located in the first M rows of the base matrix, including: the first element is located in the M1 row of the first M rows of the base matrix, where M1 is an integer greater than 2 and less than or equal to M; Where N = M1 + 1.

5. The method according to claim 4, characterized in that, M1 = 3, N = 4; The first non-zero element and the third non-zero element are located in the 3rd column of the N columns, the second non-zero element and the fourth non-zero element are located in the 4th column of the N columns, and the first non-zero element and the second non-zero element are located in the 3rd row of the M1 rows.

6. The method according to claim 4, characterized in that, M1 = 3, N = 4; The first non-zero element and the third non-zero element are located in the first column of the N columns, the second non-zero element and the fourth non-zero element are located in the second column of the N columns, and the first non-zero element and the second non-zero element are located in the second row of the M1 rows.

7. The method according to claim 5 or 6, characterized in that, The first region is any one of the following: or 8. The method according to claim 4, characterized in that, M1 = 4, N = 5; The first non-zero element and the third non-zero element are located in the first column of the N columns, the second non-zero element and the fourth non-zero element are located in the second column of the N columns, and the first non-zero element and the second non-zero element are located in the second row of the M1 rows.

9. The method according to claim 4, characterized in that, M1 = 4, N = 5; The first non-zero element and the third non-zero element are located in the 4th column of the N columns, the second non-zero element and the fourth non-zero element are located in the 5th column of the N columns, and the first non-zero element and the second non-zero element are located in the 4th row of the M1 rows.

10. The method according to claim 8 or 9, characterized in that, The first region is any one of the following: or 11. The method according to any one of claims 1 to 3, characterized in that, In the first region When one row of the second region is [1, 1, 0, 0], the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix, including at least one of the following: Q = SV1 - SV2 + (x22 - x21); Q = SV1 - SV2 + (x13 - x14 + x22 - x21 + x34 - x33); Q = SV1 - SV2 + (x14 - x13 + x22 - x21 + x33 - x34); Where Q represents the first value, SV1 represents the non-zero element in the first column of one row of the second region, SV2 represents the non-zero element in the second column of one row of the second region, xuv represents the shift value corresponding to the element in the u-th row and v-th column of the first region, u = 1, 2, 3, v = 1, 2, 3, 4, and mod represents the modulo operation.

12. The method according to any one of claims 1 to 3, characterized in that, In the first region When one row of the second region is [1, 1, 1, 0], the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix, including at least one of the following: Q = SV1 - SV2 + (x22 - x21); Q = SV1 - SV2 + (x13 - x14 + x22 - x21 + x34 - x33); Q = SV1 - SV2 + (x14 - x13 + x22 - x21 + x33 - x34); Q = SV1 - SV3 + (x13 - x11); Q = SV1 - SV3 + (x13 - x12 + x22 - x21); Q = SV1 - SV3 + (x14 - x11 + x33 - x34); Q=SV1-SV3+(x14-x12+x22-x21+x33-x34); Q=SV2-SV3+(x13-x11+x21-x22); Q=SV2-SV3+(x13-x12); Q=SV2-SV3+(x14-x11+x21-x22+x33-x34); Q=SV2-SV3+(x14-x12+x33-x34); Where Q represents the first value, SV1 represents the non-zero element in the first column of one row of the second region, SV2 represents the non-zero element in the second column of one row of the second region, SV3 represents the non-zero element in the third column of one row of the second region, xuv represents the shift value corresponding to the element in the u-th row and v-th column of the first region, u = 1, 2, 3, v = 1, 2, 3, 4, and mod represents the modulo operation.

13. A decoding method, characterized in that, The method includes: Based on the boosting factor, determine the shift value corresponding to each element in the basis matrix of the LDPC code; The parity check matrix is ​​determined based on the shift values ​​corresponding to each element in the base matrix; Decode the bit sequence to be decoded based on the parity matrix; Wherein, the first value is not an integer multiple of the lifting factor, and the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the basis matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the basis matrix; The first region includes the first element in the N columns of the base matrix, and the first element is located in the first M rows of the base matrix; the second region includes the second element in the N columns of the base matrix, and the second element is located in rows M+d1 to M+d2 of the base matrix; M is an integer greater than 2, N is an integer greater than or equal to M, d1 and d2 are integers greater than or equal to 1, and d1 is less than or equal to d2.

14. The method according to claim 13, characterized in that, The first region of the base matrix contains at least two non-zero elements, including a first non-zero element and a second non-zero element located in the same row. The second region of the base matrix contains at least two non-zero elements, including a third non-zero element and a fourth non-zero element located in the same row. The first non-zero element and the third non-zero element are located in the same column, and the second non-zero element and the fourth non-zero element are located in the same column. The first value is related to the shift values ​​corresponding to the first non-zero element, the second non-zero element, the third non-zero element, and the fourth non-zero element.

15. The method according to claim 14, characterized in that, The first value satisfies the following formula: Q = V3 - V4 + V2 - V1 Where Q represents the first value, V1 represents the shift value corresponding to the first non-zero element, V2 represents the shift value corresponding to the second non-zero element, V3 represents the shift value corresponding to the third non-zero element, and V4 represents the shift value corresponding to the fourth non-zero element.

16. The method according to claim 14 or 15, characterized in that, The first element is located in the first M rows of the base matrix, including: the first element is located in the M1 row of the first M rows of the base matrix, where M1 is an integer greater than 2 and less than or equal to M; Where N = M1 + 1.

17. The method according to claim 16, characterized in that, M1 = 3, N = 4; The first non-zero element and the third non-zero element are located in the 3rd column of the N columns, the second non-zero element and the fourth non-zero element are located in the 4th column of the N columns, and the first non-zero element and the second non-zero element are located in the 3rd row of the M1 rows.

18. The method according to claim 16, characterized in that, M1 = 3, N = 4; The first non-zero element and the third non-zero element are located in the first column of the N columns, the second non-zero element and the fourth non-zero element are located in the second column of the N columns, and the first non-zero element and the second non-zero element are located in the second row of the M1 rows.

19. The method according to claim 17 or 18, characterized in that, The first region is any one of the following: or 20. The method according to claim 16, characterized in that, M1 = 4, N = 5; The first non-zero element and the third non-zero element are located in the first column of the N columns, the second non-zero element and the fourth non-zero element are located in the second column of the N columns, and the first non-zero element and the second non-zero element are located in the second row of the M1 rows.

21. The method according to claim 16, characterized in that, M1 = 4, N = 5; The first non-zero element and the third non-zero element are located in the 4th column of the N columns, the second non-zero element and the fourth non-zero element are located in the 5th column of the N columns, and the first non-zero element and the second non-zero element are located in the 4th row of the M1 rows.

22. The method according to claim 20 or 21, characterized in that, The first region is any one of the following: or 23. The method according to any one of claims 13 to 15, characterized in that, In the first region When one row of the second region is [1, 1, 0, 0], the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix, including at least one of the following: Q = SV1 - SV2 + (x22 - x21); Q = SV1 - SV2 + (x13 - x14 + x22 - x21 + x34 - x33); Q = SV1 - SV2 + (x14 - x13 + x22 - x21 + x33 - x34); Where Q represents the first value, SV1 represents the non-zero element in the first column of one row of the second region, SV2 represents the non-zero element in the second column of one row of the second region, xuv represents the shift value corresponding to the element in the u-th row and v-th column of the first region, u = 1, 2, 3, v = 1, 2, 3, 4, and mod represents the modulo operation.

24. The method according to any one of claims 13 to 15, characterized in that, In the first region When one row of the second region is [1, 1, 1, 0], the first value is related to the shift values ​​corresponding to at least two non-zero elements in the first region of the base matrix and the shift values ​​corresponding to at least two non-zero elements in the same row in the second region of the base matrix, including at least one of the following: Q = SV1 - SV2 + (x22 - x21); Q = SV1 - SV2 + (x13 - x14 + x22 - x21 + x34 - x33); Q = SV1 - SV2 + (x14 - x13 + x22 - x21 + x33 - x34); Q = SV1 - SV3 + (x13 - x11); Q = SV1 - SV3 + (x13 - x12 + x22 - x21); Q = SV1 - SV3 + (x14 - x11 + x33 - x34); Q=SV1-SV3+(x14-x12+x22-x21+x33-x34); Q=SV2-SV3+(x13-x11+x21-x22); Q=SV2-SV3+(x13-x12); Q=SV2-SV3+(x14-x11+x21-x22+x33-x34); Q=SV2-SV3+(x14-x12+x33-x34); Where Q represents the first value, SV1 represents the non-zero element in the first column of one row of the second region, SV2 represents the non-zero element in the second column of one row of the second region, SV3 represents the non-zero element in the third column of one row of the second region, xuv represents the shift value corresponding to the element in the u-th row and v-th column of the first region, u = 1, 2, 3, v = 1, 2, 3, 4, and mod represents the modulo operation.

25. A communication device, characterized in that, The device includes a processor coupled to a memory in which a computer program is stored; the processor is configured to invoke part or all of the computer program in the memory such that the method as described in any one of claims 1 to 24 is executed.

26. A communication system, characterized in that, The communication system includes a first communication device and a second communication device; wherein the first communication device is used to perform the method as described in any one of claims 1 to 12, and the second communication device is used to perform the method as described in any one of claims 13 to 24.

27. A computer program product, characterized in that, The computer program product includes instructions that, when executed, implement the method of any one of claims 1 to 24.

28. A computer-readable storage medium, characterized in that, The storage medium stores a computer program or instructions, which, when executed, implement the method described in any one of claims 1 to 24.

29. A chip, characterized in that, The chip includes a processor for implementing the method of any one of claims 1 to 24.

Images