Chip, preparation method therefor, package structure and electronic device

Abstract

The present application relates to the field of semiconductors, and provides a chip, a preparation method therefor, a package structure, and an electronic device, which can effectively prevent boron atoms having a relatively small atomic radius from penetrating through a first gate to enter a gate dielectric and a channel layer. The chip comprises a P-type transistor. The P-type transistor comprises a channel layer, a gate dielectric, a first gate, a first electrode, and a second electrode, the channel layer, the gate dielectric, and the first gate being stacked, and the first electrode and the second electrode being arranged on the channel layer and respectively being disposed on two sides of the gate dielectric. Materials of the first gate comprise a boron element, a silicon element, and a tetravalent element coordinated with the silicon element. A material of the channel layer comprises a silicon element.

Description

Chips and their fabrication methods, packaging structures, and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510479928.0, filed on April 16, 2025, entitled "Chip and its preparation method, packaging structure, electronic device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the semiconductor field, and more particularly to a chip, its fabrication method, packaging structure, and electronic device. Background Technology

[0003] As the thickness of the gate dielectric decreases further, the problem of boron penetration becomes increasingly serious. For example, when the gate dielectric thickness of metal oxide semiconductor field-effect transistors (MOSFETs) is reduced to below 3 nm, the impact of boron penetration through the thin gate dielectric on MOSFET performance becomes a critical issue in deep submicron processes. Boron penetration is particularly prone to occur in surface-channel MOSFETs; for instance, P-type MOSFETs using P-type polysilicon as the gate material are especially sensitive to boron penetration.

[0004] Boron punch-through refers to the phenomenon where boron impurities in P-type polysilicon can pass through a thin gate dielectric to reach the channel layer of a MOSFET. Since the channel layer of a MOSFET is made of silicon, the introduction of boron into the channel layer will alter the MOSFET's performance, leading to issues such as threshold voltage drift, capacitance-voltage curve distortion, increased leakage current, and reduced gate dielectric reliability. Therefore, improving boron punch-through is crucial for obtaining highly reliable MOSFETs. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a chip, its fabrication method, packaging structure, and electronic device, which can effectively prevent boron atoms with small atomic radii from penetrating the first gate and entering the gate dielectric and channel layer.

[0006] In a first aspect, this application provides a chip including a P-type transistor. The P-type transistor includes a channel layer, a gate dielectric, a first gate, a first electrode, and a second electrode. The channel layer, the gate dielectric, and the first gate are stacked. The first electrode and the second electrode are disposed on the channel layer and are located on opposite sides of the gate dielectric. The material of the first gate includes boron, silicon, and a tetravalent element coordinated with silicon. The material of the channel layer includes silicon.

[0007] In this application, since silicon has a coordination number of 4, when the material of the first gate includes silicon and a tetravalent element coordinated with silicon, the tetravalent element can occupy the atomic sites and interstitial sites of silicon. This effectively prevents boron atoms with smaller atomic radii from penetrating the first gate and entering the gate dielectric and channel layer, thus mitigating problems such as threshold voltage drift, capacitance-voltage curve distortion, increased leakage current, and reduced gate dielectric reliability caused by boron penetration. Furthermore, this application does not employ decoupled plasma nitridation (DPN) technology to form a barrier layer containing silicon-nitrogen bonds (Si-N) between the gate dielectric and the gate. Therefore, it also avoids the risk of reduced gate control over the channel layer and reliability issues in P-type transistors due to DPN enhancement.

[0008] Meanwhile, introducing a tetravalent element coordinated with silicon into the first gate will not introduce additional parameters that cause changes in the work function of the first gate, thus avoiding any negative impact on the P-type transistor due to the tetravalent element coordinated with silicon.

[0009] In some possible implementations, the P-type transistor also includes a second gate disposed on the side of the first gate away from the gate dielectric.

[0010] The second gate is made of amorphous silicon and boron. Since silicon atoms in amorphous silicon are disordered in the long range and ordered in the short range, the second gate has more scattering collisions with boron atoms, which reduces the speed of boron atoms and thus blocks them.

[0011] Alternatively, the material of the second gate may include polysilicon and boron. The presence of polysilicon in the second gate facilitates the adjustment of the work function of the second gate, thereby regulating the threshold voltage of the P-type transistor.

[0012] In some possible implementations, the material of the first gate includes Si. 1-x-y Ge x C y Where x and y both take values ​​in the range [0, 0.5], and x and y are not both 0, and x and y are not both 0.5. Germanium (Ge) and carbon (C) are both tetravalent elements that can coordinate with silicon, and can occupy atomic sites and interstitial sites of silicon, thereby effectively preventing boron atoms with smaller atomic radii from penetrating the first gate and entering the gate dielectric and channel layer.

[0013] In some possible implementations, the thickness of the gate dielectric ranges from 10 nm to 40 nm along the direction from the gate to the gate. Since the first gate of this application can effectively block boron atoms with small atomic radii from passing through, even if the thickness of the gate dielectric is small, ranging from 10 nm to 40 nm, the number of boron atoms entering the channel layer can still be reduced.

[0014] Secondly, embodiments of this application provide a packaging structure including a substrate and the chip described in the first aspect, wherein the chip is disposed on the substrate.

[0015] The second aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the second aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0016] Thirdly, this application provides an electronic device, which includes a circuit board and the packaging structure described in the second aspect. The packaging structure is disposed on the circuit board, and the substrate of the packaging structure is located between the chip and the circuit board.

[0017] The third aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the third aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here.

[0018] Fourthly, this application provides a method for fabricating a chip, the chip including a P-type transistor. The method for fabricating the P-type transistor includes: sequentially forming a dielectric layer and a first semiconductor layer on a channel layer, wherein the material of the first semiconductor layer includes silicon and a tetravalent element coordinated with silicon, and the material of the channel layer includes silicon. Boron is implanted into the first semiconductor layer along a direction pointing from the first semiconductor layer to the dielectric layer. Partial removal is performed on the dielectric layer and the first semiconductor layer after boron implantation to obtain a first gate and a gate dielectric, wherein the first gate is located on the side of the gate dielectric away from the channel layer. A first electrode and a second electrode are formed on the channel layer, the first electrode and the second electrode being disposed on opposite sides of the gate dielectric.

[0019] In some possible implementations, after sequentially forming a dielectric layer and a first semiconductor layer on the channel layer, and before implanting boron into the first semiconductor layer in the direction pointing from the first semiconductor layer to the dielectric layer, the fabrication method of the P-type transistor further includes: forming a second semiconductor layer on the side of the first semiconductor layer away from the dielectric layer, the material of the second semiconductor layer including amorphous silicon or polycrystalline silicon. Simultaneously with implanting boron into the first semiconductor layer in the direction pointing from the first semiconductor layer to the dielectric layer, the fabrication method of the P-type transistor further includes: implanting boron into the second semiconductor layer in the direction pointing from the first semiconductor layer to the dielectric layer. Partial removal of the dielectric layer and the first semiconductor layer after boron implantation to obtain a first gate and a gate dielectric includes: partially removing the dielectric layer and the first and second semiconductor layers after boron implantation to obtain a stacked gate dielectric, a first gate, and a second gate.

[0020] In some possible implementations, after partially removing the dielectric layer and the first semiconductor layer after boron implantation, before forming the first and second electrodes on the channel layer, the fabrication method of the P-type transistor further includes: forming a hard mask on the side of the first gate away from the gate dielectric, the hard mask material including at least one of silicon oxide and silicon nitride; and implanting boron into the first gate along the direction toward the sidewall of the first gate.

[0021] Since boron is implanted into the first semiconductor layer (or the first semiconductor layer and the second semiconductor layer) along the direction from the first semiconductor layer to the dielectric layer as described above, the portion of the first gate (or the first gate and the second gate) facing the dielectric layer has less boron doping. By implanting boron into the first gate (or the first gate and the second gate) along the direction facing the sidewall of the first gate (or the first gate and the second gate), boron can be uniformly doped into the first gate (or the first gate and the second gate).

[0022] In some possible implementations, after sequentially forming a dielectric layer and a first semiconductor layer on the channel layer, and before implanting boron into the first semiconductor layer in the direction from the first semiconductor layer to the dielectric layer, the fabrication method of the P-type transistor further includes: forming an oxide layer on the side of the first semiconductor layer opposite to the dielectric layer. After implanting boron into the first semiconductor layer in the direction from the first semiconductor layer to the dielectric layer, and before partially removing the dielectric layer and the first semiconductor layer after boron implantation, the fabrication method of the P-type transistor further includes: removing the oxide layer. Since the oxide layer is usually relatively dense and uniform, implanting boron into the first and second semiconductor layers allows boron to uniformly enter the first semiconductor layer.

[0023] The fourth aspect and any implementation thereof correspond to the first aspect and any implementation thereof, respectively. The technical effects of the fourth aspect and any implementation thereof are similar to those of the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0024] Figure 1a is a schematic diagram of an electronic device provided in an embodiment of this application;

[0025] Figure 1b is an interaction diagram of the modules in the memory provided in the embodiment of this application;

[0026] Figure 2a is a schematic diagram of the structure of a surface-channel transistor provided by related technologies;

[0027] Figure 2b is a schematic diagram of the structure of a surface-channel transistor provided by related technologies;

[0028] Figure 3 is a schematic diagram of the structure of a P-type transistor provided in an embodiment of this application;

[0029] Figure 4 is a schematic diagram of the structure of a P-type transistor provided in an embodiment of this application;

[0030] Figure 5 is a flowchart of the chip fabrication process provided in the embodiments of this application;

[0031] Figure 6a is a diagram illustrating the fabrication process of the chip provided in an embodiment of this application;

[0032] Figure 6b is a diagram illustrating the fabrication process of the chip provided in an embodiment of this application;

[0033] Figure 6c is a diagram illustrating the fabrication process of the chip provided in an embodiment of this application;

[0034] Figure 6d is a diagram illustrating the fabrication process of the chip provided in the embodiment of this application;

[0035] Figure 6e is a diagram illustrating the fabrication process of the chip provided in an embodiment of this application;

[0036] Figure 6f is a diagram illustrating the fabrication process of the chip provided in an embodiment of this application;

[0037] Figure 6g is a diagram illustrating the fabrication process of the chip provided in the embodiment of this application. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0040] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0041] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0042] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0043] This application provides an electronic device, which may be a consumer electronics product, a home electronics product, an automotive electronics product, a financial terminal product, a communication electronics product, or any other device containing a P-type transistor.

[0044] Consumer electronics include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smartwatches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, and drones. Home electronics include smart door locks, televisions, smart speakers, refrigerators, and robot vacuum cleaners. In-vehicle electronics include car navigation systems and in-vehicle displays. Financial terminal products include automated teller machines (ATMs) and self-service terminals. Communication electronics include servers, memory, radar, base stations, and other devices containing P-type transistors.

[0045] The electronic device includes a circuit board and a package structure disposed on the circuit board. The package structure includes a substrate and at least one chip. At least one chip is disposed on the substrate and electrically connected to the circuit board via traces in the substrate. This application does not limit the package structure; the package structure may include at least a portion of the functional modules in the electronic device to achieve at least some of the functions of each functional module.

[0046] Taking the memory module in an electronic device as an example, Figure 1a is a schematic diagram of the structure of a memory in an electronic device provided in this application. The memory can be, for example, DRAM, resistive random-access memory (RRAM), magnetic random-access memory (MRAM), ferroelectric random-access memory (FeRAM), etc.

[0047] As shown in Figure 1b, the memory includes a memory array, a controller, row decoders, column decoders, etc. Taking a chip with a packaged structure that can implement the function of a memory array as an example, the memory array includes memory cells, and each memory cell includes a transistor and a capacitor. The transistor can be a surface-channel metal-oxide-semiconductor field-effect transistor. The processor can send the address of the selected memory cell to the row decoder and column decoder through the controller. After decoding the received address, the row decoder and column decoder determine at least one memory cell in the memory array as the selected memory cell, and then perform read and write operations on the selected memory cell.

[0048] Of course, surface-channel metal-oxide-semiconductor field-effect transistors can also be applied to other functional modules of electronic devices, and this application does not limit this application. For example, surface-channel metal-oxide-semiconductor field-effect transistors can be applied to logic circuits such as central processing units (CPUs) and static random-access memory (SRAM).

[0049] Surface-channel MOSFETs are a key technology for achieving chip miniaturization; therefore, they can be used as transistors in memory cells. As shown in Figure 2a, a surface-channel MOSFET includes a channel layer 11, a first electrode 12, a second electrode 13, a gate dielectric 14, and a gate 15. The gate dielectric 14 and the gate 15 are stacked on the channel layer 11, and the first electrode 12 and the second electrode 13 are also disposed on the channel layer 11, with the first electrode 12 and the second electrode 13 located on opposite sides of the gate 15. In this application, the first electrode 12 is the source and the second electrode 13 is the drain; or, the first electrode 12 is the drain and the second electrode 13 is the source.

[0050] As mentioned in the background section, the boron punch-through problem becomes increasingly severe as the thickness of the gate dielectric 14 decreases. For example, when the thickness of the MOSFET gate dielectric 14 is reduced to below 3nm, the impact of boron punch-through through the thin gate dielectric 14 on MOSFET performance becomes a critical issue in deep submicron processes. Boron punch-through is particularly prone to occur in surface-channel MOSFETs. For instance, P-type MOSFETs using P-type polysilicon as the gate material 15 are especially sensitive to boron punch-through. Boron impurities in the P-type polysilicon can pass through the thin gate dielectric 14 and reach the MOSFET's channel layer 11. Since the channel layer 11 contains silicon, the introduction of boron into the channel layer 11 will alter MOSFET performance, including threshold voltage drift, capacitance-voltage curve distortion, increased leakage current, and reduced gate dielectric 14 reliability. Therefore, improving boron punch-through is crucial for obtaining highly reliable MOSFETs.

[0051] Furthermore, taking 28nm polysilicon oxynitride (polySiON) as an example, a single polysilicon cell is typically used as the gate. After boron is implanted into the polysilicon along the direction from the gate 15 to the gate dielectric 14, the boron is mainly concentrated on the side of the gate 15 furthest from the gate dielectric 14. However, both technology computer-aided design (TCAD) simulations and experimental results show that after high-temperature heat treatment, the distribution of boron in the entire gate 15 is nearly uniform. The portion of the gate 15 closer to the gate dielectric 14 contains more boron; therefore, additional high-temperature heat treatment using special processes will further exacerbate the severe boron punch-through effect.

[0052] As shown in Figure 2b, to address the aforementioned issues, related technologies propose employing a decoupled plasma nitriding process to form a barrier layer 20 containing silicon-nitrogen bonds (Si-N) between the gate dielectric 14 and the gate 15, thereby preventing boron penetration. However, as the thickness of the gate dielectric 14 further decreases, if the DPN (dielectric permeability) is further aggravated, it will not only affect the gate 15's control over the channel layer 11 but also introduce reliability risks to the P-type transistor. For example, negative bias temperature instability (NBTI) is at risk of worsening with increased DPN.

[0053] Based on this, as shown in Figure 3, this application embodiment provides a chip including a P-type transistor. The P-type transistor includes a channel layer 11, a first electrode 12, a second electrode 13, a gate dielectric 14, and a first gate 151. The channel layer 11, the gate dielectric 14, and the first gate 151 are stacked. The material of the first gate 151 includes boron, silicon, and a tetravalent element coordinated with silicon. The material of the channel layer 11 includes silicon, for example, silicon. The first electrode 12 and the second electrode 13 are disposed on the channel layer 11 and are located on opposite sides of the gate dielectric 14. This P-type transistor structure is the aforementioned surface-channel transistor.

[0054] In this application, since silicon has a coordination number of 4, when the material of the first gate 151 includes silicon and a tetravalent element coordinated with silicon, the tetravalent element can occupy the atomic sites and interstitial sites of silicon. This effectively prevents boron atoms with smaller atomic radii from penetrating the first gate 151 and entering the gate dielectric 14 and the channel layer 11, thus improving problems such as threshold voltage drift, capacitance-voltage curve distortion, increased leakage current, and reduced reliability of the gate dielectric 14 caused by boron penetration. Furthermore, this embodiment does not use the DPN process to form a barrier layer 20 containing silicon-nitrogen bonds (Si-N) between the gate dielectric 14 and the gate 15. Therefore, it can also avoid the risk of reduced control capability of the gate 15 over the channel layer 11 due to DPN, and the risk of reliability problems in the P-type transistor.

[0055] Meanwhile, introducing a tetravalent element coordinated with silicon into the first gate 151 will not introduce additional parameters that cause changes in the work function of the first gate 151, thus avoiding any negative impact on the P-type transistor due to the tetravalent element coordinated with silicon.

[0056] In some possible implementations, the embodiments of this application do not limit the tetravalent element coordinated with silicon. Optionally, the tetravalent element coordinated with silicon may include at least one of germanium (Ge) and carbon (C). For example, the material of the first gate 151 includes Si. 1-x-y Ge x Cy The values ​​of x and y are both in the range of [0, 0.5], and x and y are not both 0 at the same time, and x and y are not both 0.5 at the same time.

[0057] When x = 0 and y is (0, 0.5], the material of the first gate 151 includes silicon carbide (SiC).

[0058] When y = 0 and x is (0, 0.5], the material of the first gate 151 includes silicon germanium (SiGe).

[0059] When x is (0, 0.5] and y is (0, 0.5), or when x is (0, 0.5) and y is (0, 0.5), the material of the first gate 151 includes germanium-silicon-carbon (Si). 1-x-y Ge x C y .

[0060] Furthermore, it should be understood that although silicon can also be used as a tetravalent element, the tetravalent element in the embodiments of this application is a tetravalent element coordinated with silicon. Therefore, the tetravalent element coordinated with silicon does not contain silicon.

[0061] In some possible implementations, the material of the first gate 151 may include other P-type doping elements in addition to boron, for example, the material of the first gate 151 may also include germanium (Ge).

[0062] In some possible implementations, the material of the gate dielectric 14 is not limited, as long as the material of the gate dielectric 14 is a dielectric material. Optionally, the material of the gate dielectric 14 may include a material with a high dielectric constant (high K). For example, the material of the gate dielectric 14 includes silicon oxynitride (SiON).

[0063] In some possible implementations, the thickness of the gate dielectric 14 is not limited in this application embodiment. Optionally, in this application, the thickness of the thinner gate dielectric 14 along the direction pointing from the gate dielectric 14 to the first gate 151 can range from 10 nm to 40 nm. Since the first gate 151 of this application can effectively block boron atoms with small atomic radii from passing through, even if the thickness of the gate dielectric 14 is small, ranging from 10 nm to 40 nm, the number of boron atoms entering the channel layer 11 can still be reduced.

[0064] In some embodiments, as shown in FIG4, the P-type transistor further includes a second gate 152, which is disposed on the side of the first gate 151 away from the gate dielectric 14.

[0065] Optionally, the material of the second gate 152 includes amorphous silicon and boron. Since silicon atoms in amorphous silicon are disordered in the long range and ordered in the short range, the second gate 152 has more scattering collisions with boron atoms, reducing the velocity of boron atoms and thus blocking them.

[0066] Optionally, the material of the second gate 152 includes polysilicon and boron. The inclusion of polysilicon in the second gate 152 facilitates adjustment of its work function, thereby regulating the threshold voltage of the P-type transistor.

[0067] In another embodiment, this application also provides a method for fabricating a chip, the chip including a P-type transistor, as shown in FIG5. The P-type transistor can be implemented in the following manner:

[0068] S110, as shown in FIG6a, a dielectric layer 141 and a first semiconductor layer 1511 are sequentially formed on the channel layer 11. The material of the first semiconductor layer 1511 includes silicon and a tetravalent element coordinated with silicon. The material of the channel layer 11 includes silicon. For example, the material of the channel layer 11 includes silicon.

[0069] Figure 6a illustrates an exemplary schematic diagram of fabricating an N-type transistor and a P-type transistor, wherein the P-type transistor includes an N-type channel layer 11 and the N-type transistor includes a P-type channel layer 21.

[0070] The chip also has a shallow trench isolation (STI) 31, which is disposed on the surface of the dielectric layer 141 away from the channel layer 11 and the channel layer 21, and is located between the channel layer 11 and the channel layer 21 to isolate the N-type transistor and the P-type transistor.

[0071] In some possible implementations, the first semiconductor layer 1511 is processed to become the first gate 151 mentioned above. As shown in Figure 6b, if the P-type transistor also includes a second gate 152, then after forming the first semiconductor layer 1511, a second semiconductor layer 1521 can also be formed on the side of the first semiconductor layer 1511 facing away from the dielectric layer 141. The material of the second semiconductor layer 1521 includes polycrystalline silicon or amorphous silicon.

[0072] The second semiconductor layer 1521, after processing, becomes the second gate 152 in this embodiment of the application. The material of the second semiconductor layer 1521 includes polycrystalline silicon or amorphous silicon; that is, the material of the second gate 152 includes polycrystalline silicon or amorphous silicon. When the material of the second gate 152 is amorphous silicon, because silicon atoms in amorphous silicon have long-range disorder and short-range order, the second gate 152 has more scattering collisions with boron atoms, reducing the velocity of boron atoms and thus blocking them. When the material of the second gate 152 is polycrystalline silicon, the work function of the second gate 152 is easily adjusted, thereby adjusting the threshold voltage of the P-type transistor.

[0073] In some possible implementations, the embodiments of this application do not limit the tetravalent element coordinated with silicon. Optionally, the tetravalent element coordinated with silicon may include at least one of germanium (Ge) and carbon (C). For example, the material of the first gate 151 includes Si. 1-x-y Ge x C y The values ​​of x and y are both in the range of [0, 0.5], and x and y are not both 0 at the same time, and x and y are not both 0.5 at the same time.

[0074] When x = 0 and y is (0, 0.5], the material of the first gate 151 includes silicon carbide (SiC).

[0075] When y = 0 and x is (0, 0.5], the material of the first gate 151 includes silicon germanium (SiGe).

[0076] When x is (0, 0.5] and y is (0, 0.5), or when x is (0, 0.5) and y is (0, 0.5), the material of the first gate 151 includes germanium-silicon-carbon (Si). 1-x-y Ge x C y .

[0077] Furthermore, it should be understood that although silicon can also be used as a tetravalent element, the tetravalent element in the embodiments of this application is a tetravalent element coordinated with silicon. Therefore, the tetravalent element coordinated with silicon does not contain silicon.

[0078] In some possible implementations, the material of the first gate 151 may include other P-type doping elements in addition to boron, for example, the material of the first gate 151 may also include germanium (Ge).

[0079] In some possible implementations, the material of the dielectric layer 141 is not limited, as long as the material of the dielectric layer 141 is a dielectric material. Optionally, the material of the dielectric layer 141 may include a material with a high dielectric constant. For example, the material of the dielectric layer 141 includes silicon oxynitride (SiON).

[0080] In some possible implementations, the thickness of the dielectric layer 141 is not limited in this application embodiment. Optionally, in this application, the thickness of the relatively thin dielectric layer 141 along the direction from the dielectric layer 141 to the first semiconductor layer 1511 can range from 10 nm to 40 nm. Since the first gate 151 to be formed in this application can effectively block boron atoms with small atomic radii from passing through, even if the thickness of the dielectric layer 141 is small, ranging from 10 nm to 40 nm, the number of boron atoms entering the channel layer 11 can still be reduced.

[0081] S120, as shown in FIG6c, boron element is implanted into the first semiconductor layer 1511 in the direction from the first semiconductor layer 1511 to the dielectric layer 141.

[0082] In this application, the first semiconductor layer 1511 is processed to obtain the first gate 151 of this application. The material of the first semiconductor layer 1511 includes silicon and a tetravalent element coordinated with silicon. That is, the material of the first gate 151 to be formed includes silicon and a tetravalent element coordinated with silicon. After implanting boron into the first semiconductor layer 1511, the first gate 151 also includes boron. Since the coordination number of silicon is 4, when the material of the first gate 151 includes silicon and a tetravalent element coordinated with silicon, the tetravalent element can occupy the atomic sites and interstitial sites of silicon, thereby effectively preventing boron atoms with smaller atomic radii from penetrating the first gate 151 and entering the gate dielectric 14 and the channel layer 11. This improves the problems caused by boron penetration, such as threshold voltage drift, capacitance-voltage curve distortion, increased leakage current, and reduced reliability of the gate dielectric 14. Furthermore, this embodiment does not employ the DPN process to form a barrier layer 20 containing silicon-nitrogen bonds (Si-N) between the gate dielectric 14 and the gate 15. Therefore, it can also avoid the risk of reduced control capability of the gate 15 over the channel layer 11 due to the increased DPN, as well as the risk of reliability problems in the P-type transistor.

[0083] Meanwhile, introducing a tetravalent element coordinated with silicon into the first gate 151 will not introduce additional parameters that cause changes in the work function of the first gate 151, thus avoiding any negative impact on the P-type transistor due to the tetravalent element coordinated with silicon.

[0084] In some possible implementations, as shown in FIG6c, after step S110 and before step S120, the method for fabricating a P-type transistor further includes: forming a protective layer 32 on the side of the first semiconductor layer 1511 opposite to the dielectric layer 141, with the protective layer 32 exposing the portion of the first semiconductor layer 1511 located in the P-type transistor and covering the region where the N-type transistor is located. Then, under the protection of the protective layer 32, boron is implanted into the portion of the first semiconductor layer 1511 located in the region where the P-type transistor is located, along the direction from the first semiconductor layer 1511 to the dielectric layer 141. Since the protective layer 32 covers the region where the N-type transistor is located, the portion of the first semiconductor layer 1511 located in the region where the N-type transistor is located is not implanted with boron.

[0085] It should be understood that, as shown in Figure 6c, if a second semiconductor layer 1521 is also disposed on the first semiconductor layer 1511, the protective layer 32 is disposed on the side of the second semiconductor layer 1521 facing away from the dielectric layer 141. Boron is implanted into the first semiconductor layer 1511 and simultaneously into the second semiconductor layer 152.

[0086] In some possible implementations, when the first semiconductor layer 1511 has grain boundaries, boron, after entering the first semiconductor layer 1511, tends to concentrate within the grain boundaries. Based on this, as shown in FIG6d, after step S110 and before step S120, the method for fabricating a P-type transistor further includes forming an oxide layer 33 on the first semiconductor layer 1511. Since the oxide layer 33 is typically dense and uniform, implanting boron into the first semiconductor layer 1511 and the second semiconductor layer 1521 allows boron to uniformly enter the first semiconductor layer 1511.

[0087] It should be understood that if a second semiconductor layer 1521 is also provided on the first semiconductor layer 1511, an oxide layer 33 can be used to allow boron to uniformly enter the first semiconductor layer 1511 and the second semiconductor layer 1521. In particular, when the material of the second semiconductor layer 1521 includes polycrystalline silicon, the presence of more grain boundaries in polycrystalline silicon can effectively prevent boron from accumulating in the grain boundaries of polycrystalline silicon.

[0088] Of course, before step S130, the oxide layer 33 should be removed before the patterning process step S130 can be performed.

[0089] In some possible implementations, the embodiments of this application do not limit the process of implanting boron. Optionally, boron can be implanted into the first semiconductor layer 1511 (or the first semiconductor layer 1511 and the second semiconductor layer 1521) using an ion implantation process (IMP).

[0090] In step S130, as shown in Figure 6e, the dielectric layer 141 and the first semiconductor layer 1511 after boron implantation are partially removed. After the first semiconductor layer 1511 is partially removed, a first gate 151 is obtained. After the dielectric layer 141 is partially removed, a gate dielectric 14 is obtained. The first gate 151 is located on the side of the gate dielectric 14 opposite to the channel layer 11. Optionally, the protective layer 33 is removed before step S130.

[0091] In some possible implementations, if a second semiconductor layer 1521 is also disposed on the first semiconductor layer 1511, then while partially removing the dielectric layer 141 and the first semiconductor layer 1511 after boron implantation, the second semiconductor layer 1521 is also partially removed to obtain the second gate 152. The gate dielectric 14, the first gate 141, and the second gate 142 are stacked, and the stacked patterns of the gate dielectric 14, the first gate 141, and the second gate 142 are identical.

[0092] In some possible implementations, besides implanting boron into the first semiconductor layer 1511 in the direction pointing from the first semiconductor layer 1511 to the dielectric layer 141, boron can also be implanted into the first semiconductor layer 1511 in other directions. Specifically, after step S130 and before step S140, the method for fabricating a P-type transistor further includes forming a hard mask on the side of the first gate 151 (or the second gate 152) facing away from the gate dielectric 14.

[0093] In some possible implementations, Figure 6e shows a process diagram of the fabrication of N-type and P-type transistors. While partially removing the dielectric layer 141 and the first semiconductor layer 1511 after boron implantation, the patterns of the gate dielectric 24, the third gate 251, and the fourth gate 252 in the N-type transistor can also be formed.

[0094] In some possible implementations, after the patterning of the gate dielectric 14 and the first gate 151 (or the first gate 151 and the second gate 152) is formed, the sidewalls of the gate dielectric 14 and the first gate 151 (or the first gate 151 and the second gate 152) are exposed. Based on this, as shown in FIG6f, after step S130 and before step S140, the method for fabricating a P-type transistor further includes: forming a hard mask 34 on the side of the first gate 151 (or the first gate 151 and the second gate 152) facing away from the gate dielectric 14, the material of the hard mask 34 including at least one of silicon oxide and silicon nitride. Next, boron is implanted into the first gate 151 (or the first gate 151 and the second gate 152) along the direction toward the sidewall of the first gate 151 (or the first gate 151 and the second gate 152).

[0095] Since boron is implanted into the first semiconductor layer 1511 (or the first semiconductor layer 1511 and the second semiconductor layer 1521) in step S120 along the direction from the first semiconductor layer 1511 to the dielectric layer 141, the portion of the first gate 151 (or the first gate 151 and the second gate 152) facing the dielectric layer 141 has less boron doping. By implanting boron into the first gate 151 (or the first gate 151 and the second gate 152) along the direction facing the sidewall of the first gate 151 (or the first gate 151 and the second gate 152), the boron can be uniformly doped into the first gate 151 (or the first gate 151 and the second gate 152).

[0096] The material of the hard mask 34 can prevent boron from passing through. Therefore, by using the hard mask 34 to block the surface of the first gate 151 (or the second gate 152) away from the gate medium 14, it is also possible to prevent boron from re-entering the first gate 151 (or the second gate 152) in the direction of injecting boron into the first gate 151 (or the second gate 151) in the direction of the first gate 151 pointing towards the gate medium 14 during the process of injecting boron into the first gate 151 (or the second gate 152) in the direction of the first gate 151 pointing towards the gate medium 14.

[0097] S140, as shown in Figure 6g, a first electrode 12 and a second electrode 13 are formed on the channel layer 11, with the first electrode 12 and the second electrode 13 respectively disposed on both sides of the gate dielectric 14.

[0098] Furthermore, other explanations and beneficial effects of the embodiments of this application are the same as those of the previous embodiment, and will not be repeated here.

[0099] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip, characterized by The transistor includes a P-type transistor, which includes a channel layer, a gate dielectric, a first gate, a first electrode, and a second electrode. The channel layer, the gate dielectric, and the first gate are stacked; the material of the first gate includes boron, silicon, and a tetravalent element coordinated with the silicon; the material of the channel layer includes silicon. The first electrode and the second electrode are disposed on the channel layer and are located on both sides of the gate dielectric.

2. The chip according to claim 1, characterized in that, The P-type transistor further includes a second gate, which is disposed on the side of the first gate opposite to the gate dielectric. The material of the second gate includes amorphous silicon and the boron element, or the material of the second gate includes polycrystalline silicon and the boron element.

3. The chip according to claim 1 or 2, characterized in that, The material of the first gate includes Si 1-x-y Ge x C y ; wherein, the value range of x and y is [0, 0.5], and x and y are not 0 at the same time, and x and y are not 0.5 at the same time.

4. The chip according to any one of claims 1 to 3, characterized in that The thickness of the gate dielectric is in the range of 10nm-40nm, along the direction from the gate dielectric to the gate electrode.

5. A package structure, characterized by, It includes a substrate and a chip as described in any one of claims 1-4, wherein the chip is disposed on the substrate.

6. An electronic device, comprising: The device includes a circuit board and the packaging structure of claim 5, wherein the packaging structure is disposed on the circuit board and the substrate of the packaging structure is located between the chip and the circuit board.

7. A method of producing a chip, characterized by The chip includes a P-type transistor, and the method for fabricating the P-type transistor includes: A dielectric layer and a first semiconductor layer are sequentially formed on the channel layer. The material of the first semiconductor layer includes silicon and a tetravalent element coordinated with the silicon. The material of the channel layer includes silicon. Boron is implanted into the first semiconductor layer in the direction pointing from the first semiconductor layer to the dielectric layer; The dielectric layer and the first semiconductor layer after boron implantation are partially removed to obtain a first gate and a gate dielectric, wherein the first gate is located on the side of the gate dielectric away from the channel layer; A first electrode and a second electrode are formed on the channel layer, with the first electrode and the second electrode respectively located on both sides of the gate dielectric.

8. The method for fabricating a chip according to claim 7, characterized in that, After the dielectric layer and the first semiconductor layer are sequentially formed on the channel layer, and before the boron element is implanted into the first semiconductor layer in the direction pointing from the first semiconductor layer to the dielectric layer, the method for fabricating the P-type transistor further includes: forming a second semiconductor layer on the side of the first semiconductor layer away from the dielectric layer, wherein the material of the second semiconductor layer includes amorphous silicon or polycrystalline silicon. While implanting boron into the first semiconductor layer along the direction pointing from the first semiconductor layer to the dielectric layer, the method for fabricating the P-type transistor further includes: implanting the boron into the second semiconductor layer along the direction pointing from the first semiconductor layer to the dielectric layer; The step of partially removing the dielectric layer and the first semiconductor layer after boron implantation to obtain the first gate and the gate dielectric includes: partially removing the dielectric layer and the first and second semiconductor layers after boron implantation to obtain the stacked gate dielectric, the first gate, and the second gate.

9. The method of claim 7 or 8, wherein the chip is prepared by a method comprising: After partially removing the dielectric layer and the first semiconductor layer after boron implantation, and before forming the first and second electrodes on the channel layer, the fabrication method of the P-type transistor further includes: A hard mask is formed on the side of the first gate opposite to the gate dielectric, and the material of the hard mask includes at least one of silicon oxide and silicon nitride; Boron is injected into the first gate along the direction toward the sidewall of the first gate.

10. The method for fabricating a chip according to any one of claims 7-9, characterized in that, After the dielectric layer and the first semiconductor layer are sequentially formed on the channel layer, and before the boron element is implanted into the first semiconductor layer in the direction pointing from the first semiconductor layer to the dielectric layer, the method for fabricating the P-type transistor further includes: forming an oxide layer on the side of the first semiconductor layer away from the dielectric layer. After implanting boron into the first semiconductor layer in the direction pointing from the first semiconductor layer to the dielectric layer, and before partially removing the dielectric layer and the first semiconductor layer after the boron implantation, the method for fabricating the P-type transistor further includes: removing the oxide layer.

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