Encoding or decoding method and communication apparatus

Abstract

Provided in the present application are an encoding or decoding method and an apparatus. A first region, in a base matrix, satisfying corresponding characteristics is defined, and shift values corresponding to elements of the first region are designed. Any row of the first region comprises at least two elements "1", and shift values corresponding to any two elements "1" of the at least two elements "1" satisfy a constraint relationship. The constraint relationship can be: a result of a first value modulo a lifting value is not zero, and the first value is related to the shift values corresponding to any two elements "1" of the at least two elements "1". The shift values designed on the basis of the constraint relationship enables the base matrix to have better performance at an error floor, such as improving the error correction capability and lowering the error floor.

Description

Encoding or decoding methods and communication devices

[0001] This application claims priority to Chinese Patent Application No. 202510481445.4, filed on April 16, 2025, entitled "Method for Encoding or Decoding and Communication Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of channel coding, and more specifically, to a method for channel coding or decoding and a communication apparatus. Background Technology

[0003] Low-density parity-check (LDPC) codes are channel coding schemes very close to the Shannon limit and have been chosen as the data channel coding scheme for fifth-generation (5G) systems. Mainstream LDPCs have a quasi-cyclic (QC) structure, and practical QC-LDPCs are represented using a base graph (BG). The base graph can also be written in matrix form, called the base matrix. Based on the boost value and the shift values ​​corresponding to the non-empty positions in the base matrix, the base matrix can be expanded into a complete parity-check matrix for encoding or decoding.

[0004] However, the performance of the basis matrix in the known schemes still needs to be improved. In some scenarios, such as ultra-reliable and low-latency communication (URLLC), there is a significant error floor. Summary of the Invention

[0005] This application provides an encoding or decoding method and a communication device, which are applied to the design of translation values ​​corresponding to elements in the basis matrix of LDPC, and can improve the performance of the basis matrix.

[0006] Specifically, a first region is defined for the basis matrix, which is a region in the basis matrix that satisfies certain characteristics. When the translation values ​​corresponding to the elements in the first region satisfy the constraints proposed in this application, the performance of the basis matrix can be improved, for example, by reducing erroneous planes.

[0007] Based on the constraints proposed in this application, the translation values ​​corresponding to the elements in the first region of the basis matrix can be determined. Combined with the boosting value, the basis matrix can be expanded into a parity-check matrix for encoding or decoding. Therefore, the technical solution of this application is applicable to both the encoding and decoding sides of LDPC.

[0008] Firstly, an encoding method is provided, which can be executed by a communication device (or encoding device). Unless otherwise specified, the communication device can refer to a communication equipment (e.g., a network-side device, a terminal-side device, or an encoding device), or it can refer to a component used in the communication equipment (e.g., a processor, chip, circuit, or a logic module, hardware, and / or software that implements all or part of the functions of the communication equipment). The component used in the communication equipment can be deployed within the communication equipment, or it can be independent of the communication equipment but coupled to it. The method can include: the encoding device acquiring information bits and encoding the information bits based on a parity-check matrix to obtain an encoded sequence. After obtaining the encoded sequence, the encoding device outputs the encoded sequence.

[0009] The verification matrix is ​​obtained based on the translation values ​​corresponding to each element in the base matrix. The base matrix includes a first region, the columns of the first region include at least two core verification columns of the base matrix, and the rows of the first region include rows in the incremental redundancy region of the base matrix that contain at least two elements "1". The translation values ​​corresponding to any two of the at least two elements "1" satisfy a constraint relationship, which includes: the result of taking the first value modulo the boost value is not zero, and the first value is related to the translation values ​​corresponding to any two of the at least two elements "1".

[0010] In the technical solution of this application, a first region in the basis matrix is ​​defined, and a design scheme for the translation values ​​corresponding to the elements of the first region is provided. By satisfying the constraint relationship between any two "1" elements in the row of the first region, the basis matrix performs better in error planes, thereby improving the performance of the basis matrix.

[0011] Secondly, a decoding method is provided, which can be executed by a communication device (or decoding device). This communication device can refer to any communication equipment (e.g., network-side equipment, terminal-side equipment, or decoding device), or it can refer to components used in the communication equipment (e.g., processors, chips, circuits, or logic modules, hardware, and / or software that implement all or part of the functions of the communication equipment). The components used in the communication equipment can be deployed within the communication equipment, or they can be independent of the communication equipment but coupled to it. The method includes: the decoding device acquiring a received value sequence; the decoding device decoding the received value sequence based on a parity check matrix to obtain a decoded sequence; and the decoding device outputting the decoded sequence after obtaining it. The parity check matrix used by the decoding device is the same as the parity check matrix in the encoding device, and the decoding device can obtain the parity check matrix using the same method as the encoding device. For brevity, the description of the parity check matrix can be found in the first aspect and will not be repeated here.

[0012] In one implementation of the first or second aspect, after determining the translation values ​​corresponding to each element in the base matrix based on the method provided in this application, the translation value matrix corresponding to the base matrix is ​​stored on the encoding device side and the decoding device side in a manner specified by protocol or predefined. During encoding or decoding, the encoding device and the decoding device respectively read these translation values ​​and perform cyclic shifting and expansion (expansion based on the lift value) on the elements at the corresponding positions in the base matrix to obtain a parity check matrix for encoding or decoding.

[0013] The translation values ​​of the basis matrix determined based on the scheme of this application can refer to the storage method of BG1 or BG2 in the 5G system. The main difference is the design of the translation values ​​corresponding to the elements of the first region of the basis matrix defined in this application.

[0014] In addition, the methods in the first or second aspect also involve concepts such as core rows, core check columns, and incremental redundancy regions of the base matrix. These concepts are terms defined in the protocol when describing the structure of the base matrix (or the regional division of the base matrix), and can be found in the description in the embodiments.

[0015] In some implementations of the first or second aspect, the first region may include at least one column of the information columns of the base matrix, in addition to including at least two core check columns of the base matrix.

[0016] In this implementation, in addition to at least two core check columns and satisfying certain characteristics, the first region of the base matrix may also include at least one column of information columns.

[0017] In some implementations of the first or second aspect, the values ​​of the elements in the first matrix and the corresponding translation values ​​in the translation value matrix have the following correspondence: if an element at a certain position in the first matrix is ​​1, then the translation value at that position in the translation value matrix is ​​any non-negative integer; or, if an element at a certain position in the first matrix is ​​0, then the translation value at that position in the translation value matrix is ​​null.

[0018] In some implementations of the first or second aspect, the first region may contain one or more rows. When the first region has multiple rows, for any two rows, the column indices corresponding to element "1" may be the same or different. Regardless of whether the first region contains one or more rows, for any row in the first region, the shift values ​​corresponding to any two elements "1" satisfy the above-mentioned constraint relationship.

[0019] In this embodiment of the application, when the first region contains multiple rows, each row satisfies the above-mentioned constraint relationship. However, for a row, the first value in the constraint relationship it satisfies may be different from or the same as that of other rows, depending on the specific structure of region B of the basis matrix.

[0020] In some implementations of the first or second aspect, the first value in the constraint relationship is related to the translation values ​​corresponding to the two elements "1" and the first translation value. The first translation value is one of the translation values ​​corresponding to each element in the first matrix, the rows of the first matrix include the core rows of the base matrix, the columns of the first matrix include the columns of the first region, the first element corresponding to the first translation value in the first matrix is ​​located in the at least two core verification columns, and the first translation value is a non-zero integer.

[0021] In this implementation, the first value is not only related to the translation value corresponding to any two elements "1" in any row of the first region, but also to the first translation value. The first translation value is one of the translation values ​​corresponding to the elements in the first matrix. The first matrix is ​​defined based on the first region. Specifically, the element corresponding to the first translation value in the first matrix is ​​an element in at least two core verification columns of the first region.

[0022] Taking a row in the first region as an example, suppose the row index of this row is q, and since the first row has at least two elements "1", the column index corresponding to any two of these two "1" elements is represented as c. i and c j Then the positions of any two elements "1" can be represented as (q, c). i ) and (q,c j At the same time, set these two positions (q, c) i ) and (q,c j The corresponding translation value is represented as SV. i and SV j Then the constraint relationship can be: SV i -SV j +k·x>0mod(Z C ), where SV i -SV j +k·x is the first value, Z C Let x be the first shift value and k be an integer, representing the lift value. It can be seen that in this constraint, the first value and SV... i SV j And related to the first translation value.

[0023] In some implementations of the first or second aspect, the constraint relationship can be: SV i -SV j >0mod(Z C ), where SV i -SV j Z is the first value. C For the aforementioned boost value, SV i and SV jLet be the translation value corresponding to any two elements "1". It can be seen that in this implementation, the first value is only related to SV. i SV j This is relevant. At this point, the constraint relationship SV can also be considered... i -SV j +k·x>0mod(Z C In ), k = 0.

[0024] For any row in the first region, when the row contains multiple elements "1", the column index corresponding to the element "1" at different positions is different. Therefore, the combination of the column indices corresponding to any two elements "1", i.e., c i and c j They are also different. Therefore, the SV in the constraint relationship... i and SV j The values ​​of the subscripts also vary, as detailed in the examples provided in the embodiments.

[0025] In some implementations of the first or second aspect, SV i and SV j The corresponding lift values ​​are the same, belonging to the first lift value set, and the lift value Z in the constraint relationship. C It can be the maximum value in the first set of boost values.

[0026] In one possible implementation, region B of the basis matrix has a double diagonal structure, as detailed in the embodiment in the specification.

[0027] In some implementations of the first or second aspect, for one or more rows in the first region, k = 0 in the constraint relation, and the constraint relation is: A i -SV j >0mod(Z C In this implementation, it can also be considered that the first value in the constraint relation is related to SV. i SV j It is related to, but not to, the first translation value.

[0028] In some implementations of the first or second aspect, for one or more rows in the first region, k·x in the constraint relation is any positive integer. In this case, the constraint relation can be understood as: SV i -SV j +positive integer>0 mod(Z) C ).

[0029] In some implementations of the first or second aspect, for one or more rows in the first region, k·x in the constraint relation is an arbitrary negative integer. In this case, the constraint relation can be understood as: SV i -SV j +negative integer > 0 mod (Z)C ).

[0030] For example, k = 1 or k = -1.

[0031] In some implementations of the first or second aspect, the rows of the first matrix include core rows, the columns of the first matrix include all core check columns of the base matrix, the first matrix includes a column with a weight of 3, and the weights of the remaining columns of the first matrix other than the column with a weight of 3 are 2; and the first translation value in the constraint relation is the translation value corresponding to the element in the first matrix located at the position with a row weight of 3 and a column weight of 3.

[0032] Here, column weight refers to the number of 1s in a column of the matrix. In the LDPC involved in this application, this matrix can be a basis matrix or a parity check matrix, without limitation.

[0033] For example, if the first matrix is ​​a 4x4 matrix, when the first matrix is... The first translation value is the translation value x corresponding to the element in the 3rd row and 1st column of the first matrix. 3_1 x 3_1 It is a non-zero integer. In this case, if k = 1, then the above constraint relationship is specifically: SV i -SV j +x 3_1 >0mod(Z C If k = -1, then the above constraint relationship is specifically: SV i -SV j -x 3_1 >0mod(Z C ).

[0034] In another possible implementation, the B region of the basis matrix has a non-double diagonal structure.

[0035] In some implementations of the first or second aspect, the constraint relation SV i -SV j +k·x i_j >0mod(Z C In this context, k is a value in the set {-(C-1),-(C-2),…,0,…,C-2,C-1}, and C is the number of columns in the first region.

[0036] For any row in the first region, when the position of the element "1" is different, k is a partial value in the set {-(C-1),-(C-2),...,0,...,C-2,C-1}, as detailed in the example in the embodiment.

[0037] In some implementations of the first or second aspect, the rows of the first matrix include the core rows of the base matrix, the columns of the first matrix include all the core check columns of the base matrix, and the column weight of all columns of the first matrix is ​​3.

[0038] In one implementation of the first or second aspect, the base matrix includes four core check columns, the column indices of which are 1 to 4;

[0039] When {c i ,c j}={1,2},{SV i ,SV j} = {SV1,SV2}, where k is a value from the set {-3,-2,-1,0,1,2};

[0040] When {c i ,c j}={1,3},{SV i ,SV j} = {SV1,SV3}, where k is a value from the set {-3,-2,-1,0,1};

[0041] When {c i ,c j}={1,4},{SV i ,SV j} = {SV1,SV4}, where k is a value from the set {1,2,3};

[0042] When {c i ,c j}={2,3},{SV i ,SV j} = {SV2,SV3}, where k is a value from the set {-3,-1,0,1,2};

[0043] When {c i ,c j}={2,4},{SV i ,SV j} = {SV2,SV4}, where k is a value from the set {1,3,4};

[0044] When {c i ,c j}={3,4},{SV i ,SV j} = {SV3,SV4}, where k is a value in the set {2,4}.

[0045] In this implementation, at least one of these enumerated items can be satisfied.

[0046] As an example, the matrix of translation values ​​corresponding to each element in the first matrix (hereinafter referred to as the translation value matrix) is as follows: In the translation value matrix, x represents the first translation value. It can be seen that when the weight of all columns in the first matrix is ​​3, each column in the translation value matrix contains only one -1 (corresponding to the element 0 in the corresponding column of the first matrix).

[0047] In one implementation of the first or second aspect, the base matrix includes four core check columns, the column indices of which are 1 to 4;

[0048] When {c i ,c j}={1,2},{SV i ,SV j} = {SV1,SV2}, where k is a value in the set {-2,-1,0,1};

[0049] When {c i ,c j}={1,3},{SV i ,SV j} = {SV1,SV3}, where k is a value in the set {-2,-1};

[0050] When {c i ,c j}={1,4},{SV i ,SV j} = {SV1,SV4}, where k is a value from the set {1,2};

[0051] When {c i ,c j}={2,3},{SV i ,SV j} = {SV2,SV3}, where k is a value in the set {-2,-1,0};

[0052] When {c i ,c j}={2,4},{SV i ,SV j} = {SV2,SV4}, where k is a value from the set {1,2,3};

[0053] When {c i ,c j}={3,4},{SV i ,SV j}={SV3,SV4},k=3.

[0054] In this implementation, at least one of these enumerated items can be satisfied.

[0055] As an example, the translation value matrix is: In the translation value matrix, x is the first translation value. When the weight of all columns in the first matrix is ​​3, in the translation value matrix, each column has only one -1 (corresponding to the element 0 in the corresponding column of the first matrix).

[0056] The above-mentioned different translation values ​​for the elements in the first region of the basis matrix can improve the overall performance of the basis matrix.

[0057] Thirdly, a communication device is provided, which has the function of implementing the method in the first aspect or any possible implementation of the first aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0058] Fourthly, a communication device is provided, which has the function of implementing the method in the second aspect or any possible implementation of the second aspect. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-described function.

[0059] Fifthly, a communication device is provided, comprising at least one processor configured to cause the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor is coupled to at least one memory for storing a computer program or instructions, the at least one processor being configured to call and execute the computer program or instructions from the at least one memory, causing the communication device to execute the method of the first aspect or any possible implementation thereof; or to execute the method of the second aspect or any possible implementation thereof. Optionally, the at least one processor may be included in the communication device or may be configured outside the communication device. Optionally, the communication device further includes the at least one memory. Optionally, the communication device further includes at least one communication interface. As an example, the communication interface may include an input interface and / or an output interface, or may be an interface circuit.

[0060] Sixthly, a communication device is provided, comprising a communication interface and a circuit. The communication interface is configured to receive a signal to be processed and transmit the signal to the circuit. The circuit is configured to process the signal to perform a method as described in the first aspect or any possible implementation thereof; or to perform a method as described in the second aspect or any possible implementation thereof. Optionally, the communication interface is further configured to output a signal processed by the circuit. Optionally, the signal may include information and / or data. Optionally, the communication device may be a chip (e.g., a baseband chip) or a chip system.

[0061] A seventh aspect provides a computer-readable storage medium storing computer program code or instructions that, when executed on a computer, cause the method of the first aspect or any possible implementation thereof to be implemented; or, the method of the second aspect or any possible implementation thereof to be implemented.

[0062] Eighthly, a computer program product is provided, the computer program product comprising computer program code or instructions, which, when executed on a computer, cause the method in the first aspect or any possible implementation thereof to be implemented; or, as in the second aspect or any possible implementation thereof, the method to be implemented.

[0063] A ninth aspect provides a wireless communication system, including a communication device as described in the third aspect and a communication device as described in the fourth aspect. Attached Figure Description

[0064] Figure 1 is a schematic diagram of the basis matrix structure of LDPC.

[0065] Figure 2 is a schematic diagram of the parity check matrix of LDPC.

[0066] Figure 3 shows schematic diagrams of double diagonal structures of different sizes.

[0067] Figure 4 shows an example of a communication system applicable to the technical solution of this application.

[0068] Figure 5 is a schematic diagram of the basic process of wireless communication.

[0069] Figure 6 is a schematic flowchart of the encoding or decoding method provided in this application.

[0070] Figure 7 is a schematic diagram of the rows and columns of the first region.

[0071] Figure 8 is a schematic diagram of the rows and columns of the first region.

[0072] Figure 9 is a schematic diagram of the row discontinuity in the first region.

[0073] Figure 10 is a schematic diagram of the discontinuous columns in the first region.

[0074] Figure 11 is a schematic diagram of the first region.

[0075] Figure 12 is a schematic diagram of the first region where the row has two elements "1".

[0076] Figure 13 is a schematic diagram of the first matrix.

[0077] Figure 14 is a schematic diagram of the first matrix and the translation values ​​in its corresponding translation value matrix.

[0078] Figure 15 shows an example of a double diagonal structure in region B and its corresponding translation value matrix.

[0079] Figures 16 to 24 show the performance simulation results of the technical solution of this application.

[0080] Figure 25 is a schematic structural diagram of the communication device provided in this application.

[0081] Figure 26 is a schematic structural diagram of another communication device provided in this application.

[0082] Figure 27 is a schematic structural diagram of the chip provided in this application. Detailed Implementation

[0083] The technical solutions in this application will now be described with reference to the accompanying drawings.

[0084] The LDPC of the fifth generation (5G) system has two base graphs (BG): BG1 and BG2, which have a common matrix structure, as shown in Figure 1.

[0085] Figure 1 is a schematic diagram of the base matrix of LDPC. As shown, the base matrix includes: part A, which is the information column region, corresponding to high bit rate; part B, which is the core check region, corresponding to high bit rate; part C, which is the all-zero region; part D, which is the incremental redundancy region, corresponding to low bit rate; and part E, which is the raptor-like region.

[0086] The first two columns of both BG1 and BG2 are punched columns. In terms of matrix characteristics, the column weight of the first two columns is very large; in terms of transmission characteristics, the bits corresponding to the punched bits are not transmitted. The decoding side sets the log-likelihood ratio of this part of the received information to 0 and recovers it through decoding.

[0087] Figure 2 is a schematic diagram of the LDPC parity check matrix. As shown in Figure 2, in actual use, by truncating the first T rows and the first Q columns of the parity check matrix, the bitrate decreases, T and Q gradually increase, and the area of ​​the matrix used gradually expands.

[0088] The BG graph model of QC-LDPC is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the verification equation, F is the edge relationship, and the expansion factor is Z. c After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is its edge relationship, corresponding to the number of columns in the check matrix N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c The number of non-zero elements in the parity check matrix is ​​|E|=Z|F|.

[0089] BG can also be written in matrix form H BG Based on the basis matrix and the lifting value Z c (Lifting size) can expand the basis matrix into a complete parity-check matrix for encoding or decoding. c It can also be called expansion factor, boosting factor, expansion value, expansion coefficient, or boosting size, etc.

[0090] Elements in the base graph (BG) are either 0 or 1. A value of 0 represents an empty element, and a value of 1 represents an edge in the base graph, or an association between a corresponding check and a variable. The lifting process involves promoting elements in the base matrix to a Z-value. c ×Z c A square matrix. Among them, element 0 is promoted to Z. c ×Z c The zero matrix is ​​transformed into an identity matrix by promoting element 1 to P and cyclically shifting it. i,j The matrix P. i,j SV is the shift value (SV) corresponding to the i-th row and j-th column of the basis matrix, simply referred to as the SV value. Circular shift refers to the following form:

[0091] Taking a 4x4 identity matrix as an example, if the translation values ​​are 0, 1, and 3, the result after cyclic shifting is as follows:

[0092] If the translation value is 0, the result after the cyclic shift is:

[0093] If the shift value is 1, the result after the cyclic shift is:

[0094] If the shift value is 3, the result after the cyclic shift is:

[0095] In one known implementation, the B region of the basis matrix can be designed with a double diagonal structure.

[0096] Figure 3 shows schematic diagrams of double-diagonal structures of different sizes. As shown in Figure 3, the main feature of the double-diagonal structure is that it contains two diagonals, and also includes one triple column. The degree distribution consists of one triple column and the rest are double columns, exhibiting a coupled structure. The encoding process involves first XORing all rows to obtain the bit values ​​of the parity nodes corresponding to the triple columns, and then sequentially obtaining the bit values ​​of new parity nodes based on the currently obtained parity bit values, until all parity bits are encoded.

[0097] While double-diagonal structures offer low coding complexity, they inevitably generate trap sets (TS). In ultra-reliable low-latency communications (URLLC) scenarios, this can lead to severe error layers.

[0098] In view of this, this application proposes an encoding or decoding method, mainly a design scheme for the translation values ​​corresponding to the elements in the basis matrix, which has better error level performance in URLLC scenarios, such as reducing the error level and thus improving the performance of the basis matrix.

[0099] The technical solution of this application is described below.

[0100] The technical solutions of this application can be applied to various communication systems, including but not limited to: satellite communication systems, fifth-generation (5G) systems or new radio (NR) systems, long-term evolution (LTE) systems, LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems, etc. The technical solutions provided in this application can also be applied to future communication systems. Furthermore, they can be applied to sidelink (SL) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited herein.

[0101] The communication system applicable to this application may include one or more transmitters and one or more receivers. Optionally, one of the transmitters and receivers may be a terminal device, and the other may be a network device.

[0102] For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. In the embodiments of this application, the terminal device may be a device that provides voice and / or data connectivity to a user, and can be used to connect people, objects, and machines, such as a handheld device with wireless connectivity, in-vehicle equipment, etc. The terminal device in the embodiments of this application may be a mobile phone, tablet computer, laptop computer, PDA, mobile internet device (MID), wearable device, virtual reality (VR) device, augmented reality (AR) device, wireless terminal in industrial control, wireless terminal in self-driving, wireless terminal in remote medical surgery, wireless terminal in smart grid, wireless terminal in transportation safety, wireless terminal in smart city, wireless terminal in smart home, etc. Optionally, the UE may be used to act as a base station. For example, the UE may act as a scheduling entity, providing sidelink signals between UEs in V2X or SL, etc.

[0103] In this embodiment, the device for implementing the terminal-side function can be a terminal device or a device capable of supporting the terminal device in implementing the function, such as a chip, chip system, hardware circuit, software module, or a combination of hardware circuit and software module. This device can be installed in the terminal device or used in conjunction with the terminal device. The chip system can be composed of chips or can include chips and other discrete components.

[0104] The network device in this application embodiment may include a network-side device that communicates with the terminal device, and the network device may include an access network device. The access network device in this application embodiment may refer to a radio access network (RAN) node (or device) that connects the terminal device to the wireless network. Access network equipment can broadly encompass or be replaced by various names such as: wireless access network equipment, base station, NodeB, evolved NodeB (eNB), next-generation NodeB (gNB), relay station, access point, transmitting and receiving point (TRP), transmitting point (TP), master station, auxiliary station, motor slide retainer (MSR) node, home base station, network controller, access node, wireless node, access point (AP), transmission node, transceiver node, baseband unit (BBU), remote radio unit (RRU), active antenna unit (AAU), remote radio head (RRH), central unit (CU), distributed unit (DU), radio unit (RU), positioning node, etc. A base station can be a macro base station, micro base station, relay node, donor node, or a combination thereof. A base station can also refer to a communication module, modem, or chip installed within the aforementioned equipment or apparatus. A base station can also be a mobile switching center, equipment performing base station functions in D2D, V2X, and M2M communications, network-side equipment in future communication networks, or equipment performing base station functions in future communication systems. A base station can support networks using the same or different access technologies. Optionally, a RAN node can also be a server, wearable device, vehicle, or in-vehicle equipment. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU). The embodiments of this application do not limit the specific technologies or equipment forms used in the network equipment.

[0105] Base stations can be fixed or mobile. For example, an airplane, helicopter, or drone can be configured to act as a mobile base station, and one or more cells can move depending on the location of the mobile base station. In other examples, an airplane, helicopter, or drone can be configured as a device to communicate with another base station.

[0106] In some deployments, the network devices mentioned in the embodiments of this application may be devices including CU, DU, or CU and DU, or devices with control plane CU nodes (central unit-control plane (CU-CP)) and user plane CU nodes (central unit-user plane (CU-UP)) and DU nodes. For example, the network devices may include gNB-CU-CP, gNB-CU-UP, and gNB-DU.

[0107] In some deployments, multiple RAN nodes collaborate to assist terminals in achieving wireless access, with different RAN nodes each implementing some of the base station's functions. For example, RAN nodes can be CUs, DUs, CU-CPs, CU-UPs, or RUs. CUs and DUs can be configured separately or included in the same network element, such as a BBU. RUs can be included in radio frequency equipment or radio frequency units, such as RRUs, AAUs, or RRHs.

[0108] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open radio access network (ORAN / O-RAN) system, CU can also be called an open CU (open CU, O-CU), and DU can also be called an open DU (open DU, O-DU). CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0109] In this embodiment, the device for implementing network-side functions can be a network device or a device capable of supporting the network device in implementing corresponding functions, such as a chip, chip system, hardware circuit, software module, or a combination of hardware circuit and software module. This device can be installed in the network device or used in conjunction with the network device. The chip system can be composed of chips or may include chips and other discrete components.

[0110] The encoding method and corresponding decoding method provided in this application can be applied to a variety of communication scenarios.

[0111] Figure 4 illustrates an example of a communication system applicable to the technical solution of this application. The encoding method and corresponding decoding method provided in this application are applicable to communication between the network device and the terminal device shown in Figure 4, i.e., uplink or downlink communication. In this communication scenario, the encoding device in this paper can be a terminal-side device in uplink communication or a network-side device in downlink communication; correspondingly, the decoding device can be a network-side device in uplink communication or a terminal-side device in downlink communication. Furthermore, it can also be applied to other communication scenarios without limitation.

[0112] Figure 5 is a schematic diagram of the basic process of wireless communication. As shown in Figure 5, at the signal transmitting end (or encoding side), the signal source is transmitted after sequentially undergoing source coding, channel coding, and digital modulation. At the signal receiving end (or decoding side), the received signal is sequentially processed through digital demodulation, channel decoding, and source decoding before being output to the destination.

[0113] The encoding method provided in this application corresponds to the channel encoding process shown in Figure 5, and the decoding method corresponds to the channel decoding process shown in Figure 5. Optionally, the encoding or decoding method can be used in dedicated equipment or general-purpose equipment. Specifically, the encoding method is mainly implemented by the encoding unit (e.g., an encoder or a device that supports these devices in implementing the corresponding encoding function) in these devices; the decoding method is mainly implemented by the decoding unit (e.g., a decoder or a device that supports these devices in implementing the corresponding decoding function) in these devices.

[0114] The encoding or decoding methods provided in this application are described below. As an example, the encoding method can be executed by a communication device. Unless otherwise specified, the communication device can refer to a communication equipment (e.g., a network-side device, a terminal-side device, or an encoding device), or it can refer to components used in the communication equipment (e.g., processors, chips, circuits, or logic modules, hardware, and / or software that can implement all or part of the functions of the communication equipment). Correspondingly, the decoding method can be executed by a communication device, which can refer to a communication equipment (e.g., a network-side device, a terminal-side device, or a decoding device), or it can refer to components used in the communication equipment (e.g., processors, chips, circuits, or logic modules, hardware, and / or software that can implement all or part of the functions of the communication equipment). The components used in the communication equipment can be deployed within the communication equipment, or they can be independent of the communication equipment but coupled to it.

[0115] Figure 6 is a schematic flowchart of the encoding or decoding method provided in this application.

[0116] 610. The encoding device acquires information bits.

[0117] Here, "information bit" refers to the bit to be encoded in general. It can be the original information bit, or it can be limited to the original information bit. For example, it can also include cyclic redundancy check (CRC) bits, other redundant information, etc., without limitation.

[0118] 620. The encoding device encodes the information bits based on the parity check matrix to obtain the encoded sequence.

[0119] The parity-check matrix is ​​obtained based on the translation values ​​corresponding to each element in the base matrix. Specifically, the encoding device obtains the parity-check matrix based on the lift value and the translation value corresponding to the element "1" in the base matrix. Specifically, the element "1" in the base matrix is ​​expanded to Z. c ×Z c The identity matrix, and based on the translation value corresponding to that position, the Z... c ×Z c The identity matrix is ​​cyclically shifted, and the cyclic shift value is the same as the translation value. When the translation value is 0, it means that the cyclic shift value is 0, that is, the shift of Z... c ×Z c The identity matrix is ​​not cyclically shifted. Elements "0" in the basis matrix are promoted to Z. c ×Z c A matrix of all zeros.

[0120] In this embodiment, the base matrix includes a first region. The rows of the first region include at least two core check rows of the base matrix, and the columns of the first region include rows in the incremental redundancy region of the base matrix that have two elements "1".

[0121] For ease of description, the regional division of the basis matrix is ​​defined as follows.

[0122] Region A: Corresponds to information bits (or information bits, system bits, etc.);

[0123] Region B: This is a square matrix corresponding to the core parity bits (or core parity digits). The core parity can be the parity corresponding to the highest bit rate, or it can be a parity where all degrees are greater than or equal to 2, or it can be a parity node corresponding to a set of rows that meets certain conditions. For example, the set of rows that meets certain conditions can include, but is not limited to: the set of rows corresponding to the maximum row weight, and the set of rows whose row weight difference with other rows exceeds a set threshold (or, in other words, the set of rows whose row weight is significantly higher than other rows).

[0124] Region C: is a matrix consisting entirely of zeros;

[0125] Region D: Incremental redundancy region;

[0126] Region E, also referred to as the raptor-like region, may be an identity matrix, corresponding to parity bits for low code rate extension.

[0127] Wherein both the B region and the E region are parity parts, the B region is defined as a core parity region, and may be characterized as a coding part matrix that is not a lower triangular matrix (i.e., values above the diagonal are not all 0), or a coding part with a column weight greater than 1; while the E region is an extended parity region, and may be characterized as a coding part that is a lower triangular matrix (i.e., values above the diagonal are all 0), or a diagonal matrix.

[0128] More specifically, for BG1 of NR, the columns of the B region are columns 23 to 26, and for BG2 of NR, the columns of the B region are columns 11 to 14.

[0129] The above regions A to E may also be referred to as one submatrix respectively. Therefore, based on the above definitions, the base matrix may include submatrix A, submatrix B, submatrix C, submatrix D and submatrix E, and each part of the base matrix is as follows:

[0130] Submatrix A is rows 0 to x1 and columns 0 to y1 of the base matrix;

[0131] Submatrix B is rows 0 to x1 and columns y1+1 to y2 of the base matrix;

[0132] Submatrix C is rows 0 to x1 and columns y2+1 to Y of the base matrix;

[0133] Submatrix D is rows x1+1 to X and columns 1 to y2 of the base matrix;

[0134] Submatrix E is rows x1+1 to X and columns y2+1 to Y of the base matrix,

[0135] Wherein 0<x1<X, 0<y1<y2<Y, and x1, y1, y2, X and Y are all integers.

[0136] In the above representation, the indices of the rows and columns of the base matrix all start from 0. Therefore, the above region division also indicates that the base matrix includes a total of X-1 rows and Y-1 columns.

[0137] In addition, from another perspective, the columns of the base matrix may include information columns and parity columns.

[0138] Information columns: corresponding to information bits, which are the columns corresponding to region A;

[0139] Check columns: Corresponding to the check bits, these are the columns in regions B and C, and can include core check columns and extended check columns. The core check column is the column corresponding to region B, and the extended check columns are the columns corresponding to regions C or E. Extended check columns can also be called raptor-like columns. Alternatively, the core check column is the check column in region B with a column weight greater than 1 (there are 1 elements both above and below the diagonal of region B), and the extended check columns are the remaining check columns besides the core check column, or check columns with a column weight equal to 1.

[0140] Based on the above-mentioned region division of the basis matrix of LDPC, the encoding or decoding method provided in this application is mainly about determining the translation value of the first region of the basis matrix.

[0141] Based on the design of the base matrix (or, in some embodiments, the translation value matrix corresponding to the base matrix) provided in the embodiments of this application, those skilled in the art can also determine the design of the translation value matrix or the parity check matrix without any doubt. When this scheme is applied to the translation value matrix or the parity check matrix, the essence of the technical solution is the same, and the corresponding technical effect can also be obtained. For simplicity, the following embodiments use the base matrix as an example to illustrate the design of the translation values ​​corresponding to the elements in its first region.

[0142] In summary, the rows of the first region include rows in the incremental redundancy region (i.e., region D) of the base matrix that contain at least two elements "1", and the columns of the first region include at least two core check columns of the base matrix. As mentioned above, each column of region B is a core check column, and the first region includes at least two core check columns.

[0143] Based on the distribution of each part of the base matrix, the first region can also be described as follows: the columns of the first region include at least two columns from the y1+1 to y2 columns of the base matrix, and the rows of the first region include rows from the x1+1 to X rows of the base matrix that have at least two elements "1".

[0144] In one implementation, the columns of the first region include all the core validation columns, as shown in Figure 7.

[0145] Figure 7 is a schematic diagram of the rows and columns of the first region. In Figure 7, the columns of the first region include all the columns of region B, that is, the columns of the first region include all the core check columns, and the rows of the first region include some of the rows of region D. The columns corresponding to at least two elements "1" can be continuous or non-contiguous in all the columns of the first region.

[0146] In another implementation, the columns corresponding to the first region include all the core verification columns, as well as at least one column from region A, as shown in Figure 8.

[0147] Figure 8 is a schematic diagram of the rows and columns of the first region. In Figure 8, the columns of the first region include all the core check columns, and in addition, at least one column from region A. That is, the columns of the first region include all the core check columns and at least one information column. The rows of the first region include a portion of the rows from region D.

[0148] For any row in the first region, the row has at least two elements "1".

[0149] The columns corresponding to the at least two elements "1" can be consecutive or non-consecutive within all columns of the first region. For example, if the columns of the first region include all columns of region B but not all columns of region A, then the columns corresponding to the at least two elements "1" can be at least two columns of region B. These at least two columns of region B can be consecutive or non-consecutive, without limitation. As another example, if the columns of the first region include all columns of region B and at least one column of region A, then the columns corresponding to the at least two elements "1" contain at least two columns of region B, and may also include one or more columns of region A. These at least two columns of region B, and one or more columns of region A, can be consecutive or non-consecutive, without limitation.

[0150] In the examples in Figures 7 and 8 above, the rows in the first region are continuous. As in other examples, the rows in the first region may not be continuous.

[0151] Figure 9 is a schematic diagram showing the discontinuity of rows in the first region. In Figure 9, the first region includes region ① and region ②, or in other words, region ① and region ② together constitute the first region, with region ① or region ② being a part of the first region. Region ① and region ② are discontinuous because the row located between region ① and region ② does not belong to the first region as defined in this application.

[0152] Figure 10 is a schematic diagram showing the discontinuous columns in the first region. In Figure 10, the first region includes region ③ and region ④, or rather, region ③ and region ④ together constitute the first region, with region ③ or region ④ being a part of the first region. Alternatively, region ③ and region ④ are discontinuous because the columns located between region ③ and region ④ do not belong to the first region as defined in this application. As an example, any row in region ③ includes at least two elements "1", and any row in region ④ includes one or more elements "1". Regions ③ and ④ contain the same rows as region D.

[0153] Based on the various forms of the first region described in Figures 7 to 10 above, those skilled in the art can combine them to obtain other presentation methods of the first region. For example, the first region includes multiple sub-regions, such as regions ① to ② and regions ③ to ④ in the above examples. Any two sub-regions of these sub-regions may include one or more possibilities such as row continuation, column continuation, row discontinuity, or column discontinuity. These will not be listed one by one in this application.

[0154] In the cases shown in Figures 7 and 8, the first region is a rectangle. In the cases shown in Figures 9 and 10, the first region is no longer a matrix. Alternatively, it can be viewed from another perspective: in the case shown in Figure 9, multiple discontinuous regions, such as regions ① and ②, each constitute a first region. In the case shown in Figure 10, multiple discontinuous regions together form the first region.

[0155] As an alternative description, the rows of the first region include rows in region D that have at least two elements "1". Alternatively, it can be expressed as: rows in region D that are associated with columns of the first region at least Q times (or, at least Q columns of columns associated with the first region), where Q is an integer greater than or equal to 2. For example, Q = 2. Taking a row in the first region as an example, when Q = 2, it means that the row in the first region is associated with two columns of the first region, which also means that the row in the first region has two elements "1". Similarly, when Q = 3, it means that the row in the first region is associated with three columns of the first region, which also means that the row in the first region has three elements "1", and so on.

[0156] The first region defined in this embodiment can also be understood as:

[0157] In one example, first determine all columns of region B of the basis matrix as the columns of the first region. Then, determine the rows in region D that have at least two elements "1", which are the rows of the first region. Once the columns and rows of the first region are determined, the first region itself can also be determined.

[0158] In another example, all columns of region B of the basis matrix and at least one column of region A are first defined as columns of the first region. Then, rows with at least two "1" elements are determined from the rows of region D. Unlike the previous example, when the columns of the first region contain at least one column of region A, a row in region D with at least two "1" elements (e.g., row #a) means that the portion of row #a corresponding to the column of region B has at least two "1" elements. Furthermore, the portion of row #a corresponding to the aforementioned "at least one column" of region A has one or more "1" elements. In other words, any row in the first region contains two "1" elements located in the portion corresponding to the column of region B. Additionally, it can also contain one or more "1" elements in the portion corresponding to at least one column of region A, as illustrated in the example in Figure 11. In this example, at least one column of region A can be contiguous with region B; for example, at least one column of region A may be to the left of and adjacent to the first column of region B. Alternatively, the at least one column of region A contained in the columns of the first region can be located anywhere within region A, without limitation.

[0159] The characteristics of the first region will be further illustrated below with reference to Figure 11.

[0160] Figure 11 is a schematic diagram of the first region. As shown in Figure 11(a), the row and column distribution of the first region is consistent with that shown in Figure 7. The columns of the first region only include the columns of region B. Taking one row of the first region as an example, this row has two elements "1", and the corresponding columns are both core verification columns.

[0161] As shown in Figure 11(b), the row and column distribution of the first region is consistent with that shown in Figure 8. The columns of the first region include all the columns of region B and one column of region A. Taking one row of the first region as an example, this row has three elements "1". Among them, the columns corresponding to two elements "1" belong to the core verification column, and the column corresponding to the other element "1" belongs to the information column.

[0162] As shown in Figure 11(c), the distribution of rows and columns in the first region is similar to that shown in Figure 9. The first region contains two rows. One row contains three elements "1", and the corresponding columns belong to the core verification column and the information column. The other row contains two elements "1", and the corresponding columns belong to the core verification column.

[0163] As shown in Figure 11(d), a row of the first region is shown, which has four elements "1". One of the columns corresponding to the element "1" belongs to the information column and is not adjacent to (or contiguous with) the first column of region B.

[0164] The above figure 11 is merely an example and only shows some possible implementations of the rows of the first region. Those skilled in the art, based on the definition of the first region and the examples in the figure, can clearly understand which regions in the basis matrix can constitute the first region.

[0165] For ease of description, let's assume that a row in the first region is represented as row, and the position of the element "1" in that row is uniformly represented as N(row).

[0166] Figure 12 is a schematic diagram showing that the first region has two elements "1" in its rows. Figure 12 shows regions A, B, and D. The first 10 columns are the columns of region A, and the last 4 columns are the columns of region B. The area within the dashed box in the last row of region D corresponds to the 4 columns of region B and has two elements "1", which meets the definition of the first region in this application. Therefore, the part within the dashed box is the first region in this example.

[0167] In another formulation, if the column index of the first column of region A is denoted as starting from 1, and the matrix portion shown in Figure 12 represents columns 11 to 14 of the base matrix, then the rows of the first region are associated with the columns of the first region (i.e., columns 11 to 14 of the base matrix) at least twice. Specifically, the rows of the first region are associated with columns 12 and 14 once each (i.e., there are two elements "1" in this row, with corresponding column indices of 12 and 14 respectively). Meanwhile, the remaining rows in region D corresponding to the four columns of region B are associated with columns 11 to 14 once each. Therefore, the row-to-column association of the first region can be represented as N(row) = {12, 14}.

[0168] Based on the above division of the base matrix and the description of the first region, it can be seen that the columns of the first region belong to the y1+1 to y2 columns of the base matrix, and the rows of the first region belong to the x1+1 to X rows of the base matrix.

[0169] The following describes the method for determining the translation value of the first region.

[0170] To facilitate the explanation of the scheme, we first introduce the first matrix and the translation value matrix corresponding to the first matrix.

[0171] Let BG0 be the matrix formed by the core row and the columns of the first region, and call it the first matrix. Furthermore, let BG0 be the translation value matrix corresponding to the translation values ​​of each element in the first matrix, hereinafter referred to as the translation value matrix.

[0172] Among them, BG0 and BG_S0 satisfy the following relationship:

[0173] If the element at the i-th row and j-th column of BG0 is 1, then the translation value at the i-th row and j-th column of BG_S0 is x. i _ j;or,

[0174] If the element at the i-th row and j-th column of BG0 is 0, the element at the i-th row and j-th column of BG_S0 will be -1 or NaN, indicating that the value at this position is empty. During the expansion of the base matrix into the parity check matrix, the position of the empty value in BG0 is expanded into Z. c ×Z c The zero matrix.

[0175] Figure 13 is a schematic diagram of the first matrix.

[0176] In Figure 13(a), the columns of the first region contain all the columns of the B region. According to the definition of the first matrix, the first matrix consists of the core rows and the columns of the first region. Therefore, the first matrix is ​​the matrix part shown in BG0.

[0177] In Figure 13(b), the columns of the first region include all the columns of region B and some of the columns of region A. According to the definition of the first matrix, the first matrix consists of a core row and columns of the first region; therefore, the first matrix is ​​the matrix portion shown in BG0.

[0178] It is understandable that when the rows or columns of the first region are not continuous, the method for determining the first matrix is ​​similar. For example, as shown in Figure 9, the first matrix can be determined for regions ① and ② of the first region, respectively. For example, the first matrix for region ① is shown in Figure 13(a), and the first matrix for region ② is shown in Figure 13(b). As another example, as shown in Figure 10, matrix regions can be determined for regions ③ and ④ of the first region, and these matrix regions together form the first matrix, as shown in Figure 13(c).

[0179] In summary, based on the division of regions A to D of the basis matrix in the technical solution of this application, the inventors discovered that region B has a severe trap set (composed of cycles with a small number of connections to the outside), which is the main cause of obvious erroneous layering. Therefore, the inventors selected the region in region B where columns are connected to the edges in region D (i.e., the first region) to enhance the trap set properties, which can improve the trap set properties overall and reduce erroneous layering.

[0180] Considering some common properties of the encoding structure of region B (e.g., ease of encoding), the structure of region B has the property of block-level elimination, which is equivalent to having a specific set of traps. Therefore, considering the avoidance of the system from entering these undesirable specific trap sets through constraint relationships (i.e., circumventing these specific trap sets) can reduce the error level. The design of the constraint relationships is as follows:

[0181] As shown above, any row in the first region contains at least two elements "1". The translation values ​​corresponding to any two of these "1" elements satisfy a constraint relationship. This constraint relationship can be: the result of taking the first value modulo the lift value is not zero, where the first value and the positions of any two "1" elements (i.e., positions (q, c)) satisfy a constraint relationship. i ) and (q,c j The corresponding translation value.

[0182] Taking row q in the first region as an example, the column index corresponding to any two elements "1" in row q is represented as c. i and c j Then the row with row index q includes the position (q, c) i ) and (q,c j This can be understood as the position (q, c) i ) and (q,c j All elements at position (q, c) are "1". i ) and (q,c j The corresponding translation values ​​are represented as SV. i and SV j SV i and SV j The above constraint relationship must be satisfied between them, and this constraint relationship can be: SV i -SV j >0mod(Z C ), where SV i -SV j Z is the first value. C To increase the value, SV i and SV j The translation value is the value corresponding to any two elements "1".

[0183] In one implementation, the first value in the constraint relationship is related to the translation values ​​corresponding to the positions of any two elements "1", as well as the first translation value. The first translation value is one of the translation values ​​corresponding to each element in the first matrix, the first element corresponding to the first translation value in the first matrix is ​​located in the at least two core verification columns, and the first translation value is a non-zero integer.

[0184] This can be understood, or described, as follows: the constraint is related to the translation value, lift value, and first translation value corresponding to the positions of any two elements "1". Once the lift value is determined, the constraint will differ depending on the position of the first translation value in the translation value matrix. Furthermore, since the translation values ​​in the translation value matrix are related to whether the elements in the first matrix are 1 or 0, it can be said that the constraint is related to the specific structure of the first matrix. Here, the specific structure of the first matrix refers to the distribution of elements 1 and 0 in the first domain matrix. When the first matrix contains the core rows and all the core check columns (excluding information columns), the first matrix is ​​a submatrix B of the base matrix.

[0185] Figure 14 is a schematic diagram of the first matrix and the translation values ​​in its corresponding translation value matrix. As mentioned above, the translation value corresponding to the position of element "1" in BG0 is x. i_j x i_j `a` is any non-negative integer. The shift value corresponding to the position of element "0" in BG0 is NaN, representing a null value. As an example, the shift value corresponding to the position of element "0" in BG0 can also be represented as "-1", representing a null value.

[0186] More specifically, SV i and SV j Based on the size of BG0, it will be further subdivided into two cases:

[0187] Case 1: The number of rows and columns in BG0 are equal, meaning the columns in the first region include all the columns in region B, or c i c j All of them are columns located in region B, as shown in the first region of Figure 7;

[0188] Case 2: The number of rows and columns of BG0 are not equal, that is, the columns of the first region include the columns of the B region and at least one column of the information column, as shown in Figure 8 or the first region shown in Figure 10.

[0189] Due to the characteristics of the translation values ​​of the basis matrix, the code will not change if any row and / or column is simultaneously increased or decreased by the same value. Therefore, BG_S0 in the embodiments of this application can also be obtained by simultaneously increasing or decreasing the same value in any row and / or any column of an initial BG_S0. Furthermore, the rows and columns that are increased or decreased by the same value can be one or more, without limitation. It can be understood that "increasing or decreasing the same value" refers to a single row or column. When more than one row and / or column is increased or decreased, the increased or decreased values ​​in different rows or columns can be the same or different.

[0190] As mentioned in the above embodiment, the constraint relationship can be: the result of taking the first value modulo the lift value is zero, and the first value and SV... i SV j Related to, or, the first value and SV i SV j This relates to the first translation value. Below are some examples of constraint relationships.

[0191] In one example, SV i and SV j Satisfy: SV i -SV j +k·x>0mod(Z C Z C For SV i and SV j The corresponding first lift value is one of the lift values ​​in the set of lift values, where k is an integer.

[0192] In this constraint, `mod` represents the modulo operation, which calculates the remainder after dividing two integers. `a mod b` means taking the remainder of `a` modulo `b`. Therefore, the above constraint means: the first value pair Z... C The result of modulo operation is greater than zero; alternatively, the above constraint also means that the first value is positive for Z. C The result of modulo operation is not equal to zero, or the first value is not Z. C Integer multiples of, etc. Alternatively, this constraint can be replaced with other equivalent descriptions. Where the first value is SV. i -SV j +k·x. Or, in some implementations, the first value simplifies to SV. i -SV j .

[0193] In this example, k can be a positive integer, 0, or a negative integer.

[0194] When k = 0, the constraint relationship is SV. i -SV j >0mod(Z C ), where the first value is SV i -SV j .

[0195] When k is a non-zero integer, the first value in the constraint relation is SV. i -SV j +k·x, where x is the first translation value.

[0196] The process of expanding a basis matrix into a parity check matrix typically involves the following steps: First, a lift value is determined, belonging to a set of lift values, referred to in this embodiment as the first lift value set. The first lift value set is one of multiple lift value sets, each corresponding to an index. SV i and SV j Belonging to the same lift value set (i.e., the first lift value set), once the first lift value set is determined, its corresponding index can also be obtained. Further, based on the index corresponding to the first lift value set, the translation value corresponding to the position of a non-null value in the base matrix is ​​queried. Positions in the base matrix where elements are null are not recorded. After determining the translation values ​​corresponding to the positions of non-null values, each non-null value position is expanded into an identity matrix of the lift value size, and cyclically shifted based on the translation value corresponding to that position. Simultaneously, the positions of null values ​​are expanded into a zero matrix of the lift value size, obtaining the parity matrix.

[0197] As an example, multiple promotion sets can be as shown in Table 1, where the first promotion set can be the promotion set corresponding to any one of the indices 0 to 7.

[0198] Table 1

[0199] In the embodiments of this application, Z C This can be a lift value from the first lift value set; for example, it could be the maximum value in the first lift value set. Then, based on the constraint relation SV... i -SV j +k·x>0mod(Z C ), determine SV i and SV j The value of .

[0200] Furthermore, the row index (i.e., set index) of the promoted value in Table 1 corresponds to a column index of the shifting value (SV) table. This can be understood as: each sex index corresponds to a set of shifting values ​​(SV).

[0201] Each set index corresponds to a set of translation values. Therefore, the translation values ​​described in this application embodiment satisfy a constraint relationship. The lifting value involved in the constraint relationship is the lifting value corresponding to this sex index.

[0202] Taking sex index = 0 as an example, the translation value and Z corresponding to the positions of any two elements "1" in the first region. C The constraint condition is satisfied, where Z in the constraint condition is satisfied. CThe promotion value corresponding to sex index = 0 can be 2, 4, 8, 16, 32, 64, 128, or 256. In one example, Z... C The maximum value among this set of boost values, for example, Z. C =256, or, Z C For example, Z is the second largest value in this set of boost values. C =128.

[0203] As mentioned above, the translation values ​​corresponding to any two positions with element "1" in the first region satisfy the constraint relationship. When a row in the first region has more than two positions with element "1", the translation values ​​corresponding to each pair of positions satisfy the above constraint relationship.

[0204] In this context, it is assumed that the positions of every two elements "1" are called a group. The constraints between the translation values ​​of different groups may be different, but the above constraints are satisfied between the translation values ​​of different groups.

[0205] For example, in a certain row of the first region, there are three positions with the element "1", let's call them positions 1 to 3. The constraint relationship between the translation values ​​corresponding to positions 1 and 2 is SV1 - SV2 > 0 mod (Z). C ), that is, k = 0; the constraint relationship between the translation values ​​corresponding to positions 1 and 3 is SV1 - SV3 + x > 0 mod (Z C ), that is, k=1; the constraint relationship between the translation values ​​corresponding to positions 2 and 3 is SV1-SV3-x>0mod(Z C ), that is, k = -1. The above is just an example. It can be understood that when a row in the first region has more positions containing the element "1", the constraint relationship between the translation values ​​corresponding to the two positions in each group can have other forms, but all satisfy the above constraint relationship: SV i -SV j +k·x>0mod(Z C ).

[0206] As mentioned above, in one implementation, the first value in the constraint relation is related to SV. i SV j It relates to the first translation value, which is a translation value in the translation value matrix corresponding to the first matrix. When the first matrix is ​​a submatrix B (or region B) of the base matrix, the first translation value is the translation value corresponding to the element in submatrix B. When the specific structure of submatrix B is different, the first translation value can be the translation value corresponding to the element at a specific position in submatrix B with a specific structure. Some examples are given below.

[0207] Example 1

[0208] Taking region B as an example with a double diagonal structure

[0209] In one implementation, region B includes one column with a weight of 3, and the remaining columns are columns with a weight of 2.

[0210] Figure 15 shows an example of a double diagonal structure in region B and its corresponding translation value matrix.

[0211] As shown in Figure 15, the left image is the first matrix BG0, and the right image is the translation value matrix BG_S0 corresponding to the first matrix. As described above, the position of element "1" in BG0 corresponds to any non-negative integer translation value in BG_S0; the position of element "0" in BG0 corresponds to a null value in BG_S0, which is represented by "-1" in Figure 15.

[0212] The first matrix shown in Figure 15 is the same as submatrix B of the basis matrix; that is, the first matrix at this time is submatrix B. Submatrix B is (i.e., BG0 is):

[0213] As can be seen, the structure of submatrix B is characterized by: a double diagonal structure, a column with a weight of 3, a degree distribution consisting of a column with a weight of 3 and the remaining columns with a weight of 2, and a coupled structure. This means that the structure cannot be easily split into two or more independent submatrices (i.e., split into shorter codes). The advantage of this structure is that encoding can be performed with high parallelism without requiring bit-level equation solving.

[0214] The element at the position of the 3rd row and 1st column of submatrix B is 1. This position is located in both the 3rd row and the 3rd column of the double diagonal structure.

[0215] If we represent the shift value corresponding to the position of the 3rd row and 1st column of BG_S0 as x 3_1 At this point, BG_S0 is:

[0216] As an example, when the first matrix is ​​submatrix B, and submatrix B has a double diagonal structure, the first translation value is the translation value corresponding to the element in submatrix B with a row weight of 3 and a column weight of 3, such as the translation value x. 3_1 .

[0217] In this case, suppose that for a certain row in the first region (e.g., row number 'row'), the column indices of the two columns containing the element "1" are represented as c. i c j SV i For the row number and cth row of the first region i The translation value corresponding to the column position, SV j For the row number and cth row of the first regionj The shift value corresponding to the column position. SV i and SV j The satisfied constraints can be described as follows:

[0218] SV i -SV j >0mod(Z c ), SV i -SV j +x 3_1 >0mod(Z c ), SV i -SV j -x 3_1 >0mod(Z c ).

[0219] At this point, k = 1 or k = -1 in the constraint relationship.

[0220] In this example, the columns of the first region contain all four core check columns of the B region. Therefore, for a row in the first region, if there are two or more positions with the element "1", the possible combinations of the indexes of the two columns corresponding to each pair of elements "1" are as follows: {1,2}, {1,3}, {1,4}, {2,3}, {2,4}, and {3,4}.

[0221] As an example, for any pair of elements "1" corresponding to the translation value SV i and SV j At least one of the following constraints must be satisfied:

[0222] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2, respectively. SV1-SV2>0 mod(Z) c );

[0223] The column indices corresponding to the two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3>0 mod(Z) c );

[0224] The column indices corresponding to the two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3+x 3_1 >0mod(Z c );

[0225] The column indices corresponding to the two elements "1" in a certain row of the first region are 1 and 4, respectively. SV1-SV4+x 3_1 >0mod(Z c );

[0226] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 4, respectively. SV1-SV4>0 mod(Z) c );

[0227] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3, respectively. SV2-SV3>0 mod(Z) c );

[0228] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3, respectively. SV2-SV3+x 3_1 >0mod(Z c );

[0229] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 4, respectively. SV2-SV4+x 3_1 >0mod(Z c );

[0230] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 4, respectively. SV2-SV4>0mod(Z) c );

[0231] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 3 and 4, respectively. SV3-SV4+x 3_1 >0mod(Z c );

[0232] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 3 and 4, respectively. SV3-SV4-x 3_1 >0mod(Z c );

[0233] The column indices corresponding to the two elements "1" in a certain row of the first region are 3 and 4, respectively. SV3 - SV4 > 0 mod (Z) c ).

[0234] In one example, the translation value SV corresponding to the positions of two "1" elements in a row of the first region. i and SV j Some or all of the items that satisfy the above constraints.

[0235] In one implementation, for the column index combination corresponding to the positions of two elements "1" in a row of the first region, at least one of the constraints involving that column index combination mentioned above must be satisfied. In other words, if the column indexes corresponding to the positions of two elements "1" in a row of the first region are a combination of 1 and 2, then at least one of the constraints listed above concerning column indices 1 and 2 must be satisfied; if the column indexes corresponding to the positions of two elements "1" in a row are a combination of 1 and 3, then at least one of the constraints listed above concerning column indices 1 and 3 must be satisfied; and so on, for column index combinations of 1 and 4, 2 and 3, 2 and 4, 3 and 4, the same applies. Further details will not be elaborated further.

[0236] Here is an example. For instance, the column indices corresponding to the two elements "1" in row #1 of the first region are 1 and 2, satisfying SV1-SV2>0 mod (Z). c The column indices corresponding to the two elements "1" in row #2 of the first region are 1 and 3, which satisfy SV1-SV3>0 mod (Z). c );

[0237] The column indices corresponding to the two elements "1" in row #3 of the first region are 1 and 4, which satisfy SV1-SV4+x. 3_1 >0mod(Z c The column indices corresponding to the two elements "1" in row #4 of the first region are 2 and 3, which satisfy SV2-SV3>0 mod (Z). c The other two elements "1" in row #4 of the first region have column indices of 2 and 4, satisfying SV2-SV4+x. 3_1 >0mod(Z c The column indices corresponding to the two elements "1" in row #5 of the first region are 3 and 4, satisfying SV3-SV4+x. 3_1 >0mod(Z c It is evident that for any combination of two column indexes, at least one of the constraints relating to the combination of column indexes is satisfied (i.e., at least one constraint relating to the combination of column indexes is satisfied).

[0238] In another example, the first region contains all items that satisfy the above constraints.

[0239] It should be noted that in the above constraints, the first translation value is x. 3_1 x 3_1 This represents the translation value corresponding to the position with a row weight of 3 and a column weight of 3 in a double-diagonal structure when the submatrix B of the base matrix is ​​double-diagonal. In the example above, since this position is located in the 3rd row and 1st column of the double-diagonal structure, it is represented by x. 3_1This indicates that, alternatively, when the double diagonal structure is a different variant, x... 3_1 It should also be replaced with the translation value corresponding to the position in the deformed structure where the row weight is 3 and the column weight is 3.

[0240] Example 2

[0241] Taking region B as an example of other encoding structures.

[0242] In one implementation, the column weight of all columns in region B is 3.

[0243] As an example, suppose the first matrix BG0 is a 4x4 matrix, then the first matrix BG0 is:

[0244] In this example, BG_S0 can be:

[0245] Where -x represents the translation value Z c -x, -2x indicates a translation value of Z. c -2x, and so on. x represents the translation value, which is the first translation value.

[0246] In Example 2, the columns of the first region contain all four core check columns of the B region. Therefore, for a row in the first region, if the row has two or more positions with the element "1", the possible combinations of the indexes of the two columns corresponding to each pair of elements "1" are as follows: {1,2}, {1,3}, {1,4}, {2,3}, {2,4}, and {3,4}.

[0247] As an example, with submatrix B (which is the first matrix BG0 in this example) and its corresponding translation matrix BG_S0 as shown above, the translation value SV corresponding to the positions of any two "1" elements in a row of the first region is... i and SV j At least one of the following constraints must be satisfied between them:

[0248] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2, respectively. SV1-SV2-3x>0mod(Z) c );

[0249] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2, respectively. SV1-SV2>0 mod(Z) c );

[0250] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2, respectively. SV1-SV2-2x>0mod(Z) c );

[0251] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2. SV1-SV2+2x>0 mod(Z) c );

[0252] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2. SV1-SV2+x>0mod(Z) c );

[0253] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2, respectively. SV1-SV2-x>0mod(Z) c );

[0254] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3-x>0mod(Z) c );

[0255] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3-3x>0mod(Z) c );

[0256] The column indices corresponding to the two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3>0 mod(Z) c );

[0257] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3-2x>0mod(Z) c );

[0258] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3+x>0mod(Z) c );

[0259] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3-x>0mod(Z) c );

[0260] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 4. SV1-SV4+x>0mod(Z) c );

[0261] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 4. SV1-SV4+2x>0 mod(Z) c );

[0262] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 4. SV1-SV4+3x>0mod(Z) c );

[0263] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3. SV2 - SV3 + 2x > 0 mod (Z) c );

[0264] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3, respectively. SV2-SV3>0 mod(Z) c );

[0265] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3, respectively. SV2-SV3-x>0mod(Z) c );

[0266] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3, respectively. SV2-SV3-3x>0mod(Z) c );

[0267] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3. SV2 - SV3 + x > 0 mod (Z) c );

[0268] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 4. SV2 - SV4 + 4x > 0 mod (Z) c );

[0269] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 4. SV2-SV4+x>0mod(Z) c );

[0270] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 4. SV2 - SV4 + 3x > 0 mod (Z) c );

[0271] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 3 and 4. SV3 - SV4 + 2x > 0 mod (Z) c );

[0272] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 3 and 4. SV3 - SV4 + 4x > 0 mod (Z) c ).

[0273] Similar to the implementation in Example 1, in one implementation, the translation value SV corresponding to the positions of the two "1" elements in a row of the first region is... i and SV j Some or all of the items that satisfy the above constraints.

[0274] For example, for the column index combination corresponding to the positions of two elements "1" in a row of the first region, at least one of the constraints involving that column index combination must be satisfied. In other words, if the column indexes corresponding to the positions of two elements "1" in a row of the first region are a combination of 1 and 2, then at least one of the constraints listed above involving column indices 1 and 2 is satisfied; if the column indexes corresponding to the positions of two elements "1" in a row are a combination of 1 and 3, then at least one of the constraints listed above involving column indices 1 and 3 is satisfied; and so on, for column index combinations of 1 and 4, 2 and 3, 2 and 4, 3 and 4, the same applies. Further details are omitted. For example, all items in the first region that satisfy the above constraints.

[0275] Based on the example above, the first region has at least one of the following implementations:

[0276] When the column indices corresponding to the positions of the two elements "1" are 1 and 2, that is, {c i ,c j}={1,2},{SV i ,SV j} = {SV1,SV2}, where k is a value from the set {-3,-2,-1,0,1,2};

[0277] When the column indices corresponding to the positions of the two elements "1" are 1 and 3, that is, {c i ,c j}={1,3},{SV i ,SV j} = {SV1,SV3}, where k is a value from the set {-3,-2,-1,0,1};

[0278] When the column indices corresponding to the positions of the two elements "1" are 1 and 4, that is, {c i ,c j}={1,4},{SV i ,SV j} = {SV1,SV4}, where k is a value from the set {1,2,3};

[0279] When the column indices corresponding to the positions of the two elements "1" are 2 and 3, that is, {c i ,c j}={2,3},{SV i ,SVj} = {SV2,SV3}, where k is a value from the set {-3,-1,0,1,2};

[0280] When the column indices corresponding to the positions of the two elements "1" are 2 and 4, that is, {c i ,c j}={2,4},{SV i ,SV j}={SV2,SV4}, where k is a value in the set {1,3,4}; and,

[0281] When the column indices corresponding to the positions of the two elements "1" are 3 and 4, that is, {c i ,c j}={3,4},{SV i ,SV j} = {SV3,SV4}, where k is a value in the set {2,4}.

[0282] In another example, assuming BG_S0 is a 4x4 matrix, the first matrix BG0 can be:

[0283] In this example, the translation value SV corresponds to the positions of any two "1" elements in a row of the first region. i and SV j At least one of the following constraints must be satisfied between them:

[0284] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2, respectively. SV1-SV2-2x>0mod(Z) c );

[0285] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2, respectively. SV1-SV2>0 mod(Z) c );

[0286] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2, respectively. SV1-SV2-x>0mod(Z) c );

[0287] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 2. SV1-SV2+x>0mod(Z) c );

[0288] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3-2x>0mod(Z) c );

[0289] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 3, respectively. SV1-SV3-x>0mod(Z) c );

[0290] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 4. SV1-SV4+x>0mod(Z) c );

[0291] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 1 and 4. SV1-SV4+2x>0 mod(Z) c );

[0292] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3, respectively. SV2-SV3>0 mod(Z) c );

[0293] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3, respectively. SV2-SV3-2x>0mod(Z) c );

[0294] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 3, respectively. SV2-SV3-x>0mod(Z) c );

[0295] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 4. SV2 - SV4 + 3x > 0 mod (Z) c );

[0296] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 4. SV2-SV4+x>0mod(Z) c );

[0297] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 2 and 4. SV2 - SV4 + 2x > 0 mod (Z) c );

[0298] The column indices corresponding to the positions of two elements "1" in a certain row of the first region are 3 and 4. SV3 - SV4 + 3x > 0 mod (Z) c ).

[0299] In one implementation, the translation value SV corresponds to the positions of two "1" elements in a row of the first region. i and SV j Some or all of the items that satisfy the above constraints.

[0300] For example, for the column index combination corresponding to the positions of two elements "1" in a row of the first region, at least one of the constraints involving that column index combination must be satisfied. In other words, if the column indexes corresponding to the positions of two elements "1" in a row of the first region are a combination of 1 and 2, then at least one of the constraints listed above involving column indices 1 and 2 is satisfied; if the column indexes corresponding to the positions of two elements "1" in a row are a combination of 1 and 3, then at least one of the constraints listed above involving column indices 1 and 3 is satisfied; and so on, for column index combinations of 1 and 4, 2 and 3, 2 and 4, 3 and 4, the same applies. Further details are omitted. For example, all items in the first region that satisfy the above constraints.

[0301] Based on the example above, the first region has at least one of the following implementations:

[0302] When the column indices corresponding to the positions of the two elements "1" are 1 and 2, that is, {c i ,c j}={1,2},{SV i ,SV j} = {SV1,SV2}, where k is a value in the set {-2,-1,0,1};

[0303] When the column indices corresponding to the positions of the two elements "1" are 1 and 3, that is, {c i ,c j}={1,3},{SV i ,SV j} = {SV1,SV3}, where k is a value in the set {-2,-1};

[0304] When the column indices corresponding to the positions of the two elements "1" are 1 and 4, that is, {c i ,c j}={1,4},{SV i ,SV j} = {SV1,SV4}, where k is a value from the set {1,2};

[0305] When the column indices corresponding to the positions of the two elements "1" are 2 and 3, that is, {c i ,c j}={2,3},{SV i ,SV j} = {SV2,SV3}, where k is a value in the set {-2,-1,0};

[0306] When the column indices corresponding to the positions of the two elements "1" are 2 and 4, that is, {c i ,c j}={2,4},{SV i ,SV j}={SV2,SV4}, where k is a value in the set {1,2,3}; and,

[0307] When the column indices corresponding to the positions of the two elements "1" are 3 and 4, that is, {c i ,c j}={3,4},{SV i ,SV j}={SV3,SV4},k=3.

[0308] Based on the examples above (such as the implementations of BG0 and BG_S0 given in Example 2), SV i and SV j The conditions that are met can be described as follows:

[0309] SV i -SV j +k·x>0mod(Z c ), where k = -C+1, -C+2, ..., 0, ..., C-2, C-1, and C is the number of columns in the first region.

[0310] The design of the translation values ​​corresponding to the elements of the first region of the basis matrix provided in this application has been described in detail above. It can be understood that, in addition to the examples given above, it also includes the implementation of row and / or column transformations on the translation value matrices given in these examples. Due to the characteristics of the translation values ​​of the basis matrix, the code will not change if any row and / or column is simultaneously increased or decreased by the same value. Therefore, the design of the translation values ​​corresponding to the elements of the first region of the basis matrix can also include the transformation obtained by simultaneously increasing or decreasing the same value in any row and / or any column of BG_S0 given in the above examples. Furthermore, there can be one or more rows and columns that increase or decrease the same value, without limitation. It can be understood that "increasing or decreasing the same value" refers to a single row or column; when more than one row and / or column increases or decreases the value, the increased or decreased values ​​in different rows or columns can be the same or different.

[0311] In Example 1 above, region B has a double diagonal structure, while in Example 2, region B has a structure where all columns have a weight of 3. The trap sets corresponding to these two structures of region B are different; therefore, the methods for enhancing the trap sets differ to specifically strengthen these two structures. For any structure of region B, the above embodiments provide various specific implementations of the constraint relationships (e.g., different values ​​for the first value in the constraint relationship, different values ​​for the first translation value, etc.). The purpose of these different implementations is to increase the number of external connections in the trap set, thereby reducing the error level.

[0312] After determining the translation value corresponding to each element at each position in each region of the basis matrix using the above method, the basis matrix can be expanded into a parity check matrix by combining the lifting factor.

[0313] In the example above, the columns of the first region contain all the core check columns of region B. As described above, in another case, the columns of the first region contain all the core check columns of region B and at least one information column from region A. In this implementation, for any row in the first region, the shift values ​​corresponding to any two elements "1" also satisfy the aforementioned constraint relationship SV. i -SV j +k·x>0 mod(Z C In addition, other constraints may also be satisfied.

[0314] After determining the design of the translation values ​​of the elements in the first region of the basis matrix based on the method provided in this application, the translation values ​​and lift values ​​Z corresponding to each element in the basis matrix are then used. c The base matrix is ​​then elevated to a parity-check matrix. The process by which the encoding device encodes based on the parity-check matrix is ​​well known to those skilled in the art and will not be described in detail here.

[0315] 630. The encoding device outputs the encoded sequence.

[0316] Optionally, this application also provides a decoding method corresponding to the encoding method. The decoding process may include steps 710 to 730.

[0317] 710. The decoding device acquires the received value sequence.

[0318] 720. The decoding device decodes the received value sequence based on the parity check matrix to obtain the decoded sequence.

[0319] The process of obtaining the parity check matrix can be referred to in step 620, and will not be repeated here.

[0320] 730. The decoding device outputs the decoding sequence.

[0321] In the technical solution of this application, a design scheme for the translation values ​​corresponding to the elements of the first region in the base matrix is ​​provided, which enables the base matrix to perform better in the error plane, improves the performance of the base matrix, and is conducive to improving the performance of the code obtained by encoding based on the base matrix.

[0322] Figures 16-24 show the LDPC performance simulation results of an implementation of the technical solution proposed in this application. The horizontal axis represents the signal-to-noise ratio (SNR), and the vertical axis represents the block error rate (BLER). The LDPC represented by the asterisk symbol includes one implementation of the technical solution proposed in this application (refer to Figure 7). This can be understood as an implementation where the first region includes at least two columns of region B, but does not include columns of region A. Specifically, referring to this LDPC design, under several different code lengths and code rates, the LDPC design of this application can significantly outperform 5G BG2 in the (ultra)high reliability range (e.g., BLER = 1e-6, 1e-7), exhibiting a gain of 0.7dB to 1.2dB in all cases. Other implementations in this application (which can be understood as implementations where the first region includes at least two columns of region B and at least one column of region A) also have similar performance advantages, as shown in Figures 16-24.

[0323] The communication device provided in this application is described below.

[0324] Figure 25 is a schematic structural diagram of the communication device 1000 provided in this application. The communication device 1000 can be an encoding-side device, or a device applied to the encoding-side device and capable of implementing the corresponding functions of the encoding-side device in the method embodiments of this application, such as a chip, processor, or circuit. Alternatively, the communication device 1000 can be a decoding-side device, or a device applied to the decoding-side device and capable of implementing the corresponding functions of the decoding-side device in the method embodiments of this application, such as a chip, processor, or circuit.

[0325] Optionally, the communication device 1000 includes a processing module 1001, which may be a processor, a processing board, a processing unit, or a processing device, etc. When the communication device 1000 is an encoding-side device or a device applied to an encoding-side device, the processing module 1001 is used to: encode information bits based on a parity check matrix to obtain an encoded sequence, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here. When the communication device 1000 is a decoding-side device or a device applied to a decoding-side device, the processing module 1001 is used to: decode the received value sequence based on a parity check matrix to obtain a decoded sequence, etc. Specific processes can be found in the detailed descriptions of the corresponding steps in the method embodiments, and will not be repeated here.

[0326] Optionally, the communication device 1000 further includes a communication module 1002, which may also be referred to as a transceiver module, transceiver, transceiver unit, or transceiver device, etc., for performing receiving (or input) and / or sending (or output) operations. For example, when the communication device 1000 is an encoding-side device or a device applied to an encoding-side device, the communication module 1002 can be used to acquire information bits and transmit the information bits to be encoded to the processing module 1001; and output the encoded sequence obtained by the processing module 1001 through encoding. When the communication device 1000 is a decoding-side device or a device applied to a decoding-side device, the communication module 1002 can be used to acquire a received value sequence and send the received value sequence to the processing module 1001; and output the decoded sequence obtained by the processing module 1001 decoding the received value sequence.

[0327] The aforementioned communication module and / or processing module can be implemented as a virtual module. For example, the processing module can be implemented as a software functional unit or a virtual device, and the communication module can be implemented as a software function or a virtual device. Alternatively, the processing module or communication module can also be implemented as a physical device, such as a chip / circuit (e.g., an integrated circuit or logic circuit). The communication module can be an input / output circuit and / or a communication interface, performing input operations (corresponding to the aforementioned receiving operation) and output operations (corresponding to the aforementioned sending operation); the processing module is an integrated processor, microprocessor, or circuit (e.g., an integrated circuit, logic circuit).

[0328] The module division in this application is illustrative and represents only one logical functional division. In actual implementation, other division methods are possible. Furthermore, the functional modules in the various examples of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware, as software functional modules, or a combination of hardware and software.

[0329] Figure 26 is a schematic structural diagram of another communication device provided in this application. The communication device 1100 can be used to implement the functions of any communication device (e.g., an encoding-side device or a decoding-side device) in the communication system described in the foregoing examples. The communication device 1100 may include at least one processor 1110. Optionally, the processor 1110 (or processing device) is coupled to a memory, which may be located within the communication device, integrated with the processor, or located outside the communication device. For example, the communication device 1100 may also include at least one memory 1120. The memory 1120 stores computer programs, instructions, or data necessary for implementing any of the above method embodiments; the processor 1110 may execute the computer programs, instructions, or data stored in the memory 1120 to perform the corresponding functions of the encoding-side device or decoding-side device in any of the above embodiments.

[0330] Optionally, the communication device 1100 may further include a communication interface 1130, through which the communication device 1100 can interact with other devices. For example, the communication interface 1130 may be a transceiver, circuit, bus, module, pin, or other type of communication interface. When the communication device 1100 is a chip-type device or circuit, the communication interface 1130 in the device 1100 may also be an input / output circuit, capable of inputting information (or receiving information) and / or outputting information (or sending information). The processor may be an integrated circuit or logic circuit, etc., and the processor can determine the output information based on the input information.

[0331] The coupling in this application refers to indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, for information exchange between devices, units, or modules. The processor 1110 may operate in conjunction with the memory 1120 and the communication interface 1130. This application does not limit the connection medium between the processor 1110, the memory 1120, and the communication interface 1130.

[0332] Figure 27 is a schematic structural diagram of the chip provided in this application. Chip 30 includes circuit 31 and communication interface 32. Circuit 31 can be a logic circuit, integrated circuit, etc., and communication interface 32 can also be called input / output circuit, input / output interface, interface circuit, etc., which can input information (or receive information) or output information (or send information). Chip 30 can execute the methods executed by the encoding-side device or decoding-side device in the various embodiments of this application.

[0333] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause operations and / or processes performed by an encoding-side device or a decoding-side device in the various method embodiments of this application to be executed.

[0334] This application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the encoding-side device or decoding-side device in the various method embodiments of this application are executed.

[0335] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory, such that operations and / or processes performed by an encoding-side device or a decoding-side device in any method embodiment are executed. Further, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Further, the chip may also include the memory.

[0336] This application provides a communication system, including the encoding-side device and decoding-side device in the above method embodiments.

[0337] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0338] The processor in this application embodiment has signal processing capabilities and can be a central processing unit (CPU), or a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. It can implement or execute the methods, steps, and logic block diagrams disclosed in this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in this application can be directly implemented by the hardware processor, or implemented by a combination of hardware and software modules within the processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0339] In the embodiments of this application, the memory can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM). The memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0340] The technical solutions provided in this application can be implemented in whole or in part through software, hardware, firmware, or any combination thereof. When implemented using software, they can be implemented in whole or in part as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a terminal device, an access network device, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., digital video discs (DVDs)), or semiconductor media, etc.

[0341] In this application's embodiments, "at least one" refers to one or more items, and "multiple" refers to two or more items. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of a single item, a plural item, or all items. For example, "at least one of A, B, and C" includes A, B, C, AB, AC, BC, or ABC. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0342] The term "comprising" and any variations thereof used in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0343] In this application, examples may reference each other without logical contradiction. For example, methods and / or terms between method embodiments may reference each other, functions and / or terms between device embodiments may reference each other, and functions and / or terms between device examples and method examples may reference each other.

[0344] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0345] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0346] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0347] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0348] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0349] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

Claims

1. An encoding method, characterized in that, include: Obtain information bits; The information bits are encoded based on a parity-check matrix to obtain an encoded sequence. The parity-check matrix is ​​obtained based on the shift values ​​corresponding to each element in a base matrix. The base matrix includes a first region, the columns of which include at least two core parity columns of the base matrix, and the rows of which include rows in the incremental redundancy region of the base matrix containing at least two elements "1". The shift values ​​corresponding to any two of the at least two "1" elements satisfy a constraint relationship, which includes: the result of taking the modulo of a first value with respect to a boost value is not zero, wherein the first value is related to the shift values ​​corresponding to any two of the at least two "1" elements; and... Output the encoded sequence.

2. The method as described in claim 1, characterized in that, The columns of the first region also include at least one column from the information columns of the base matrix.

3. The method as described in claim 1 or 2, characterized in that, The first value is related to the translation values ​​corresponding to any two elements "1" and the first translation value. The first translation value is one of the translation values ​​corresponding to each element in the first matrix. The rows of the first matrix include the core rows of the base matrix, and the columns of the first matrix include the columns of the first region. The first element corresponding to the first translation value in the first matrix is ​​located in the at least two core verification columns. The first translation value is a non-zero integer.

4. The method as described in claim 3, characterized in that, The element in the i-th row and j-th column of the first matrix is ​​1, and the translation value corresponding to the element in the i-th row and j-th column of the first matrix is ​​x. i_j x i_j It can be any non-negative integer; or, The elements in the i-th row and j-th column of the first matrix are 0, and the translation values ​​corresponding to the elements in the i-th row and j-th column of the first matrix are null values.

5. The method as described in claim 3 or 4, characterized in that, The first region includes rows with row index q, and the column index corresponding to any two elements "1" in the row with row index q is c. i and c j The first row includes the position (q, c) i ) and (q,c j The position (q, c) i ) and (q,c j The corresponding translation values ​​are SV. i and SV j ; The constraint relationship includes: SV i -SV j +k·x>0 mod(Z C ), wherein: SV i -SV j +k-x is the first value, x is the first translation value; and, Z C is the boost value, and Z C is the SV i and SV j a boost value in the corresponding first set of boost values, k being an integer.

6. The method as described in claim 1 or 2, characterized in that, The constraint relationship includes: SV i -SV j > 0 mod (Z C ), wherein SV i -SV j is the first value, Z C is the promotion value, SV i and SV j are translation values corresponding to the arbitrary two elements "1".

7. The method as described in claim 5, characterized in that, The k·x can be any positive integer, or the k·x can be any negative integer.

8. The method according to any one of claims 3-5, 7, characterized in that, The rows of the first matrix include the core rows of the base matrix, the columns of the first matrix include all the core check cases of the base matrix, the first matrix includes a column with a weight of 3, and the weights of the remaining columns of the first matrix other than the column with a weight of 3 are 2; and the first shift value is the shift value corresponding to the element in the first matrix located at the position with a row weight of 3 and a column weight of 3.

9. The method according to any one of claims 3-5, 7-8, characterized in that, The first matrix is ​​a 4x4 matrix, and the first matrix is ​​as follows: the first translation value is a translation value x corresponding to an element of the first matrix located at a position of the 3rd row and the 1st column 3_1 .

10. The method as described in claim 8 or 9, characterized in that, k = 1 or k = -1.

11. The method as described in claim 5, characterized in that, k is a value in the set {-(C-1),-(C-2),…,0,…,C-2,C-1}, and C is the number of columns in the first region.

12. The method as described in claim 11, characterized in that, The rows of the first matrix include the core rows of the base matrix, the columns of the first matrix include all the core check columns of the base matrix, and the column weight of all columns of the first matrix is ​​3.

13. The method as described in claim 11 or 12, characterized in that, The base matrix includes 4 core check columns, column indexes of the 4 core check columns are 1-4; and the SV i and SV j satisfies at least one of the following: When the {c i ,c j} = {1,2}, the {SV i ,SV j} = {SV1,SV2}, and k is one value in the set {-3,-2,-1,0,1,2}. When the {c i ,c j }={1,3}, the {SV i ,SV j } = {SV1,SV3}, where k is a value from the set {-3,-2,-1,0,1}; When the {c i ,c j }={1,4}, the {SV i ,SV j } = {SV1,SV4}, where k is a value from the set {1,2,3}; When the {c i ,c j }={2,3}, the {SV i ,SV j } = {SV2,SV3}, where k is a value from the set {-3,-1,0,1,2}; When the {c i ,c j }={2,4}, the {SV i ,SV j } = {SV2,SV4}, where k is a value from the set {1,3,4}; When the {c i ,c j }={3,4}, the {SV i ,SV j } = {SV3, SV44}, where k is a value in the set {2, 4}.

14. The method according to any one of claims 3-5, 11-13, characterized in that, The first matrix is ​​a 4x4 matrix, and the matrix of translation values ​​corresponding to each element in the first matrix is ​​as follows:

15. The method as described in claim 11 or 12, characterized in that, The base matrix includes four core check columns, with column indices of 1 to 4; and the SV i and SV j At least one of the following must be met: When the {c i ,c j }={1,2}, the {SV i ,SV j } = {SV1,SV2}, where k is a value in the set {-2,-1,0,1}; When the {c i ,c j }={1,3}, the {SV i ,SV j } = {SV1,SV3}, where k is a value in the set {-2,-1}; When the {c i ,c j }={1,4}, the {SV i ,SV j } = {SV1,SV4}, where k is a value from the set {1,2}; When the {c i ,c j }={2,3}, the {SV i ,SV j } = {SV2,SV3}, where k is a value in the set {-2,-1,0}; When the {c i ,c j }={2,4}, the {SV i ,SV j } = {SV2,SV4}, where k is a value from the set {1,2,3}; When the {c i ,c j }={3,4}, the {SV i ,SV j }={SV3,SV4},k=3.

16. The method according to any one of claims 3-5, 11-12, and 15, characterized in that, The first matrix is ​​a 4x4 matrix, and the matrix of translation values ​​corresponding to each element in the first matrix is ​​as follows:

17. A decoding method, characterized in that, include: Obtain the sequence of received values; The received value sequence is decoded based on a parity-check matrix to obtain a decoded sequence. The parity-check matrix is ​​obtained based on the translation values ​​corresponding to each element in a base matrix. The base matrix includes a first region, the columns of which include at least two core parity columns of the base matrix, and the rows of which include rows in the incremental redundancy region of the base matrix containing at least two elements "1". The translation values ​​corresponding to any two of the at least two "1" elements satisfy a constraint relationship, which includes: the result of taking the modulus of a first value with respect to a boost value is not zero, wherein the first value is related to the translation values ​​corresponding to any two of the at least two "1" elements; and... Output the decoded sequence.

18. The method as described in claim 17, characterized in that, The columns of the first region also include at least one column from the information columns of the base matrix.

19. The method as described in claim 17 or 18, characterized in that, The first value is related to the translation values ​​corresponding to any two elements "1" and the first translation value. The first translation value is one of the translation values ​​corresponding to each element in the first matrix. The rows of the first matrix include the core rows of the base matrix, and the columns of the first matrix include the columns of the first region. The first element corresponding to the first translation value in the first matrix is ​​located in the at least two core verification columns. The first translation value is a non-zero integer.

20. The method as described in claim 19, characterized in that, The element in the i-th row and j-th column of the first matrix is ​​1, and the translation value corresponding to the element in the i-th row and j-th column of the first matrix is ​​x. i_j x i_j It can be any non-negative integer; or, The elements in the i-th row and j-th column of the first matrix are 0, and the translation values ​​corresponding to the elements in the i-th row and j-th column of the first matrix are null values.

21. The method as described in claim 19 or 20, characterized in that, The first region includes rows with row index q, and the column index corresponding to any two elements "1" in the row with row index q is c. i and c j The first row includes the position (q, c) i ) and (q,c j The position (q, c) i ) and (q,c j The corresponding translation values ​​are SV. i and SV j ; The constraints include: SV i -SV j +k·x>0 mod(Z C ),in: SV i -SV j +k·x is the first value, x is the first translation value; and, Z C The increase value is Z, and Z C For SV i and the SV j The corresponding first lift value is one of the lift values ​​in the set of lift values, where k is an integer.

22. The method as described in claim 17 or 18, characterized in that, The constraints include: SV i -SV j >0 mod(Z C ), where SV i -SV j Z is the first value. C For the aforementioned boost value, SV i and SV j The translation value is the value corresponding to any two elements "1".

23. The method as described in claim 21, characterized in that, The k·x can be any positive integer, or the k·x can be any negative integer.

24. The method according to any one of claims 19-21, 23, characterized in that, The rows of the first matrix include the core rows of the base matrix, the columns of the first matrix include all the core check cases of the base matrix, the first matrix includes a column with a weight of 3, and the weights of the remaining columns of the first matrix other than the column with a weight of 3 are 2; and the first shift value is the shift value corresponding to the element in the first matrix located at the position with a row weight of 3 and a column weight of 3.

25. The method according to any one of claims 19-21, 23-24, characterized in that, The first matrix is ​​a 4x4 matrix, and the first matrix is ​​as follows: The first translation value is the translation value x corresponding to the element located in the 3rd row and 1st column of the first matrix. 3_1 .

26. The method as described in claim 24 or 25, characterized in that, k = 1 or k = -1.

27. The method as described in claim 21, characterized in that, k is a value in the set {-(C-1),-(C-2),…,0,…,C-2,C-1}, and C is the number of columns in the first region.

28. The method as described in claim 27, characterized in that, The rows of the first matrix include the core rows of the base matrix, the columns of the first matrix include all the core check columns of the base matrix, and the column weight of all columns of the first matrix is ​​3.

29. The method as described in claim 27 or 28, characterized in that, The base matrix includes four core check columns, with column indices of 1 to 4; and the SV i and SV j At least one of the following must be met: When the {c i ,c j }={1,2}, the {SV i ,SV j } = {SV1,SV2}, where k is a value from the set {-3,-2,-1,0,1,2}; When the {c i ,c j }={1,3}, the {SV i ,SV j } = {SV1,SV3}, where k is a value from the set {-3,-2,-1,0,1}; When the {c i ,c j }={1,4}, the {SV i ,SV j } = {SV1,SV4}, where k is a value from the set {1,2,3}; When the {c i ,c j }={2,3}, the {SV i ,SV j } = {SV2,SV3}, where k is a value from the set {-3,-1,0,1,2}; When the {c i ,c j }={2,4}, the {SV i ,SV j } = {SV2,SV4}, where k is a value from the set {1,3,4}; When the {c i ,c j }={3,4}, the {SV i ,SV j } = {SV3,SV4}, where k is a value in the set {2,4}.

30. The method according to any one of claims 19-21, 27-29, characterized in that, The first matrix is ​​a 4x4 matrix, and the matrix of translation values ​​corresponding to each element in the first matrix is ​​as follows:

31. The method as described in claim 27 or 28, characterized in that, The base matrix includes four core check columns, with column indices of 1 to 4; and the SV i and SV j At least one of the following must be met: When the {c i ,c j }={1,2}, the {SV i ,SV j } = {SV1,SV2}, where k is a value in the set {-2,-1,0,1}; When the {c i ,c j }={1,3}, the {SV i ,SV j } = {SV1,SV3}, where k is a value in the set {-2,-1}; When the {c i ,c j }={1,4}, the {SV i ,SV j } = {SV1,SV4}, where k is a value from the set {1,2}; When the {c i ,c j }={2,3}, the {SV i ,SV j } = {SV2,SV3}, where k is a value in the set {-2,-1,0}; When the {c i ,c j }={2,4}, the {SV i ,SV j } = {SV2,SV4}, where k is a value from the set {1,2,3}; When the {c i ,c j }={3,4}, the {SV i ,SV j }={SV3,SV4},k=3.

32. The method according to any one of claims 19-21, 27-28, and 31, characterized in that, The first matrix is ​​a 4x4 matrix, and the matrix of translation values ​​corresponding to each element in the first matrix is ​​as follows:

33. An encoding device, characterized in that, include: The communication module is used to acquire information bits. A processing module is used to encode the information bits based on a parity-check matrix to obtain an encoded sequence. The parity-check matrix is ​​obtained based on the shift values ​​corresponding to each element in a base matrix. The base matrix includes a first region, the columns of which include at least two core parity columns of the base matrix, and the rows of which include rows in the incremental redundancy region of the base matrix containing at least two elements "1". The shift values ​​corresponding to any two of the at least two "1" elements satisfy a constraint relationship, which includes: the result of taking the modulus of a first value with respect to a boost value is not zero, wherein the first value is related to the shift values ​​corresponding to any two of the at least two "1" elements; and... The communication module is also used to output the encoded sequence.

34. A decoding device, characterized in that, include: The communication module is used to: acquire the sequence of received values; A processing module is used to decode the received value sequence based on a parity check matrix to obtain a decoded sequence. The parity check matrix is ​​obtained based on the translation values ​​corresponding to each element in a base matrix. The base matrix includes a first region, the columns of which include at least two core parity check columns of the base matrix, and the rows of which include rows in the incremental redundancy region of the base matrix containing at least two elements "1". The translation values ​​corresponding to any two of the at least two "1" elements satisfy a constraint relationship, which includes: the result of taking the modulus of a first value with respect to a boost value is not zero, wherein the first value is related to the translation values ​​corresponding to any two of the at least two "1" elements; and... The communication module is also used to output the decoded sequence.

35. A communication device, characterized in that, The system includes a communication interface and circuitry. The communication interface is used to acquire information required to perform the method as described in any one of claims 1-16, and to send the information to the circuitry, which is used to perform the method as described in any one of claims 1-16 based on the received information; or... The communication interface is used to acquire information required to perform the method as described in any one of claims 17-32, and to send the information to the circuit, which is used to perform the method as described in any one of claims 17-32 based on the received information.

36. A communication device, characterized in that, Includes modules or units for performing the method as described in any one of claims 1-32.

37. A communication device, characterized in that, The device includes a processor coupled to a memory, the processor being configured to execute a computer program or instructions stored in the memory to cause the communication device to perform the method as described in any one of claims 1-32.

38. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that, when executed on a computer, implement the method as described in any one of claims 1-32.

39. A computer program product, characterized in that, It includes computer program code or instructions, which, when run on a computer, implement the method as described in any one of claims 1-16, or the method as described in any one of claims 17-32.

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