Solar cell and preparation method therefor, and electrical device

Abstract

Provided in the present application are a solar cell and a preparation method therefor, and an electrical device. The solar cell comprises: a first electrode; and a polysilicon layer, which comprises an electrode contact region and an electrode non-contact region that are distributed along a first direction, wherein the electrode contact region corresponds to the position of the first electrode, the first direction intersects with the direction from the first electrode to the polysilicon layer, and the electrode non-contact region is doped with light atoms, which light atoms include one or more of carbon, nitrogen and oxygen.

Description

Solar cells and their preparation methods, and electrical equipment

[0001] This application claims priority to Chinese patent applications filed on April 14, 2025, with application number 202510479410.7, filed on June 20, 2025, with application number 202510838523.1, filed on June 30, 2025, with application number 202510901631.9, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of solar cells, specifically to a solar cell and its preparation method and electrical equipment. Background Technology

[0003] A solar cell is a semiconductor device that converts light energy into electrical energy based on the photovoltaic effect. There are many types of solar cells, such as crystalline silicon solar cells, gallium arsenide thin-film solar cells, and organic thin-film solar cells. Among these types of solar cells, crystalline silicon solar cells are widely used in human production and daily life because they are green, low-cost, and the most efficient.

[0004] In crystalline silicon solar cells, the photoelectric conversion efficiency of the cells needs to be further improved. Summary of the Invention

[0005] This application provides a solar cell and its preparation method, as well as an electrical device, which helps to reduce parasitic absorption losses in TOPCon cells while avoiding increased resistance.

[0006] This application provides a solar cell, comprising: a first electrode; a polycrystalline silicon layer including an electrode contact region and an electrode non-contact region distributed along a first direction, wherein the electrode contact region corresponds to the position of the first electrode, and the first direction intersects the direction along the first electrode to the polycrystalline silicon layer; the electrode non-contact region is doped with light atoms, wherein the light atoms include one or more of carbon, nitrogen, and oxygen.

[0007] In some embodiments, the non-contact region of the electrode is further doped with a first atom, the first atom comprising one or more of phosphorus and boron.

[0008] In some embodiments, in the electrode non-contact area, the ratio of the number of light atoms to the number of the first atoms is 1% to 150%.

[0009] In some embodiments, the number of the first atoms in the electrode non-contact region is 10. 17 ~10 22pcs / cm 3 .

[0010] In some embodiments, the electrode contact region is doped with a second atom, the second atom comprising one or more of phosphorus and boron.

[0011] In some embodiments, the number of the second atoms in the electrode contact region is 10. 17 ~10 22 pcs / cm 3 .

[0012] In some embodiments, the second atom does not include the light atom.

[0013] In some embodiments, the substrate further includes a substrate, wherein the first electrode is provided on both opposite sides of the substrate.

[0014] In some embodiments, at least one side of the substrate is further provided with the polycrystalline silicon layer.

[0015] In some embodiments, the thickness of the electrode contact area is 1–500 nm; and / or, the thickness of the electrode non-contact area is 1–500 nm.

[0016] This application also provides a method for fabricating a solar cell as described above, comprising: forming the polycrystalline silicon layer, wherein the doped polycrystalline silicon layer includes a first opening corresponding to the first electrode and an electrode non-contact region defining the first opening; forming the electrode contact region of the doped polycrystalline silicon layer in the first opening; and disposing the first electrode at a position corresponding to the electrode contact region to obtain the solar cell.

[0017] In some embodiments, the method further includes: providing a substrate; and forming the polycrystalline silicon layer on at least one side of the substrate.

[0018] This application provides an electrical device, including a solar cell as described above or a solar cell prepared according to the preparation method described above, wherein the solar cell serves as the power supply for the electrical device.

[0019] The application provides a solar cell and a preparation method thereof and an electric device. Since the bond energy of the bond between a light atom and a Si atom is large, doping the light atom can effectively increase the band gap of a poly-Si layer, reduce the absorption of low-energy photons, help reduce the parasitic absorption loss of the poly-Si layer, and the electrode non-contact area is not blocked by the electrode and is a main area for absorbing sunlight in the solar cell. Doping the light atom in the electrode non-contact area (metal non-blocking area) can greatly reduce the parasitic absorption loss, thereby helping to optimize the open-circuit voltage, improve the short-circuit current and conversion efficiency. Meanwhile, the electrode non-contact area doped with the light atom does not correspond to the position of the electrode (first electrode), which helps to reduce the adverse effects of the light atom on the carrier transport and collection, avoids the loss of the fill factor, and avoids the increase of the cell resistance. Therefore, the solar cell in the embodiments of the application can have good optical and electrical properties, high open-circuit voltage, short-circuit current and photoelectric conversion efficiency, and high fill factor and low resistance. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0021] FIG. 1 is a structural schematic diagram of a solar cell of Comparative Example 1;

[0022] FIG. 2 is a structural schematic diagram of a solar cell of some embodiments;

[0023] FIG. 3 is a structural schematic diagram of a solar cell of some embodiments;

[0024] FIG. 4 is a schematic diagram of a back surface selective emitter structure of a solar cell in the prior art;

[0025] FIG. 5 is a schematic diagram of a back surface selective emitter structure of a solar cell in an embodiment of the application;

[0026] FIG. 6 is a schematic diagram of a back surface selective emitter structure of a solar cell in an embodiment of the application;

[0027] FIG. 7 is a schematic diagram of a back surface selective emitter structure of a solar cell in an embodiment of the application;

[0028] FIG. 8 is a schematic diagram of a back surface selective emitter structure of a solar cell in an embodiment of the application;

[0029] FIG. 9 is a schematic diagram of a back surface selective emitter structure of a solar cell in an embodiment of the application;

[0030] Fig. 10 is a cross-sectional view of a single crystal silicon substrate according to an embodiment of the present application;

[0031] Fig. 11 is a cross-sectional view of an intermediate product according to an embodiment of the present application, in which a first mask is formed on a single crystal silicon substrate;

[0032] Fig. 12 is a cross-sectional view of an intermediate product according to an embodiment of the present application, in which a second mask is formed on a single crystal silicon substrate;

[0033] Fig. 13 is a cross-sectional view of an intermediate product according to an embodiment of the present application, in which a second passivation layer for a back surface and a second passivation layer for a side surface are formed on a substrate having a textured surface on a light receiving surface;

[0034] Fig. 14 is a cross-sectional view of an intermediate product according to an embodiment of the present application, in which a first passivation layer for a light receiving surface is formed on a substrate having a textured surface on a light receiving surface;

[0035] Fig. 15 is a cross-sectional view of an intermediate product according to an embodiment of the present application, in which a first passivation layer for a light receiving surface is formed on a substrate having a textured surface on a light receiving surface;

[0036] Fig. 16 is a cross-sectional view of an intermediate product according to an embodiment of the present application, in which a second doped layer for a back surface is formed on a substrate;

[0037] Fig. 17 is a cross-sectional view of an intermediate product according to an embodiment of the present application, in which a first oxide layer for a light receiving surface is formed on a substrate;

[0038] Fig. 18 is a cross-sectional view of an intermediate product according to an embodiment of the present application, in which a second oxide layer is formed on a back surface of a substrate;

[0039] Fig. 19 is a schematic view of a solar cell according to an embodiment of the present application;

[0040] Fig. 20 is a cross-sectional view of an intermediate product according to another embodiment of the present application, in which a first passivation layer for a light receiving surface and a first passivation layer for a side surface are formed on a substrate;

[0041] Fig. 21 is a cross-sectional view of an intermediate product according to another embodiment of the present application, in which a first doped layer for a light receiving surface and a first doped layer for a side surface are formed on a substrate;

[0042] Fig. 22 is a cross-sectional view of an intermediate product according to another embodiment of the present application, in which a second doped layer for a back surface and a second doped layer for a side surface are formed on a substrate;

[0043] Fig. 23 is a cross-sectional view of an intermediate product according to another embodiment of the present application, in which a first oxide layer for a light receiving surface and a first oxide layer for a side surface are formed on a substrate;

[0044] Fig. 24 is a cross-sectional view of an intermediate product according to another embodiment of the present application, in in which a second oxide layer is formed on a back surface of a substrate;

[0045] Fig. 25 is a schematic view of a solar cell according to another embodiment of the present application;

[0046] Figure 26 is a circuit diagram of an existing photovoltaic module containing a bypass diode;

[0047] Figure 27 is a circuit diagram of the photovoltaic module without a bypass diode according to this application.

[0048] Reference numerals: 1 Substrate, 3 Polysilicon layer, 4 Passivation layer, 5 Anti-emission layer, 6 First electrode; 31 Electrode contact area, 32 Electrode non-contact area; 10 Silicon substrate, 20 Tunneling layer, 30 Doped polysilicon layer, 30-1 First doped polysilicon layer, 30-2 Second doped polysilicon layer, 40 Barrier layer, 50 Passivation and anti-reflection layer, 60 Electrode, 70 Intrinsic polysilicon layer; 100 Single crystal silicon substrate, 102 First mask layer, 103 Second mask layer, 201 First passivation layer, 202 First passivation layer on the side, 211 First doped layer, 212 First doped layer on the side, 301 Second passivation layer, 302 Second passivation layer on the side, 311 Second doped layer, 312 Second doped layer on the side, 221 First oxide layer, 222 First oxide layer on the side, 321 Second oxide layer, 231 First gate line, 331 Second gate line. Detailed Implementation

[0049] To enable those skilled in the art to better understand the solutions of this application, a further detailed description of this application is provided below. The specific embodiments listed below are merely descriptions of the principles and features of this application; the examples are only for explaining this application and are not intended to limit its scope. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0050] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0051] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0052] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0053] In this application, substrate, N-type silicon substrate, silicon substrate, and monocrystalline silicon substrate all refer to the underlying material used to support photoelectric conversion materials and serve as the structural basis in solar cells.

[0054] Metal contact area and electrode contact area both refer to the areas in a solar cell where the metal electrode and semiconductor material are in direct contact to achieve current conduction. Non-metal contact area and electrode non-contact area both refer to the areas in a solar cell that are not covered by metal electrodes, which avoid recombination loss and may be used for light absorption or passivation.

[0055] Anti-reflective layer and passivation anti-reflection layer both refer to thin film layers on the surface of solar cells that improve light absorption efficiency by reducing light reflection.

[0056] A quantum tunneling layer is an ultrathin insulating oxide layer in a solar cell (such as the TOPCon structure) that allows charge carriers to tunnel through.

[0057] The TOPCon cell structure includes a silicon dioxide (SiO2) layer and a polycrystalline silicon (polySi) layer, which respectively provide excellent chemical and field passivation, allowing only majority carriers to selectively pass through and be collected by the electrodes. The passivation structure formed by the silicon dioxide (SiO2) layer and the polycrystalline silicon (polySi) layer significantly improves the theoretical maximum efficiency of the TOPCon cell, reaching 28.7%.

[0058] However, in practical applications, due to limitations in existing fabrication processes, polysilicon (polySi) layers are often doped with a large number of phosphorus / boron atoms, leading to significant parasitic absorption losses. To reduce these losses, it is possible to dope the polysilicon (polySi) layer with light atoms, such as carbon, nitrogen, and oxygen. The bond energies between the doped light atoms and Si atoms are larger, effectively increasing the band gap of the polySi layer and reducing its absorption of low-energy photons, thus helping to lower parasitic absorption losses. However, since the doped light atoms occupy lattice sites, they inevitably suppress the activation of phosphorus / boron atoms, thereby reducing the transport and collection of majority carriers in the polySi layer and increasing the cell resistance.

[0059] Therefore, how to reduce the parasitic absorption loss of TOPCon batteries while avoiding increasing resistance is a technical problem that urgently needs to be solved in the field.

[0060] In order to overcome the defects in the prior art, in a first aspect, embodiments of this application provide a solar cell, including: a first electrode; a polycrystalline silicon layer including an electrode contact area and an electrode non-contact area distributed along a first direction, the electrode contact area corresponding to the position of the first electrode, the first direction intersecting the direction from the first electrode to the polycrystalline silicon layer; the electrode non-contact area is doped with light atoms, the light atoms including one or more of carbon, nitrogen and oxygen.

[0061] According to research and analysis, since the bond energy between light atoms and Si atoms is relatively large, doping with light atoms can effectively adjust the band gap of the polysilicon layer (polySi layer), reduce the absorption of low-energy photons, and help reduce parasitic absorption losses in the polysilicon layer. In addition, the electrode non-contact area is not blocked by the electrode and is the main area for absorbing sunlight in solar cells. Doping with light atoms in the electrode non-contact area (metal non-blocking area) can further reduce parasitic absorption losses, thereby helping to optimize open-circuit voltage, improve short-circuit current and conversion efficiency. At the same time, the electrode non-contact area doped with light atoms does not correspond to the position of the electrode (first electrode), which helps to reduce the adverse effects of light atoms on carrier transport and collection, avoid loss of fill factor and avoid increase in cell resistance.

[0062] Therefore, the solar cells of the present application embodiments can achieve both good optical and electrical performance, with high open-circuit voltage, short-current and photoelectric conversion efficiency, as well as high fill factor and low resistance.

[0063] The first direction intersects with the direction along the first electrode to the polysilicon layer (the second direction). Understandably, the first direction and the second direction are not parallel.

[0064] Specifically, the first direction is perpendicular to the direction along the first electrode to the polysilicon layer.

[0065] The polycrystalline silicon layer includes an electrode contact region and an electrode non-contact region distributed along a first direction. That is, along the first direction, the polycrystalline silicon layer is divided into an electrode contact region and an electrode non-contact region.

[0066] The electrode contact area corresponds to the position of the first electrode. This can be understood as the first electrode blocking the electrode contact area, preventing at least a portion of the contact area from receiving sunlight.

[0067] Specifically, the first electrode is in contact with the surface of the electrode contact area. In this way, the first electrode collects the current generated by each part of the solar cell through the electrode contact area and blocks the electrode contact area, so that at least a part of the electrode contact area cannot receive sunlight.

[0068] Understandably, the position of the non-contact area of ​​the electrode does not correspond to that of the first electrode. That is, the first electrode does not block the non-contact area of ​​the electrode, allowing the non-contact area of ​​the electrode to fully receive sunlight. Therefore, the non-contact area of ​​the electrode undertakes most of the task of absorbing sunlight.

[0069] The embodiments of this application do not impose special limitations on the material and quantity of the first electrode, which can be set according to conventional methods in the art. For example, the first electrode can be a silver electrode, and the quantity can be greater than or equal to one, such as 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10.

[0070] In some embodiments of this application, the electrode non-contact region (i.e., the polycrystalline silicon layer corresponding to the electrode non-contact region) is also doped with a first atom, which includes one or more of phosphorus and boron.

[0071] Phosphorus is a pentavalent element. When incorporated into the non-contact region of the electrode, it provides additional free electrons, thereby increasing the electron concentration of the polycrystalline silicon layer. Due to the increase in free electrons, the conductivity of the non-contact region of the electrode is significantly improved.

[0072] Boron is a trivalent element. When incorporated into the non-contact region of the electrode, it creates holes (i.e., electron vacancies), thereby increasing the hole concentration in the polycrystalline silicon layer. This increase in holes also improves the conductivity of the non-contact region of the electrode.

[0073] The non-contact region of the electrode with first-atom doping has high conductivity, which helps to reduce the resistance of the solar cell and improve the fill factor.

[0074] In some embodiments, the number of first atoms in the electrode non-contact region is 10. 17 ~10 22 pcs / cm 3 .

[0075] For example, the number of the first atoms mentioned above can be 10.17 10 18 10 19 10 20 10 21 10 22 pcs / cm 3 .

[0076] By controlling the number of the first atoms in the non-contact region of the electrode to meet the above range, the non-contact region of the electrode has higher conductivity, which helps to reduce the resistance of the solar cell and improve the fill factor.

[0077] In some embodiments of this application, the ratio of the number of light atoms to the number of first atoms in the electrode non-contact area is 1% to 150%.

[0078] For example, the ratio of the number of light atoms to the number of first atoms can be a range of 1%, 5%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%, 110%, 120%, 130%, 140%, 150%, or any combination thereof.

[0079] By controlling the content of light atoms in the non-contact area of ​​the electrode to meet the above range, it is ensured that the light atoms can reduce parasitic absorption losses while avoiding an increase in battery resistance.

[0080] In some embodiments of this application, the electrode contact region (i.e., the polycrystalline silicon layer corresponding to the electrode contact region) is doped with a second atom, which includes one or more of phosphorus and boron.

[0081] Phosphorus is a pentavalent element. When incorporated into the electrode contact area, it provides additional free electrons, thereby increasing the electron concentration of the polycrystalline silicon layer. Due to the increase in free electrons, the conductivity of the electrode contact area is significantly improved.

[0082] Boron is a trivalent element. When incorporated into the electrode contact region, it creates holes (i.e., electron vacancies), thereby increasing the hole concentration in the polycrystalline silicon layer. This increase in holes also improves the conductivity of the electrode contact region.

[0083] The electrode contact region doped with the second atom has high conductivity, which helps to reduce the resistance of the solar cell and improve the fill factor.

[0084] In some embodiments, the number of second atoms in the electrode contact region is 10. 17 ~10 22 pcs / cm 3 .

[0085] For example, the number of the second atoms mentioned above can be 10. 17 10 18 1019 10 20 10 21 10 22 pcs / cm 3 .

[0086] By controlling the number of the first atoms in the electrode contact area to meet the above range, the electrode contact area can have higher conductivity, which helps to reduce the resistance of the solar cell and improve the fill factor.

[0087] In some embodiments, the second atom does not include light atoms.

[0088] That is, the electrode contact area is not doped with light atoms.

[0089] Doping the electrode contact area without light atoms helps reduce parasitic absorption losses while lowering the battery resistance. The reason is as follows: As mentioned earlier, the first electrode blocks sunlight from reaching the electrode contact area (metal blocking area). Therefore, even if light atoms are doped in the electrode contact area (metal blocking area), the effect of reducing parasitic losses cannot be fully realized. Furthermore, light atoms occupy lattice sites, inhibiting the excitation of phosphorus / boron atoms. Research has shown that doping light atoms only in the non-contact area (metal non-blocking area) and not in the electrode contact area fully utilizes the effect of reducing parasitic absorption losses while avoiding excessive lattice site occupation. This ensures effective activation of phosphorus / boron atoms in the electrode contact area, which facilitates carrier transport and collection in the polycrystalline silicon layer, optimizes open-circuit voltage, improves short-circuit current and conversion efficiency, enhances conductivity in the electrode contact area, lowers battery resistance, and does not compromise the fill factor.

[0090] In some specific embodiments of this application, the solar cell further includes a substrate, and a first electrode is provided on each of the opposite sides of the substrate.

[0091] The design of the electrodes on both sides helps to collect photogenerated carriers (electrons and holes) more effectively, thereby improving the photoelectric conversion efficiency of solar cells.

[0092] Specifically, the substrate may include a silicon substrate, such as crystalline silicon (c-Si).

[0093] In some embodiments, at least one side of the substrate is further provided with a polycrystalline silicon layer.

[0094] A polysilicon layer is provided on at least one side of the substrate. That is, a polysilicon layer is also provided on at least one side of the substrate on which the first electrode is provided.

[0095] For example, on both sides of the substrate with the first electrode, only one side is provided with a polycrystalline silicon layer, as shown in FIG2.

[0096] The back of the solar cell in Figure 2 (bottom of Figure 2) has a polyfin structure.

[0097] For example, polycrystalline silicon layers are also provided on both sides of the substrate where the first electrode is located, as shown in Figure 3. The front side (top of Figure 3) and back side (bottom of Figure 3) of the solar cell in Figure 3 both have a polyfin structure. The design of polycrystalline silicon layers on both sides helps to improve light absorption efficiency and increase photogenerated carriers (electrons and holes), thereby improving photoelectric conversion efficiency.

[0098] Understandably, the polysilicon layer and the first electrode on the same side satisfy the aforementioned relationship, that is, the polysilicon layer includes an electrode contact area and an electrode non-contact area distributed along the first direction, the electrode contact area corresponds to the position of the first electrode, and the first direction intersects the direction along the first electrode to the polysilicon layer.

[0099] Furthermore, the first electrode on the same side refers to the first electrode and the polysilicon layer being located on the same side of the substrate.

[0100] In some embodiments, the thickness of the electrode contact region (i.e., the polysilicon layer corresponding to the electrode contact region) is 1–500 nm.

[0101] For example, the thickness of the electrode contact area can be a range of 1, 10, 50, 100, 150, 200, 300, 400, 500 nm or any combination thereof.

[0102] In some embodiments, the thickness of the electrode non-contact region (i.e., the polysilicon layer corresponding to the electrode non-contact region) is 1–500 nm.

[0103] For example, the thickness of the non-contact region of the electrode can be a range of 1, 10, 50, 100, 150, 200, 300, 400, 500 nm or any combination thereof.

[0104] The thickness of the electrode contact area and the thickness of the electrode non-contact area can be the same or different.

[0105] In some embodiments, the solar cell may further include at least one of an anti-reflection layer, a passivation layer, and a tunneling layer.

[0106] For example, as shown in FIG2, the solar cell includes, from the back to the front (from bottom to top in FIG2), an anti-reflection layer 5, a polycrystalline silicon layer 3, a tunneling layer 20, a substrate 1, a passivation layer 4, and an anti-reflection layer 5. A first electrode 6 is provided on both sides of the solar cell (substrate). The polycrystalline silicon layer 3 includes an electrode contact area 31 (metal blocking area) and an electrode non-contact area 32 (metal non-blocking area).

[0107] The back of the solar cell shown in Figure 2 uses a polycrystalline silicon layer and a tunneling layer (passivation structure), which helps to further optimize the open-circuit voltage, improve the short-circuit current and conversion efficiency, and reduce the resistance. The solar cell has both excellent optical and electrical performance.

[0108] For example, as shown in FIG3, the solar cell includes, from the back to the front (from bottom to top in FIG3): an anti-reflection layer 5, a polycrystalline silicon layer 3, a tunneling layer 20, a substrate 1, a tunneling layer 20, a polycrystalline silicon layer 3, a passivation layer 4, and an anti-reflection layer 5. A first electrode 6 is provided on both sides of the solar cell (substrate). The polycrystalline silicon layer 3 includes an electrode contact area 31 (metal blocking area) and an electrode non-contact area 32 (metal non-blocking area).

[0109] The solar cell shown in Figure 3 uses polycrystalline silicon layers and tunneling layers (passivation structures) on both the front and back sides, which can achieve higher passivation performance, help to further optimize open-circuit voltage, improve short-circuit current and conversion efficiency, and reduce resistance. The solar cell has excellent passivation performance, optical performance and electrical performance.

[0110] The anti-reflective layer may include silicon nitride (SiN) x ).

[0111] The thickness of the anti-reflective layer can be 50–200 nm.

[0112] Passivation layers may include aluminum oxide (AlO2) x .

[0113] The thickness of the passivation layer can be 1–50 nm.

[0114] The substrate may include a silicon substrate. Specifically, the silicon substrate may include an N-type silicon substrate (N-type silicon wafer) or a silicon substrate with alternating P / N / intrinsic regions.

[0115] In this case, the PN junction of the N-silicon substrate is on the front side.

[0116] The tunneling layer may include silicon oxide (SiO2) x ).

[0117] The thickness of the tunneling layer (ultra-thin tunneling layer) can be 0.5–2 nm.

[0118] Secondly, embodiments of this application also provide a method for preparing a solar cell according to a first aspect, comprising: forming a polycrystalline silicon layer, the polycrystalline silicon layer including a first opening corresponding to a first electrode and an electrode non-contact region defining the first opening; forming an electrode contact region of the polycrystalline silicon layer in the first opening; and setting a first electrode at a position corresponding to the electrode contact region to obtain a solar cell.

[0119] A solar cell can be prepared by the above preparation method. This solar cell has a high open-circuit voltage, a high short-current, a high fill factor, and a low resistance.

[0120] The above preparation method may further include: after forming a polycrystalline silicon layer, forming a first opening corresponding to the first electrode and an electrode non-contact area defining the first opening on the polycrystalline silicon layer by etching technology (such as wet etching).

[0121] Alternatively, the electrode contact area of ​​the polycrystalline silicon layer can be formed by depositing the raw material of the electrode contact area into the first opening.

[0122] Generally, the process of setting the first electrode at the corresponding position in the electrode contact area can be achieved by forming the first electrode in the passivation structure through laser ablation or screen printing.

[0123] In some specific embodiments of this application, the above-mentioned preparation method further includes: providing a substrate; forming a polycrystalline silicon layer on at least one side of the substrate.

[0124] Understandably, "at least one side of the substrate" refers to one side or both sides of the substrate.

[0125] Taking the solar cell shown in Figure 2 as an example, its fabrication method will be explained in detail. The fabrication method includes:

[0126] 1) Form raised structures (such as pyramid textured surfaces) on both sides of the substrate;

[0127] 2) Then, a PN junction is formed on the front side of the substrate, and the back side of the substrate is polished.

[0128] 3) A tunneling layer is formed on the back side of the polished substrate, then an amorphous silicon layer doped with light atoms is formed on the tunneling layer, and then a mask layer is formed on the amorphous silicon layer doped with light atoms to obtain the battery intermediate.

[0129] 4) Next, the battery intermediate is annealed and crystallized to form a polycrystalline silicon layer;

[0130] 5) Part of the mask layer and polysilicon layer are removed by etching technology (such as wet etching) to form a first opening corresponding to the first electrode and an electrode non-contact area defining the first opening;

[0131] 6) Then the raw material (such as an undoped amorphous silicon layer) of the electrode contact area is deposited in the first opening to form the electrode contact area of ​​the polycrystalline silicon layer, and then a mask layer is formed on it, followed by annealing and crystallization.

[0132] 7) Remove excess mask layer and excess electrode contact area material (such as undoped light atom amorphous silicon layer) in the area outside the first opening by etching technology, then form an anti-reflection layer on it again, and set the electrodes (such as screen printing).

[0133] 8) A passivation layer and an anti-reflection layer are sequentially formed on the front side of the substrate to obtain a solar cell.

[0134] PN junctions can be formed on the front side of a substrate using methods such as LPCVD (low-pressure chemical vapor deposition), HWCVD (hot-wire chemical vapor deposition), or PECVD (plasma-enhanced chemical vapor deposition).

[0135] In step 3), the thickness of the amorphous silicon layer doped with light atoms can be 1–500 nm, preferably 5–250 nm, and the thickness of the mask layer can be 1–10 nm.

[0136] A tunneling layer can be formed on the back side of a polished substrate using methods such as PEALD, thermal oxidation, PECVD, and HWCVD.

[0137] The annealing and crystallization temperature can be 800-1100℃.

[0138] The method for fabricating the solar cell shown in Figure 3 is basically the same as that for fabricating the solar cell shown in Figure 2. The difference is that steps 3) to 7) are repeated sequentially on the front side of the substrate, that is, a passivation structure including a tunneling layer and a polycrystalline silicon layer is formed on both the front and back sides of the substrate to obtain the solar cell.

[0139] Thirdly, embodiments of this application also provide an electrical device, including the solar cell described above or a solar cell prepared according to the above method, wherein the solar cell serves as the power supply for the electrical device.

[0140] In some embodiments, as shown in Figures 5-7, the back selective emitter structure of the solar cell includes: a silicon substrate 10, a tunneling layer 20 and a first doped polycrystalline silicon layer 301 sequentially disposed on the silicon substrate, a barrier layer 40 disposed in a portion of the first doped polycrystalline silicon layer, and a second doped polycrystalline silicon layer 302 and a passivation antireflection layer 50 sequentially disposed on the barrier layer.

[0141] As shown in Figure 4, the existing technology has an intrinsic polysilicon layer 70 between the tunneling layer 20 and the barrier layer 40. The disadvantages of this technology are as follows: 1) The doping concentration gradient between the intrinsic polysilicon layer 70 and the doped polysilicon layer 30 is large, which may lead to an uneven electric field distribution at the interface, affecting the passivation effect. 2) Carrier selectivity: The intrinsic polysilicon layer 70 has poor selectivity for carriers, and there is no electric field provided by the dopant to distinguish between majority carriers and minority carriers. The first doped polysilicon layer 301 of this application can provide a certain electric field, optimize the transport path of carriers, make it easier for majority carriers to pass through, and suppress the transport of minority carriers. This structure can more effectively separate charge carriers and reduce recombination losses at the interface, thereby improving carrier selectivity; 3) Light utilization: The presence of the intrinsic polycrystalline silicon layer 70 causes photogenerated carriers to undergo more scattering when passing through the intrinsic polycrystalline silicon layer 70, resulting in light loss; the first doped polycrystalline silicon layer 301 has weaker light absorption and can optimize the transport path of photogenerated carriers, reducing losses during transport. In summary, the applicant of this application, through extensive experiments, has adopted the first doped polycrystalline silicon layer 301 to replace the intrinsic polycrystalline silicon layer 70 in the prior art, thereby improving the performance of solar cells.

[0142] In some embodiments, the selective emitter structure on the back of the solar cell includes: a silicon substrate, a tunneling layer and a first doped polycrystalline silicon layer sequentially disposed on the silicon substrate, and a barrier layer disposed in a portion of the first doped polycrystalline silicon layer. If the entire region is provided with a barrier layer, if the barrier layer is made of a material with high insulation, it will lead to poor conductivity; if the barrier layer is made of a material with good conductivity, it will lead to poor passivation. In order to balance the conductivity and passivation of the selective emitter structure on the back of the solar cell, the applicant of this application, after conducting multiple experiments and analyzing and considering the experimental results, adopted the method of providing a barrier layer in a portion of the first doped polycrystalline silicon layer.

[0143] In some embodiments, the area of ​​the portion containing the barrier layer accounts for 10%-90% of the area of ​​the first doped polysilicon layer; if the area of ​​the portion is too small, it cannot effectively block the diffusion of dopant atoms. Exemplarily, the area of ​​the portion containing the barrier layer accounts for 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% of the area of ​​the first doped polysilicon layer.

[0144] In some embodiments, the area of ​​the portion of the barrier layer is 70%-90% of the area of ​​the first doped polysilicon layer.

[0145] In some embodiments, the doping concentration of the second doped polysilicon layer is greater than or equal to the doping concentration of the first doped polysilicon layer.

[0146] In some embodiments, the second doped polysilicon layer is made of heavily doped polysilicon, and the first doped polysilicon layer is made of lightly doped polysilicon. This achieves both a high doping concentration for good passivation and contact effects, and avoids the excessive diffusion of atoms from the first doped polysilicon layer to the silicon substrate due to high doping. Furthermore, the light doping of the first doped polysilicon layer reduces dark saturation current, enhances carrier collection, and improves tunneling efficiency. The doping concentrations of the heavily and lightly doped polysilicon are common in the art; for example, the doping concentration of the heavily doped polysilicon is 1 × 10⁻⁶. 20 cm -3 ~1×10 21 cm -3 The doping concentration of lightly doped polycrystalline silicon is controlled at 1×10⁻⁶. 19 ~1×10 20 cm -3 .

[0147] The tunneling layer is made of a common tunneling layer material in the art. In some embodiments, it is selected from at least one of silicon oxide, aluminum oxide, and silicon nitride. The preparation method is one of the common processes in the art, namely plasma chemical gas deposition (PECVD), magnetron sputtering (PVD), and atomic layer deposition (ALD). The first doped polysilicon layer and / or the second doped polysilicon layer are common n-type or p-type doped polysilicon layers in the art, and the doping element is phosphorus or boron. In some embodiments, the barrier layer is made of at least one of silicon oxide, aluminum oxide, and indium tin oxide. In some embodiments, the passivation and antireflection layer is made of a common passivation and antireflection layer material in the art. The preparation method is a common tubular or plate-type PECVD deposition of the passivation and antireflection layer. In some embodiments, the passivation and antireflection layer is selected from at least one of silicon oxide, silicon oxynitride, and silicon nitride.

[0148] In some embodiments, the thickness of the silicon substrate is 100nm-160nm, the thickness of the tunnel layer is 0.5nm-2nm, the thickness of the first doped polysilicon layer is 20nm-80nm, the thickness of the barrier layer is 0.5nm-3nm, and the thickness of the passivation antireflection layer is 70nm-100nm. If the barrier layer is too thick, the carrier transport efficiency will decrease; if it is too thin, it will not effectively function as a barrier layer.

[0149] As one embodiment of this application, as shown in Figure 8, the region of the first doped polysilicon layer without a barrier layer is sequentially provided with a second doped polysilicon layer 302 and a passivation antireflection layer 50; the region of the first doped polysilicon layer 301 without a barrier layer is provided with a metal electrode 60, which is a metal contact region (i.e., an electrode contact region); the region of the first doped polysilicon layer 301 with a barrier layer does not have a metal electrode, which is a non-metal contact region (i.e., an electrode non-contact region); the thickness of the second doped polysilicon layer 302 in the non-metal contact region is A, and the thickness of the second doped polysilicon layer 302 in the metal contact region is B, where A is less than B. It is clear from Figure 8 that A is less than B. The advantage of A being less than B is that it reduces the parasitic absorption of light by the second doped polysilicon layer, improves light utilization, and thus improves the cell efficiency of the solar cell.

[0150] In some embodiments, the ratio of A to B is 1:5 to 2:3. Within this range, it is possible to reduce parasitic absorption while retaining the chemical passivation and field passivation effects of tunneling and the first-doped polycrystalline silicon and second-doped polycrystalline silicon structures, thereby improving the cell efficiency of the solar cell.

[0151] In some embodiments, the thickness A of the second doped polysilicon layer in the non-metallic contact region is 40 nm to 300 nm.

[0152] As another embodiment of this application, as shown in FIG9, the region of the first doped polycrystalline silicon layer 301 with a barrier layer is provided with an electrode 60 (specifically a metal), which is a metal contact region; the region of the first doped polycrystalline silicon layer without a barrier layer does not have a metal electrode and is a non-metal contact region; in the non-metal contact region, a passivation anti-reflection layer 50 is provided on the first doped polycrystalline silicon layer 301. Its advantage is that there is no second doped polycrystalline silicon layer in the non-metal contact region, so the thickness of A is 0. This structure reduces the problem of inward expansion of doped atoms in the metal contact region, improves the field passivation effect, enhances contact performance, and the resulting solar cell exhibits an improved fill factor.

[0153] In some embodiments, the thickness B of the second doped polysilicon layer in the metal contact region is 40 nm to 300 nm.

[0154] In some embodiments, the solar cell is a Topcon cell or a TBC cell.

[0155] Based on the above principles and objectives, this application discloses a method for fabricating the aforementioned selective emitter structure on the back side of a solar cell, mainly comprising:

[0156] (1) For N-type silicon substrates, the back side of the silicon substrate is wet-polished to make its reflectivity range from 40% to 60%.

[0157] (2) A tunneling silicon oxide layer with a thickness of 0.5 nm-2 nm is deposited on the back polished surface of the silicon substrate. The preparation method is one of the common processes in the art, namely plasma chemical gas deposition (PECVD), magnetron sputtering (PVD), and atomic layer deposition (ALD).

[0158] (3) On the tunneling oxide layer, using phosphine or boron trichloride, which are commonly used in the art, as diffusion sources, a first doped n-type or p-type polycrystalline silicon layer is deposited with a thickness of 20nm-80nm and a doping concentration of 1×10⁻⁶. 19 -1×10 20 atoms / cm 3 PECVD, a common technique in this field, can be used.

[0159] (4) Using a masking method, a barrier layer is deposited in a portion of the first doped polysilicon layer. The thickness of the barrier layer is 0.5nm-3nm, and the material can be alumina, indium tin oxide, etc.

[0160] (5) After depositing a barrier layer in some areas, a second doped n-type or p-type polycrystalline silicon layer is deposited with a thickness of 40-300 nm and a doping concentration of 1×10⁻⁶. 20 -1×10 21 atoms / cm 3 .

[0161] (6) Deposit a passivation anti-reflection layer on the second doped n-type or p-type polysilicon layer;

[0162] (7) Print electrodes to obtain the selective emitter structure on the back of the solar cell of this application.

[0163] This application also provides a method for fabricating a solar cell, using a Topcon cell as an example below.

[0164] On the front side of the N-type silicon substrate with the selective emitter structure on the back of the aforementioned solar cell, a boron emitter, an aluminum oxide passivation layer, an antireflection layer, and an electrode are sequentially fabricated.

[0165] The boron emitter is made by high-temperature boron diffusion with a diffusion thickness of 800nm-1000nm. The preparation method is well known to those skilled in the art, for example, by low-pressure thermal diffusion deposition.

[0166] The alumina layer, with a thickness of 3-5 nm, is prepared by a method known to those skilled in the art, such as plasma chemical gas deposition (PECVD), magnetron sputtering (PVD), or atomic layer deposition (ALD).

[0167] The antireflection layer is made of at least one of silicon oxide, silicon oxynitride, and silicon nitride, and is prepared by one of the following processes: plasma chemical gas deposition (PECVD), magnetron sputtering (PVD), and atomic layer deposition (ALD).

[0168] The electrodes are made of one or more metals such as silver, copper, and gold, and are prepared using screen printing or electroplating processes.

[0169] In some embodiments, as shown in FIG19, the solar cell includes: a monocrystalline silicon substrate 100, the substrate having a textured surface as the light-facing surface, and a first passivation layer 201, a first doped layer 211, a first oxide layer 221, and a first grid line 231 sequentially disposed from the inside to the outside on the textured surface of the light-facing surface; a second passivation layer 301, a second doped layer 311, a second oxide layer 321, and a second grid line 331 sequentially disposed from the inside to the outside on the back-lighting surface disposed from the inside to the outside; and at least a side second passivation layer 302 and a side first oxide layer 222 sequentially disposed from the inside to the outside on the side surface of the substrate. By providing the second passivation layer 302 on the side surface, this application can effectively passivate the side surface of the solar cell, suppress edge recombination effects, thereby effectively optimizing the on-state voltage and fill factor, optimizing efficiency, and improving the photoelectric conversion efficiency of the obtained solar cell.

[0170] The purpose of setting the first oxide layer and / or the second oxide layer is to increase the lateral transport capability of charge carriers and to allow photons to pass through effectively.

[0171] In some embodiments, the second passivation layer 302 on the side is made of intrinsic silicon, and the first oxide layer 222 on the side is made of indium oxide.

[0172] In some embodiments, the thickness of the second passivation layer 302 on the side is 4nm-15nm, and the thickness of the first oxide layer 222 on the side is 60nm-130nm.

[0173] In some embodiments, one end of the second passivation layer on the side is connected to the first passivation layer, and the other end of the second passivation layer on the side is connected to the second passivation layer.

[0174] In some embodiments, the single-crystal silicon substrate is made of N-type silicon, a material commonly known to those skilled in the art; the first passivation layer is made of intrinsic silicon, a material commonly known to those skilled in the art; the first doped layer is made of a doped material commonly known to those skilled in the art, specifically, it can be at least one of oxygen-doped amorphous silicon, oxygen-doped microcrystalline silicon, carbon-doped amorphous silicon, carbon-doped microcrystalline silicon, oxygen- and carbon-doped amorphous silicon, and oxygen- and carbon-doped microcrystalline silicon; the first oxide layer is made of an oxide material commonly known to those skilled in the art, specifically, it can be an indium oxide-based material; for example, the first oxide layer can be indium oxide or indium tin oxide. The first gate line is made of a gate line material commonly known to those skilled in the art, specifically, it can be silver or copper; the second passivation layer is made of intrinsic silicon; the second doped layer is made of a doped material commonly known to those skilled in the art, specifically, it can be at least one of oxygen-doped amorphous silicon, oxygen-doped microcrystalline silicon, carbon-doped amorphous silicon, carbon-doped microcrystalline silicon, oxygen- and carbon-doped amorphous silicon, and oxygen- and carbon-doped microcrystalline silicon; the second oxide layer is made of an oxide material commonly known to those skilled in the art, specifically, it can be an indium oxide-based material, for example, indium oxide or indium tin oxide. The material of the second gate line is a common gate line material known to those skilled in the art; specifically, it can be one of silver or copper. In some embodiments, the material of the second passivation layer on the side is the same as the material of the second passivation layer; the material of the first oxide layer on the side is the same as the material of the first oxide layer. This makes it easier to manufacture, lowers the manufacturing cost, and is conducive to large-scale production.

[0175] In this design, the first and second doped layers have different conductivity types, meaning their doping types are opposite. Specifically, one is P-type and the other is N-type. For example, if the first doped layer is a P-type silicon film, then the second doped layer is an N-type silicon film; conversely, if the first doped layer is an N-type silicon film, then the second doped layer is a P-type silicon film. The P-type silicon film can be achieved through boron doping, and the N-type silicon film can be achieved through phosphorus doping. In some embodiments, the first doped layer is an N-type silicon film, and the second doped layer is a P-type silicon film. This is because the second doped layer material can effectively suppress the diffusion of P-type dopants from the first doped layer into the crystalline silicon substrate. Specifically, the first doped layer can be a phosphorus-doped N-type silicon film, and the second doped layer can be a boron-doped P-type silicon film.

[0176] The thickness of the single-crystal silicon substrate is a thickness commonly known to those skilled in the art, and in some embodiments, it can be 50μm-170μm; the thickness of the first passivation layer, the thickness of the first doped layer, and the thickness of the first oxide layer are thicknesses commonly known to those skilled in the art, and in some embodiments, the thickness of the first passivation layer is 4-15nm; the thickness of the first doped layer is 5-30nm; and the thickness of the first oxide layer is 60-130nm.

[0177] In some embodiments, the thickness of the second passivation layer is 4-15 nm; the thickness of the second doped layer is 10-35 nm; and the thickness of the second oxide layer is 70-150 nm.

[0178] In some embodiments, the thickness of the second passivation layer is 6-10 nm.

[0179] This application also provides a method for preparing the aforementioned solar cell.

[0180] (1) All surfaces of the single-crystal silicon substrate 100 shown in Figure 10 are polished and covered with an alkali-resistant first mask. The polishing method is a common polishing method in the art. Specifically, polishing can be performed with a hot alkaline solution. The alkaline solution is NaOH or KOH with a mass concentration of 1.5%-12.0%. The temperature of the alkaline solution process is 55℃-82℃, and the reaction time is 30-300s. The single-sided thinning of the substrate is 2-8μm, and the reflectivity of the polished surface is 36%-48%. Optionally, the substrate can be subjected to getter treatment, or it can be left untreated. It is preferred to perform getter treatment. The getter treatment method is a common getter treatment method in the art. Specifically, the reaction temperature is 700-1000℃, the reaction gas is oxygen and phosphorus oxychloride, and the reaction time is 2min-30min. If getter treatment is performed, a tank pickling process is required to remove the phosphosilicate glass layer. The pickling solution is HF solution. A first alkali-resistant mask layer 102 can be applied to all surfaces of a single-crystal silicon substrate using a thermal oxidation process or a plasma chemical vapor deposition process, resulting in the single-crystal silicon substrate shown in Figure 11. The first mask layer 102 is prepared using a common method in the art, such as thermal oxidation in a tube furnace at a deposition temperature of 750-1000℃; or wet oxidation using water vapor. The first mask layer 102 is composed of one of silicon oxide, silicon nitride, silicon oxynitride, or indium tin oxide, and has a thickness of 15nm-50nm.

[0181] (2) A second mask layer 103, which is resistant to acid but not resistant to alkali, is formed on the back surface and side of the substrate to obtain a single crystal silicon substrate as shown in Figure 12. The preparation method of the second mask layer 103 is a common preparation method in the art. For example, the second mask layer 103 can be obtained by chemical vapor deposition.

[0182] (3) The first acid pickling removes the alkali-resistant first mask layer 102 on the light-facing side, followed by alkaline texturing in a tank to texturize the light-facing side. The second mask layer 103 on the back side is etched simultaneously. The second acid pickling removes the alkali-resistant first mask layer 102 on the remaining surfaces, resulting in a substrate with a textured surface on the light-facing side. The pickling solution used in the first or second acid pickling is a common pickling solution in the art, such as HF solution. Alkaline texturing is a common texturing method in the art. Specifically, the texturing solution can be a KOH solution with a KOH concentration of 0.5%–6.0%, and the temperature of the texturing reaction solution is 55℃–82℃. The reaction time is 200s–800s.

[0183] (4) A second passivation layer 301 on the back surface and a second passivation layer 302 on the side surface, a first passivation layer 201 on the light-facing surface, and a first doped layer 211 on the light-facing surface are sequentially prepared on the substrate; the substrate changes during the process are shown in Figures 13, 14, and 15; the preparation methods of the second passivation layer, the second passivation layer on the side surface, the first passivation layer on the light-facing surface, and the first doped layer on the light-facing surface can be plasma chemical vapor deposition (PECVD), which is common in the art;

[0184] (5) Prepare a second doped layer 311 on the backlight surface on the substrate; obtain the substrate shown in Figure 16; the preparation method of the second doped layer 311 can be PECVD, which is common in the art;

[0185] (6) A light-facing first oxide layer 221 and a side first oxide layer 222 are formed on the substrate to obtain the substrate shown in Figure 17. The preparation method of the light-facing first oxide layer 221 and the side first oxide layer 222 can be PECVD, which is common in the art.

[0186] (7) A second oxide layer 321 is formed on the back surface; a substrate as shown in Figure 18 is obtained; the second oxide layer 321 can be prepared by PECVD, which is common in the art; grid lines 231 and 331 are formed to obtain a solar cell. The grid lines can be prepared by screen printing, which is common in the art.

[0187] The use of the first mask layer 102 and the second mask layer 103 allows this application to use a tank cleaning device, avoiding the introduction of traditional chain cleaning equipment, simplifying the process, and reducing the scratches and blackening phenomenon that may be caused by chain cleaning equipment during electroluminescence testing.

[0188] This application also provides a photovoltaic module, including the solar cell described above.

[0189] In some embodiments, there are multiple solar cells connected in series, as shown in FIG16. The multiple cells form a series of cell groups, and a bypass diode is connected between adjacent cell groups. The bypass diode protects the circuit from damage caused by the hot plate effect caused by physical obstruction. Such a photovoltaic module is the same as the photovoltaic modules commonly used in the art.

[0190] As a preferred embodiment of this application, as shown in FIG25, the side surface of the substrate is provided with a second passivation layer 302, a first passivation layer 202, a first doped layer 212, a second doped layer 312, and a first oxide layer 222 in sequence from the inside to the outside. This side film layer configuration firstly reduces the blackening of solar cells during photoluminescence (PL) testing, improving the yield of cells on the production line. Secondly, the addition of the second doped layer 312, where the first and second doped layers 212 form a PN junction on the side, constitutes a bypass diode, effectively preventing hot spot effects. Photovoltaic modules composed of such solar cells can avoid the need for additional bypass diodes at the module end, simplifying the fabrication process. As shown in FIG27, the presence of the first and second doped layers 212 on the side eliminates the need for bypass diodes in the solar cells of this photovoltaic module, simplifying the fabrication process and reducing the cost of the photovoltaic module. As shown in FIG26, circuits containing diodes are common components. Each solar cell is connected in series. However, if a solar cell is shaded, it not only fails to generate electricity but also acts as a resistor, producing a large amount of heat and creating a hot spot effect. If a diode is present, and a solar cell is shaded, that section of the circuit is short-circuited by the diode. This section then ceases to function as a resistor or a battery to protect the circuit, thus affecting the conversion efficiency of the photovoltaic module. In this application, each solar cell is essentially equipped with a diode. When this type of solar cell is shaded, it can be isolated, preventing it from affecting other solar cells and thus minimizing the impact on the conversion efficiency of the photovoltaic module.

[0191] To facilitate product fabrication, in some embodiments, the material of the first passivation layer 202 on the side is the same as that of the first passivation layer 201; the material of the first doped layer 212 on the side is the same as that of the first doped layer 211; and the material of the second doped layer 312 on the side is the same as that of the second doped layer 311.

[0192] In some embodiments, the thickness of the first passivation layer 202 on the side is 4-15 nm, the thickness of the first doped layer 212 on the side is 5-30 nm, and the thickness of the second doped layer 312 on the side is 5-30 nm.

[0193] In some embodiments, the solar cell is a heterojunction cell.

[0194] This application also provides a method for preparing the aforementioned solar cell.

[0195] (1) Polish all surfaces of the single crystal silicon substrate 100 as shown in Figure 10; cover all surfaces of the single crystal silicon substrate with an alkali-resistant first mask layer 102 by a thermal oxidation process or a plasma chemical vapor deposition process; and obtain the single crystal silicon substrate as shown in Figure 11.

[0196] (2) A second mask layer 103, which is acid-resistant but not alkali-resistant, is formed on the back surface and side of the substrate; thus, a single-crystal silicon substrate as shown in Figure 12 is obtained.

[0197] (3) The first acid pickling removes the alkali-resistant first mask layer 102 on the light-facing side, and then the tank alkaline solution texturing is performed to texturize the light-facing side. The second mask layer 103 on the back side is etched at the same time. The second acid pickling removes the alkali-resistant first mask layer 102 on the remaining surfaces, resulting in a substrate with a textured surface on the light-facing side; as shown in Figure 13.

[0198] (4) A second passivation layer 301 and a second passivation layer 302 on the back surface, a first passivation layer 201 and a first passivation layer 202 on the side surface, a first doped layer 211 on the light-facing surface and a first doped layer 212 on the side surface are sequentially prepared on the substrate; the substrate obtained in the preparation process is shown in Figure 20-21.

[0199] (5) A second doped layer 311 on the back surface and a second doped layer 312 on the side surface are prepared on the substrate; the resulting substrate is shown in Figure 22.

[0200] (6) A light-facing first oxide layer 221 and a side first oxide layer 222 are formed on the substrate; the resulting substrate is shown in Figure 23;

[0201] (7) A second oxide layer 321 is formed on the back surface; the resulting substrate is shown in Figure 24; a first grid line 231 and a second grid line 331 are formed to obtain a solar cell. The grid lines can be fabricated by screen printing, a method commonly used by those skilled in the art.

[0202] This application also provides a photovoltaic module, including the solar cell described above.

[0203] In some embodiments, there are multiple solar cells connected in series. As shown in Figure 27, multiple cells form rows of cell groups. There is no need to provide bypass diodes between adjacent rows of cell groups, for the reasons mentioned above, which will not be repeated here.

[0204] The present application will be further described below through specific embodiments and comparative examples. Unless otherwise specified, the reagents, materials and instruments used below are all conventional reagents, materials and instruments, all of which are commercially available, and the reagents and materials involved can also be synthesized by conventional synthetic methods.

[0205] Example 1

[0206] This embodiment provides a solar cell, the structure of which is shown in Figure 2. The solar cell includes: a substrate with first electrodes on both sides, and a tunneling layer, a polycrystalline silicon layer, and an anti-reflection layer sequentially disposed on the back side of the substrate (bottom of Figure 2), and a passivation layer and an anti-reflection layer sequentially disposed on the front side of the substrate (top of Figure 2). The front side of the substrate has a raised structure, which has a pyramid-like textured surface.

[0207] The first electrode is a silver electrode, and the substrate includes crystalline silicon (c-Si); the tunneling layer includes silicon oxide (SiO2). x The tunneling layer has a thickness of 1 nm; the anti-reflective layer consists of oxynitride and has a thickness of 80 nm; the passivation layer consists of aluminum oxide and has a thickness of 4 nm.

[0208] The polycrystalline silicon layer includes an electrode contact region and an electrode non-contact region distributed along a first direction. The electrode contact region corresponds to the position of the first electrode, and the first direction is perpendicular to the direction from the first electrode to the polycrystalline silicon layer. The electrode non-contact region is doped with oxygen atoms and phosphorus atoms, and the ratio of the number of oxygen atoms to the number of phosphorus atoms in the electrode non-contact region is 10%, and the number of phosphorus atoms is 10. 21 pcs / cm 3 The electrode contact area is doped with only phosphorus atoms, and the number of phosphorus atoms in the electrode contact area is 10. 21 pcs / cm 3 Furthermore, the thickness of the electrode contact area is 100 nm; the thickness of the electrode non-contact area is 100 nm.

[0209] Example 2

[0210] This embodiment provides a solar cell, the structure of which is shown in Figure 3. The solar cell includes: a substrate with first electrodes on both sides, and a tunneling layer, a polycrystalline silicon layer and an anti-reflection layer sequentially disposed on the front side of the substrate (above Figure 3), and a tunneling layer, a polycrystalline silicon layer and an anti-reflection layer sequentially disposed on the back side of the substrate (below Figure 3). The front side of the substrate has a raised structure, which has a pyramid-like textured surface.

[0211] The first electrode is a silver electrode, and the substrate includes crystalline silicon (c-Si); the tunneling layer includes silicon oxide (SiOx) with a thickness of 1 nm; the anti-reflection layer includes oxynitride with a thickness of 80 nm; and the passivation layer includes aluminum oxide with a thickness of 4 nm.

[0212] The polysilicon layer on the back side of the substrate includes an electrode contact area and an electrode non-contact area distributed along a first direction. The electrode contact area corresponds to the position of the first electrode, and the first direction is perpendicular to the direction from the first electrode to the polysilicon layer. The electrode non-contact area is doped with oxygen atoms and phosphorus atoms, and the ratio of the number of oxygen atoms to the number of phosphorus atoms in the electrode non-contact area is 10%, and the number of phosphorus atoms is 10. 21 pcs / cm 3 The electrode contact area is doped with only phosphorus atoms, and the number of phosphorus atoms in the electrode contact area is 10. 21 pcs / cm 3 Furthermore, the thickness of the electrode contact area is 100 nm; the thickness of the electrode non-contact area is 50 nm. The polysilicon layer on the front side of the substrate includes electrode contact areas and electrode non-contact areas distributed along a first direction. The electrode contact areas correspond to the positions of the first electrode, and the first direction is perpendicular to the direction from the first electrode to the polysilicon layer. The electrode non-contact areas are doped with carbon atoms and boron atoms, and the ratio of the number of carbon atoms to the number of boron atoms in the electrode non-contact areas is 10%, and the number of boron atoms is 10%. 20 pcs / cm 3 The electrode contact region is doped with only boron atoms, and the number of boron atoms in the electrode contact region is 10. 20 pcs / cm 3 In addition, the thickness of the electrode contact area is 100 nm; the thickness of the electrode non-contact area is 50 nm.

[0213] Example 3

[0214] This embodiment is basically the same as Embodiment 1, except that:

[0215] The non-contact region of the electrode is doped with nitrogen and phosphorus atoms, and the ratio of nitrogen atoms to phosphorus atoms in the non-contact region is 20%, while the number of phosphorus atoms is 10. 21 pcs / cm 3 ;

[0216] The electrode contact area is doped with only phosphorus atoms, and the number of phosphorus atoms in the electrode contact area is 10. 22 pcs / cm 3 ;

[0217] The thickness of the electrode contact area is 100 nm; the thickness of the electrode non-contact area is 50 nm; other conditions remain unchanged.

[0218] Example 4

[0219] This embodiment is basically the same as Embodiment 1, except that:

[0220] The non-contact region of the electrode is doped with carbon and phosphorus atoms, and the ratio of carbon atoms to phosphorus atoms in the non-contact region is 5%, while the number of phosphorus atoms is 10. 21 pcs / cm 3 ;

[0221] The electrode contact area is doped with only phosphorus atoms, and the number of phosphorus atoms in the electrode contact area is 10. 22 pcs / cm 3 ;

[0222] The thickness of the electrode contact area is 100 nm; the thickness of the electrode non-contact area is 10 nm.

[0223] All other conditions remain unchanged.

[0224] Example 5

[0225] This embodiment is basically the same as embodiment 2, except that:

[0226] The electrode non-contact area on the front side of the substrate is doped with carbon, nitrogen, and boron atoms. The ratio of carbon atoms to boron atoms in this area is 10%, the ratio of nitrogen atoms to boron atoms is 5%, and the number of boron atoms is 10. 20 pcs / cm 3 Other conditions remain unchanged.

[0227] Example 6

[0228] This embodiment is basically the same as embodiment 2, except that:

[0229] The thickness of the electrode contact area is 200 nm; the thickness of the electrode non-contact area is 30 nm; other conditions remain unchanged.

[0230] Comparative Example 1

[0231] This comparative example provides a solar cell, the structure of which is shown in Figure 1. The solar cell includes: a substrate 1 with first electrodes 6 on both sides, a passivation layer 4 and an anti-reflection layer 5 sequentially disposed on the front side of the substrate (above Figure 1), and a tunneling layer 20, a polycrystalline silicon layer 3 and an anti-reflection layer 5 sequentially disposed on the back side of the substrate (below Figure 1). The front side of the substrate 1 has a raised structure, which has a pyramid-like textured surface.

[0232] The first electrode is a silver electrode, and the substrate includes crystalline silicon (c-Si); the tunneling layer includes silicon oxide (SiOx) with a thickness of 1 nm; the anti-reflection layer includes oxynitride with a thickness of 80 nm; and the passivation layer includes aluminum oxide with a thickness of 4 nm.

[0233] The polycrystalline silicon layer is doped with only phosphorus atoms, and the number of phosphorus atoms is 10. 21 pcs / cm3 The thickness of the polycrystalline silicon layer is 100nm.

[0234] Test case

[0235] The following performance characteristics of the solar cells in each embodiment and comparative example were tested:

[0236] According to the IEC 60904 series standards, under standard test conditions (STC), the spectrum is AM1.5 and the illuminance is 1000 W / m². 2 The temperature is 25℃. The open-circuit voltage (Voc), short-circuit current (Jsc), fill factor (FF), and conversion efficiency (ETA) are tested. The test method is: current-voltage characteristic curve test (IV test).

[0237] Table 1

[0238] Data Analysis:

[0239] As can be seen from the data of Examples 1-6 and Comparative Example 1, the solar cells of the present application embodiments can achieve both good optical and electrical performance, with high open-circuit voltage, short-current and photoelectric conversion efficiency, as well as high fill factor and low resistance.

[0240] Example 7

[0241] Figure 5 shows a selective emitter structure on the back of a solar cell according to this application. The fabrication method mainly includes:

[0242] (1) An N-type silicon substrate 10 with a thickness of 130 nm is subjected to wet polishing on the back side of the silicon substrate to make its reflectivity range of 50%.

[0243] (2) A tunneling silicon oxide layer with a thickness of 1.4 nm is deposited on the back polished surface of the silicon substrate by PECVD.

[0244] (3) On the tunneling oxide layer, using phosphine, a common material in the art, as a diffusion source, a first doped polycrystalline silicon layer 301 (specifically n-type) is deposited by PECVD with a thickness of 30 nm and a doping concentration of 1 × 10⁻⁶. 20 atoms / cm 3 ;

[0245] (4) Using a mask method, in a portion of the first doped polysilicon layer, a barrier layer 40 is deposited, the area of ​​which is 75% of the area of ​​the first doped polysilicon layer. The thickness of the barrier layer is 2nm and the material is indium tin oxide.

[0246] (5) After depositing a barrier layer in some areas, a second doped polysilicon layer 302 (specifically n-type) is deposited by PECVD using phosphine, a common source in the art, as the diffusion source. The layer is 50 nm thick and has a doping concentration of 1 × 10⁻⁶. 20 atoms / cm 3 The region of the first doped polysilicon layer without a barrier layer has a metal electrode, which is a metal contact region; the region of the first doped polysilicon layer with a barrier layer does not have a metal electrode, which is a non-metal contact region; the thickness of the second doped polysilicon layer in the non-metal contact region is A, and the thickness of the second doped polysilicon layer in the metal contact region is B, as shown in Figure 5. In this embodiment, A = B. In this embodiment, the barrier layer is located in the non-metal contact region.

[0247] (6) A passivation and antireflection layer 50 is deposited on the second doped n-type polysilicon layer. The material of the passivation and antireflection layer is silicon nitride, and the thickness is 50 nm.

[0248] (7) Print silver electrodes to obtain the selective emitter structure on the back of the solar cell of this application.

[0249] A topcon cell was fabricated by sequentially fabricating a boron emitter, an aluminum oxide passivation layer, an antireflection layer, and an electrode on the front side of the N-type silicon substrate with the selective emitter structure on the back side of the solar cell obtained in step (7) above, thus obtaining the topcon cell prepared in this application. The boron emitter was fabricated by high-temperature boron diffusion and plasma chemical gas deposition to obtain a boron emitter thickness of 800 nm. An aluminum oxide layer with a thickness of 5 nm was prepared by PECVD. An antireflection layer with a thickness of 70 nm was prepared by PECVD. A silver electrode was screen-printed to prepare the solar cell of Example 7 of this application.

[0250] Example 8

[0251] Figure 6 shows a selective emitter structure on the back of a solar cell according to this application, which is basically the same as that in Embodiment 1. As shown in Figure 6, in this embodiment, the barrier layer is disposed in the metal contact area. The doping concentration of the second doped polycrystalline silicon layer 302 is 4 × 10⁻⁶. 20 atoms / cm 3 .

[0252] Example 9

[0253] Figure 7 shows a selective emitter structure on the back of a solar cell according to this application, which is basically the same as that in Embodiment 7, except that the area of ​​the part with the barrier layer accounts for 22% of the area of ​​the first doped polycrystalline silicon layer; as shown in Figure 7, in this embodiment, the barrier layer is located in the non-metallic contact area.

[0254] Example 10

[0255] The invention is basically the same as in Example 9, except that the area of ​​the region with the barrier layer accounts for 60% of the area of ​​the first doped polysilicon layer.

[0256] Example 11

[0257] It is basically the same as Example 9, except that the area of ​​the region with the barrier layer accounts for 90% of the area of ​​the first doped polysilicon layer.

[0258] Example 12

[0259] Figure 8 shows a selective emitter structure on the back of a solar cell according to this application, which is basically the same as that in Example 7. In this embodiment, the barrier layer is located in the non-metallic contact area. The difference from Example 7 is step (5).

[0260] Step (5) in this embodiment is as follows: After depositing a barrier layer in a partial area, a second doped n-type polysilicon layer with a thickness of 50 nm and a doping concentration of 4 × 10⁻⁶ is deposited by PECVD using phosphine, a common material in the art, as a diffusion source. 20 atoms / cm 3 The region of the first doped polysilicon layer without a barrier layer has a metal electrode and is a metal contact region; the region of the first doped polysilicon layer with a barrier layer does not have a metal electrode and is a non-metal contact region; the thickness of the second doped polysilicon layer in the non-metal contact region is A, and the thickness of the second doped polysilicon layer in the metal contact region is B.

[0261] The non-metallized area on the back side is scanned using a laser, followed by wet alkaline removal. This process partially removes the second doped polysilicon layer in the non-metallic contact area, reducing the thickness of A. In this embodiment, the thickness of A is 30 nm, meaning 20 nm of the second doped polysilicon layer has been removed. The thickness of B remains unchanged at 50 nm.

[0262] Example 13

[0263] Figure 9 shows a selective emitter structure on the back of a solar cell according to this application, which is basically the same as that in Example 10. The difference is that in this embodiment, the barrier layer is located in the metal contact area, and step (5) is also included.

[0264] (5) The non-metallized area on the back side is scanned using a laser, and then removed by wet alkali removal, thereby removing the second doped polysilicon layer in the non-metallic contact area. Even if the thickness of A is reduced to 0, the thickness of A in this embodiment is 0 nm. The thickness of B remains unchanged at 50 nm.

[0265] Comparative Example 2

[0266] Figure 4 shows a selective emitter structure on the back of a solar cell in the prior art. The difference between this structure and that of Example 7 lies in steps (3), (4), and (5).

[0267] (3) An intrinsic polycrystalline silicon layer 70, commonly known to those skilled in the art, is prepared on the tunneling oxide layer. The material of 70 is intrinsic polycrystalline silicon, and the thickness is 60 nm.

[0268] (4) A barrier layer 40 is deposited on 70, the thickness of the barrier layer is 2nm, and the material is indium tin oxide;

[0269] (5) On the barrier layer, using phosphine, a common material in the art, as a diffusion source, a PECVD-deposited doped polycrystalline silicon layer 30 (specifically n-type) with a thickness of 50 nm and a doping concentration of 1 × 10⁻⁶ is deposited. 20 atoms / cm 3 .

[0270] The performance of the batteries prepared in the embodiments and comparative examples of this application was tested using testing methods known to those skilled in the art, and the test results are shown in Table 2.

[0271] Table 2

[0272] Analysis of the data in Table 2 shows that the battery efficiency and fill factor of Examples 7-13 are superior to those of Comparative Example 2. Although the current density of Examples 9 or 10 is slightly lower than that of Comparative Example 2 (less than 0.05%), the decrease is relatively small, so it can be considered that Examples 7-8 of this application are basically equivalent to Comparative Example 2 in terms of current density. Similarly, the fill factor of Examples 9 or 10 is basically equivalent to that of Comparative Example 2, while the open-circuit voltage and battery efficiency of Examples 9 or 10 are improved. In Example 8 of this application, the material of the second doped polycrystalline silicon layer is heavily doped polycrystalline silicon, while the material of the first doped polycrystalline silicon layer is lightly doped polycrystalline silicon. In Example 7 of this application, the doping concentration of the second doped polycrystalline silicon layer is equal to the doping concentration of the first doped polycrystalline silicon layer. A comparison of Examples 8 and 7 further verifies that Example 8 achieves both high doping concentration for good passivation and contact effects, while avoiding the large-scale diffusion of atoms into the silicon substrate due to high doping in the first doped polycrystalline silicon layer. Simultaneously, the light doping of the first doped polycrystalline silicon layer reduces dark saturation current, enhances carrier collection, and improves tunneling efficiency, thereby increasing the fill factor and cell efficiency of the solar cell. Example 12 of this application has A less than B, reducing parasitic absorption of light by the second doped polycrystalline silicon layer, improving light utilization, and thus increasing the cell efficiency of the solar cell. Example 13 of this application has no second doped layer at the non-metallic contact, i.e., the thickness of A is 0. This structure reduces the inward diffusion of doped atoms in the metal contact region, improves field passivation, enhances contact performance, and the resulting solar cell exhibits an improved fill factor; that is, the fill factor of the cell in Example 13 is higher than that in Example 12.

[0273] In summary, compared with the prior art, Comparative Example 2, 7-13 of this application improves the conversion efficiency, open-circuit voltage, and battery efficiency of the battery.

[0274] Example 14

[0275] (1) All surfaces of an N-type single-crystal silicon substrate 100 with a thickness of 120 μm, as shown in Figure 10, are polished with a hot alkaline solution. The alkaline solution is NaOH with a mass concentration of 10%. The temperature of the alkaline solution process is 60°C and the reaction time is 30 s. The single-sided thinning amount of the substrate is 2 μm, and the reflectivity range of the polished surface is 40%. An alkali-resistant first mask layer 102 is coated on all surfaces of the single-crystal silicon substrate by tubular PECVD. The composition of the first mask layer is silicon oxide and the thickness is 15 nm.

[0276] (2) A second mask layer 103, which is resistant to acid but not resistant to alkali, is formed by chemical vapor deposition on the back surface and side of the substrate to obtain a single crystal silicon substrate as shown in Figure 12; the material of the second mask layer 103 is intrinsic amorphous silicon and the thickness is 15nm.

[0277] (3) The first HF solution acid washing removes the alkali-resistant first mask layer 102 on the light-facing side, and then the tank alkaline KOH solution is used for texturing to process the light-facing side. The second mask layer 103 on the back side is etched at the same time. The second HF solution acid washing removes the alkali-resistant first mask layer 102 on the remaining surfaces to obtain a substrate with a textured surface on the light-facing side.

[0278] (4) On a substrate with a textured surface facing the light-facing side, an intrinsic silicon second passivation layer 301 with a thickness of 6 nm and an intrinsic silicon side passivation layer 302, an intrinsic silicon first passivation layer 201 with a thickness of 10 nm and an amorphous silicon first doped layer 211 with a thickness of 10 nm are sequentially prepared on the back light-facing side by PECVD.

[0279] (5) A second doped layer 311 of amorphous silicon backlight with a thickness of 10 nm was prepared on the substrate by PECVD; the substrate shown in Figure 16 was obtained.

[0280] (6) A first oxide layer 221 indium tin oxide with a thickness of 70 nm on the light-facing side and a first oxide layer 222 indium tin oxide with a side side are formed on the substrate by PECVD to obtain the substrate shown in Figure 17.

[0281] (7) A second oxide layer 321 of indium tin oxide with a thickness of 70 nm is formed on the back side by PECVD; a substrate as shown in Figure 18 is obtained; a first grid line 231 of silver material is screen printed on the light-facing side, and a second grid line 331 of silver material is screen printed on the back side, to obtain a solar cell as shown in Figure 19.

[0282] Example 15

[0283] The difference from Example 13 is that there is an intrinsic silicon second passivation layer 301 with a thickness of 8 nm on the back surface and an intrinsic silicon side passivation layer 302.

[0284] Example 16

[0285] The difference from Example 13 is that there is an intrinsic silicon second passivation layer 301 with a thickness of 10 nm on the back surface and an intrinsic silicon side passivation layer 302.

[0286] Example 17

[0287] (1) All surfaces of an N-type single-crystal silicon substrate 100 with a thickness of 120 micrometers as shown are polished with a hot alkaline solution, wherein the alkaline solution is NaOH with a mass concentration of 10%, the temperature during the alkaline solution process is 60°C, and the reaction time is 30s; the single-sided thinning amount of the substrate is 2μm, and the reflectivity range of the polished surface is 40%; an alkali-resistant first mask layer 102 is coated on all surfaces of the single-crystal silicon substrate by tubular PECVD, wherein the composition of the first mask layer is silicon oxide and the thickness is 15nm;

[0288] (2) A second mask layer 103, which is resistant to acid but not resistant to alkali, is formed by chemical vapor deposition on the back surface and side of the substrate to obtain a single crystal silicon substrate as shown in Figure 12; the material of the second mask layer 103 is intrinsic amorphous silicon and the thickness is 15nm.

[0289] (3) The first HF solution acid washing removes the alkali-resistant first mask layer 102 on the light-facing side, and then the tank alkaline KOH solution is used for texturing to process the light-facing side. The second mask layer 103 on the back side is etched at the same time. The second HF solution acid washing removes the alkali-resistant first mask layer 102 on the remaining surfaces to obtain a substrate with a textured surface on the light-facing side.

[0290] (4) On a substrate with a textured surface facing the light-facing side, an intrinsic silicon second passivation layer 301 and a side passivation layer 302 with a thickness of 6 nm, an intrinsic silicon first passivation layer 201 and an intrinsic silicon first side passivation layer 202 with a thickness of 10 nm, and an amorphous silicon first doped layer 211 and an amorphous silicon first doped layer 212 with a thickness of 10 nm are sequentially fabricated on the back-light-facing side using PECVD. The substrate obtained during the fabrication process is shown in Figures 20-21.

[0291] (5) An amorphous silicon backlight second doped layer 311 and an amorphous silicon side surface second doped layer 312 with a thickness of 10 nm are prepared on the substrate; the resulting substrate is shown in Figure 22.

[0292] (6) A light-facing first oxide layer 221 indium tin oxide and a side first oxide layer 222 indium oxide with a thickness of 70 nm were formed on the substrate by PECVD; the resulting substrate is shown in Figure 23.

[0293] (7) A second oxide layer 321 with a thickness of 70 nm is formed on the back side by PECVD; the resulting substrate is shown in Figure 24; a first grid line 231 of silver material is screen printed on the light-facing side, and a second grid line 331 of silver material is screen printed on the back side to obtain the solar cell shown in Figure 25.

[0294] Example 18

[0295] The difference from Example 13 is that there is an intrinsic silicon second passivation layer 301 with a thickness of 8 nm on the back surface and an intrinsic silicon side passivation layer 302.

[0296] (5) An amorphous silicon backlight second doped layer 311 and an amorphous silicon side surface second doped layer 312 with a thickness of 20 nm are prepared on the substrate; the resulting substrate is shown in Figure 22.

[0297] Example 19

[0298] The difference from Example 13 is that there is an intrinsic silicon second passivation layer 301 with a thickness of 10 nm on the back surface and an intrinsic silicon side passivation layer 302.

[0299] (1) An amorphous silicon backlight second doped layer 311 and an amorphous silicon side surface second doped layer 312 with a thickness of 35 nm are prepared on the substrate obtained in step (5); the resulting substrate is shown in Figure 22;

[0300] Comparative Example 3

[0301] The difference from Example 13 is that:

[0302] Step (5) does not prepare the second passivation layer 302 on the side.

[0303] Step (7) does not prepare the first oxide layer 222 on the side. The solar cell of this comparative example is obtained.

[0304] The performance of the batteries prepared in the embodiments and comparative examples of this application was tested using testing methods known to those skilled in the art, and the test results are shown in Table 3.

[0305] Table 3

[0306] Analysis of the data in Table 3 reveals that, compared to Comparative Example 3, the embodiments of this application with the second passivation layer 302 on the side can improve the open-circuit voltage and conversion efficiency of the battery. Furthermore, although the open-circuit voltage and conversion efficiency of Embodiments 17-19 of this application are slightly lower than those of Embodiments 14-16, the manufacturing process of these batteries is simple, the yield of the cells is high, and the resulting photovoltaic modules do not require bypass diodes, further reducing costs. This demonstrates that having the second doped layer 312 on the side can further reduce the cost of solar cells and photovoltaic modules.

[0307] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A solar cell, wherein, include: First electrode; A polycrystalline silicon layer includes an electrode contact area and an electrode non-contact area distributed along a first direction, wherein the electrode contact area corresponds to the position of the first electrode, and the first direction intersects the direction along the first electrode to the polycrystalline silicon layer; The non-contact region of the electrode is doped with light atoms, including at least one of carbon, nitrogen, and oxygen.

2. The solar cell according to claim 1, wherein, The non-contact area of ​​the electrode is also doped with a first atom, which includes at least one of phosphorus and boron.

3. The solar cell according to claim 2, wherein, In the non-contact region of the electrode, the ratio of the number of light atoms to the number of the first atoms is 1% to 150%.

4. The solar cell according to claim 2 or 3, wherein, In the non-contact region of the electrode, the number of the first atoms is 10. 17 ~10 22 pcs / cm 3 .

5. The solar cell according to any one of claims 1-4, wherein, The electrode contact area is doped with a second atom, which includes at least one of phosphorus and boron.

6. The solar cell according to claim 5, wherein, In the electrode contact region, the number of the second atoms is 10. 17 ~10 22 pcs / cm 3 .

7. The solar cell according to claim 5 or 6, wherein, The second atom does not include the light atom.

8. The solar cell according to any one of claims 1-7, wherein, It also includes a substrate, on which the first electrode is respectively provided on opposite sides.

9. The solar cell according to claim 8, wherein, The polycrystalline silicon layer is further provided on at least one side of the substrate.

10. The solar cell according to any one of claims 1-9, wherein, The solar cell satisfies at least one of the following: The thickness of the electrode contact area is 1–500 nm; The thickness of the non-contact region of the electrode is 1–500 nm.

11. A method for preparing a solar cell according to any one of claims 1-10, wherein, include: The polysilicon layer is formed, and the doped polysilicon layer includes a first opening corresponding to the first electrode and an electrode non-contact region defining the first opening; The electrode contact region of the doped polycrystalline silicon layer is formed in the first opening; The first electrode is disposed at a position corresponding to the electrode contact area to obtain the solar cell.

12. The method for preparing a solar cell according to claim 11, wherein, Also includes: Provide substrate; The polycrystalline silicon layer is formed on at least one side of the substrate.

13. An electrical appliance, wherein, The solar cell includes the solar cell according to any one of claims 1-10 or the solar cell obtained according to the preparation method according to claim 11 or 12, wherein the solar cell serves as the power supply for the electrical device.

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