Data processing method and apparatus, and storage medium

Abstract

The present application belongs to the field of computing. Disclosed are a data processing method and apparatus, and a storage medium. The method is applied to a computing device, the computing device comprises a plurality of different types of computing units, and the method comprises: on the basis of an operator for processing data to be processed, determining a plurality of computing units capable of processing said data; on the basis of an overhead of each computing unit among the plurality of computing units in processing a corresponding computing instruction, determining the data volume of said data processed by each computing unit when the overhead of using the plurality of computing units to process said data is minimized; on the basis of the data volume, allocating from said data processed sub-data to each computing unit among the plurality of computing units; and the plurality of computing units processing in parallel the sub-data corresponding to each computing unit. The present application can improve the efficiency of data processing.

Description

Data processing methods, devices and storage media

[0001] This application claims priority to Chinese Patent Application No. 202510473893.X, filed on April 15, 2025, entitled “Data Processing Method, Apparatus and Storage Medium”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of computing, and in particular to a data processing method, apparatus and storage medium. Background Technology

[0003] In a computing system, there are typically multiple processor resources, each containing different types of computing units, each capable of performing different data processing tasks. However, in related technologies, the efficiency of data processing is relatively low when using the processor resources of a computing system to process data. Summary of the Invention

[0004] This application provides a data processing method, apparatus, and storage medium to improve data processing efficiency. The technical solution is as follows:

[0005] In a first aspect, this application provides a data processing method applied to a computing device, which includes multiple different types of computing units. In the method, multiple computing units capable of processing the data to be processed are determined based on operators that process the data to be processed. The amount of data to be processed processed by each computing unit is determined based on the overhead of each computing unit processing a corresponding computation instruction, minimizing the overhead of using multiple computing units to process the data to be processed. Sub-data to be processed is allocated from the data to be processed to each computing unit among the multiple computing units based on this data amount. The multiple computing units process the sub-data corresponding to each computing unit in parallel.

[0006] Since the amount of data to be processed by each computing unit is determined based on the overhead of each computing unit in processing the corresponding computing instructions, the amount of data to be processed by multiple computing units is determined to minimize the overhead of processing the data to be processed by multiple computing units. Thus, based on this amount of data, sub-data to be processed is allocated from the data to be processed to each computing unit in multiple computing units. Multiple computing units process the sub-data corresponding to each computing unit in parallel, so that the overhead required for multiple computing units to process the data to be processed is minimized, thereby improving the data processing efficiency.

[0007] In one possible implementation, the sub-data processed by each computing unit is converted into at least one computing instruction corresponding to each computing unit, based on the data format processed by that computing unit. Each computing unit then loads the corresponding at least one computing instruction to perform data processing. This ensures that each computing unit can successfully load its corresponding computing instruction to successfully perform data processing.

[0008] In another possible implementation, multiple computing units may belong to the same processor or different processors, thus increasing the flexibility of adding computing instructions to the computing units.

[0009] In another possible implementation, each computational unit processes its corresponding sub-data using a processing method corresponding to the operator. This ensures the correctness of the processed data.

[0010] In another possible implementation, the multiple computation units are at least two of the following: fixed-length vector computation units, variable-length vector computation units, scalar computation units, or matrix computation units.

[0011] In another possible implementation, multiple proportions of sub-data allocated to each computing unit according to the types of multiple computing units are obtained; the cost of the computing unit with the highest overhead when multiple computing units process the data to be processed in parallel after the data to be processed is divided in parallel according to each proportion is determined as the overhead corresponding to each proportion; from the overheads corresponding to multiple proportions, the amount of data to be processed by each computing unit is determined by the proportion with the lowest overhead. In this way, the amount of data to be processed when the overhead of processing the data to be processed using multiple computing units is minimized is successfully obtained.

[0012] In a second aspect, this application provides a computing device, the computing device including a processor and a memory, the memory storing instructions; the processor is configured to execute the instructions stored in the memory so that the computing device performs the method of the first aspect or any possible implementation thereof.

[0013] Thirdly, this application provides a computer program product containing instructions that, when executed by a computing device, cause the computing device to perform the method in the first aspect or any possible implementation thereof.

[0014] Fourthly, this application provides a computer-readable storage medium including computer program instructions, which, when executed by a computing device, perform the method of the first aspect or any possible implementation thereof.

[0015] Fifthly, this application provides a chip including a memory and a processor, wherein the memory is used to store computer instructions, and the processor is used to call and execute the computer instructions from the memory to perform the method in the first aspect or any possible implementation thereof. Attached Figure Description

[0016] Figure 1 is a schematic diagram of a computing device provided in an embodiment of this application;

[0017] Figure 2 is a schematic diagram of the structure of a processor provided in an embodiment of this application;

[0018] Figure 3 is a flowchart of a data processing method provided in an embodiment of this application;

[0019] Figure 4 is a schematic diagram of an input command provided in an embodiment of this application;

[0020] Figure 5 is a schematic diagram of a data processing device provided in an embodiment of this application;

[0021] Figure 6 is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0022] A computing device has the function of processing data and can be used to process data. Optionally, a computing device can be a device in a data processing system. For example, a computing device is a server in a data processing system.

[0023] Referring to Figure 1, the computing device includes at least one processor, which is used to process data. The at least one processor may include one or more of the following: a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), an embedded neural network processor (NPU), a data processing unit (DPU), or an application-specific integrated circuit (ASIC), etc.

[0024] Referring to Figure 2, for some processors in at least one processor, the processor may include at least one computing unit. A computing unit is a unit within the processor capable of independently executing computing instructions; it is a computing logic processing unit within the processor, and the computing instructions are instructions for processing data.

[0025] For example, the processor may be a CPU, which may include multiple computing units. These computing units have computational functions and can be used to process data. Optionally, as shown in Figure 2, the computing units in the CPU may include one or more of the following: arithmetic logic unit (ALU)1, ALU2 / branch logic unit (BLU)1, ALU3 / BLU2, floating point / advance single instruction multiple data (FP / AMISD)1 or FP / AMISD2, etc.

[0026] In some embodiments, the CPU may also include at least one loading unit, each loading unit being used to read data to be processed, and then the reading data is processed by the computing unit.

[0027] In some embodiments, the CPU may also include at least one storage unit, each storage unit being used to store the processing results obtained by the computing unit from processing data. For example, the storage unit may store the processing results into a storage object, which may be an array, a linked list, a graph, or other data structure used for storing data.

[0028] Optionally, at least one loading unit corresponds one-to-one with at least one storage unit. The one-to-one corresponding loading unit and storage unit can be two different units or integrated into one unit. For example, as shown in Figure 2, the CPU may also include Load / Store 0 and / or Load / Store 1, etc. Load / Store 0 is a unit that integrates the one-to-one corresponding loading unit and storage unit, and Load / Store 1 is a unit that integrates the one-to-one corresponding loading unit and storage unit.

[0029] Besides CPUs, which include multiple computing units, other processors may also include computing units; for example, a GPU may include one or more computing units. For some processors with at least one processor, the processor itself is a computing unit, meaning the processor includes a computing unit. For example, processors like FPGAs or ASICs are computing units.

[0030] Therefore, it can be concluded that at least one processor includes multiple computing units, which include computing units in a portion of the processor and computing units in another portion of the processor. For example, as shown in Figure 2, the multiple computing units in at least one processor include multiple computing units in a CPU, computing units in a GPU, computing units in a DPU, computing units in an NPU, FPGAs, and ASICs, etc.

[0031] The computing device also includes operators, which define how data is processed. An operator is the smallest logical unit that implements an operation in an algorithm or programming. It is represented by a function, code, or encapsulated algorithm node and is used to perform mathematical operations, logical processing, or data transformation on data (such as constants or variables).

[0032] For ease of explanation, the operators included in the computing device are referred to as the first operator. The first operator is generated by the computing device using existing operator generation methods, or it is an operator received by the computing device from other devices. For example, the first operator is an operator received by the computing device from a management device or a user's terminal device.

[0033] In some embodiments, the first operator may include an input variable and a first calculation instruction. The input variable is used to receive data to be processed, and the first calculation instruction is used to process the data to be processed. The processing method corresponding to the first operator is the processing method indicated by the first calculation instruction. The processing method indicated by the first calculation instruction includes addition, subtraction, multiplication, division, or other methods.

[0034] When processing data, the computing device can use a computing unit to process the data based on a first computing instruction. That is, the first computing instruction is executed by the computing unit, which processes the data by executing the first computing instruction.

[0035] For example, the first operator shown below includes input variables SourceA and SourceB, and a first calculation instruction c = co_op(x, y). The first calculation instruction can also be represented as SCALAR_ADD_X(c, x, y). The first calculation instruction is used to add the data to be processed received by input variable SourceA and the data to be processed received by input variable SourceB. That is, the processing method indicated by the first calculation instruction is addition.

[0036] void func(ValueType*SourceA, ValueType*SourceB, ValueType*Sink){

[0037] ValueType x=co_load(SourceA);

[0038] ValueType y=co_load(SourceB);

[0039] ValueType c = co_op(x, y);

[0040] co_store(Sink, c);

[0041] }

[0042] In some embodiments, in addition to input variables and a first calculation instruction, the first operator may also include a storage object for storing the processing result obtained by the first calculation instruction processing the data. For example, as shown above, the first operator further includes a storage object Sink, which is an array.

[0043] Optionally, the first operator may include a loading instruction corresponding to the first calculation instruction. The loading instruction corresponding to the first calculation instruction is used to add the data to be processed to the calculation unit, and then the calculation unit processes the loaded data to be processed based on the first calculation instruction.

[0044] For example, as shown in the first operator above, the first operator also includes two loading instructions corresponding to the first calculation instruction, namely x = co_load(SourceA) and y = co_load(SourceB). The loading instruction x = co_load(SourceA) is used to load the data to be processed (represented by x) received by the input variable SourceA into the calculation unit, and the loading instruction y = co_load(SourceB) is used to load the data to be processed (represented by y) received by the input variable SourceB into the calculation unit. Then, the calculation unit performs addition on the data to be processed x and the data to be processed y based on the first calculation instruction c = co_op(x, y) to obtain the processing result (represented by c).

[0045] Optionally, the processing result obtained from the first calculation instruction in the first operator may need to be saved to a storage object. Therefore, the first operator may include a storage instruction corresponding to the first calculation instruction, which is used to save the processing result to the storage object.

[0046] For example, as shown above, the first operator also includes a storage instruction co_store(Sink, c) corresponding to the first calculation instruction. The storage instruction co_store(Sink, c) is used to save the processing result c into the storage object Sink.

[0047] Optionally, for some simpler first operators, the first operator may not include the load instruction and / or the store instruction corresponding to the first calculation instruction. For example, the first operator shown below has relatively simple logic. It includes an input variable and a first calculation instruction c = co_op(x, y). The input variable is used to receive the data A and B to be processed by the first calculation instruction c = co_op(x, y). The first operator also includes a return instruction return c, used to return the processing result c.

[0048] void func(ValueType*A, ValueType*B){

[0049] ValueType c = co_op(A, B);

[0050] return c;

[0051] }

[0052] In some embodiments, the first operator includes a first computation instruction that is a computation instruction of a first instruction type, and each computation unit in at least one processor corresponds to at least one instruction type.

[0053] In some embodiments, the first instruction type may be a fixed-length vector instruction type, a variable-length vector instruction type, a scalar instruction type, or a matrix instruction type, etc.

[0054] For example, the three computing units ALU1, ALU2 / BLU1, and ALU3 / BLU2 in the CPU shown in Figure 2 all correspond to scalar instruction types. The two computing units FP / AMISD1 and FP / AMISD2 in the CPU shown in Figure 2 both correspond to fixed-length vector instruction types and variable-length vector instruction types.

[0055] In some embodiments, the computation unit corresponding to the fixed-length vector instruction type can be called a fixed-length vector computation unit, the computation unit corresponding to the variable-length vector instruction type can be called a variable-length vector computation unit, the computation unit corresponding to the scalar instruction type can be called a scalar computation unit, and the computation unit corresponding to the matrix instruction type can be called a matrix computation unit.

[0056] Optionally, some computation units may correspond to both fixed-length vector instruction types and variable-length vector instruction types. Such computation units can be called either fixed-length vector computation units or variable-length vector computation units.

[0057] For example, referring to Figure 2, the instruction types corresponding to the three computing units ALU1, ALU2 / BLU1, and ALU3 / BLU2 in the CPU are all scalar instruction types. ALU1, ALU2 / BLU1, and ALU3 / BLU2 can all be called scalar computing units. The instruction types corresponding to the two computing units FP / AMISD1 and FP / AMISD2 in the CPU include both fixed-length vector instruction types and variable-length vector instruction types. FP / AMISD1 and FP / AMISD2 can be called both fixed-length vector computing units and variable-length vector computing units.

[0058] The first calculation instruction needs to be executed on the calculation unit corresponding to the first instruction type. In other words, only the calculation unit corresponding to the first instruction type can process the data to be processed based on the first calculation instruction of the first instruction type.

[0059] Any computation instruction of the fixed-length vector instruction type can be called a fixed-length vector instruction. A fixed-length vector instruction processes a fixed number of data units of length each time. Let's assume the number of data units of length processed by a fixed-length vector instruction each time is n, where n is an integer greater than or equal to 1. Before processing the n data units, the fixed-length vector instruction organizes the n data units into a vector and then processes that vector.

[0060] Optionally, n = 1, 2, 3 or 4, etc. The length of data processed by a fixed-length vector instruction each time is equal to the bit width of the processor. Therefore, the number of data units n processed by a fixed-length vector instruction each time is equal to the ratio between the bit width of the processor and the unit length.

[0061] For example, assuming the processor's bit width is 128 bits and the unit length is 32 bits, the number of data units n processed by a fixed-length vector instruction each time is 4, that is, the fixed-length vector instruction processes 4 units of data each time, which means that the data length processed by the fixed-length vector instruction each time is 128 bits.

[0062] Any computation instruction of variable-length vector instruction type can be called a variable-length vector instruction. The number of data units of length processed by a variable-length vector instruction can vary each time. However, the length of data processed by a variable-length vector instruction at one time is not unlimited; it must be less than or equal to the maximum data length defined by the processor. Therefore, the number of data units processed by a variable-length vector instruction at one time is less than or equal to m, where m is an integer greater than 1, and m is equal to the ratio between the maximum data length and the unit length.

[0063] For example, the maximum data length that a variable-length vector instruction defined by the processor can process at one time is 1024 bits, and the unit length is 32 bits. Therefore, the number of data units of the unit length processed by the variable-length vector instruction each time is less than or equal to 32, that is, m = 32.

[0064] Fixed-length vector commands can process n data points. Before processing, the n data points are organized into a vector, and then the vector is processed.

[0065] Variable-length vector commands can process multiple data sets. Before processing, the multiple data sets are organized into a vector containing less than or equal to m data sets, and then the vector is processed.

[0066] Any computation instruction of the scalar instruction type can be called a scalar instruction. A scalar instruction processes data of one unit length at a time.

[0067] Any calculation instruction of the matrix instruction type can be called a matrix instruction. A matrix instruction processes multiple data points of unit length at a time. Before using a matrix instruction to process multiple data points, these data points can be organized into a multi-row, multi-column matrix, and then the matrix can be processed.

[0068] For any of the above instruction types, there may be multiple computation instructions belonging to that instruction type, and these multiple computation instructions may indicate different processing methods.

[0069] For example, among multiple variable-length vector instructions of the variable-length vector instruction type, some variable-length vector instructions indicate the processing mode as addition, some as subtraction, some as multiplication, and / or, and some as division.

[0070] For example, among multiple fixed-length vector instructions of the fixed-length vector instruction type, some fixed-length vector instructions indicate the processing mode as addition, some as subtraction, some as multiplication, and / or, and some as division.

[0071] For the aforementioned first operator, the first operator typically includes one or more first computation instructions of a first instruction type. The operating system of the computing device can deploy the one or more first computation instructions on one or more computing units corresponding to the first instruction type, and the computing units corresponding to the first instruction type can process data based on the first computation instructions.

[0072] In related technologies, the overhead of the computing unit processing data based on the first computing instruction is relatively large, resulting in low data processing efficiency of the computing unit in the computing device. In order to improve the data processing efficiency of the computing unit, the first operator can be processed using the following method.

[0073] Referring to Figure 3, this application embodiment provides a data processing method 300. The method 300 can be applied to the computing device shown in Figure 1, which includes various types of computing units. The executing entity of the method 300 can be the computing device. The method 300 includes the following process.

[0074] Step 301: Determine multiple computing units capable of processing the data to be processed based on the first operator that processes the data to be processed.

[0075] Step 302: Determine the amount of data to be processed by each computing unit when the overhead of processing the corresponding computing instructions in multiple computing units is minimized.

[0076] Step 303: Allocate the sub-data to be processed to each of the multiple computing units from the data to be processed according to the amount of data to be processed by each computing unit.

[0077] Step 304: Multiple computing units process the sub-data corresponding to each computing unit in parallel.

[0078] In some embodiments, the entity performing steps 301 to 303 above may be the operating system of a computing device.

[0079] Next, we will list and explain each of the above steps in detail.

[0080] Regarding step 301 above, the plurality of computing units can be computing units of different types, that is, computing units corresponding to different instruction types. Optionally, the computing device includes computing units of multiple instruction types, and the plurality of computing units can include computing units of these multiple instruction types.

[0081] The processing method for the data by these multiple computing units is the first processing method corresponding to the first operator.

[0082] Optionally, the multiple calculation units are at least two of the following: fixed-length vector calculation units, variable-length vector calculation units, scalar calculation units, or matrix calculation units.

[0083] For example, assuming the computing device includes a fixed-length vector calculation unit corresponding to a fixed-length vector instruction type, a variable-length vector calculation unit corresponding to a variable-length vector instruction type, a scalar calculation unit corresponding to a scalar instruction type, and a matrix calculation unit corresponding to a matrix instruction type, then these multiple calculation units can include a fixed-length vector calculation unit, a variable-length vector calculation unit, a scalar calculation unit, and a matrix calculation unit. As another example, assuming the computing device includes a fixed-length vector calculation unit corresponding to a fixed-length vector instruction type, a scalar calculation unit corresponding to a scalar instruction type, and a matrix calculation unit corresponding to a matrix instruction type, then these multiple calculation units can include a fixed-length vector calculation unit, a scalar calculation unit, and a matrix calculation unit.

[0084] In other words, the number of computing units determined can include computing units corresponding to the various instruction types that the computing device has. Alternatively, if the computing device has computing units with multiple instruction types, the number of determined computing units can include computing units for some of those instruction types.

[0085] In some embodiments, the first operator includes a first calculation instruction, and the processing method corresponding to the first operator includes the processing method indicated by the first calculation instruction.

[0086] In step 301, assuming the computing device includes computing unit 1 corresponding to the first instruction type and computing unit 2 corresponding to the second instruction type, the following process can be used to determine multiple computing units capable of processing the data to be processed, including computing unit 1 corresponding to the first instruction type and computing unit 2 corresponding to the second instruction type.

[0087] 3011: Obtain a second calculation instruction of the second instruction type based on the first operator, and the processing method indicated by the second calculation instruction is the same as that indicated by the first calculation instruction.

[0088] In 3011, based on the processing method indicated by the first calculation instruction included in the first operator, a second calculation instruction of the second instruction type is obtained, and the second calculation instruction is also used to indicate the processing method.

[0089] Therefore, the calculation instructions that can be obtained in step 3011 include a first calculation instruction of the first instruction type and a second calculation instruction of the second instruction type.

[0090] In some embodiments, if the computing device further includes a computing unit corresponding to the third instruction type, then in step 301, a third computing instruction of the third instruction type can also be obtained based on the first operator, and the processing method indicated by the third computing instruction is also the processing method.

[0091] Therefore, the calculation instructions obtained in step 3011 also include third calculation instructions of the third instruction type.

[0092] Similarly, if the computing device also includes computing units corresponding to other instruction types, then in step 3011, computing instructions of other instruction types can also be obtained. The processing method indicated by the computing instructions of other instruction types is also the same processing method, which will not be listed and explained one by one here.

[0093] The first, second, third, and other instruction types mentioned above can be fixed-length vector instruction types, variable-length vector instruction types, matrix instruction types, and scalar instruction types. That is, in 3011, calculation instructions of any two, any three, or all of the following instruction types can be obtained: fixed-length vector instruction types, variable-length vector instruction types, matrix instruction types, and scalar instruction types.

[0094] In some embodiments, the first operator in the computing device may be an operator received by the computing device from another device, which is generated by the other device using an operator generation method. Alternatively, the first operator in the computing device may be generated by the computing device itself based on an operator generation method.

[0095] In some embodiments, the first operator may include one or more computation instructions of one instruction type, that is, the number of first computation instructions of the first instruction type included in the first operator may be one or more.

[0096] In some embodiments, the first operator further includes an input variable corresponding to the first calculation instruction. The input variable is used to receive input data to be processed, which may include the data to be processed from the first calculation instruction.

[0097] Optionally, the first operator may include one or more input variables, each of which may be used to receive data to be processed from the first calculation instruction.

[0098] Optionally, the data to be processed may include one or more units of data.

[0099] For example, consider the first operator shown below. The first operator includes two input variables and a first calculation instruction of scalar instruction type. There are two input variables, namely input variable SourceA and input variable SourceB. The first calculation instruction of scalar instruction type is SCALAR_ADD_X(c, a, b). The processing method indicated by the first calculation instruction SCALAR_ADD_X(c, a, b) is addition, that is, the first calculation instruction SCALAR_ADD_X(c, a, b) is used to add the data to be processed received by input variable SourceA and input variable SourceB.

[0100] First operator:

[0101] void func(ValueType*SourceA, ValueType*SourceB, ValueType*Sink){

[0102] ValueType x=co_load(SourceA);

[0103] ValueType y=co_load(SourceB);

[0104] ValueType c;

[0105] SCALAR_ADD_X(c, x, y);

[0106] co_store(Sink, c);

[0107] }

[0108] Assume that at least one processor of the computing device includes a scalar computation unit corresponding to a scalar instruction type, a variable-length vector computation unit corresponding to a variable-length vector instruction type, a matrix computation unit corresponding to a matrix instruction type, and a fixed-length vector computation unit corresponding to a fixed-length vector instruction type.

[0109] The aforementioned first operator includes a first calculation instruction of scalar instruction type SCALAR_ADD_X(c, a, b), which indicates the processing method as addition. The first calculation instruction SCALAR_ADD_X(c, a, b) is a scalar instruction. Thus, in step 3011, based on this processing method (addition), a second calculation instruction of variable-length vector instruction type is obtained as svc = svadd(pg, sva, svb), and a third calculation instruction of matrix instruction type is obtained as matrix_add_za(smc, sma, smb). The second calculation instruction of variable-length vector instruction type svc = svadd(pg, sva, svb) indicates the processing method as addition, and the second calculation instruction svc = svadd(pg, sva, svb) is a variable-length vector instruction. Furthermore, the third calculation instruction of the matrix instruction type, matrix_add_za(smc, sma, smb), also indicates the processing method as addition. The third calculation instruction, matrix_add_za(smc, sma, smb), is a matrix instruction.

[0110] In some embodiments, the first operator may further include a loading instruction corresponding to the first calculation instruction, and the number of loading instructions corresponding to the first calculation instruction may be one or more. The loading instruction corresponding to the first calculation instruction is used to load data to be processed into a computing unit that has the first calculation instruction deployed thereon, and the computing unit processes the data to be processed based on the first calculation instruction to obtain a processing result.

[0111] In some embodiments, the first operator may further include a storage object and a storage instruction corresponding to the first calculation instruction. The number of storage instructions corresponding to the first calculation instruction may be one or more. The storage instruction corresponding to the first calculation instruction is used to save the processing result obtained based on the first calculation instruction into the storage object.

[0112] For example, in the example of the first operator shown above, the first operator also includes two load instructions corresponding to the first calculation instruction SCALAR_ADD_X(c, a, b), namely the load instruction x = co_load(SourceA) and the load instruction y = co_load(SourceB).

[0113] The loading instruction x = co_load(SourceA) loads the data A to be processed received by the input variable SourceA into the computing unit, and the loading instruction y = co_load(SourceB) loads the data B to be processed received by the input variable SourceB into the computing unit. The computing unit is equipped with the first computing instruction SCALAR_ADD_X(c, a, b). Based on the first computing instruction SCALAR_ADD_X(c, a, b), the computing unit adds the data A and data B to obtain the processing result, which is the sum of data A and data B.

[0114] In the example of the first operator shown above, the first operator also includes the storage object Sink and the storage instruction co_store(Sink, c) corresponding to the first calculation instruction SCALAR_ADD_X(c, a, b), where the storage object Sink is an array.

[0115] The storage instruction co_store(Sink, c) is used to save the processing result obtained by the first calculation instruction SCALAR_ADD_X(c, a, b) into the storage object Sink.

[0116] In some embodiments, the first operator may include computation instructions of multiple instruction types, and the number of computation instructions of each instruction type may be one or more.

[0117] 3012: Determine multiple computing units, including computing unit 1 corresponding to a first instruction type and computing unit 2 corresponding to a second instruction type.

[0118] If the third calculation instruction corresponding to the third instruction type is also obtained in 3011, the plurality of calculation units also include calculation unit 3 corresponding to the third instruction type.

[0119] Regarding step 302 above, step 302 records: determining the amount of data to be processed by each computing unit when the overhead of processing the corresponding computing instruction by each computing unit in the multiple computing units is minimized.

[0120] The plurality of computing units includes computing unit 1 corresponding to the first instruction type and computing unit 2 corresponding to the second instruction type. The overhead of each computing unit in processing the corresponding computing instruction includes the overhead of the computing instruction of the first instruction type and the overhead of the computing instruction of the second instruction type.

[0121] In step 302, based on the overhead of computation instructions of the first instruction type and the overhead of computation instructions of the second instruction type, the proportion of data allocated to each computation unit when the overhead of processing the data to be processed using multiple computation units is minimized is obtained. Then, based on this proportion, the amount of data to be processed by each computation unit is determined.

[0122] Optionally, this ratio can be the ratio of the number of data items to be processed between the first instruction type calculation instructions and the second instruction type calculation instructions.

[0123] If a third computation instruction of the third instruction type is also obtained in step 3011, the multiple computation units also include computation unit 3 corresponding to the third instruction type. In step 302, based on the overhead of the computation instructions of the first instruction type, the overhead of the computation instructions of the second instruction type, and the overhead of the computation instructions of the third instruction type, the proportion of data allocated to each computation unit when the overhead of processing the data to be processed using multiple computation units is minimized is obtained.

[0124] Optionally, this ratio is the ratio of the number of data to be processed among the calculation instructions of the first instruction type, the calculation instructions of the second instruction type, and the calculation instructions of the third instruction type.

[0125] In some embodiments, the overhead of a computation instruction of the first instruction type may include the execution time of the computation instruction of the first instruction type or the time for the computation instruction of the first instruction type to process a piece of data, the length of which is a unit length.

[0126] The computing units in at least one processor of a computing device may include variable-length vector computing units corresponding to variable-length vector instruction types, fixed-length vector computing units corresponding to fixed-length vector instruction types, scalar computing units corresponding to scalar instruction types, and / or matrix computing units corresponding to matrix instruction types.

[0127] The calculation instructions for the variable-length vector instruction type are variable-length vector instructions, the calculation instructions for the fixed-length vector instruction type are fixed-length vector instructions, the calculation instructions for the scalar instruction type are scalar instructions, and the calculation instructions for the matrix instruction type are matrix instructions.

[0128] The overhead of variable-length vector instructions includes the time T it takes for a variable-length vector instruction to process one piece of data. 变长 And the maximum number of data items, m, that a variable-length vector instruction can process in one pass. The overhead of a fixed-length vector instruction includes its execution time, T. 定长 And the number of data items n processed by each fixed-length vector instruction, and the execution time T of the fixed-length vector instruction. 定长 The overhead of a scalar instruction is equal to the time it takes for a fixed-length vector instruction to process n data items. The overhead of a scalar instruction includes the time T it takes to process one data item. 标量 Scalar instructions process one data item at a time, with a duration of T. 标量 The overhead of a matrix instruction is equal to the execution time of a scalar instruction. The overhead of a matrix instruction includes the time T it takes to process one data item. 矩阵 The above data refers to data per unit length.

[0129] If the computation instructions obtained in 3011 include four instruction types: fixed-length vector instruction, variable-length vector instruction, scalar instruction, and matrix instruction, then based on the overhead of the computation instructions for each of the four instruction types, the proportion of data allocated to each computation unit when the overhead of processing the data to be processed using multiple computation units is minimized is obtained. Optionally, this proportion is the ratio of the number of data items to be processed among the computation instructions for the four instruction types.

[0130] If the computation instructions obtained in 3011 include computation instructions of three instruction types, namely, any three of the following: fixed-length vector instruction type, variable-length vector instruction type, scalar instruction type, and matrix instruction type, then based on the overhead of the computation instructions of the three instruction types, the proportion of data allocated to each computation unit when the overhead of processing the data to be processed using multiple computation units is minimized is obtained. Optionally, this proportion is the ratio of the number of data to be processed among the computation instructions of the three instruction types.

[0131] If the computation instructions obtained in 3011 include two instruction types, which are any two of the following: fixed-length vector instruction, variable-length vector instruction, scalar instruction, and matrix instruction, then based on the overhead of the computation instructions for the two instruction types, the proportion of data allocated to each computation unit when the overhead of processing the data to be processed using multiple computation units is minimized is obtained. Optionally, this proportion is the ratio of the number of data items to be processed between the computation instructions of the two instruction types.

[0132] Next, we can take the computation instructions obtained in 3011, which include four instruction types, as an example. These four instruction types are the variable-length vector instruction type, fixed-length vector instruction type, scalar instruction type, and matrix instruction type mentioned above. The proportion of the number of data items to be processed among the four instruction types is obtained according to the following process. The four computation units corresponding to these four instruction types are the variable-length vector computation unit, the fixed-length vector computation unit, the scalar computation unit, and the matrix computation unit. This proportion is the proportion of data allocated to the variable-length vector computation unit, the fixed-length vector computation unit, the scalar computation unit, and the matrix computation unit.

[0133] If the calculation instructions obtained in step 301 include calculation instructions of three types or calculation instructions of two types, then the relevant content of the corresponding instruction type can be subtracted in the following process.

[0134] 3021: Obtain the overhead of computation instructions for four instruction types.

[0135] For the variable-length vector instruction type among these four instruction types, obtain the overhead of the variable-length vector instruction, which includes the maximum number of data items m that the variable-length vector instruction can process and the time T for the variable-length vector instruction to process one data item. 变长 .

[0136] Optionally, some processors in at least one of the processors in the computing device include computation units corresponding to variable-length vector instruction types. The computing device can obtain the processor's specification sheet, which records the maximum number of data points m processed per instruction cycle by the variable-length vector instruction. The computing device can obtain the maximum number of data points m processed per instruction cycle by the variable-length vector instruction from the processor's specification sheet. And / or, the specification sheet records the time T for a variable-length vector instruction to process one data point. 变长 The computing device can obtain the time T for variable-length vector instructions to process one piece of data from the processor's specifications. 变长 .

[0137] Optionally, the processing time T for a variable-length vector instruction is... 变长 The computing device includes a computing unit corresponding to a variable-length vector instruction type. The computing device can measure the time T for the variable-length vector instruction to process one piece of data based on the computing unit. 变长 .

[0138] Optionally, in implementation: the computing device can input a variable-length vector instruction to the computing unit to obtain multiple data points, all of which are unit-length data. This data is then input into the computing unit corresponding to the variable-length vector instruction type. The computing unit combines these multiple data points into at least one vector, where each vector contains less than or equal to m data points. Based on the variable-length vector instruction, the at least one vector is processed to obtain a processing result for the multiple data points, which is then output. The computing device obtains the input timestamp of the multiple data points input to the computing unit and the output timestamp of the processing result output by the computing unit. Based on the input and output timestamps, the total processing time of the variable-length vector instruction for the multiple data points is obtained. Based on the total processing time and the number of data points, the processing time T for one data point by the variable-length vector instruction is obtained. 变长 .

[0139] For the fixed-length vector instruction type among these four instruction types, obtain the overhead of the fixed-length vector instruction, which includes the execution time T of the fixed-length vector instruction. 定长 And the number of data items n processed by the fixed-length vector instruction each time.

[0140] Optionally, some processors in at least one of the processors in the computing device include computation units corresponding to fixed-length vector instruction types. The computing device can obtain the processor's specification sheet, which records the execution time T of the fixed-length vector instructions. 定长 And the number of data points n processed by a fixed-length vector instruction at a time. The computing device can obtain the number of data points m processed by a fixed-length vector instruction at a time and the execution time T of the fixed-length vector instruction from the processor's specifications. 定长 .

[0141] Optionally, if the processor's specifications do not record the execution time T of fixed-length vector instructions... 定长 For at least one processor of a computing device that includes a computing unit corresponding to a fixed-length vector instruction type, the computing device can measure the execution time T of executing the fixed-length vector instruction based on the computing unit. 定长 .

[0142] Optionally, in implementation: the computing device can input a fixed-length vector instruction to the computing unit to obtain Q data points, where Q is an integer multiple of n, and each of the Q data points is a unit-length data point. The computing unit then inputs these Q data points into the computing unit corresponding to the fixed-length vector instruction type. The computing unit combines these Q data points into Q / n vectors, each vector containing n data points. Based on the fixed-length vector instruction, it processes these Q / n vectors to obtain the processing result for the Q data points and outputs the processing result. The computing device obtains the input timestamp of the Q data points input to the computing unit and the output timestamp of the processing result output by the computing unit. Based on the input and output timestamps, it obtains the total processing time T of the fixed-length vector instruction for the Q data points. Based on the total processing time T, Q, and n, it obtains the execution time T of the fixed-length vector instruction. 定长 = (T*n) / Q.

[0143] For the scalar instruction type among the four instruction types, obtain the overhead of the scalar instruction, which includes the execution time T of the scalar instruction. 标量 .

[0144] Optionally, some processors in at least one of the processors in the computing device include computation units corresponding to scalar instruction types. The computing device can obtain the processor's specification sheet, which records the execution time T of the scalar instruction. 标量 The computing device can obtain the time T for a scalar instruction to process a piece of data from the processor's specifications. 标量 .

[0145] Optionally, if the processor's specifications do not record the time T for a scalar instruction to process one piece of data... 标量 For at least one processor of a computing device that includes a computing unit corresponding to a scalar instruction type, the computing device can measure the time T for a scalar instruction to process a piece of data based on that computing unit. 标量 .

[0146] Optionally, in implementation: the computing device can input scalar instructions to the computing unit to obtain at least one piece of data, where each piece of data is a unit-length data, and input the at least one piece of data into the computing unit corresponding to the scalar instruction type. The computing unit processes the at least one piece of data based on the scalar instructions, processing one piece of data at a time, obtaining a processing result for the at least one piece of data, and outputting the processing result. The computing device obtains the input timestamp of the at least one piece of data input to the computing unit and the output timestamp of the computing unit outputting the processing result. Based on the input timestamp and the output timestamp, it obtains the total duration of the scalar instruction processing the at least one piece of data. Based on the total duration and the number of at least one piece of data, it obtains the duration T of the scalar instruction processing one piece of data.标量 .

[0147] For the matrix instruction type among these four instruction types, obtain the overhead of the matrix instruction, which includes the time T for the matrix instruction to process one piece of data. 矩阵 .

[0148] Optionally, some processors in at least one of the processors in the computing device include computation units corresponding to matrix instruction types. The computing device may obtain the processor's specification sheet, which records the time T for a matrix instruction to process one piece of data. 矩阵 The computing device can obtain the time T for a matrix instruction to process a piece of data from the processor's specifications. 矩阵 .

[0149] Optionally, if the processor's specifications do not record the time T for a matrix instruction to process one data item... 矩阵 For at least one processor of a computing device that includes a computing unit corresponding to a matrix instruction type, the computing device can measure the time T for a matrix instruction to process a piece of data based on that computing unit. 矩阵 .

[0150] Optionally, in implementation: the computing device can input matrix instructions to the computing unit, acquire multiple data points, all of which are unit-length data, and input these data points into the computing unit corresponding to the matrix instruction type. The computing unit combines these multiple data points into a multi-row, multi-column matrix, processes the matrix based on the matrix instruction, obtains the processing result of the multiple data points, and outputs the processing result. The computing device acquires the input timestamp of the multiple data points input to the computing unit and the output timestamp of the processing result output by the computing unit. Based on the input timestamp and the output timestamp, it acquires the total duration of the matrix instruction processing the multiple data points. Based on the total duration and the number of multiple data points, it acquires the duration T of the matrix instruction processing one data point. 矩阵 .

[0151] 3022: Based on the overhead of the computation instructions of the four instruction types, obtain the ratio of the number of data to be processed among the computation instructions of the four instruction types when the overhead of processing the data to be processed using multiple computing units is minimized. That is, obtain the proportion of data allocated to each computing unit when the overhead of processing the data to be processed using multiple computing units is minimized.

[0152] In 3022, based on the overhead of the computation instructions of the four instruction types, the ratio of the number of data to be processed among the computation instructions of the four instruction types is obtained by the following first formula when the overhead of processing the data to be processed using multiple computing units is minimized.

[0153] First formula:

[0154] In the first formula, N represents the total number of data items to be processed, which is a preset value, such as N = 100, 200, 300, or 800. Cost represents the overhead of using multiple computing units to process the data items, which is also the overhead required for the four instruction types to process these N data items. α represents the number of data items to be processed by the fixed-length vector instruction of the fixed-length vector instruction type, β represents the number of data items to be processed by the variable-length vector instruction of the variable-length vector instruction type, γ represents the number of data items to be processed by the matrix instruction of the matrix instruction type, and λ represents the number of data items to be processed by the scalar instruction of the scalar instruction type. α:β:γ:λ represents the ratio of the number of data items to be processed among the four instruction types.

[0155] In some embodiments, the first formula can be solved by a heuristic solution method or a solver. When the ratio α:β:γ:λ of a certain number of data is found to minimize the cost, the ratio α:β:γ:λ of the number of data is output. The ratio α:β:γ:λ of the number of data is the ratio of the number of data to be processed among the four instruction types when the overhead of using multiple computing units to process the data to be processed is minimized.

[0156] In some embodiments, multiple ratios α:β:γ:λ can be enumerated and input into the first formula to obtain the ratio α:β:γ:λ that minimizes the cost. This ratio α:β:γ:λ is the ratio of the number of data to be processed among the four instruction types when the overhead of processing the data to be processed using multiple computing units is minimized. It can also be referred to as the ratio of the data allocated to each computing unit when the overhead of processing the data to be processed using multiple computing units is minimized.

[0157] Then, based on the proportion of data allocated to each computing unit when the overhead of using multiple computing units to process the data to be processed is minimized, the amount of data to be processed by each computing unit is determined.

[0158] For example, given the ratio α:β:γ:λ, it can be determined that the data to be processed by the fixed-length vector calculation unit includes data of length α, meaning the amount of data processed by the fixed-length vector calculation unit is equal to the total amount of data of length α. Similarly, it can be determined that the data to be processed by the variable-length vector calculation unit includes data of length β, meaning the amount of data processed by the variable-length vector calculation unit is equal to the total amount of data of length β. Likewise, it can be determined that the data to be processed by the matrix calculation unit includes data of length γ, meaning the amount of data processed by the matrix calculation unit is equal to the total amount of data of length γ. Finally, it can be determined that the data to be processed by the scalar calculation unit includes data of length λ, meaning the amount of data processed by the scalar calculation unit is equal to the total amount of data of length λ.

[0159] In step 302, the following process can also be followed:

[0160] 1. Obtain multiple proportions of sub-data allocated to each computing unit according to the type of multiple computing units.

[0161] Multiple ratios α:β:γ:λ can be enumerated.

[0162] 2. Determine the cost of the computing unit with the highest overhead when multiple computing units process the data to be processed in parallel after the data to be processed is divided in parallel according to each ratio, and use that cost as the cost corresponding to each ratio.

[0163] The overhead of a computation unit is the overhead of the computation instruction of the instruction type corresponding to the computation unit. That is, the overhead of a fixed-length vector computation unit is the overhead of a fixed-length vector instruction of the fixed-length vector instruction type, the overhead of a variable-length vector computation unit is the overhead of a variable-length vector instruction of the variable-length vector instruction type, the overhead of a scalar computation unit is the overhead of a scalar instruction of the scalar instruction type, and the overhead of a matrix computation unit is the overhead of a matrix instruction of the matrix instruction type.

[0164] For each ratio α:β:γ:λ, the overhead of the computing unit with the highest overhead when multiple computing units process the data to be processed in parallel after the data to be processed is divided in parallel according to the following second formula is used as the overhead corresponding to that ratio.

[0165] The second formula is:

[0166] In the second formula, the Cost ratio is the cost of the computing unit with the highest cost when multiple computing units process the data to be processed in parallel after the data to be processed is divided in parallel according to the ratio α:β:γ:λ. This cost is taken as the cost corresponding to the ratio α:β:γ:λ.

[0167] 3. From the various ratios of overhead, determine the amount of data to be processed by each computing unit based on the ratio with the lowest overhead.

[0168] That is, select the ratio with the lowest cost from multiple ratios, and determine the amount of data to be processed by each computing unit based on the ratio with the lowest cost.

[0169] Regarding step 304 above, step 304 records that: multiple computing units process the sub-data corresponding to each computing unit in parallel. Optionally, in implementation, the sub-data processed by each computing unit is converted into at least one computing instruction corresponding to each computing unit according to the data format processed by each computing unit; each computing unit loads the corresponding at least one computing instruction to perform data processing.

[0170] In some embodiments, a second operator is obtained based on the proportion of data allocated to each computing unit when the overhead of processing the data to be processed using multiple computing units is minimized. The second operator includes at least one computing instruction corresponding to each computing unit.

[0171] Optionally, the plurality of computing units include computing unit 1 and computing unit 2 as described above. The second operator includes a first computing instruction corresponding to computing unit 1 and a second computing instruction corresponding to computing unit 2.

[0172] The second operator also includes input variables, which are the same as those included in the first operator. When the computing device runs the second operator, data to be processed is input into it. The input variables in the second operator are used to receive the data to be processed.

[0173] The input variables in the second operator receive data to be processed, including first sub-data to be processed by the first calculation instruction and second sub-data to be processed by the second calculation instruction. The first sub-data includes one or more data units of length, and the second sub-data includes one or more data units of length. The amount of the first sub-data is equal to the amount of data processed by calculation unit 1, and the first sub-data is the sub-data allocated to calculation unit 1. The amount of the second sub-data is equal to the amount of data processed by calculation unit 2, and the second sub-data is the sub-data allocated to calculation unit 2.

[0174] The second operator is used to instruct computing unit 1 to process the first sub-data based on the first computing instruction, and computing unit 2 to process the second sub-data based on the second computing instruction. The processing method of computing unit 1 for processing the first sub-data is the same as the processing method of computing unit 2 for processing the second sub-data.

[0175] In implementation, the computing device can input a first calculation instruction into computing unit 1 and a second calculation instruction into computing unit 2. The sub-data allocated to computing unit 1 includes the first sub-data, which computing unit 1 processes based on the first calculation instruction. The sub-data allocated to computing unit 2 includes the second sub-data, which computing unit 2 processes based on the second calculation instruction.

[0176] In some embodiments, the first operator includes a loading instruction corresponding to a first calculation instruction, and the second operator further includes a first loading instruction corresponding to the first calculation instruction and a second loading instruction corresponding to the second calculation instruction. The first loading instruction is used to load a first sub-data from the data to be processed into the calculation unit 1, thereby allocating the first sub-data to the calculation unit 1. The second loading instruction is used to load a second sub-data into the calculation unit 2, thereby allocating the second sub-data to the calculation unit 2. The first loading instruction and the second loading instruction are derived based on this ratio.

[0177] In some embodiments, the first loading instruction includes a first starting offset of the first sub-data, and the second loading instruction includes a second starting offset of the second sub-data. The first loading instruction is used to load the first sub-data in the data to be processed into the computing unit 1 based on the first starting offset, and the second loading instruction is used to load the second sub-data in the data to be processed into the computing unit 2 based on the second starting offset. The first starting offset and the second starting offset are obtained based on this ratio.

[0178] In implementation, at least one processor of the computing device includes a first loading unit and a second loading unit. The computing device can input a first loading instruction into the first loading unit and a second loading instruction into the second loading unit. Then, based on a first starting offset, the first loading unit loads a first sub-data from the data to be processed into computing unit 1 by executing the first loading instruction; the second loading unit loads a second sub-data from the data to be processed into computing unit 2 by executing the second loading instruction based on a second starting offset.

[0179] In some embodiments, the first operator further includes a storage object and a storage instruction corresponding to the first calculation instruction, and the second operator further includes a first storage instruction corresponding to the first calculation instruction and a second storage instruction corresponding to the second calculation instruction. The first storage instruction is used to save the first processing result to the storage object, and the second storage instruction is used to save the second processing result to the storage object. The first processing result is the result obtained by the calculation unit 1 processing the first sub-data, and the second processing result is the result obtained by the calculation unit 2 processing the second sub-data. The first storage instruction and the second storage instruction are obtained based on this ratio.

[0180] In some embodiments, the first storage instruction includes a first storage offset, and the second storage instruction includes a second storage offset. The first storage offset and the second storage offset are offset addresses in the storage object. The first storage offset and the second storage offset are obtained based on this ratio. The first storage instruction is used to save a first processing result to the storage object based on the first storage offset, and the second storage instruction is used to save a second processing result to the storage object based on the second storage offset.

[0181] In implementation, at least one processor of the computing device includes a first storage unit and a second storage unit. The computing device can input a first storage instruction into the first storage unit and input a second storage instruction into the second storage unit. Then, the first storage unit saves a first processing result into a storage object by executing the first storage instruction based on a first storage offset; the second storage unit saves a second processing result into the storage object by executing the second storage instruction based on a second starting offset.

[0182] In some embodiments, if a third calculation instruction of a third instruction type is also obtained in step 301, that is, the second operator further includes a third calculation instruction, the plurality of calculation units further include a calculation unit 3 corresponding to the third instruction type.

[0183] The data to be processed also includes third sub-data to be processed by the first calculation instruction. The third sub-data includes one or more data units of length, and the amount of the third sub-data is equal to the amount of data processed by the calculation unit 3. The second operator is also used to instruct the calculation unit 3 to process the third sub-data based on the third calculation instruction. The third sub-data is the sub-data allocated to the calculation unit 3.

[0184] In some embodiments, the first operator includes a loading instruction corresponding to the first calculation instruction, and the second operator also includes a third loading instruction corresponding to the third calculation instruction. The third loading instruction is used to load the third sub-data into the calculation unit 3 to allocate the third sub-data to the calculation unit 3. The third loading instruction is obtained based on this ratio.

[0185] In some embodiments, the third loading instruction includes a third starting offset of the third sub-data. The third loading instruction is used to load the third sub-data in the data to be processed into the computing unit 3 based on the third starting offset, which is obtained based on this ratio.

[0186] In some embodiments, the second operator further includes a prefetch instruction. The data to be processed received by the input variables in the first operator is stored in the memory of the computing device. The prefetch instruction is used to read the data to be processed from the memory of the computing device and load the data to be processed into the cache of the computing device. Thus, the first loading instruction reads the first sub-data from the cache and loads the first sub-data into computing unit 1; the second loading instruction reads the second sub-data from the cache and loads the second sub-data into computing unit 2; and the third loading instruction reads the third sub-data from the cache and loads the third sub-data into computing unit 3.

[0187] In some embodiments, the first operator further includes a storage object and a storage instruction corresponding to the first calculation instruction, and the second operator further includes a third storage instruction corresponding to the third calculation instruction. The third storage instruction is used to save the third processing result into the storage object. The third processing result is the result obtained by the calculation unit 3 processing the third sub-data. The third storage instruction is obtained based on this ratio.

[0188] In some embodiments, the third storage instruction includes a third storage offset, which is an offset address in the storage object. The third storage offset is obtained based on this ratio, and the third storage instruction is used to save the third processing result to the storage object based on the third storage offset.

[0189] For the example of the first operator above, assume the ratio of the number of data items to be processed among the scalar instruction, variable-length vector instruction, and matrix instruction is x:y:z, where x, y, and z are all integers greater than or equal to 1. Based on this ratio, the second operator shown below is generated. The second operator includes input variables SourceA and SourceB, a first calculation instruction of scalar instruction type SCALAR_ADD_X(c, a, b), a second calculation instruction of variable-length vector instruction type svc = svadd(pg, sva, svb), and a third calculation instruction of matrix instruction type matrix_add_za(smc, sma, smb). Here, the first calculation instruction SCALAR_ADD_X(c, a, b) is a scalar instruction, the second calculation instruction svc = svadd(pg, sva, svb) is a variable-length vector instruction, and the third calculation instruction matrix_add_za(smc, sma, smb) is a matrix instruction.

[0190] The second operator also includes the second loading instruction corresponding to the second calculation instruction svc = svadd(pg, sva, svb). The second loading instruction includes sv a = svload(pg, &SourceA[i]), sv b = svload(pg, &SourceB[i]), and pg = svwhilelt_b32(i, i+y). The data to be processed received by the input variable SourceA includes the second sub-data 1 to be processed by the second calculation instruction svc = svadd(pg, sva, svb), which includes data A1 with a length of y units. The data to be processed received by the input variable SourceB includes the second sub-data 2 to be processed by the second calculation instruction svc = svadd(pg, sva, svb), which includes data B1 with a length of y units. i is the starting offset of the second sub-data 1 (y data A1) in the data to be processed received by the input variable SourceA or the starting offset of the second sub-data 2 (y data B1) in the data to be processed received by the input variable SourceB. i+y represents the end offset of the second sub-data 1 in the data to be processed received by input variable SourceA, or the end offset of the second sub-data 2 in the data to be processed received by input variable SourceB. pg represents the data volume of the second sub-data 1 or the data volume of the second sub-data 2, which is the total data volume of y data A1 or the total data volume of y data B1. The total data volume of y data A1 can be equal to the total data volume of y data B1. The second calculation instruction is the calculation instruction corresponding to calculation unit 2. The sub-data to be processed allocated to calculation unit 2 includes the second sub-data 1 and the second sub-data 2, that is, the sub-data allocated to calculation unit 2 includes y data A1 and y data B1.

[0191] The second operator also includes a first load instruction corresponding to the first calculation instruction SCALAR_ADD_X(c, a, b), which includes SCALAR_load_X(a, &SourceA[i+y]) and SCALAR_load_X(b, &SourceB[i+y]). The data to be processed received by the input variable SourceA includes the first sub-data 1 to be processed by the first calculation instruction SCALAR_ADD_X(c, a, b), which includes data A2 with a length of y units. The data to be processed received by the input variable SourceB includes the first sub-data 2 to be processed by the first calculation instruction SCALAR_ADD_X(c, a, b), which includes data B2 with a length of x units. i+y is the starting offset of the first sub-data 1 (x data A2) in the data to be processed received by the input variable SourceA or the starting offset of the first sub-data 2 (x data B2) in the data to be processed received by the input variable SourceB. The first calculation instruction is the calculation instruction corresponding to calculation unit 1. The sub-data to be processed allocated to calculation unit 1 includes first sub-data 1 and first sub-data 2, that is, the sub-data allocated to calculation unit 1 includes x data A2 and x data B2.

[0192] The second operator also includes the third load instruction corresponding to the third calculation instruction matrix_add_za(smc, sma, smb), which includes sma = matrix_load(i, &SourceA[i+x+y]) and smb = matrix_load(i, &SourceB[i+x+y]). The input variable SourceA receives the data to be processed, including the third sub-data 1 to be processed by the third calculation instruction matrix_add_za(smc, sma, smb), which includes data A3 of length z units. The input variable SourceB receives the data to be processed, including the third sub-data 2 to be processed by the third calculation instruction matrix_add_za(smc, sma, smb), which includes data B3 of length z units. i+x+y is the starting offset of the third sub-data 1 (z data A3) in the data to be processed received by the input variable SourceA or the starting offset of the third sub-data 2 (z data B3) in the data to be processed received by the input variable SourceB. The third calculation instruction is the calculation instruction corresponding to calculation unit 3. The sub-data to be processed allocated to calculation unit 3 includes third sub-data 1 and third sub-data 2, that is, the sub-data allocated to calculation unit 3 includes z data A3 and z data B3.

[0193] The second operator also includes the second storage instruction corresponding to the second calculation instruction svc = svadd(pg, sva, svb), the second storage instruction is svstore(&Sink[i], svc), where i is the storage offset in the storage object.

[0194] The second operator also includes the first storage instruction corresponding to the first calculation instruction SCALAR_ADD_X(c, a, b), the first storage instruction being SCALAR_store_X(&Sink[i+y], c), where i+y is the storage offset in the storage object Sink.

[0195] The second operator also includes the third storage instruction corresponding to the third calculation instruction matrix_add_za(smc, sma, smb), which is matrix_store(&Sink[i+x+y], smc), where i+x+y is the storage offset in the storage object Sink.

[0196] The second operator also includes the prefetch instruction prefetch(), which loads the data to be processed received by input variable SourceA and input variable SourceB from the memory of the computing device into the cache of the computing device.

[0197] Second operator:

[0198] void func(ValueType*SourceA, ValueType*SourceB, ValueType*Sink){

[0199] svbool_t pg;

[0200] / / Define variables a, b, c in scalar instructions

[0201] SCALAR_VAR_X(a, ValueType);

[0202] SCALAR_VAR_X(b, ValueType);

[0203] SCALAR_VAR_X(c, ValueType);

[0204] / / Define the variables sva, svb, and svc in the variable-length vector instruction.

[0205] sv_ValueType sva, svb, svc;

[0206] / / Define the variables sma, smb, and smc in the matrix command.

[0207] sm_ValueType sma, smb, smc;

[0208] int batch_size = x + y + z;

[0209] for(int i=0; i<=Sink.size(); i+=batch_size){

[0210] / / Set the data length processed by variable-length vector commands

[0211] pg=svwhilelt_b32(i,i+y);

[0212] / / Prefetch data, used to load data from memory into the cache.

[0213] prefetch();

[0214] / / Loading instructions corresponding to variable-length vector instructions

[0215] sva=svload(pg,&SourceA[i]);

[0216] svb=svload(pg,&SourceB[i]);

[0217] / / Load instructions corresponding to scalar instructions

[0218] SCALAR_load_X(a,&SourceA[i+y]);

[0219] SCALAR_load_X(b,&SourceB[i+y]);

[0220] / / Loading instructions corresponding to matrix instructions

[0221] sma=matrix_load(i,&SourceA[i+x+y]);

[0222] smb=matrix_load(i,&SourceB[i+x+y]);

[0223] / / calculate

[0224] svc=svadd(pg,sva,svb);

[0225] SCALAR_ADD_X(c, a, b);

[0226] matrix_add_za(smc, sma, smb);

[0227] / / Storing data

[0228] svstore(&Sink[i], svc);

[0229] SCALAR_store_X(&Sink[i+y], c);

[0230] matrix_store(&Sink[i+x+y],smc);

[0231] }}.

[0232] Referring to Figure 4, the operating system of the computing device can input the first load instructions SCALAR_load_X(a, &SourceA[i+y]) and SCALAR_load_X(b, &SourceB[i+y]) into the first load unit. The second load instructions sv a = svload(pg, &SourceA[i]), sv b = svload(pg, &SourceB[i]), and pg = svwhilelt_b32(i, i+y) into the second load unit. The third load instructions sma = matrix_load(i, &SourceA[i+x+y]) and smb = matrix_load(i, &SourceB[i+x+y]) into the third load unit. The prefetch instruction prefetch() is input into the fourth load unit. The first calculation instruction SCALAR_ADD_X(c, a, b) is input into the calculation unit 1 corresponding to the scalar instruction type (a scalar calculation unit). The second calculation instruction svc = svadd(pg, sva, svb) is input into the calculation unit 2 corresponding to the variable-length vector instruction type (a variable-length vector calculation unit). The third calculation instruction matrix_add_za(smc, sma, smb) is input into the calculation unit 3 corresponding to the matrix instruction type (a matrix calculation unit). The first storage instruction SCALAR_store_X(&Sink[i+y], c) is input into the first storage unit. The second storage instruction svstore(&Sink[i], svc) is input into the second storage unit. The third storage instruction matrix_store(&Sink[i+x+y], smc) is input into the third storage unit.

[0233] Thus, when the computing device runs the second operator, it inputs the data to be processed to the second operator's SourceA and to the input variable SourceB. The data to be processed received by input variable SourceA and input variable SourceB are stored in the computing device's memory. The fourth loading unit executes the prefetch() instruction to read the data to be processed received by input variable SourceA and input variable SourceB from the computing device's memory and loads the two sets of data into a cache.

[0234] The second loading unit, based on the starting offset i and the data volume pg, executes the second loading instructions sv a = svload(pg, &SourceA[i]), sv b = svload(pg, &SourceB[i]), and pg = svwhilelt_b32(i, i+y) to read the second sub-data 1 (y data A1) from the data to be processed received from the input variable SourceA in the cache, and the second sub-data 2 (y data B1) from the data to be processed received from the input variable SourceB in the cache, and loads the read second sub-data 1 and second sub-data 2 into the calculation unit 2. The calculation unit 2 processes the second sub-data 1 and second sub-data 2 by executing the second calculation instruction svc = svadd(pg, sva, svb) to obtain the second processing result svc. The second storage unit, based on the storage offset i, saves the second processing result svc into the storage object Sink by executing the second storage instruction svstore(&Sink[i], svc).

[0235] The first loading unit, based on the starting offset i+y, executes the first loading instructions SCALAR_load_X(a, &SourceA[i+y]) and SCALAR_load_X(b, &SourceB[i+y]) to read the first sub-data 1 (x data A2) from the data to be processed received from the input variable SourceA in the cache, and the first sub-data 2 (x data B2) from the data to be processed received from the input variable SourceB in the cache, and loads the read first sub-data 1 and first sub-data 2 into the calculation unit 1. The calculation unit 1 processes the first sub-data 1 and first sub-data 2 by executing the first calculation instruction SCALAR_ADD_X(c, a, b) to obtain the first processing result c. The first storage unit, based on the storage offset i+y, saves the first processing result c into the storage object Sink by executing the first storage instruction SCALAR_store_X(&Sink[i+y], c).

[0236] The third loading unit, based on the starting offset i+x+y, executes the third loading instructions sma = matrix_load(i, &SourceA[i+x+y]) and smb = matrix_load(i, &SourceB[i+x+y]) to read the third sub-data 1 (z data A3s) from the data to be processed received from the input variable SourceA in the cache, and the third sub-data 2 (z data B3s) from the data to be processed received from the input variable SourceB in the cache. The read third sub-data 1 and third sub-data 2 are then loaded into the calculation unit 3. The calculation unit 3 processes the third sub-data 1 and third sub-data 2 by executing the third calculation instruction matrix_add_za(smc, sma, smb) to obtain the third processing result smc. The third storage unit, based on the storage offset i+x+y, saves the third processing result smc into the storage object Sink by executing the third storage instruction matrix_store(&Sink[i+x+y], smc).

[0237] In some embodiments, in this step, an operator generator can be used to generate a second operator based on this ratio. When generating scalar variables and scalar instructions, to increase the readability of the operators, the operator generator uses macro definitions to package the scalar instructions. The macro definition for a basic scalar variable is SCALAR_VAR_SINGLE(base_name, index, type), where base_name is the variable name, index is used to enumerate the index number of the scalar variable, and type is the actual data type. A scalar variable of length N is declared as SCALAR_VAR_N(base_name, type), consisting of N macro definitions for basic scalar variables. Scalar operation macro definitions are similar to those for variables; the macro definition for a binary operator is SCALAR_OP_N(base_name, a, b), where the variable name of the destination operator consists of base_name and the index number, and the variable name of the source operator consists of the source variable name and the index number, performing N OP operations.

[0238] In this embodiment, the amount of data to be processed by each computing unit is determined based on the overhead of each computing unit processing the corresponding computational instruction, minimizing the overhead of using multiple computing units to process the data to be processed. Therefore, based on this amount of data, sub-data to be processed is allocated from the data to be processed to the computing units among the multiple computing units. The multiple computing units process the sub-data corresponding to each computing unit in parallel, minimizing the overhead required for processing the data to be processed by the multiple computing units, thereby improving the efficiency of data processing. When multiple computing units process the sub-data corresponding to each computing unit in parallel, the sub-data processed by each computing unit is converted into at least one computational instruction corresponding to each computing unit according to the data format processed by each computing unit. This ensures that each computing unit can successfully load the corresponding at least one computational instruction, guaranteeing successful parallel processing of the data to be processed by multiple computing units, significantly improving the efficiency of data processing.

[0239] Referring to Figure 5, this application embodiment provides a data processing apparatus 500. The apparatus 500 is applied to a computing device, which may be the computing device shown in Figure 1 or the computing device in method 300 shown in Figure 3. The computing device includes multiple computing units of different types. The apparatus 500 includes a determining unit 501, an allocating unit 502, and a controlling unit 503.

[0240] The determining unit 501 is used to determine multiple computing units capable of processing the data to be processed based on the operators that process the data to be processed.

[0241] The determining unit 501 is also used to determine the amount of data to be processed by each computing unit when the overhead of each computing unit in processing the corresponding computing instruction is minimized when using multiple computing units to process the data to be processed.

[0242] The allocation unit 502 is used to allocate the sub-data to be processed from the data to be processed to each of the multiple computing units according to the amount of data;

[0243] The control unit 503 is used to control multiple computing units to process the sub-data corresponding to each computing unit in parallel.

[0244] Optionally, the detailed implementation process of determining multiple computing units capable of processing the data to be processed by the determining unit 501 based on the operator for processing the data to be processed can be found in the relevant content of step 301 of method 300 shown in Figure 3, and will not be described in detail here.

[0245] Optionally, the detailed implementation process of determining the amount of data to be processed by each computing unit when the overhead of each computing unit in processing the corresponding computing instruction is minimized by determining the amount of data to be processed by the multiple computing units can be found in step 302 of method 300 shown in Figure 3, and will not be described in detail here.

[0246] Optionally, the detailed implementation process of the allocation unit 502 allocating the sub-data to be processed from the data to be processed to each of the multiple computing units according to the amount of data can be found in the relevant content of step 303 of method 300 shown in Figure 3, and will not be described in detail here.

[0247] Optionally, the detailed implementation process of the control unit 503 controlling multiple computing units to process the sub-data corresponding to each computing unit in parallel can be found in step 304 of method 300 shown in Figure 3, and will not be described in detail here.

[0248] Optionally, the control unit 503 is used for:

[0249] Based on the data format processed by each computing unit, the sub-data processed by each computing unit is converted into at least one computing instruction corresponding to each computing unit;

[0250] Each computing unit is controlled to load at least one corresponding computing instruction for data processing.

[0251] Optionally, the detailed implementation process of the control unit 503 converting the sub-data processed by each computing unit into at least one computing instruction corresponding to each computing unit according to the data format processed by each computing unit can be found in the relevant content of step 304 of method 300 shown in Figure 3, and will not be described in detail here.

[0252] Optionally, the detailed implementation process of the control unit 503 controlling each computing unit to load at least one corresponding computing instruction for data processing can be found in step 304 of method 300 shown in Figure 3, and will not be described in detail here.

[0253] Alternatively, multiple computing units may belong to the same processor or to different processors.

[0254] Optionally, each computing unit processes the sub-data corresponding to each computing unit in a processing manner corresponding to the operator.

[0255] Optionally, the multiple calculation units are at least two of the following: fixed-length vector calculation units, variable-length vector calculation units, scalar calculation units, or matrix calculation units.

[0256] Optionally, the determining unit 501 is used for:

[0257] Obtain multiple proportions of sub-data allocated to each computing unit according to the type of the plurality of computing units;

[0258] The overhead of the computing unit with the highest cost when multiple computing units process the data to be processed in parallel after the data to be processed is divided in parallel according to each ratio is taken as the overhead corresponding to each ratio.

[0259] From the various ratios of overhead, the amount of data to be processed by each computing unit is determined by the ratio with the lowest overhead.

[0260] Optionally, the detailed implementation process of determining unit 502 to obtain multiple proportions of sub-data allocated to each computing unit according to the type of the plurality of computing units can be found in the relevant content of step 302 of method 300 shown in Figure 3, and will not be described in detail here.

[0261] Optionally, the determining unit 501 determines the overhead of the computing unit with the largest overhead when multiple computing units process the data to be processed in parallel after the data to be processed is divided in parallel according to each ratio. For the detailed implementation process of the overhead corresponding to each ratio, please refer to the relevant content in step 302 of method 300 shown in Figure 3, which will not be described in detail here.

[0262] Optionally, the detailed implementation process of determining the amount of data to be processed by each computing unit from the overhead corresponding to multiple ratios, with the ratio of the lowest overhead, can be found in step 302 of method 300 shown in Figure 3, and will not be described in detail here.

[0263] In this embodiment, since the amount of data to be processed by each computing unit is determined by the determining unit based on the overhead of each computing unit in processing the corresponding computing instructions, the overhead of using multiple computing units to process the data to be processed is minimized. Thus, the allocation unit allocates the sub-data to be processed from the data to be processed to each computing unit in the multiple computing units based on this amount of data. The multiple computing units process the sub-data corresponding to each computing unit in parallel, so that the overhead required for the multiple computing units to process the data to be processed is minimized, thereby improving the efficiency of data processing.

[0264] Referring to Figure 6, this application embodiment provides a computing device 600. For example, the computing device 600 may be the computing device shown in Figure 1, or the computing device in method 300 shown in Figure 3. The computing device 600 includes at least one processor 601, internal connections 602, and a memory 603.

[0265] The computing device 600 is a hardware-structured device.

[0266] In some embodiments, the computing device 600 can be used to implement the functional modules in the apparatus 500 shown in FIG. 5. For example, those skilled in the art will realize that the determining unit 501, the allocation unit 502, and the control unit 503 in the apparatus 500 shown in FIG. 5 can be implemented by the at least one processor 601. The computing device 600 can also be used to implement the functions of the computing device in any of the above embodiments.

[0267] The processor 601 described above is, for example, a general-purpose central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor, or one or more integrated circuits for implementing the solutions of this application. For example, processor 601 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A PLD may be, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), generic array logic (GAL), or any combination thereof. It can implement or execute various logic blocks, modules, and circuits described in connection with the embodiments of this application. The processor can also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0268] The aforementioned internal connection 602 may include a pathway for transmitting information between the components. Internal connection 602 may be a single board or a bus, etc. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of illustration, only one thick line is used in Figure 6, but this does not indicate that there is only one bus or one type of bus.

[0269] In some embodiments, the computing device 600 may further include at least one communication interface 604. The communication interface 604 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, wireless access networks, or wireless local area networks (WLANs). The communication interface 604 may include a wired communication interface or a wireless communication interface. Specifically, the communication interface 604 may be an Ethernet interface, a Fast Ethernet (FE) interface, a Gigabit Ethernet (GE) interface, an Asynchronous Transfer Mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface may be an optical interface, an electrical interface, or a combination thereof. In this embodiment, the communication interface 604 can be used for the computing device 600 to communicate with other devices.

[0270] The aforementioned memory 603 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory may exist independently and be connected to the processor via a bus. The memory 603 may also be integrated with the processor 601.

[0271] In a specific implementation, as one embodiment, processor 601 may include one or more CPUs, such as CPU0 and CPU1 in FIG. 6. Each of these CPUs may be a single-core processor or a multi-core processor. Here, processor may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0272] In a specific implementation, as one embodiment, the computing device 600 may include multiple processors, such as processor 601 and processor 607 in FIG. 6. Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0273] This application also provides a computer program product including program instructions stored in a computer-readable storage medium. A processor of a computing device reads the program instructions from the computer-readable storage medium and executes the program instructions, causing the computing device to perform a portion of the flow shown in FIG3.

[0274] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium capable of being stored by a computing device, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct a computing device to perform the method provided in any of the above embodiments.

[0275] In this application, the terms "first" and "second," etc., are used to distinguish identical or similar items that have substantially the same function and purpose. It should be understood that there is no logical or temporal dependency between "first" and "second," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first" and "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of various examples, a first calculation instruction can be referred to as a second calculation instruction, and similarly, a second calculation instruction can be referred to as a first calculation instruction. Both the first and second calculation instructions are calculation instructions, and in some cases, they can be separate and distinct calculation instructions.

[0276] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0277] The above description is merely an optional embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A data processing method, characterized in that, The method is applied to a computing device, which includes various types of computing units, and the method includes: Multiple computing units capable of processing the data to be processed are determined based on the operators that process the data to be processed; The amount of data to be processed by each computing unit is determined based on the overhead of each computing unit in processing the corresponding computing instruction, when the overhead of using the multiple computing units to process the data to be processed is minimized. Based on the amount of data, sub-data to be processed is allocated from the data to be processed to each of the plurality of computing units; The multiple computing units process the sub-data corresponding to each computing unit in parallel.

2. The method as described in claim 1, characterized in that, The multiple computing units process the sub-data corresponding to each computing unit in parallel, including: Based on the data format processed by each computing unit, the sub-data processed by each computing unit is converted into at least one computing instruction corresponding to each computing unit; Each computing unit loads at least one corresponding computing instruction to perform data processing.

3. The method as described in claim 1 or 2, characterized in that, The multiple computing units may belong to the same processor or to different processors.

4. The method according to any one of claims 1-3, characterized in that, Each computing unit processes the sub-data corresponding to it in a processing method corresponding to the operator.

5. The method according to any one of claims 1-4, characterized in that, The plurality of calculation units are at least two of the following: fixed-length vector calculation unit, variable-length vector calculation unit, scalar calculation unit, or matrix calculation unit.

6. The method as described in claim 5, characterized in that, The step of determining the amount of data to be processed by each computing unit when the overhead of processing corresponding computing instructions by each of the plurality of computing units is minimized includes: Obtain multiple proportions of sub-data allocated to each computing unit according to the type of the plurality of computing units; The overhead of the computing unit with the largest overhead when the multiple computing units process the data to be processed in parallel after the data to be processed is divided in parallel according to each ratio is determined as the overhead corresponding to each ratio. From the various ratios corresponding to overhead, the amount of data to be processed by each computing unit is determined by the ratio with the lowest overhead.

7. A data processing apparatus, characterized in that, The device is applied to a computing device, which includes multiple computing units of different types, and the device includes a determination unit, an allocation unit, and a control unit. The determining unit is used to determine multiple computing units capable of processing the data to be processed based on the operators that process the data to be processed. The determining unit is further configured to determine the amount of data to be processed by each computing unit when the overhead of each computing unit in processing the corresponding computing instruction is minimized when using the plurality of computing units to process the data to be processed. The allocation unit is configured to allocate the sub-data to be processed from the data to be processed to each of the plurality of computing units according to the amount of data; The control unit is used to control the multiple computing units to process the sub-data corresponding to each computing unit in parallel.

8. The apparatus as claimed in claim 7, characterized in that, The control unit is used for: Based on the data format processed by each computing unit, the sub-data processed by each computing unit is converted into at least one computing instruction corresponding to each computing unit; Each computing unit is controlled to load at least one corresponding computing instruction for data processing.

9. The apparatus as claimed in claim 7 or 8, characterized in that, The multiple computing units may belong to the same processor or to different processors.

10. The apparatus according to any one of claims 7-9, characterized in that, Each computing unit processes the sub-data corresponding to it in a processing method corresponding to the operator.

11. The apparatus according to any one of claims 7-10, characterized in that, The plurality of calculation units are at least two of the following: fixed-length vector calculation unit, variable-length vector calculation unit, scalar calculation unit, or matrix calculation unit.

12. The apparatus as claimed in claim 11, characterized in that, The determining unit is used for: Obtain multiple proportions of sub-data allocated to each computing unit according to the type of the plurality of computing units; The overhead of the computing unit with the largest overhead when the multiple computing units process the data to be processed in parallel after the data to be processed is divided in parallel according to each ratio is determined as the overhead corresponding to each ratio. From the various ratios corresponding to overhead, the amount of data to be processed by each computing unit is determined by the ratio with the lowest overhead.

13. A computing device, characterized in that, The computing device includes a processor and a memory, the memory storing instructions; The processor is configured to execute instructions stored in the memory to cause the computing device to perform the method as described in any one of claims 1-6.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes computer program instructions that, when executed by a computing device, perform the method as described in any one of claims 1-6.

15. A computer program product containing instructions, characterized in that, When the computer program product is executed by a computing device, the computing device performs the method as described in any one of claims 1-6.

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