Read-out circuit for a pinned photo diode and method for converting a light signal into a signal

Abstract

The invention relates to a Read-out circuit (1) comprising: - at least one pixel subcircuit (2) with a photodiode (10) the cathode terminal of which is electrically connected to one terminal of a transmission gate transistor (16), said transmission gate transistor (16) with its other terminal being electrically connected to a floating diffusion capacitance (18) via a circuit readout node (14); - a first read-out subcircuit (4) having an input node (21) electrically connected to an output terminal of a at least one select transistor (19) via at least one pixel node (19a), wherein the input terminal of the select transistor (19) is connected to the output terminal of at least one source follower transistor (20), the gate terminal of which is electrically connected to said circuit readout node (14); and - at least one second read-out subcircuit (6) the input of which is connected to an input terminal of at least one reset transistor (12) via at least one reset node (13), the output terminal of which is connected to said circuit readout node (14), wherein the number of reset transistors (12), reset nodes (13), select transistors (19), pixel nodes (19a), and source follower transistors (20) is equal to the number of pixel subcircuits (2).

Description

[0001] 2024PF01731 1

[0002] READ-OUT CIRCUIT FOR A PINNED PHOTO DIODE AND METHOD FOR CONVERTING A LIGHT SIGNAL INTO A SIGNAL

[0003] DESCRIPTION

[0004] TECHNICAL FIELD

[0005] The invention relates to a read-out circuit for a pinned photodiode . It further relates to a method for converting a light signal into a signal, in particular a digital signal .

[0006] BACKGROUND

[0007] In the field of detection of light, photo diodes are known to the person skilled in the art for converting a light signal into an electrical signal . A photodiode is a semiconductor device . In particular, in ambient light sensors ("ALS") that are broadly used in a multitude of applications in cameras, smartphones, wearables, or other mobile devices, photodiodes are used to generate a photocurrent . This photocurrent is then integrated on a capacitor, which generates a voltage that is proportional to the integral of the incoming light

[0008] It is important to have on one hand side a good linearity of the photodiode itself over its full dynamic range from a very low illumination to a very high illumination and to have a low dark count, meaning electrical output signal if there is no illumination. A low dark count reduces the noise in the signal .

[0009] Typically arrays of PPD' s are arranged in a sensor in order to compensate on one hand for a certain variation within the PPD fabrication process and on the other hand for reducing electrical noise effects .

[0010] Using a pinned photodiode as a sensor for light, the pinned photodiode (PPD) is typically integrated into a so-called pixel subcircuit . This pixel subcircuit comprises the PPD, which is the device sensitive to light . The PPD is reset to2024PF01731 2

[0011] an initial state, in particular by applying a reset voltage . After the reset, the PPD is electrically separated from the first and second read-out subcircuit for accumulating electron charges generated from photons of the received light . The accumulated charges of the PPD are then transferred to a Floating diffusion (FD) capacitance and converted into a voltage .

[0012] The design of such a Pixel subcircuit is typically optimized to make the FD capacitance very small to maximize the conversion gain in terms of voltage per electrons .

[0013] The voltage of the FD capacitance is then propagated to the next stage through a source follower (SF) transistor . This output voltage of the pixel is thus fed into an Analog to Digital converter (ADC) in order to convert the light input signal into a digital output signal .

[0014] In one design of a converter circuit according to the state of the art, the pixel is connected via a sampling and hold module and a buffer to the ADC .

[0015] Standard light sensor ' s photodiodes current is integrated on a capacitor with an integrator ("CTIA") . The integration capacitance is one of the limiting factors for the gain of the read-out circuit . Amplifier properties limit the maximum gain of the read-out circuit as well . An important factor in this system is the capacitance of the photodiode since this limits the maximum gain that can be applied in the CTIA. As long as the photodiode is small enough, the low-light detection level can be improved by either increasing the gain or by increasing the photodiode area .

[0016] However, there are applications where a range above this limit would be desirable . In modern sensor systems, due to increasing necessity to detect ever decreasing light intensities, performance levels are reached where neither of these methods can give the necessary increase in sensitivity anymore . These issues are becoming more severe as the number of photodiodes in the light sensor increases .2024PF01731 3

[0017] Thus, it is an obj ect of the current invention to provide a higher conversion gain for a photodiode and sensor systems comprising a multitude of photodiodes .

[0018] SUMMARY

[0019] According to one aspect of the invention a read-out circuit is proposed, the circuit comprising:

[0020] at least one pixel subcircuit (2 ) with a photodiode ( 10) the cathode terminal of which is electrically connected to one terminal of a transmission gate transistor ( 16) , said transmission gate transistor ( 16) with its other terminal being electrically connected to a floating diffusion capacitance ( 18 ) via a circuit readout node ( 14 ) ;

[0021] a first read-out subcircuit (4 ) having an input node (21 ) electrically connected to an output terminal of at least one select transistor ( 19) via at least one pixel node ( 19a) , wherein the input terminal of the select transistor ( 19) is connected to the output terminal of at least one source follower transistor (20) , the gate terminal of which is electrically connected to said circuit readout node ( 14 ) ; and at least one second read-out subcircuit ( 6) the input of which is connected to an input terminal of at least one reset transistor ( 12 ) via at least one reset node ( 13) , the output terminal of which is connected to said circuit readout node (14 ) ,

[0022] wherein the number of reset transistors ( 12 ) , reset nodes ( 13) , select transistors ( 19) , pixel nodes ( 19a) , and source follower transistors (20) is equal to the number of pixel subcircuits ( 2 ) .

[0023] The advantage of the read-out circuit is that the first and second read-out subcircuit may complement each other or constitute a back-up read-out subcircuit . In particular, the first read-out subcircuit and the second read-out subcircuit may be configured for different sampling ranges, thus for different sampling times and light intensities, in order to extend the maximum gain. In particular, and in one aspect of2024PF01731 4

[0024] the invention, the two read-out subcircuits are provided in a configuration in which they can be combined into a true "hybrid use" in which a parallel use of the two paths is possible .

[0025] Furthermore, this read-out circuit allows the incorporation of a multitude of photodiodes . The select transistor serves to cycle through all the pixels for individual photodiode readouts . The selection of the number and which photodiodes to be read out is possible by separate control signals for the RST signals of individual pixels, which are fed into the read-out circuit via the gate of the reset transistor .

[0026] Accordingly, in one aspect of the invention the inputs of both subcircuits are connected to a common, joint readout node of the pixel subcircuit .

[0027] In one aspect of the invention, the first read-out subcircuit may be a CIS read-out path. In this context and as referred to later, "CIS" in particular shall be understood as CMOS Image sensor, and therefore a "CIS read-out path" shall be understood as a "typical" pixel readout, in which the signal is read out on floating diffusion via an active component, and then amplifying and converting said signal .

[0028] In another aspect of the invention the second read-out subcircuit may be at least one CTIA read-out path. In this context and as referred to later, "CTIA" in particular shall be understood as "Capacitive TransImpedance Amplifier"; a circuit that integrates current (as the incoming signal that is generated in a pinned photo diode) over a capacitor and converts it into a voltage that then can be amplified and converted further . Therefore, a "CTIA read-out path" in more general terms may be understood as an integrator path. In particular, the first read-out subcircuit may be configured for low signals VOUT_PPD as input and the second read-out subcircuit may be configured for high signals VOUT_PPD as input . One or both of the first read-out subcircuit and2024PF01731 5

[0029] second read-out subcircuit may be configured to amplify the voltage signal .

[0030] The advantage of this embodiment is that there are two ranges, which extend the maximum gain. In particular, the first read-out subcircuit and the second read-out subcircuit can be configured to have some overlap . Optionally, there might be an intermediate range of signals VOUT_PPD, where both the first read-out subcircuit and the second read-out subcircuit can be used in parallel for obtaining an amplified output voltage signal .

[0031] In preferred embodiment, the CTIA read-out path comprises at least one CTIA connect transistor, of which the input terminal is connected to the at least one reset node . This embodiment allows the addition of the signal of multiple pixels in the CTIA readout, reducing the noise on that readout . As a result, resolution of individual pixels may be traded for accuracy, as the input from a multitude of photodiodes is being averaged, resulting in higher signal to noise ratio .

[0032] According to an embodiment, the first read-out subcircuit and / or the second read-out subcircuit comprises an analog-to-digital converter (ADC) to convert the signal into a digital signal .

[0033] The input switch and the reset switch might be configured by the same switch. The capacitance might be intrinsic to the PPD.

[0034] The source follower transistor is in particular connected in such a way that an output voltage depends on the light input of the diode .

[0035] The input switch might be any kind of suitable switch known to the skilled person. In particular, the input switch might be configured as transistor .2024PF01731 6

[0036] According to an embodiment, the readout circuit may comprise an additional, reset subcircuit having a reset switch the output of which is connected to the input terminal of the at least one reset transistor, to feed a reset voltage V_RST to the at least one pixel subcircuit . The additional subcircuit might be provided with an input for an output signal of the pixel subcircuit, which might be identical to the output connected to the pixel subcircuit, and an output towards the second subcircuit .

[0037] According to an embodiment, the first read-out subcircuit comprises or is a CMOS, "tpical", image sensor read-out chain, in particular comprising a sample and hold subcircuit . The second read-out subcircuit is optionally provided with an input switch.

[0038] According to an embodiment, the first read-out subcircuit is connected to the source follower (SF) transistor . In this case the output voltage of the SF transistor is the input voltage for the first read-out subcircuit .

[0039] According to an embodiment, the second read-out subcircuit comprises or is a current based read-out chain, in particular comprising an amplifier and an integration capacity. The second read-out subcircuit is optionally provided with an input switch.

[0040] According to an embodiment, the second read-out subcircuit is connected to the pixel subcircuit through the at least one reset transistor . This, in accordance with one aspect considered independently inventive, allows to use the second read-out circuit also to apply the reset voltage to the pixel subcircuit, thus potentially rendering a separate reset subcircuit obsolete . In particular, the second read-out subcircuit may be connected to the connection between the additional subcircuit and the pixel subcircuit . In such a way, it is possible to choose via opening and closing the input switch of the pixel subcircuit, whether to use or not the second read-out subcircuit .2024PF01731 7

[0041] According to one aspect of the invention, a method for converting a light signal into a digital signal is provided, the method comprising:

[0042] - Converting the light signal received at a photodiode into an electrical signal through a pixel subcircuit by generating charges in said photodiode during an integration phase, - skimming packets of the generated charges from said photodiode to a readout node of said photodiode in individual pulses during said integration phase .

[0043] In particular, the invention contemplates to improve the readout operation by transferring charges from the photodiode to its readout node (or components subsequently connected to it) in order to enhance availability of the photodiode for additional generation of charges . This partial transfer of packets of generated charges, during the still ongoing integration phase, shall be referred to by "skimming" .

[0044] In particular, and in one aspect of the present invention which is considered independently inventive, the suggested method may be used in systems in which the photodiode is used in combination with a transmission gate transistor . For the purpose of skimming, in one embodiment of the invention, the transfer gate as given by the transmission gate transistor may be opened partially, thereby transferring part of the charges stored in the photodiode to its readout node (and, preferably, to the floating diffusion ("FD") capacitance connected therewith) . In such partial transfer, all charges below the transfer threshold will be unaffected, and thus skimming will not disturb low-light signal readout . In aspects of the invention, each considered independently inventive, the "skimming voltage" applied to the transfer gate in order to effect said partial opening may be provided constantly during said integration phase, thereby constantly keeping the transfer gate at the skimming voltage during the integration phase, or the skimming voltage may be applied in2024PF01731 8

[0045] the form of pulses, thereby advantageously reducing dark current .

[0046] According to an embodiment, the method further comprises transferring the skimmed packets of charges to a readout path connected to said readout node during said integration phase .

[0047] The skimming pulses in one aspect of the invention may be applied in regular time intervals during said integration phase . In a preferred embodiment, however, a mode of smart timing may be applied wherein time intervals between subsequent skimming pulses are chosen in dependence of a voltage signal detected in a readout path connected to said readout node .

[0048] According to one aspect of the invention a sensor is proposed, the sensor comprising a multitude of photodiodes integrated into read-out circuits as described above .

[0049] BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Exemplary embodiments of the invention are discussed below with reference to the accompanying drawing. Therein,

[0051] FIG. 1 shows a wire diagram of a read-out circuit,

[0052] FIG. 2 shows a signal timing diagram of the embodiment according to FIG. 1 for CIS read-out (FIG. 2a) and for CTIA read-out (FIG. 2b) ,

[0053] FIG. 3 schematically shows a signal diagram for a parallel use of a CIS read-out and a CTIA read-out in the manner of charge skimming,

[0054] FIG. 4 shows a wire diagram of a read-out circuit suitable for charge skimming, and2024PF01731 9

[0055] FIGs . 5-7 each show a signal timing diagram for a parallel use of a CIS read-out and a CTIA read-out in the manner of charge skimming.

[0056] Identical components are provided with the same reference numerals in all figures .

[0057] DETAILED DESCRIPTION

[0058] FIG. 1 shows a wire diagram of a read-out circuit 1 according to an embodiment of the present invention. The circuit 1 comprises a pixel subcircuit 2, a first, "CIS"-type or pixel read-out subcircuit 4 and a second, "CTIA"-type read-out subcircuit 6. The circuit 1, in the embodiment shown, further comprises an optional reset subcircuit 8. The general principle of operation of the circuit 1 is as follows : Light is converted by the pixel subcircuit 2 into an output voltage VOUT_PPD. This output voltage VOUT_PPD can be transferred to the first read-out subcircuit 4 and / or to the second read-out subcircuit 6. The pixel subcircuit 2, upon initiation of a detection or measurement cycle, can be reset by a reset voltage .

[0059] In the embodiment shown in FIG. 1 in the form of a wire diagram, the pixel subcircuit 2 comprises a pinned photodiode ("PPD") 10, which is a device sensitive to light . In a detection or measuring cycle, the PPD 10 first is reset to an initial state, in particular by applying a reset voltage V_RST . For applying the reset voltage V_RST, a reset switch 12 in the form of a reset transistor 12 is provided in the pixel subcircuit 2, which can be switched by applying a reset or reference signal RST to the gate terminal of the reset transistor 12. The input terminal of the reset transistor 12 for supplying the reset voltage V_RST to the pixel subcircuit 2 is connected to a first input node 13, which in the embodiment shown is connected to the (optional) reset subcircuit 8, whereas the output terminal of the reset transistor 12 is connected to a readout node 14 of the pixel circuit 2. The reset subcircuit 8 is configured to have a2024PF01731 10

[0060] reset switch 15, also in the form of a transistor 15, to feed the reset voltage V_RST to the reset input node 13 and thereby to the pixel subcircuit 2. Thus, the reset subcircuit 8 has in principle two switching stages, providing no output voltage as output or the reset voltage V_RST as output .

[0061] In case the output of the reset subcircuit 8 is switched in a way that the output voltage is the reset voltage V_RST, the pixel subcircuit 2 is reset, if the reset transistor 12 is set to open by application of the reset signal RST to the gate terminal of the reset transistor 12. In case the output of the reset subcircuit 8 is switched in a way that its output voltage is set to no output voltage, the pixel subcircuit 2 may be switched to have the input switch 12 open or closed.

[0062] After the reset, when the CIS read-out 4 is used the PPD 10 is electrically separated from the read-out subcircuits 4, 6 to allow for accumulation of electron charges generated from photons of the received light directly inside the PPD 10. The accumulated charges of the PPD 10 are then, via a transmission gate transistor 16 transferred to a Floating Diffusion (FD) capacitance 18 and converted into a voltage . Accordingly, in the example shown the gate transistor 16 is provided for the function of a transfer switch, and one terminal of the gate transistor 16 is electrically connected to the cathode terminal of the photodiode 10, and the other terminal is electrically connected to the circuit readout node 14 which in turn is connected to the Floating Diffusion capacitance 18. A gate terminal of the transfer transistor 16 is configured to receive a transfer signal TRAN in order to switch the transmission gate transistor 16.

[0063] The voltage of the FD capacitance 18 is then propagated to the next stage through a source follower (SF) transistor 20. In the embodiment shown, a gate terminal of the source follower transistor 20, also known as common-drain amplifier, is electrically connected to the readout node 14. A source terminal forms the output of the source follower transistor2024PF01731 11

[0064] 20 and is electrically connected to the input terminal of a select transistor 19 which in case of a multitude of pixel subcircuits 2 allows to select the type and number of photodiode output signals to be transferred to the first read-out subcircuit 4. From the output terminal of the select transistor 19, the signal is transferred to an input node 21 of the first read-out subcircuit 4. This first read-out subcircuit 4 is provided as a CMOS image sensor read-out chain, in the embodiment shown comprising a sample and hold subcircuit 22 or S / H stage 22. The first read-out subcircuit 4 is designed as a "CIS"-type read-out, i . e . a "typical" pixel readout chain as defined above . A drain terminal of the source follower transistor 20 is electrically connected to a further supply terminal 23, which may also provide VDD. In summary, the pixel subcircuit 2 is connected through the SF transistor 20 to the first read-out subcircuit 4 which is configured in particular for low signals VOUT_PPD as input .

[0065] The select transistor 19 serves to cycle through all the pixels for individual photodiode readouts . The selection of the number and which photodiodes to be read out is possible by separate control signals for the RST signals for individual pixels, which are fed into the read-out circuit 1, 1 ' via the gate of the reset transistor 12.

[0066] In aspects of the invention, the design of the pixel subcircuit 2 might be optimized to make the FD capacitance 18 very small to maximize the conversion gain in terms of voltage per electrons .

[0067] If the reset transistor 12 is closed, an output voltage VOUT_PPD of the SF transistor 20 is fed only to the first read-out subcircuit 4. This read-out path is in particular suitable for low light intensities .

[0068] The circuit 1 is further provided with the second read-out subcircuit 6 which is configured for high signals VOUT_PPD as input . This second read-out subcircuit 6 is connected to the reset transistor 12 of the pixel subcircuit 2, in particular2024PF01731 12

[0069] to the input node 13 between the reset transistor 12 and the reset switch 15 of the reset subcircuit 8. The connection to the second read-out subcircuit 6 might start from the reset subcircuit 8 .

[0070] The second read-out subcircuit 6 is provided with an amplifier 24 and an integration capacitor 26 as well as with a further switch 28, which might be configured as an on-off switch. The second read-out subcircuit 6 is designed as a "CTIA"-type read-out, as defined above . Both the first readout subcircuit 4 and the second read-out 6 are in particular connected to an Analog to digital converter (DAC) , which is not shown.

[0071] The CTIA read-out path comprises a CTIA connect transistor 25, of which the input terminal is connected to the reset node 13. This embodiment allows the addition of the signal of multiple pixels (not shown in the current embodiment) in the CTIA readout, reducing the noise on that readout . As a result, resolution of individual pixels may be traded for accuracy, as the input from a multitude of photodiodes 10 is being averaged, resulting in higher signal to noise ratio .

[0072] Thus, in the embodiment shown and in accordance with one aspect of the invention, the read-out circuit 1 provides a pinned photodiode 10 in combination with a CTIA as one of its read-out subcircuits 6.

[0073] In principle and in accordance with aspects of the current invention and of the disclosure of un-published prior German patent application no . DE 10 2024 136 063.1, these elements of the read-out circuit 1 might be used in a combined system allowing for alternative use of the first, CIS read-out subcircuit 4 and the second, CTIA read-out subcircuit 6. In particular, in such combined system, in low-light conditions, the first, CIS read-out path 4 may be used. In this mode, the PPD 10 is operated in a standard pixel PPD, or "4T", configuration, with the integration of incoming light fully2024PF01731 13

[0074] internal within the PPD 10. The signal is then read out via the CIS readout path 4.

[0075] In high-light conditions, however, the read-out circuit 1 may be used in its alternative mode . In this, the gate transistor 16 is constantly active or in "on" state, and consequently the PPD 10 is operated as a diode . In order to minimize dark current, in this mode it is biased at (or close to) 0V. The integration consequently then is effected on the capacitor 26 of the CTIA read-out path 6.

[0076] In both modes of operation of this configuration, multiple pixels or PPDs 10 may be connected to a joint or common readout path in order to maximize the incoming signal and / or minimize noise . In the configuration described above, the read-out paths or read-out subcircuits 4, 6 are provided for alternative modes of operation, i . e . they are completely isolated from each other, and during operation one of them must be selected before integration starts . This is shown schematically in the time diagram of FIG. 2.

[0077] FIG. 2 shows possible signal timing patterns during an integration phase for the first, CIS read-out path 4

[0078] (FIG. 2a) and for the alternative second, CTIA read-out path 6 (FIG. 2b) . It should be noted that the signal timing shown is more of an example and could be varied. Furthermore, the scaling of the time intervals should not be taken as an exact indication. Even further, exposure and frame storage can be global operations, i . e . exposure and frame storage can affect each pixel arrangement of an array of pixels simultaneously.

[0079] FIG. 2, for each branch, shows the timing of the Light Detection, ADC CTIA, ADC CIS, the reset signal RST, the CTIA initiation CTIA_init, the transfer signal TRAN, the CIS capture, the CTIA output CTIA_OUT, and the CIS output CIS_OUT . In particular, these signals can be in an activated state (high state) or in a deactivated state (low state) . Applying or activating the respective signal can mean that the signal is switched to the activated state . Deactivating2024PF01731 14

[0080] the respective signal can mean that the signal is switched to the deactivated state .

[0081] In the system described above, during operation, the read-out mode (CIS or CTIA) is selected before integration is started. Timing in the read-out subcircuits 4, 6 is therefore completely independent from the respective other subcircuit 4, 6. If the CIS read-out subcircuit 4 is selected, the pattern shown in FIG. 2a is followed: Light detection is started with resetting in phase 50, and thereafter integration is started, lasting for phase 52. At step 54, after resetting phase 50 has ended, the gate transistor 16 is switched to "off" state by setting the transfer signal TRAN to "low", thereby putting the PPD 10 in integration mode . Then, towards the end of integration phase 52, in step 56 both reset and CIS capture are initiated by switching the RST and CIS-capture signals . CIS-capture is initiated by a pulse signal 58, and terminated by another pulse signal 60, after capture time has expired. Correspondingly, the transfer signal TRAN at the gate transistor 16 is set to "high", thereby switching the gate transistor 16 to "on", thus allowing for the accumulated charges to be transferred to the floating diffusion capacitance 18. Accordingly, the CIS output CIS_OUT accumulates until the final result level 62 is reached .

[0082] If, on the other hand side, the CTIA read-out subcircuit 6 is selected, the pattern shown in FIG. 2b is followed: Light detection, also, is started with resetting in phase 50, and thereafter integration is started, lasting for phase 52.

[0083] During resetting phase 50, a CTIA initiation signal 64 is provided via the CTIA_init signal . During the entire period, the gate transistor 16 is kept at "on" state by keeping the transfer signal TRAN to "high", thereby putting the PPD 10 in operation as a diode . As a consequence, charges are accumulated on the capacitor 26, until, at the end of integration phase 52 the final result level 66 is reached in the CTIA OUT channel .2024PF01731 15

[0084] This version of a hybrid readout-circuit 1, in accordance with aspects of the invention, has some advantages, namely:

[0085] • the sensitivity in low-light conditions can be significantly improved due to the high conversion gain of the respective "pixel"

[0086] • the capacitance of the diode is likely much smaller than that of a normal diode due to the buried nature of the PPD 10 • dark current will likely be smaller by using the PPD 10 due to the buried nature of the PPD 10.

[0087] In contrast, an important disadvantage of this setup may be seen in that the concept of providing two fully separate readout paths 4, 6 means that there is a certain crossover point at which switching over from one readout 4, 6 to the other is necessary; this will likely lead to jumps in the response curve . Further, in this configuration the PPD 10 is not used as it typically is, when biasing at ~0 V with the transfer gate transistor 16 constantly open.

[0088] In accordance with one aspect, the present invention therefore suggests to improve this concept by providing a truly hybrid read-out circuit 1 ' , by enabling the circuit 1 ' to be used in truly parallel mode of both read-out paths 4, 6. In this aspect of the invention, during integration phase 52, charge skimming is provided by partially opening the gate of the transmission gate transistor 16. As a consequence of partially opening the transfer gate 16, a part of the charges that are stored in the PPD 10 can be transferred to the readout node 14 and from there to the CTIA readout path 6. It is noted that charges below the transfer threshold are unaffected by this operation, and hence skimming will not disturb low-light signal readout .

[0089] FIG. 3 by way of example shows possible signal patterns for the principle of a "skimming" operation, in particular in a parallel use of the CIS read-out path 4 and the CTIA read-out path 6. In this schematic diagram, it shows the timing pattern of the Light Detection, the transfer signal TRAN, the charge storage on the PPD 10, and the FD voltage at the2024PF01731 16

[0090] floating diffusion capacitance 18. During operation, the CTIA readout path 6 is kept in connection with the reset transistor 12 of the pixel subcircuit 2. Further, the input reference of the CTIA is set to a relatively high voltage ( In particular higher than the "VPIN" of the PPD10) , thereby allowing the CTIA to effectively act as the reset voltage to the pixel subcircuit 2 .

[0091] As can be seen in FIG. 3, comparably to the use mode for the CIS read-out subcircuit 4 explained above, at step 54, after resetting phase 50 has ended, the gate transistor 16 is switched to "off" state by setting the transfer signal TRAN to "low", thereby putting the PPD 10 in operation in standard "4T" configuration. Consequently, PPD charge storage starts to increase continuously as integration proceeds . In pulses 70, however, the transmission gate transistor 16 is partially opened by setting the transfer signal TRAN to a partial, "SKIM" value or skim level 72. As a consequence, charges above the transfer threshold will be transferred from the PPD 10 to the readout node 14 and from there to the floating diffusion capacitance 18 ("FD") . Accordingly, as a consequence of each pulse 70, the PPD charge storage decreases slightly, and correspondingly the FD voltage at the floating diffusion capacitance 18 increases in accordance with the accumulation of charges on the floating diffusion capacitance 18, thereby manifesting the intended "skimming" of charges .

[0092] It is noted that in the summary of the skimming operation given above, the skimmed charges are assumed to be left on the FD node 18 and accumulated there . In actual applications and in a preferred embodiment, however, during the skimming operation the CTIA readout path 6 should be connected, thereby draining the charges from the floating diffusion capacitance 18

[0093] Then, again similarly to the use mode for the CIS read-out subcircuit 4 explained above, towards the end of integration phase 52, in step 56 both reset and CIS capture are initiated2024PF01731 17

[0094] by switching the RST and CIS-capture signals .

[0095] Correspondingly, the transfer signal TRAN at the gate transistor 16 is set to "high", thereby switching the gate transistor 16 fully to "on", thus allowing for the remaining accumulated charges in the way of a "final transfer" to be transferred to the floating diffusion capacitance 18.

[0096] Accordingly, the FD voltage at the floating diffusion capacitance 18 increases to its full, final value .

[0097] FIG. 4 shows a wire diagram of a modified read-out circuit 1 ' according to an embodiment of the present invention, which is particularly suitable for the charge skimming concept described above . In this embodiment, the second, CTIA readout subcircuit 6 also is connected to the reset input node 13 of the pixel subcircuit 2 . In contrast to the embodiment shown before, in the read-out circuit 1 ' an input terminal 74 connected with the amplifier 24 of the CTIA read-out path 6 is provided in order to deliver an input reference voltage V_REFPIX to the amplifier 24 . The input reference voltage at input terminal 74 of the CTIA may then be set to a comparatively high voltage (higher than the PPD pinning voltage "VPIN") , thereby allowing the CTIA to effectively act as the reset voltage to the pixel subcircuit 2. Thus, reset of the pixel subcircuit 2 in principle might be effected via the CTIA readout path 6, and a separate reset subcircuit 8 may not be necessary.

[0098] Furthermore, the embodiment of FIG. 4 comprises a multitude of pixel subcircuits 2. More precisely, in this specific embodiment, four pixel subcircuits 2 are shown. The pixel subcircuits 2 are connected via four select transistors 19 and corresponding pixel nodes 19a to the input node 21 of the first read-out subcircuit 4. The select transistor 19 serves to cycle through all the pixels for individual photodiode 10 readouts . The selection of the number and which photodiodes 10 to be read out is possible by separate control signals for the RST signals for individual pixels, which are fed into the read-out circuit 1 ' via the gate of the reset transistor 12.2024PF01731 18

[0099] In operation, in accordance with one aspect of the invention, the reset transistor 12 during integration may be kept continuously open such that the pixel subcircuit 2 is permanently connected to the CTIA readout path 6, thereby allowing for a readout of skimmed charges through the CTIA or integrator read out path 6. Further, as mentioned before, the "TRAN" biasing of the transmission gate transistor 16 should be set to a partial, "SKIM" value 72 during integration to "skim" the charges . This, in accordance with aspects of the invention can be achieved in a variety of ways . For example, a constant low voltage can be set for TRAN that still allows some charges to escape from the PPD 10 to the floating diffusion capacitance 18 of the pixel, thereby allowing these charges to flow to the CTIA readout path 6. Alternatively, the "TRAN" biasing can be provided in the form of regular pulses 70, thus regularly pulsing "TRAN" between "off" and low voltage, which will result in transferring of charge packets to the CTIA in bursts .

[0100] Since TRAN is "off" most of the time, the dark current will be low. At the end of integration, "TRAN" may be pulsed fully "on" to transfer all remaining charges . This can then be read through the CIS or CTIA path 4, 6.

[0101] FIGs . 5 - 7 each show preferred signal timing patterns for a parallel use of the CIS read-out path 4 and the CTIA read-out path 6 in accordance with aspects of the invention. In a preferred embodiment, the timing pattern of which is shown in FIG. 5, and corresponding to the one already schematically shown in FIG. 3, the CTIA readout path 6 is used by periodically pulsing (at steps 70) the input TRAN biasing of the transmission gate transistor 16 gate to an intermediate "SKIM" level to "skim" charges from the PPD 10. At the end of integration phase 52, in step 56, reset, CTIA deactivation, and CIS capture are initiated by switching the RST, CTIA-connect and CIS-capture signals . Correspondingly, the transfer signal TRAN at the gate transistor 16 is set to "high" or pulsed fully, thereby switching the gate transistor2024PF01731 19

[0102] 16 fully to "on", thus allowing for the remaining accumulated charges in the way of a "final transfer" to be transferred to the floating diffusion capacitance 18. Accordingly, the FD voltage at the floating diffusion capacitance 18 lowers to its final value . This last charge packet can then be read out either via the CTIA path 6 or, as shown on FIG. 5, via the more sensitive CIS path 4.

[0103] In accordance with one aspect of the invention, the intermediate readouts of the CTIA path 6 can help determine which path 4, 6 is the most appropriate to use for the final readout .

[0104] In the alternative timing pattern as shown in FIG. 6, in accordance with one aspect of the invention, in step 56, instead of deactivating the CTIA readout path 6 by switching the CTIA_connect signal, the input reference V_REFPIX of the CTIA path 6 may be set to a yet increased voltage in order to increase the maximum voltage swing on the floating diffusion capacitance 18, which increases the maximum amount of charges that can be accumulated on the FD 18 and delivered to the CIS readout path 4. This configuration might even be operated without providing switches for the CTIA connection; i . e . the switch 15 and / or one of the reset transistor 12 or the switch in the CTIA readout path 6 might not be necessary.

[0105] In yet another embodiment in accordance with an aspect of the invention, the timing pattern of which is shown in FIG. 7, the read-out may be effected by using the CTIA readout path 6 alone, without involving the CIS readout path 4. This embodiment more or less corresponds to the one also shown in FIG. 3.

[0106] In one preferred aspect of the invention, which is considered independently inventive, the circuit 1 may be configured to allow for "smart timing" of the various steps during integration. In particular, as described, during the integration the collected (light generated) charges may be pushed ("skimmed") to the CTIA readout path 6 in short bursts2024PF01731 20

[0107] when the transfer gate transistor 16 (via the TRAN signal) is pulsed. Monitoring the voltage swing on the CTIA output then can be used to dynamically change the time between TRAN pulses in order to optimize readout noise and dark current . The time between TRAN pulses can also be used to do a (partial) reset of the CTIA in order to "fold" the output conversion such that the analog output swing can be used in an optimal region; this may also allow to decrease the number of gain settings that are now necessary to cover the entire dynamic range .

[0108] The improved hybrid readout concept in accordance with aspects of the invention has significant advantages in comparison with existing systems . In particular, the PPD 10 may be used in conditions, regarding, i . e . , timing and / or biasing, that typically are met in CIS pixels . Its performance regarding dark currents is very close to typical (very) low dark currents seen in PPDs in general . Even though dark current might increase when the transfer gate transistor 16 is not fully off, short skimming pulses will help to minimize the time of higher dark current significantly. As a particular benefit, with the concept as described above, there is no need to select the readout path 4, 6 before the integration starts . Thus, the optimal readout can be selected, based on intermediate output signals that are detected via the CTIA readout 6.

[0109] Further, if the illumination is small, the skimming operation will result in no signal in the CTIA readout path 6, and consequently the full signal can then be read through the high gain CIS readout path 4. Also, intermediate conversions on the CTIA output can still give info on the light level, even if the output saturates at the end. Output "folding" is made easier since there are discrete timeslots where the signal is not changing. Possible circuit complexity reductions are feasible because some gain settings can likely be removed.2024PF01731 21

[0110] LIST OF REFERENCE NUMERALS

[0111] 1 , 1 ' circuit

[0112] 2 pixel subcircuit

[0113] 4 first read-out subcircuit

[0114] 6 second read-out subcircuit

[0115] 8 reset subcircuit

[0116] 10 photodiode

[0117] 12 reset transistor

[0118] 13 reset input node

[0119] 14 readout node

[0120] 15 reset switch

[0121] 16 transmission gate transistor 18 floating diffusion capacitance 19 select transistor

[0122] 19a pixel node

[0123] 20 source follower transistor

[0124] 21 input node

[0125] 22 sample and hold subcircuit

[0126] 23 supply terminal

[0127] 24 amp 1 i f i e r

[0128] 25 CTIA connect transistor

[0129] 26 integration capacitor

[0130] 28 switch

[0131] 50, 52 phase

[0132] 54, 56 step

[0133] 58, 60 pulse signal

[0134] 62, 66 final result level

[0135] 64 CTIA initiation signal

[0136] 70 step

[0137] 72 SKIM level

[0138] 74 input terminal

Claims

2024PF01731 22CLAIMS1 . Read-out circuit ( 1 , 1 " ) comprising :at least one pixel subcircuit ( 2 ) with a photodiode ( 10 ) the cathode terminal of which is electrically connected to one terminal of a transmission gate transistor ( 16 ) , said transmission gate transistor ( 16 ) with its other terminal being electrically connected to a floating di f fusion capacitance ( 18 ) via a circuit readout node ( 14 ) ;a first read-out subcircuit ( 4 ) having an input node ( 21 ) electrically connected to an output terminal of at least one select transistor ( 19 ) via at least one pixel node ( 19a ) , wherein the input terminal of the select transistor ( 19 ) is connected to the output terminal of at least one source follower transistor ( 20 ) , the gate terminal of which is electrically connected to said circuit readout node ( 14 ) ; and at least one second read-out subcircuit ( 6 ) the input of which is connected to an input terminal of at least one reset transistor ( 12 ) via at least one reset node ( 13 ) , the output terminal of which is connected to said circuit readout node ( 14 ) ,wherein the number of reset transistors ( 12 ) , reset nodes ( 13 ) , select transistors ( 19 ) , pixel nodes ( 19a ) , and source follower transistors ( 20 ) is equal to the number of pixel subcircuits ( 2 ) .2 . The read-out circuit ( 1 , 1 " ) of claim 1 , wherein said first read-out subcircuit ( 4 ) is a CIS read-out path ( 4 ) .3 . The read-out circuit ( 1 , 1 " ) of claim 1 or 2 ,wherein the first read-out subcircuit ( 4 ) is configured for low signals as input , and / orwherein the first read-out subcircuit ( 4 ) comprises an analog-to-digital converter (ADC ) to convert the signal into a digital signal , and / orwherein the first read-out subcircuit ( 4 ) is configured to ampli fy the voltage signal .2024PF01731 234. The read-out circuit ( 1, 1" ) according to one of the preceding claims, wherein said second read-out subcircuit ( 6) is a CTIA read-out path ( 6) .

5. The read-out circuit ( 1, 1" ) according to claim 4, the CTIA read-out path ( 6) comprising at least one CTIA connect transistor (25) , of which the input terminal is connected to the at least one reset node ( 13) .

6. The read-out circuit ( 1, 1" ) according to one of the preceding claims,wherein the second read-out subcircuit ( 6) is configured for high signals VOUT_PPD as input, and / orwherein the second read-out subcircuit ( 6) comprises an analog-to-digital converter (ADC) to convert the signal into a digital signal, and / orwherein the second read-out subcircuit ( 6) is configured to amplify the voltage signal .

7. The read-out circuit ( 1, 1" ) according to one of the preceding claims, further comprising a reset subcircuit ( 8 ) having a reset switch ( 15) the output of which is connected to the input terminal of the reset transistor ( 12 ) , to feed a reset voltage V_RST to the pixel subcircuit (2 ) .

8. Read-out circuit ( 1, 1" ) according to one of the proceeding claims, wherein the first read-out subcircuit (4 ) comprises or is a CMOS image sensor read-out chain, in particular comprising a sample and hold subcircuit (22 ) .

9. Read-out circuit ( 1, 1" ) according to one of the proceeding claims, wherein the second read-out subcircuit ( 6) comprises or is a current based read-out chain, in particular comprising an amplifier (24 ) and an integration capacity (26) .

10. Method for converting a light signal into a digital signal, in particular in a read-out circuit ( 1, 1" ) according to one of the preceding claims, the method comprising:2024PF01731 24Converting the light signal received at a photodiode (10) into an electrical signal through a pixel subcircuit (2 ) by generating charges in said photodiode ( 10) during an integration phase (52 ) ,skimming packets of the generated charges from said photodiode ( 10) to a readout node ( 14 ) of said photodiode (10) in individual pulses (58, 60) during said integration phase ( 52 ) .

11. The method of claim 10, further comprising: transferring the skimmed packets of charges to a readout path (4, 6) connected to said readout node ( 14 ) during said integration phase ( 52 ) .

12. The method of claim 10 or 11, further comprising using a transmission gate transistor ( 16) associated with said photodiode ( 10) to execute skimming of said packages .

13. The method of claim 12, wherein said transmission gate transistor ( 16) during skimming is partially opened to selectively transfer charges above a transfer threshold and stored in the photodiode ( 10) to said readout node ( 14 ) .

14. The method of any one of the preceding claims, in which said skimming pulses (58, 60) are applied in regular time intervals during said integration phase (52 ) .

15. The method of any one of the preceding claims, wherein time intervals between subsequent skimming pulses (58, 60) are chosen in dependence of a voltage signal detected in a readout path (4, 6) connected to said readout node ( 14 ) .

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