Method for manufacturing a microelectronic device with increased breakdown voltage

Abstract

The invention relates to a method for manufacturing a microelectronic device (1). A donor stack (100) comprising a first III-N layer (300) having a first p- or n-doping is provided. Ion implantation is carried out in the donor stack to form an embrittlement zone (150), and then a transfer to a receiver substrate (20) is carried out. Annealing is subsequently carried out, causing cleavage at the embrittlement zone, while preserving on the receiver substrate a transferred portion (110) comprising part of the first layer, and then growth of a second III-N layer (420) having a second doping opposing the first doping is carried out. The final assembly comprises a field locking layer (30) partially formed by the transferred portion, and a layer of interest (40) at least partially formed by the second layer (420), together forming a PN junction.

Description

[0001] Method for manufacturing a microelectronic device with increased breakdown voltage

[0002] TECHNICAL FIELD OF THE INVENTION

[0003] The present invention relates to the field of microelectronic devices, in particular transistors based on an III-N material such as GaN. It finds, for example, a particularly advantageous application in the field of power electronics.

[0004] STATE OF THE ART

[0005] CO2 emission reduction targets and the massive electrification of transportation necessitate highly energy-efficient components for power conversion. Gallium Nitride (GaN) transistors, particularly lateral HEMTs (High Electron Mobility Transistors), are currently prime candidates for these applications. A prior art HEMT T is illustrated in Figure 1. It features a silicon substrate 20', an n-doped layer 40' (typically including buffer layers), and a barrier layer 50' forming a heterojunction with the n-doped layer 40'. This heterojunction creates a potential well in which electrons are confined, forming a two-dimensional electron gas 45' that can be referred to as a 45' channel.The lateral HEMT transistor T according to the prior art further includes a 1T source, a 12' drain and a 13' gate for driving the transistor.

[0006] GaN-based components, such as GaN-based HEMT transistors, can be fabricated on various substrate types. However, most have significant drawbacks. For example, silicon carbide (SiC) substrates are expensive and currently available industrially with a diameter limited to 6 inches (approximately 15 cm), possibly 8 inches (approximately 20 cm), which severely limits their cost-effectiveness. Sapphire substrates, on the other hand, are not only more expensive than silicon but also exhibit high thermal resistance, resulting in a degradation of the transistor's intrinsic electrical performance due to poor heat dissipation.

[0007] Silicon substrate is currently the most commonly used by manufacturers because it is inexpensive and available in large sizes.

[0008] However, the use of GaN-based HEMTs on silicon is currently limited to approximately 650 volts due to the limited GaN thickness allowed on the 20' silicon substrate, which cannot withstand voltages typically exceeding 650 V. During operation of the T-transistor, the 20' silicon substrate experiences high electric fields and eventually fails beyond a certain applied voltage level. This drawback is a significant limitation in the intended applications.

[0009] Several options have been considered to increase the voltage withstand capability of GaN-on-silicon HEMT transistors, and more generally of GaN-on-silicon microelectronic devices.

[0010] Increasing the thickness of the buffer layers has been considered. A breakdown voltage of approximately 800 V was obtained with a buffer layer 7 to 8 pm thick and composed of dielectric layers and carbon-doped GaN, which behaves as a deep acceptor (see M. Borga et al, Buffer breakdown in GaN-on-Si HEMTs: A comprehensive study based on a sequential growth experiment, Microelectronics Reliability 100-101 (2019) 113461).

[0011] Another solution considered is to replace GaN with an alloy (in a continuous layer or superlattice) with a higher bandgap energy such as AIGaN. This solution has made it possible to achieve a breakdown voltage of approximately 1200 V for thicknesses of approximately 5 to 6 pm (see R. Kabouche et al, Low on-resistance and low trapping effects in 1200 V superlattice GaN-on-silicon heterostructures, Phys. Status Solidi A, Appl. Mat. Sci. 217, 7 (2020) 1900687).

[0012] Another approach being pursued is the insertion of silicon-doped (donor) - carbon-doped (acceptor) GaN superlattices. This solution has made it possible to obtain voltage withstand rates between 800 V and 1000 V for buffer layers approximately 5 pm thick (see A. Dadgaret et al., High resistive buffer layers by Fermi level engineering, J. Appl. Phys. 134, 025701 (2023)).

[0013] However, all these approaches require very high buffer layer thicknesses, which complicate heteroepitaxy due to the significant difficulties in controlling thermoelastic stresses caused by the large differences in coefficients of thermal expansion between 11-N materials and silicon. Indeed, these stresses induce curvature and risk of substrate fracture, as well as risks of cracking and delamination of the epitaxially coated materials. These defects severely impact the quality and robustness of the components, which is incompatible with industrial requirements.

[0014] None of the solutions described above are therefore satisfactory.

[0015] An objective of the present invention is to provide a solution to the breakdown problem in silicon substrates, preferably one that induces little or no additional mechanical stress. Preferably, the solution will allow for an increase in the breakdown voltage compared to prior art devices, and / or a reduction in the vertical footprint of the device at a constant breakdown voltage. Advantageously, the solution will enable the fabrication of components, particularly HEMT transistors, capable of withstanding voltages exceeding 650 V.

[0016] SUMMARY OF THE INVENTION

[0017] To achieve this objective, a first aspect of the invention relates to a method for manufacturing a microelectronic device comprising:

[0018] a. a supply of a donor stack comprising a layer, called the first layer, based on a first lll-N material and having a doping of a first type among a p-type doping and an n-type doping,

[0019] b. an ionic implantation in the donor stack so as to form a zone of embrittlement,

[0020] c. a transfer of the donor stack onto a substrate called the recipient substrate,

[0021] d. a thermal annealing process configured to cause cleavage of the donor stack at the embrittlement zone, while retaining on the receiving substrate a portion of the donor stack called the carried-over portion, the carried-over portion comprising at least part of the first layer,

[0022] e. a growth of a layer, called second layer, based on a second lll-N material and having a doping of a second type among a p-type doping and an n-type doping, opposite to the first type, on the reported portion.

[0023] The assembly formed by the carried portion and the second layer thus includes a so-called field blocking layer, at least partly formed by the carried portion, and a so-called interest layer at least partly formed by the second layer, the field blocking layer and the interest layer together forming a PN junction.

[0024] A second aspect of the invention relates to a microelectronic device comprising, stacked according to a so-called stacking direction:

[0025] f. a receiving substrate,

[0026] g. a layer, called the layer of interest, based on a second 111-N material and having a doping of a second type among a p-type doping and an n-type doping. The device further comprises, between the receiving substrate and the layer of interest, a layer, called the field blocking layer, based on a first 111-N material and having a doping of a first type among a p-type doping and an n-type doping, opposite to the second type.

[0027] The field blocking layer and the layer of interest together form a PN junction.

[0028] The field blocking layer also has, depending on the stacking direction, a thickness eao, with eao^l pm.

[0029] In prior art devices, there is a juxtaposition of opposing dopings at the interface between the silicon 20' substrate, commonly of type p, and the n-doped layer 40'. As a result, the silicon 20' substrate is subjected to a very strong electric field.

[0030] In the device according to the present invention, the presence of the field-blocking layer, typically p-doped, prevents such a juxtaposition of opposing dopings at the interface between the silicon substrate and the layer of interest, typically n-doped. In the present invention, a PN junction is introduced between the field-blocking layer and the layer of interest. This PN junction is located away from the front-side components of the device. In particular, in the typical case of a side-mounted HEMT transistor, the PN junction is located away from the transistor channel.

[0031] Thanks to the introduction of the field blocking layer and therefore of the PN junction between the blocking layer and the layer of interest, the area of ​​the device which is subjected to the strongest electric fields is no longer, as in the prior art, at the interface between the lll-N material and the silicon substrate, but in the field blocking layer, which is based on an lll-N material.

[0032] However, III-N materials, and in particular GaN, exhibit a large band gap (also called wide band gap, typically on the order of 3 to 7 eV) and a much higher critical field than silicon (3.3 MV / cm versus 0.3 MV / cm). Introducing the field-blocking layer so that the strong electric fields are located there rather than in the silicon substrate thus significantly increases the voltage withstand capacity of the device. For a layer of interest with a thickness of approximately 4 pm, a field-blocking layer thickness of 25 nm, and a field-blocking layer doping level of 5 × 10⁻¹⁰ 18 cm -3 The simulations show that the breakdown voltage is increased from 700V to 1400V.

[0033] Thus, the PN junction formed by the field-blocking layer and the layer of interest serves to shift the maximum electric fields from the silicon substrate (prior art) to the field-blocking layer. Preferably, the PN junction has only this function.

[0034] The present invention thus makes it possible to improve the performance of microelectronic devices. The present invention can be used to increase the voltage withstand capacity of a device or, for a given breakdown voltage, to reduce the overall thickness of the device. Indeed, unlike prior art solutions, the present invention does not necessarily affect the overall thickness of the n-doped layer to limit breakdown in silicon, but rather the voltage withstand capacity of the newly created junction through the introduction of the blocking layer. This makes it possible to reduce or even avoid the problems due to thermoelastic stresses mentioned in the introduction and facilitates stress management during the heteroepitaxy of the different layers.

[0035] The present invention can also be exploited to increase the thickness of the layer of interest while reducing its doping, typically carbon doping, at constant voltage. This is advantageous because carbon induces charge trapping effects that impact mobility in the HEMT transistor channel. This results in an increase in the transistor's on-state resistance, leading to increased heat losses, which negatively impacts its performance. Reducing the doping level can therefore improve the performance of the fabricated device.

[0036] Furthermore, the present invention makes it possible to delay or even avoid catastrophic breakdown in silicon, which leads to the destruction of components. On the contrary, the avalanche phenomenon of the PN junction formed should, to some extent, play a protective role by managing avalanche breakdown, a feature lacking in current devices.

[0037] Furthermore, the insertion of the blocking layer allows for the depletion of a portion of the layer of interest in contact with the blocking layer through electrostatic effects (PN junction depletion zone). Leakage in the layer of interest is significantly reduced, without resorting to carbon doping, which severely impairs the transistor's dynamic performance.

[0038] This invention significantly improves the two most important performance characteristics of a power GaN transistor, namely, resistance (R on) dynamics and breakdown voltage.

[0039] The present invention stands out significantly from the solutions explored in recent years to improve the voltage withstand of lateral HEMT transistors, which consist of increasing the total thickness of the device.

[0040] It should also be noted that by eliminating the numerous and thick buffer layers used in the prior art, the growth time and manufacturing costs of the device are reduced.

[0041] The present invention, and particularly the process according to the first aspect of the invention, makes clever use of the Smart Cut® process to enable the manufacture of a microelectronic device with improved performance as described above.

[0042] The use of Smart Cut® allows for only one type of epitaxy to be performed once the transferred portion has been deposited onto the receiving substrate. Indeed, after the transfer, only the second layer, which is either n-type or p-type, needs to be formed. In the case of a first p-doped layer, any risk of contamination of the epitaxial reactor by the magnesium (Mg) dopants required for p-type doping is limited or even eliminated.

[0043] The use of Smart Cut® also improves the thermal resistance of the component. Indeed, in a manufacturing process not employing Smart Cut®, a nucleation layer is necessarily present between the substrate and the layer of interest (in the present invention, between the substrate and the field-blocking layer). This nucleation layer is typically of poor crystalline quality because it absorbs dislocations resulting from lattice mismatch between the silicon of the substrate and the III-N material of the layer of interest or the field-blocking layer in the context of the present invention. Due to this poor thermal quality, the nucleation layer exhibits high thermal resistance, which impedes heat transfer to the heat dissipation element typically located on the back side of the substrate. Thanks to the Smart Cut® process, which eliminates the need for a nucleation layer, this problem is overcome.

[0044] The process according to the present invention, in addition to enabling the manufacture of a device with improved performance, is therefore well suited to industrialization.

[0045] BRIEF DESCRIPTION OF THE FIGURES

[0046] The aims, objects, features and advantages of the invention will become clearer from the detailed description of an embodiment thereof, which is illustrated by the following accompanying drawings in which:

[0047] Figure 1 represents a lateral HEMT transistor according to the prior art.

[0048] Figure 2 represents a lateral HEMT transistor according to the invention, including in particular a field blocking layer between the substrate and the layer of interest.

[0049] Figures 3A to 3F illustrate the steps of a first embodiment of the process according to the invention.

[0050] Figures 4A to 4F illustrate the steps of a second embodiment of the process according to the invention.

[0051] Figure 5A shows the band diagram of a transistor according to the prior art. Figure 5B shows the band diagram of a transistor according to the invention. Figure 6 illustrates the variation of the breakdown voltage as a function of the thickness of the field-blocking layer for different doping levels of the latter, in a transistor according to the present invention.

[0052] Figure 7 illustrates the variation of the breakdown voltage as a function of the doping of the field blocking layer for a fixed thickness of the latter.

[0053] Figure 8 illustrates the variation of the breakdown voltage as a function of the thickness of the layer of interest, for a prior art transistor and for a transistor according to the invention. Figure 8 also illustrates the value of the breakdown voltage improvement factor. The drawings are given by way of example and are not limiting of the invention. They constitute schematic representations of principle intended to facilitate understanding of the invention and are not necessarily to scale with practical applications. In particular, the dimensions are not representative of reality.

[0054] DETAILED DESCRIPTION

[0055] Before proceeding with a detailed review of embodiments of the invention, optional features that may be used in combination or alternatively are listed below:

[0056] According to one embodiment, the process further comprises:

[0057] h. the formation, on an upper face of the layer of interest opposite the field-blocking layer, of a semiconductor-based layer, called a barrier layer, so as to form a heterojunction between the layer of interest and the barrier layer, and

[0058] i. the formation of a grid electrode on the barrier layer,

[0059] j. a formation of a first electrically conductive motif forming a source and a second electrically conductive motif forming a drain, the source and the drain being formed in contact with the barrier layer and on either side of the gate electrode. According to a first embodiment, the ion implantation is configured so that the embrittlement zone is in the first layer, the growth of the second layer is from the first layer, the field blocking layer is formed by the first layer and the layer of interest is formed by the second layer.

[0060] Preferably, in the first embodiment, the transferred portion of the donor stack is entirely formed by the first layer.

[0061] Preferably, in the first embodiment, the layer of interest is formed solely by the second layer.

[0062] In one example, the second layer is in contact with the front face of the first layer.

[0063] Preferably, the first layer has p-type doping and the second layer has n-type doping.

[0064] According to a first embodiment, the donor stack further comprises a layer, called the cleaved layer, having a doping of the second type, the ion implantation being configured so that the embrittlement zone is in the cleaved layer, the transfer of the donor stack onto the receiving substrate being done by a top face of the first layer opposite the cleaved layer, the transferred portion further comprising a portion of the cleaved layer called the primer layer, the growth of the second layer being done from the primer layer, the field blocking layer being formed by the first layer and the layer of interest being formed, preferably only, by the primer layer and the second layer.

[0065] In the preferred case of a blocking layer based on a p-doped lll-N material and a layer of interest based on an n-doped lll-N material, this embodiment is particularly advantageous because the formation of the second layer (n-doped) takes place on a primer layer that is also n-doped. This avoids having to grow an n-doped lll-N material on a p-doped layer, a complex process due to the disadvantageous passivation of the surface.

[0066] Conversely, the growth of a p-doped lll-N layer on an n-doped lll-N layer is perfectly controlled. The Mg dopant in the p-doped layer exhibits high mobility, and very good integration is observed in the p-doped lll-N layers. Mg also tends to diffuse into the n-doped lll-N material, but this can be beneficial for the PN junction.

[0067] According to a first option of the second embodiment, the donor stack supply and ion implantation steps include the following steps: k. supplying the cleaved layer, l. ion implantation so as to form the embrittlement zone in the cleaved layer, m. forming the first layer on the cleaved layer.

[0068] According to a second option of the second embodiment, the ion implantation so as to form the weakening zone in the cleaved layer is carried out through the first layer.

[0069] Preferably, the transfer of the donor stack onto the recipient substrate is achieved by molecular bonding.

[0070] According to an example of the device according to the second aspect of the invention, the layer of interest is entirely formed of the second material lll-N and the field blocking layer and the layer of interest are in contact.

[0071] According to one embodiment, the device further comprises, on an upper face of the layer of interest opposite the field blocking layer:

[0072] n. a layer based on a semiconductor, called a barrier layer, forming a heterojunction with the layer of interest,

[0073] o. a grid electrode extending over the barrier layer,

[0074] p. a first electrically conductive motif forming a source,

[0075] q. a second electrically conductive motif forming a drain, the source and the drain being in contact with the barrier layer and on either side of the gate electrode.

[0076] According to an example, the first lll-N material and the second lll-N material are identical, and are for example GaN.

[0077] Advantageously, thermal annealing is further configured to cause stress relaxation in the transferred portion.

[0078] It is specified that, within the framework of the present invention, the terms "on", "overcomes", "covers", "underlying", "opposite" and their equivalents do not necessarily mean "in contact with". Thus, for example, the depositing, transferring, gluing, assembling or applying a first layer on a second layer does not necessarily mean that the two layers are directly in contact with each other, but means that the first layer at least partially covers the second layer by being either directly in contact with it or by being separated from it by at least one other layer or at least one other element.

[0079] A layer can also be composed of several sub-layers of the same material or of different materials.

[0080] A substrate, layer, or device "based" on a material M is understood to mean a substrate, layer, or device comprising only that material M or that material M and possibly other materials, for example alloying elements, impurities, or dopant elements.

[0081] In the present invention, types of doping will be indicated. These doping methods are non-limiting examples.

[0082] Conventionally, a doping designation denoted p+ means that it is a p-type doping (doping with positive charges) where the concentration of the doping agent is greater than or equal to 1 atom of the doping agent per 1000 atoms of the semiconductor, and preferably per 10 to 100 atoms of the semiconductor layer material. Similarly, n+ means that it is an n-type doping (doping with negative charges) where the concentration of the doping agent is greater than or equal to 1 atom of the doping agent per 1000 atoms of the semiconductor, and preferably per 10 to 100 atoms of the semiconductor layer material.

[0083] In this patent application, a doping denoted p encompasses all doping with positively charged carriers, regardless of the doping concentration. Thus, a p doping includes both p+ doping concentrations and p doping concentrations lower than p+ doping. Similarly, a n doping denoted n encompasses all doping with negatively charged carriers, regardless of the doping concentration. Thus, an n doping includes both n+ doping concentrations and n doping concentrations lower than n+ doping.

[0084] A coordinate system, preferably orthonormal, comprising the X, Y, Z axes is shown in figures 1 and 2. The Z direction can be designated as the "stacking direction".

[0085] In this patent application, the terms thickness for a layer and height for a structure or device will be preferred. Height is measured perpendicular to the longitudinal XY plane. Thickness is measured in a direction normal to the principal plane of extension of the layer. Thus, a layer typically has a thickness along the Z-axis when it extends primarily along the longitudinal XY plane, and a projecting element, for example, an insulation trench, has a height along the Z-axis. The relative terms "on," "under," "above," "below," and "below" preferentially refer to positions measured along the Z-axis.

[0086] The terms "approximately", "about", "in the order of" mean "within 10%, preferably within 5%".

[0087] A microelectronic device is defined as any type of device made using microelectronic means. These devices include, in addition to purely electronic devices, micromechanical or electromechanical devices (MEMS, NEMS, etc.) as well as optical or optoelectronic devices (MOEMS, etc.). The device according to the invention will now be described with reference to Figure 2. The microelectronic device 1 comprises, at a minimum, the following components stacked along the stacking direction Z:

[0088] r. a receiving substrate 20,

[0089] s. a field blocking layer 30, also designated as blocking layer 30, t. a layer of interest 40.

[0090] According to a preferred embodiment, the microelectronic device 1 can be a transistor, preferably a side-mounted HEMT transistor. In the latter case, the microelectronic device 1 comprises, as illustrated in Figure 2:

[0091] u. A semiconductor layer called the barrier layer 50. The barrier layer 50 extends over the upper surface 41 of the layer of interest 40. The barrier layer 50 can, for example, be based on AIGaN. The barrier layer 50 forms a heterojunction with the underlying layer of interest 40, which, in operation, as in the prior art, creates a potential well allowing the confinement of electrons. This results in a two-dimensional electron gas that can be designated a channel 45.

[0092] v. A first electrically conductive motif designated source 11. Source 11 is in contact with barrier layer 50.

[0093] w. A second electrically conductive motif designated drain 12. The drain 12 is in contact with the barrier layer 50.

[0094] x. A grid electrode 13 or grid 13. In projection in the longitudinal XY plane, the source 11 and the drain 12 are located on either side of the grid 13.

[0095] The microelectronic device can also be a vertical transistor.

[0096] Alternatively, the microelectronic device can be a diode that operates in transmission or reception, thus forming a photodetector.

[0097] The receiving substrate 20 is typically silicon-based. It can also be silicon carbide (SiC), polycrystalline SiC, aluminum nitride (AIN), polycrystalline AIN, diamond, or polycrystalline diamond. Generally, the receiving substrate 20 can be made of any material with high electrical resistivity, good thermal conductivity, and a coefficient of thermal expansion close to that of the field-blocking layer material 30.

[0098] The receiving substrate 20 has an upper face 21 extending mainly parallel to an XY plane, which can be designated the longitudinal XY plane. This plane is defined by a first direction X and a second direction Y. The longitudinal XY plane is typically perpendicular to the stacking direction Z. The receiving substrate 20 also has a lower face 22, opposite its upper face 21. The receiving substrate 20 has a thickness 620 along the stacking direction Z. The thickness 620 of the receiving substrate 20 is, for example, between 200 µm and 2 mm.

[0099] According to a preferred example, the receiving substrate 20 exhibits p-type doping. The layer of interest 40 is based on a second 11-N material, typically GaN. In general, the layer of interest 40 can be based on any 11-N material with a large band gap. It exhibits a second type of doping, either p-type or n-type. In the case of n-type doping, it is typically residual doping.

[0100] The layer of interest 40 has a thickness of 640 along the stacking direction Z. The thickness of the layer of interest 40 is, for example, between 100 nm and 1 pm.

[0101] The field-blocking layer 30 is based on a first 11-N material, typically GaN or AIGaN, or any variation of a GaN-AIN-based alloy. The first 11-N material is preferably identical to the second 11-N material. For example, both the field-blocking layer 30 and the layer of interest can be GaN-based.

[0102] The field-blocking layer 30 exhibits a doping of the first type, opposite to the second type. The field-blocking layer 30 and the layer of interest 40 thus together form a PN junction.

[0103] The field-blocking layer 30 has an upper face 31 facing the layer of interest 40 and a lower face 32 facing the receiving substrate 20. Preferably, the field-blocking layer 30 is in contact with the receiving substrate 20, either directly or via a bonding interface, which may, for example, take the form of a bonding layer. In particular, preferably, there are no buffer layers between the receiving substrate 20 and the field-blocking layer 30.

[0104] The field-blocking layer 30 has a thickness eao along the stacking direction Z. The thickness e3o of the field-blocking layer 30 can be on the order of tens of nanometers or greater than one hundred nanometers. Due to the use of the Smart Cut® technique (see the description of the process according to the invention below), the thickness e3o of the field-blocking layer 30 is typically less than or equal to 1 pm.

[0105] The field blocking layer 30 and the layer of interest 40 are preferably in contact. Thus, the upper face 31 of the field blocking layer 30 and the lower face 42 of the layer of interest 40 are preferably in contact.

[0106] The field-blocking layer 30 preferably completely separates the layer of interest 40 and the receiving substrate 20. Thus, the receiving substrate 20 and the layer of interest 40 are not in contact. This prevents the formation of a juxtaposition of opposing dopings between the layer of interest 40 and the receiving substrate 20, which would lead to the application of strong fields within the receiving substrate 20, which has low resistance to the electric field.

[0107] The process according to the invention will now be described with reference to figures 3A to 4F.

[0108] The process according to the invention comprises the following steps:

[0109] y. Provide a donor stack 100 comprising a first layer 300. The first layer 300 is based on a first lll-N material and has a doping of a first type among a p-type doping and an n-type doping. The donor stack 100 can also be referred to as the donor substrate 100. In this step, the donor stack 100 typically rests on an initial substrate 5.

[0110] z. Perform ion implantation in the donor stack 100 so as to form a weakening zone 150. The ion implantation of the donor stack 100 is carried out from an upper face 101 of the latter, typically corresponding to an upper face 301 of the first layer 300. The upper face 101 of the donor stack 100 is opposite the initial substrate 5 on which the donor stack 100 rests. The ions implanted during this step are typically H+ ions.

[0111] aa. Transfer the donor stack 100 onto a recipient substrate 20. This transfer step is typically performed by molecular bonding. Optionally, the transfer of the donor stack 100 can be achieved via one or more intermediate layers to ensure bonding or to provide the desired electrical properties. These intermediate layers can, for example, be based on Si, SiC>2, or SiN. x .

[0112] bb. Perform a thermal annealing (which may be referred to as cleavage annealing) configured to cause cleavage of the donor stack 100 at the embrittlement zone 150, while retaining a portion of the donor stack 100, called the carried portion 110, on the receiving substrate 20. The nature of the carried portion 110 depends on the embodiment, as will be evident from the different embodiments described later. Generally, the carried portion 110 includes at least part of the first layer 300.

[0113] cc. Grow a second layer 420 on the reported portion 110. The second layer 420 is based on a second lll-N material and has a second type of doping among a p type doping and an n type doping, opposite to the first type.

[0114] The assembly formed by the reported portion 110 and the second layer 420 thus comprises:

[0115] dd. a field blocking layer 30, at least partly formed by the reported portion 110, and

[0116] ee. a layer of interest 40 at least partly formed by the second layer 420.

[0117] The field-blocking layer 30 and the layer of interest 40 thus together form a PN junction, as in the device according to the invention described above. The method according to the second aspect of the invention therefore makes it possible to manufacture the device according to the first aspect of the invention.

[0118] The process according to the invention thus employs the Smart Cut® principle during the ion implantation and transfer steps onto a receiving substrate. The use of this process in the context of the present invention is particularly advantageous since only a thin layer of the donor stack 100 extending from its upper face 101 is transferred onto the receiving substrate 20. In particular, the layers in contact with the initial substrate 5, typically buffer layers used for the growth of the donor stack 100 on the initial substrate 5, are not transferred. Therefore, only a thin layer of 111-N material exhibiting excellent crystalline quality is transferred, which has a positive impact on the performance of the device obtained at the end of the process.

[0119] Before the formation of the second layer 420 on the projected portion 110, and to facilitate the formation of this second layer 420 by epitaxy, it is preferable to perform high-temperature annealing. Such annealing relaxes the stresses in the projected portion 110, making it ready for resumption of epitaxy (a state commonly referred to as "epi-ready"). This stress-relieving annealing is advantageously carried out within the epitaxial reactor where the formation of the second layer 420 takes place.

[0120] In the process according to the present invention, the activation annealing of the dopants used to cleave the donor stack 100 can also serve as a stress-relieving annealing. For this annealing to have this dual function, annealing temperatures between 400°C and 1400°C are preferred.

[0121] Two main embodiments of the process according to the invention will now be described in more detail.

[0122] A first embodiment of the process is illustrated in figures 3A to 3F.

[0123] Figure 3A illustrates the provision of the donor stack 100. At this stage, the donor stack 100 typically rests on an initial substrate 5. In this embodiment, the donor stack 100 is formed by a first layer 300. The first layer 300 has a top face 301 and a bottom face 302 opposite to each other and both extending mainly parallel to the longitudinal XY plane.

[0124] Figure 3B illustrates the ion implantation step carried out in the donor stack 100. In this embodiment, the ion implantation is carried out in the first layer 300. The ion implantation makes it possible to form a weakening zone 150 in the first layer 300 illustrated by a dotted line on the figures.

[0125] Figure 3C illustrates the transfer of the donor stack 100 onto the receiving substrate 20. To do this, the assembly formed by the initial substrate 5 and the donor stack 100 is typically flipped and then transferred onto the receiving substrate 20.

[0126] Figure 3D illustrates the cleavage of the donor stack 100 at the embrittlement zone 150. This cleavage is achieved by thermal annealing. This cleavage step separates the first layer 300 into two parts: a first part that remains on the receiving substrate 20 and is designated the transferred part 110, and a second part that can be reused for a new iteration of the process according to the invention. In this first embodiment, the transferred part 110 corresponds to the blocking layer 300.

[0127] As previously stated, thermal annealing used to cleave the donor stack at the level of the embrittlement zone 150 can also allow stress relaxation within the transferred portion 110, here the blocking layer 300.

[0128] Figure 3E illustrates the stack obtained after cleavage of the donor stack 1000. This stack therefore includes, in this embodiment, the receiving substrate 20 and the blocking layer 30.

[0129] The transition from Figure 3E to Figure 3F illustrates the growth stage of the second layer 420 on the blocking layer 30. In this embodiment, the second layer 420 corresponds to the layer of interest 40.

[0130] This gives us the stacking illustrated in Figure 3F, comprising the receiving substrate 20, the blocking layer 30 and the layer of interest 40, the latter two together forming a PN junction.

[0131] A second embodiment of the process is illustrated in figures 4A to 4F.

[0132] Figure 4A illustrates a step in supplying an assembly consisting of an initial substrate 5 and a cleaved layer 400. The cleaved layer is based on the second material lll-N and has a second type of doping.

[0133] Figure 4B illustrates the formation of the first layer 300 on the cleaved layer. The first layer 300 is typically formed by epitaxy on the cleaved layer 400. Figure 4B thus illustrates the step of supplying the donor stack 100. In this embodiment, the donor stack 100 is formed by the cleaved layer 400 and the first layer 300. The first layer 300 has an opposing upper face 301 and lower face 302, both extending primarily parallel to the longitudinal XY plane. The lower face 301 of the first layer 300 is located opposite, preferably in contact with, the cleaved layer 400.

[0134] Figure 4C illustrates the ion implantation step carried out in the donor stack 100. In this embodiment, the ion implantation is carried out in the cleaved layer 400. The ion implantation makes it possible to form a weakening zone 150 in the cleaved layer 400 illustrated by a dotted line on the figures.

[0135] Figures 4A to 4C illustrate one option in which ion implantation takes place after the formation of the first 300 layer on the cleaved 400 layer, through the first 300 layer. According to another option, ion implantation can be carried out before the formation of the first 300 layer.

[0136] Figure 4D illustrates the transfer of the donor stack 100 onto the receiving substrate 20. To do this, the assembly formed by the initial substrate 5 and the donor stack 100 is typically flipped and then transferred onto the receiving substrate 20.

[0137] The donor stack 100 is then cleaved at the embrittlement zone 150 by thermal annealing. This cleavage step separates the donor stack 100 into two parts: a first part that remains on the receiving substrate 20 and is designated the transferred part 110, and a second part that can be reused for a new iteration of the process according to the invention. In this second embodiment, the transferred part 110 corresponds to the blocking layer 300 and a portion of the cleaved layer 400, called the initiator layer 410. Thus, in this embodiment, the PN junction is directly transferred to the receiving substrate 20 through cleavage within the cleaved layer 400.

[0138] As in the first embodiment, the thermal annealing used to cleave the donor stack at the level of the embrittlement zone 150 can also allow a relaxation of stresses within the transferred portion 110, here the blocking layer 300 and the initiator layer 410.

[0139] Figure 4E illustrates the stack obtained after cleavage of the donor stack 100. This stack therefore includes, in this embodiment, the receiving substrate 20, the first layer 300 and the primer layer 410.

[0140] The transition from Figure 4E to Figure 4F illustrates the growth stage of the second layer 420 on the reported portion 110, and more specifically in this embodiment on the primer layer 410. After growth of the second layer 420, the layer of interest 40 is obtained, corresponding in this embodiment to the primer layer 410 and the second layer 420.

[0141] This gives us the stacking illustrated in Figure 4F, comprising the receiving substrate 20, the blocking layer 30 and the layer of interest 40, the latter two together forming a PN junction.

[0142] Thus, the two embodiments just described make it possible to obtain a microelectronic device exhibiting a voltage withstand capability superior to the prior art.

[0143] The characteristics of the different layers, and in particular their dimensions, indicated previously with reference to the device according to the invention apply mutatis mutandis to these same layers within the framework of the process according to the invention.

[0144] Figures 5A, 5B, 6, 7, and 8 illustrate how the invention improves the performance of microelectronic devices such as transistors or diodes. The term "diode" refers to both transmitting and receiving microelectronic devices. The present invention is particularly relevant to diodes intended for power applications.

[0145] Figures 5A and 5B illustrate the 0V band diagrams of a prior art transistor and a transistor according to the invention, i.e., incorporating the field blocking layer 30, respectively. The curve labeled "Ec" corresponds to the energy at the bottom of the conduction band, the curve "Ev" to the energy at the top of the valence band, the curve "Efp" to the Fermi level on the P-side, and the curve "Efn" to the Fermi level on the N-side. Comparing Figures 5A and 5B, it appears that the addition of the field blocking layer 30 allows the pn junction to be moved from the 11N / Silicon interface to an 111-N / 111-N interface.

[0146] Figure 6 is a graph illustrating the evolution of the breakdown voltage with the thickness of the field blocking layer 30, for different doping levels of the field blocking layer 30. Simulations were performed for doping levels of 10 17 cm -3 (reference curve 602), 5*10 17cm -3 (curve 603), 10 18 cm -3 (curve 604) and 10 18 cm -3 (curve 605). For each doping level, the breakdown voltage calculation was carried out for blocking layer thicknesses 30 ranging from 0 to 500 nm.

[0147] It is noted that for all the doping levels studied, the introduction of the field blocking layer 30 significantly increases the transistor's breakdown voltage. For example, for all the doping levels studied, it is possible to at least double the breakdown voltage (from 300 V in the absence of a field blocking layer 30, to 600 V or more) of the transistor by designing a field blocking layer 30 with a thickness in the range of 0 to 500 nm. This range is very reasonable: in most of the intended applications, introducing a layer of this thickness does not result in prohibitive size increases.

[0148] In general, the breakdown voltage increases with the thickness of the field-blocking layer 30. For a doping level of 10 17 cm -3 We observe that the thickness of the field blocking layer 30 and the transistor breakdown voltage are approximately proportional (see curve 302). For higher doping levels (see curves 303, 304, 305), we observe that the transistor breakdown voltage varies approximately proportionally with the thickness of the field blocking layer 30, then plateaus. This plateau is effective:

[0149] ff. for thicknesses of approximately 170 nm to 500 nm for a doping of 5*10 17 cm -3 (breakdown voltage of approximately 740 V),

[0150] gg. for thicknesses of approximately 90 nm to 500 nm for a doping of 10 18 cm -3 (breakdown voltage of approximately 720 V),

[0151] hh. for thicknesses of approximately 20 nm to 500 nm for a doping of 5*1018 cm -3 (breakdown voltage of approximately 710 V).

[0152] The identification of these thresholds shows that for certain doping values ​​of the field blocking layer 30, it is not necessary to increase its thickness; a sufficiently small thickness is enough to obtain a very significant increase in the transistor's breakdown voltage. For a doping of 5*10 18 cm -3 For example, it is observed that the breakdown voltage increases from 300 to over 700 V by introducing a field-blocking layer 30 of only a few tens of nanometers, typically 20 nm or more. Beyond approximately 20 nm, the breakdown voltage plateaus, so increasing the thickness of the field-blocking layer 30 is pointless. To further increase the breakdown voltage, one could, for example, adjust the doping level of the field-blocking layer 30 or the thickness of the layer of interest 40 (see below). For a doping level of 5*10 17 cm 3It may be useful, if the applications in question require it, to choose a thickness for the field blocking layer 30 greater than 150 nm, to obtain a voltage withstand of the transistor greater than those obtained with the other doping levels studied.

[0153] Figure 7 is a graph illustrating the variation of the breakdown voltage as a function of the doping of the blocking layer 30, for a blocking layer 30 thickness of 25 nm. This graph was established by simulations of a transistor whose receiver substrate 20 is silicon-based and the blocking layer 30 is P-doped GaN-based. Simulations were carried out for different doping levels and in each simulation, it was verified whether the breakdown of transistor 1 took place in the silicon-based receiver substrate 20 (result identified by a square) or in the GaN-based blocking layer 30 (result identified by a circle).

[0154] First, it is observed that the breakdown voltage increases as the doping level of the blocking layer increases. This increase is roughly proportional for doping levels ranging from 0 to 3*10 18 cm -3 . In this doping range, transistor breakdown occurs in the silicon receiving substrate 20.

[0155] When the doping level of the blocking layer 30 is further increased, breakdown no longer occurs in the silicon receiving substrate 20 but in the blocking layer 30. This is notably the case for doping levels of 4*10 18 cm -3 and 5*10 18 cm -3 The breakdown voltage of the transistor is, for these doping values, approximately 750 V.

[0156] This figure thus illustrates the advantage of introducing a doped blocking layer 30, and highlights the transition from breakdown in the receiving substrate 20 to the blocking layer 30 when the doping level of the blocking layer 30 is increased. The doping level of the breakdown layer 30 at which breakdown occurs from breakdown in the receiving substrate 20 to breakdown in the breakdown layer 30 depends on several parameters, including the resistivity and doping level of the receiving substrate 20, as well as the respective thicknesses and doping levels of the breakdown layer 30 and the layer of interest 40. Generally, regardless of the type of doping of the receiving substrate 20, the blocking layer 30 will preferably be doped to have a higher doping level than the receiving substrate 20.

[0157] Figure 8 is a graph illustrating the variation of the breakdown voltage of transistor 1 with the thickness of the layer of interest 40, both for a prior art transistor (curve 801) and for a transistor according to the present invention, i.e., incorporating a blocking layer 30 (curve 802). The simulations were performed for a silicon-based receiving substrate 20 and, in the case of the transistor according to the present invention, for a pGaN-based blocking layer 30 with a thickness of 25 nm and a doping level of 5 × 10 18 cm -3 The simulations were carried out for thicknesses of the layer of interest 40 ranging from 2 pm to 5 pm.

[0158] Firstly, it is noted that the breakdown voltage values ​​obtained by simulation for a transistor according to the present invention are higher than those obtained for a prior art transistor, over the entire thickness range considered for the layer of interest 40. This demonstrates a significant improvement in the breakdown voltage thanks to the introduction of the blocking layer 30.

[0159] It should also be noted that increasing the thickness of the layer of interest 40 also increases the breakdown voltage. Therefore, it is also possible to manipulate this factor, in synergy with the presence of the blocking layer, to further increase the breakdown voltage. This can be useful in certain applications where increasing the vertical footprint of transistor 1 is acceptable.

[0160] Figure 8 also illustrates the breakdown voltage improvement factor between the prior art transistor and the transistor according to the invention (curve 803). This factor is substantially constant over the entire thickness range studied. It is approximately 2, which means that, for a given thickness and doping level of the blocking layer 30, the invention makes it possible to double the breakdown voltage regardless of the thickness of the layer of interest 40.

[0161] Figures 5A to 8 thus highlight how the introduction of the blocking layer into the structure of a microelectronic device, and particularly a transistor, increases its breakdown voltage. These figures also show that it is possible to adjust various parameters (blocking layer doping level 30, blocking layer thickness 30, thickness of the layer of interest 40) to obtain the desired breakdown voltage, taking into account the constraints specific to the intended applications, and in particular size constraints.

[0162] Through the various embodiments described above, it appears that the present invention offers a highly effective solution for improving the performance of a microelectronic device, particularly its breakdown voltage. The present invention can be used to increase the breakdown voltage of a device or, conversely, to reduce the overall thickness of the device at a constant breakdown voltage.

[0163] The invention is not limited to the embodiments previously described and extends to all embodiments covered by the invention.

Claims

DEMANDS 1. Method for manufacturing a microelectronic device (1) comprising: • a supply of a donor stack (100) comprising a layer, called the first layer (300), based on a first lll-N material and having a doping of a first type among a p-type doping and an n-type doping, • an ionic implantation in the donor stack (100) so as to form a zone of embrittlement (150), • a transfer of the donor stack (100) onto a substrate called the recipient substrate (20), • a thermal annealing configured to cause cleavage of the donor stack (100) at the level of the embrittlement zone (150), while retaining on the receiving substrate (20) a portion of the donor stack (100) called the transferred portion (110), the transferred portion (110) comprising at least part of the first layer (300), • a growth of a layer, called second layer (420), based on a second lll-N material and having a doping of a second type among a p-type doping and an n-type doping, opposite to the first type, on the reported portion (110), the whole formed of the reported portion (110) and the second layer (420) thus comprising a field blocking layer (30), at least partly formed by the reported portion (110), and a layer of interest (40) at least partly formed by the second layer (420), the field blocking layer (30) and the layer of interest (40) together forming a PN junction.

2. A method according to the preceding claim, further comprising: • a formation, on an upper face (41) of the layer of interest (40) opposite the field blocking layer (30), of a layer based on a semiconductor, called barrier layer (50), so as to form a heterojunction between the layer of interest (40) and the barrier layer (50), and • a formation of a gate electrode (13) on the barrier layer (50), • a formation of a first electrically conductive motif forming a source (11) and a second electrically conductive motif forming an undrain (12), the source (11) and the drain (12) being formed in contact with the barrier layer (50) and on either side of the gate electrode (13).

3. A method according to any one of the preceding claims in which the ion implantation is configured so that the embrittlement zone (150) is in the first layer (300), the growth of the second layer (420) is from the first layer (300), the field blocking layer (30) is formed by the first layer (300) and the layer of interest (40) is formed by the second layer (420).

4. Method according to the preceding claim wherein the carried portion (110) of the donor stack (100) is entirely formed by the first layer (300).

5. A method according to any one of the two preceding claims wherein the layer of interest (40) is formed solely by the second layer (420).

6. A method according to any one of claims 1 and 2, wherein the donor stack (100) further comprises a layer, referred to as the cleaved layer (400), having a second-type doping, the ion implantation being configured so that the embrittlement zone (150) is located in the cleaved layer (400), the transfer of the donor stack (100) onto the receiving substrate (20) being effected by means of an upper face (301) of the first layer (300) opposite the cleaved layer (400), the transferred portion (110) further comprising a portion of the cleaved layer (400) referred to as the initiator layer (410), the growth of the second layer (420) occurring from the initiator layer (410), the field-blocking layer (30) being formed by the first layer (300), and the layer of interest (40) being formed, preferably solely, by the layer primer (410) and the second layer (420).

7. A method according to the preceding claim, wherein the steps of supplying the donor stack (100) and ion implantation comprise the following steps: • a supply of the cleaved layer (400), • ion implantation so as to form the weakening zone (150) in the cleaved layer (400), • a formation of the first layer (300) on the cleaved layer (400).

8. Method according to claim 6 in which the ion implantation so as to form the embrittlement zone (150) in the cleaved layer (400) is carried out through the first layer (300).

9. A method according to any one of the preceding claims, wherein the transfer of the donor stack (100) onto the receiving substrate (20) is achieved by molecular bonding.

10. A method according to any one of the preceding claims, wherein the thermal annealing is further configured to cause stress relaxation of the transferred portion (110).

11. A method according to any one of the preceding claims wherein the first layer (300) has p-type doping and the second layer (420) has n-type doping.

12. Microelectronic device comprising, stacked along a so-called stacking direction (Z): • a receiving substrate (20), • a layer, called the layer of interest (40), based on a second 111-N material and having a doping of a second type among a p-type doping and an n-type doping, characterized in that it further comprises, between the receiving substrate (20) and the layer of interest (40), a layer, called the field-blocking layer (30), based on a first 111-N material and having a doping of a first type among a p-type doping and an n-type doping, opposite to the second type, the field blocking layer (30) and the layer of interest (40) together forming a PN junction, the field-blocking layer (30) being in contact with the receiving substrate (20), either directly or solely through a bonding interface, the field blocking layer (30) having, according to the stacking direction (Z), a thickness eao, with eso^lpm.

13. Microelectronic device according to the preceding claim in which the layer of interest (40) is entirely formed of the second material lll-N and in which the field blocking layer (30) and the layer of interest (40) are in contact.

14. Device according to any one of the two preceding claims further comprising, on an upper face (41) of the layer of interest (40) opposite the field blocking layer (30): • a semiconductor-based layer, called the barrier layer (50), forming a heterojunction with the layer of interest (40), • a grid electrode (13) extending over the barrier layer (50), • a first electrically conductive motif forming a source (11), • a second electrically conductive motif forming a drain (12), the source (11) and the drain (12) being in contact with the barrier layer (50) and on either side of the grid electrode (13).

15. Device according to any one of the three preceding claims wherein the first material lll-N and the second material lll-N are identical, and are for example GaN.

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