Method for synchronising the compute cycles of a computer from among a plurality of computers

Abstract

One aspect of the invention relates to a mechanism for synchronizing the compute cycles of a computer with one or more other computers from the same computer system.

Description

DESCRIPTION TITLE: Method for synchronizing the calculation cycles of one computer among a plurality of computers. TECHNICAL FIELD OF THE INVENTION

[0001] The technical field of the invention is that of real-time computer control and / or command systems, typically for the control of actuators and sensors.

[0002] The present invention relates to a method for synchronizing the calculation cycles of a computer in a computer system, a computer implementing this method, and a computer system. TECHNOLOGICAL BACKGROUND OF THE INVENTION

[0003] In aeronautics, integrating a single function onto a single board of an aircraft's embedded system is incompatible with the requirements of processing algorithms, which demand both computing power and responsiveness as close as possible to the sensors and actuators. In particular, the limited space available in an aircraft for mounting the system close to the sensors, coupled with the harsh environment, makes it impractical to use a single, very powerful computer. Consequently, it is known to distribute this function across multiple computers within the embedded system. However, such distribution requires specifying, designing, implementing, and integrating at least as many software components as there are embedded processors.

[0004] As a result, an aircraft-based embedded system is typically made up of several interconnected subsystems and exhibits, at the system level, a globally asynchronous locally synchronous (GALS) architecture.

[0005] Such an architecture requires the implementation of an asynchronicity compensation mechanism, for example a "first-in, first-out" (FIFO) mechanism. However, such a mechanism introduces latency in the exchange of information between the clock domains of the system's computers.

[0006] To synchronize subsystems within an embedded system, methods exist that rely on a clock generated by a single source, such as a clock from one of the subsystems, like an oscillator (or quartz crystal). This clock then serves as the reference for timing all subsystems. However, these methods are not robust to the loss of this single source, which is unacceptable in critical control systems where a simple failure must not have major consequences for the system.

[0007] Furthermore, there are approaches based on the Precise Time Protocol (PTP) algorithm of the IEEE 1588-2019 standard, which notably provides robustness against the loss of the clock source. A drawback of these approaches is that synchronizing the times of each subsystem (commonly called the real-time clock or RTC) is insufficient to guarantee synchronized execution times for processing across different computers.

[0008] Therefore, there is a need for a clock synchronization mechanism for different subsystems within an embedded system that also ensures the synchronization of processing timing across the different subsystems while being robust to the loss of the clock source. SUMMARY OF THE INVENTION

[0009] The invention provides a solution to the problems mentioned above by enabling the synchronization of processing times between one computer in a computer system and another computer. These two computers are synchronized via the synchronization of their respective real-time clocks. Implementing this processing timing synchronization across multiple computers in a network allows for the synchronization of processing across all these computers.

[0010] A first aspect of the invention relates to a method for synchronizing the calculation cycles of one computer among a plurality of computers in a computer system, the computer comprising: a counter of a real-time clock synchronized with a counter of a real-time clock of at least one other computer in the plurality of computers, the counter counting in a time base called the counter's time base, and a timer clocked at a timer frequency in a time base called the timer's time base, the process comprising: to initialize, by the timer, a current calculation cycle following an interruption of a previous calculation cycle by said timer, the current calculation cycle being initialized at the end of a duration, called the calculation time, elapsed in the timer's time base since an initialization of the previous calculation cycle, determine a correction to the timer frequency expressed in the time base of the counter by comparing a previous calculation duration with a reference duration, the previous calculation duration corresponding to the duration evaluated by the counter from the initialization until the interruption by the timer of the previous calculation cycle, determine at the initialization of the current calculation cycle a corrected calculation duration elapsed in the time base of the timer since the initialization of the current calculation cycle as a function of the correction to the timer frequency expressed in the time base of the counter, interrupt, by the timer, the current calculation cycle, the current calculation cycle being interrupted at the end of the corrected calculation time.

[0011] The term "counter time base" refers to the time reference frame in which the real-time clock counter counts the elapsed time. Since the computer's counter is synchronized with the counter of another computer, the increment of the computer's counter does not necessarily occur at a constant number of oscillations of the computer's oscillator (or quartz crystal), but at a variable number over time, depending on the mechanism that governs the synchronization of the computer's counter with that of the other computer.

[0012] A timer, also called a sequencing clock, is an incremental or decremental counter that determines the time elapsed since an interrupt based on the number of oscillations of the computer's oscillator. The timer then triggers an interrupt in a computation cycle when the time it counts matches the predefined number of oscillations to which the timer is set to trigger the interrupt. The time between two interrupts, referred to here as the computation time, corresponds to the English term "tick."

[0013] The "timer time base" refers to the time frame in which the timer counts elapsed time. When the computer's counter is synchronized with that of another computer, the timer's time base is not the same as the counter's time base. Because the timer is not synchronized with the counter, the same number of increments made by the counter and the timer does not correspond to the same elapsed time for the counter relative to the timer, and vice versa; in other words, the same physical elapsed time does not correspond to the same number of increments made by the counter and the timer, respectively.

[0014] The term "computation cycle" refers to a set of calculations performed by a processor of the computer between two timer interrupts, i.e., during a time interval equal to one tick.

[0015] Thanks to the invention, it is possible to synchronize the calculation cycles of different computers within a computer system, such as an embedded system. This is achieved by modifying the calculation time between two calculation cycles of the computer based on the synchronization imposed on the real-time clock counter of that computer, which is synchronized with the counter of another computer. Thus, the interrupts occur at regular intervals from the counter's perspective, but not from the timer's perspective.

[0016] In particular, synchronization is maintained by adjusting, at each interrupt, the timer frequency that is perceived by the counter in its own time frame (i.e., in the counter's time base). Thus, it is possible to correct the calculation time and force the timer to perform the next interrupt at the end of the corrected calculation time.

[0017] Consequently, the computer behaves as if its time base (imposed, for example, by its oscillator or quartz crystal) were the same as that of the other computer to whose counter its counter is synchronized. Put another way, implementing this method on the computers of the computer system allows this system, composed of subsystems (i.e., with a GALS-type architecture), to behave as a single board from a software perspective, thus simplifying the development and integration of this system.

[0018] In addition to the characteristics just mentioned, the process according to the first aspect of the invention may have one or more complementary characteristics from among the following, considered individually or according to all technically possible combinations.

[0019] In one embodiment, the timer frequency f tcexpressed in the time base of the counter is obtained by f t c = f ref * y^, where f ref is a reference frequency corresponding to the timer frequency in the time base of the counter determined at the initialization of the previous calculation cycle, T ref is the reference duration and T tc the previous calculation period.

[0020] In one embodiment, the corrected calculation time T c is obtained by T c = T P * f tc , where T p is the corrected calculation time expressed in the time base of the counter, the corrected calculation time expressed in the time base of the counter corresponding to a prediction, at the initialization of the current cycle, of the corrected calculation time in the time base of the counter.

[0021] The corrected calculation time is thus determined by converting the corrected calculation time (defined in the counter's time base) into the time base of the timer. It is also said to be "expressed" in the time base of the timer. The corrected calculation time expressed in the time base of the timer therefore corresponds to a desired calculation time for the current calculation cycle.

[0022] In one embodiment, T p = t thiinit - t init + T th where t thiinit esï is an expected value of the counter at the initialization of the current calculation cycle, t init being an effective value of the counter at the initialization of the current calculation cycle, and T th being a theoretical calculation time.

[0023] In one embodiment, the previous calculation cycle and the current calculation cycle are included in a plurality of successive calculation cycles, the first calculation cycle of the plurality of calculation cycles being prior to the current calculation cycle and being called the initial calculation cycle, the method comprising, before determining the corrected calculation time, implementing an interruption of the initial calculation cycle after an initial calculation time elapsed since an initialization of the initial calculation cycle, such that the counter has a value corresponding to a hyper-period of the computer system at the interruption of the initial calculation cycle.

[0024] It is therefore possible to impose the start of the synchronization of the computer's calculation cycles at the beginning of a hyper-period of the computer system, that is to say the period equal to the least common multiple of the periods of the computer system's tasks.

[0025] In one embodiment, the initial calculation time T init is determined by T init = (2 * Ti - (t0[7i])) * / o,c> where 7i is the hyper-period of the computer system, t0 is the counter value at the initialization of the initial calculation cycle and f Oc corresponds to the initial timer frequency expressed in the time base of the counter.

[0026] In one embodiment, the initial timer frequency expressed in the time base of the counter is determined by a calibration prior to the implementation of the initial calculation cycle interrupt, the calibration comprising implementing an interrupt after a predefined duration, the predefined duration being the same in the time base of the counter and in the time base, the initial timer frequency f Oc expressed in the time base of the counter being determined by f O ' c = f0T0, c where f0 is the timer frequency expressed in the time base of the timer, T Oref is the predefined duration and T Oc the duration evaluated by the counter at the interruption after the predefined duration.

[0027] It is therefore possible to express the timer frequency precisely in the time base of the counter, in order to maintain the synchronization of the calculation cycles of the computer with those of the other computer.

[0028] A second aspect of the invention relates to a computer configured to implement the method according to the invention.

[0029] Another aspect of the invention relates to a computer program product comprising instructions which, when the program is executed on a computer, cause the computer to implement the steps of the process according to the invention.

[0030] Another aspect of the invention relates to a computer-readable recording medium comprising instructions which, when executed by a computer, cause the computer to carry out the steps of the process according to the invention.

[0031] The invention and its various applications will be better understood by reading the following description and examining the accompanying figures. BRIEF DESCRIPTION OF THE FIGURES

[0032] The figures are presented for illustrative purposes only and are in no way limiting to the invention. Figure 1 is a schematic representation of a computer system according to one embodiment of the invention. Figure 2 is a synoptic diagram illustrating the sequence of steps of a method for synchronizing the calculation cycles of a computer according to an embodiment of the invention. Figure 3 is a schematic representation of an example of the application of the synchronization process according to one embodiment of the invention. Figure 4 is a schematic representation illustrating the chronological sequence of the steps in the synchronization process according to one embodiment of the invention. DETAILED DESCRIPTION

[0033] Unless otherwise specified, the same element appearing on different figures has a unique reference.

[0034] The invention described below proposes a mechanism for synchronizing the calculation cycles of a computer with one or more other computers of the same computer system.

[0035] It is well known that the operation of a computer is based on the counting of a low-level clock, called an oscillator or quartz crystal. The periodicity of the oscillations produced by this low-level clock allows the other clocks, components, and / or mechanisms of that computer (processor, memory, processing, etc.) to be synchronized. In particular, the real-time clock counter and the timer responsible for triggering interrupts in the calculation cycles of the computer's processor(s) count the passage of time in terms of the number of oscillator oscillations. When this computer is isolated, i.e., when its real-time clock is not synchronized with another clock, the passage of time is perceived in the same way by both the real-time clock counter and the timer.Conversely, when the counter is synchronized with the counter of a real-time clock on another computer, for example using existing techniques, time does not flow at the same rate for the counter and the oscillator. Consequently, the computer's calculation cycles (timed by the timer ticks) are out of sync with the counter's time count. Therefore, the computer's calculation cycles are not synchronized with those of the other computer, even if the counters of both computers are synchronized.

[0036] The invention proposes to remedy this problem by implementing a synchronization method that requires the timer to interrupt a current calculation cycle after a specified "calculation time," which is adjusted according to the synchronization of the computer counters. Specifically, this calculation time, elapsed since the beginning of the current calculation cycle, is modified by a conversion mechanism that converts the timer frequency (i.e., the frequency at which the timer counts down) into the time frame of the counter. In other words, the timing of the calculation cycles by the timer is modified according to a relationship that explains, in the time frame of the counter (synchronized with the counter of the other computer), the passage of time in the timer's time frame.

[0037] In the following, the flow of time in the time frame of the counter is called the "time base of the counter" and the flow of time in the timer's time frame is called the "time base of the timer".

[0038] By way of illustration, Figure 1 schematically represents a computer system 1 comprising a plurality of computers, here three computers 10, 20 and 30, connected to each other by a network 40. It is noted however that the method according to the invention is not limited to the synchronization of only three computers, but that it can very well be used to synchronize the calculation cycles of more or less than three computers, such as in a system embedded on an aircraft, for example aimed at controlling and / or commanding certain aircraft components.

[0039] Each calculator 10, 20, and 30 includes an oscillator (or crystal) 11, 21, and 31, respectively, on which the counter 12, 22, and 32, as well as the timer 13, 23, and 33 of each of the calculators 10, 20, and 30, are respectively clocked. It should be noted that the counter of a calculator refers to the counter of the calculator's real-time clock (RTC), and that the timer serves to interrupt the calculator's calculation cycles, and thus also to initiate a new cycle upon the interruption of the interrupted cycle. It should be noted that the oscillator of each calculator may be identical or different (i.e., have the same or a different clock rate), for all or some of the calculators in the plurality of calculators.

[0040] The synchronization method according to the invention can be implemented on each of the computers in a plurality of computers in order to synchronize the timing of their respective calculation cycles. For clarity, the implementation of the method is described hereafter for only one of these computers. It should be noted that it is through the joint implementation of this method on computers whose counters are synchronized with each other that the synchronization of the calculation cycles of these computers is ensured.

[0041] In general, the method according to the invention aims to synchronize the calculation cycles of one computer 10, 20, or 30 among a plurality of computers in a computer system 1. The counter of the computer is synchronized with the counter of another computer in the plurality of computers. That is to say, the passage of time is measured in the same time frame for these two counters, i.e., according to the time base of the counter. In other words, the time base of the counter is the same for the counting of the counter of the computer and for the counting of the counter of the other computer. This synchronization is, for example, implemented via known techniques, such as by applying the IEEE 1588-2019 PTP protocol.

[0042] It should be noted that, for the computer in question, the time base of the timer differs from that of the counter. In the time base of the timer, the timer operates at a timer frequency. It is possible to express the timer frequency in the counter's time base (corresponding to the conversion of the time frequency in the counter's time frame from the time frame of the timer).

[0043] Specifically, the timer is designed to initialize the current calculation cycle following an interruption of the previous calculation cycle, this interruption also being performed by the timer. The current calculation cycle is initialized when the calculation time corresponding to the previous cycle has elapsed. This calculation time of the previous cycle elapses in the timer's time base from the initialization of the previous calculation cycle (Le., the start of the previous calculation cycle) until the interruption of that previous calculation cycle. The timer also serves to interrupt the current calculation cycle.

[0044] In connection with Figure 2, the method 100 according to the invention aims to determine the time at which the current calculation cycle should be interrupted, taking into account the synchronization of the counter with the counter of the other computer. To this end, the method 100 implements a step 130 for correcting the calculation time to determine a corrected calculation time. The calculation cycle is thus interrupted at the end of this corrected calculation time, which elapses, in the timer's time base, from the initialization of the current calculation cycle.

[0045] The corrected calculation time is determined at the start of the current calculation cycle. This corrected calculation time is based on the timer frequency correction expressed in the counter's time base. In other words, the corrected calculation time depends on a correction to the timer frequency perceived by the counter in its time base. This timer frequency correction is obtained by comparing the time elapsed between the start and end of the previous calculation cycle, as measured in the counter's time base (and therefore perceived by the counter), with a so-called "reference" time.

[0046] The actual time elapsed between the initialization and the interruption of the previous calculation cycle in the counter's time base is called the "previous calculation time." The previous calculation time therefore corresponds to the time evaluated by the counter from the initialization until the interruption of the previous calculation cycle. The previous calculation time is thus expressed in the counter's time base.

[0047] Put another way, the approach proposed here aims to recalculate the timer frequency that is perceived by the counter, which makes it possible to determine the corrected calculation time in order to synchronize the current calculation cycle, including its interruption, with the timing of the counter, which is synchronized with the count of the other computer.

[0048] For example, it is possible to determine, within the timer's time base, a corrected calculation time (defined within the time base) based on the timer frequency correction expressed in the time base. This corrected calculation time corresponds to a prediction of the time the timer perceives before the current calculation cycle is interrupted. This corrected calculation time is then converted from the time base to the timer's time base, using the timer frequency correction to obtain the corrected calculation time at the end of which the timer should interrupt the current calculation cycle.

[0049] Put another way, it is possible to express in the counter's time base the corrected calculation time after which the interruption should occur. This corrected calculation time is then converted in the time base of the timer, to force the timer to interrupt the current calculation cycle at the end of the corrected calculation time.

[0050] Thus, by implementing this process, it is possible to synchronize the tick to the time base of the counter and thus take advantage of the synchronization of the counter with the counter of the other computer.

[0051] It is noted that step 130, which determines the corrected computation time for each calculation cycle of the computer, can be implemented when the computer performs multiple successive calculation cycles. This ensures the synchronization of calculation cycles throughout the computer's operation, even when the counter's time base changes over time, for example, through computer-to-computer synchronization such as the IEEE 1588 protocol described in the introduction. The corrected computation time is then recalculated at the beginning of each calculation cycle, when the preceding calculation cycle is interrupted.

[0052] In one embodiment, the method includes, after step 130 of determining the corrected calculation time, the implementation of the interruption of the current calculation cycle by the timer at the end of this corrected calculation time after the initialization of the current calculation cycle. It is also possible to implement this interruption after each implementation of step 130, typically in the case where this step 130 is implemented in every calculation cycle of the computer.

[0053] In one embodiment, the timer frequency is expressed in the time base of the counter, denoted f tc , is obtained such that f tc = f ref * —, with ref a reference frequency, T ref the reference duration and T tc the previous calculation time (Le., the time actually perceived by the counter between the initialization and the interruption of the previous calculation cycle).

[0054] The reference frequency f ref This corresponds to the timer frequency expressed in the time base of the counter determined at the initialization of the previous calculation cycle. Typically, the timer frequency expressed in the counter's time base corresponds to the conversion of the timer frequency in the counter's time base, particularly at the initialization of process 100, or to a previous correction of the timer frequency expressed in the counter's time base. Indeed, in the latter case, since process 100 aims to correct (in this instance, adjust) the timer frequency expressed in the counter's time base at each calculation cycle, the reference frequency can be the correction of the timer frequency expressed in the counter's time base determined at the initialization of the previous calculation cycle, which was used to determine the calculation duration.

[0055] The reference duration T refThis corresponds, for example, to the expected duration perceived (assuming the timer and counter are indeed synchronized) by the counter between the initialization and interruption of the previous calculation cycle. In other words, the reference duration can correspond to a desired calculation duration for the previous calculation cycle, in the counter's time base, determined during the initialization of the previous calculation cycle. The approach here therefore consists of correcting the timer frequency expressed in the counter's time base by taking into account the estimated time elapsed in the counter's time frame, from the initialization point of the calculation cycle to be interrupted, which is calculated during the initialization of the previous calculation cycle.In other words, at the initialization of the current calculation cycle, the reference duration corresponds to an estimate of the duration of the previous calculation cycle (elapsed between its initialization and its interruption), which is therefore the expected duration for this previous calculation cycle, in the time base of the counter, and calculated when this previous calculation cycle is initialized.

[0056] At the initialization of process 100, the reference duration is, for example, equal to a theoretical calculation duration, which corresponds to the calculation duration in the time base of the timer, therefore without conversion of this duration in the time base of the counter.

[0057] After the initialization of process 100, at the time of the interruption of the previous calculation cycle, the previous calculation time T tc may not correspond to the reference duration T ref(in the counter's time base). Indeed, since the counter's time base varies depending on its synchronization with the other computer's counter, it is possible that, from one calculation cycle to the next, the previous calculation time (evaluated via the counter) may not exactly match the expected time until the interruption, as predicted during the initialization of the previous calculation cycle. The reference time is therefore re-evaluated at the initialization of each calculation cycle, so as to maintain the tick's synchronization with the counter's time base in case the interruption time in the counter's time base is advanced or delayed.

[0058] In other words, the reference duration T ref predicted during the initialization of the previous calculation cycle may be equal to T ref = t thiinitiP - t init>p + T th where t thiinitiPis the expected value of the counter at the initialization of the previous calculation cycle (i.e., the counter value predicted before the initialization of the previous calculation cycle, typically predicted during the initialization of the calculation cycle preceding the previous calculation cycle, and which was expected at the initialization of the previous calculation cycle—which may not be the value at which the counter is located if the timer frequency expressed in the counter's time base does not exactly match the timer frequency expressed in the timer's time base), t init p is the actual value of the counter at the initialization of the previous calculation cycle (related to the previous calculation duration, i.e., the duration of the previous calculation cycle actually perceived by the counter), and T th is the theoretical calculation time.

[0059] In one embodiment, the corrected computation time, denoted T c , is obtained such that Tc = T P * f tc , where T p is the corrected calculation time expressed in the time base of the counter. That is to say, this corrected calculation time T p This corresponds to a prediction, at the initialization of the current calculation cycle, of the corrected calculation time expressed in the counter's time base. In other words, the corrected calculation time expressed in the counter's time base is a prediction, determined at the initialization of the current calculation cycle, of the calculation time perceived by the counter between the initialization and the interruption of the current calculation cycle.

[0060] Put another way, the corrected calculation time is determined from the prediction of this corrected calculation time in the time reference frame of the counter, which is then converted into the time reference frame of the timer.

[0061] In one embodiment, the corrected computation time expressed in the time base of the counter is such that T p = t th>init - t init + T th where t thiinit is an expected value of the counter at the initialization of the current calculation cycle (i.e., the value of the counter predicted at the initialization of the previous calculation cycle - which may not be the value at which the counter is located if the timer frequency expressed in the counter's time base does not perfectly match the timer frequency expressed in the timer's time base), t init being the effective value of the counter at the initialization of the current calculation cycle, and T th being the theoretical calculation time.

[0062] In one embodiment, it is possible to begin synchronizing the computer's calculation cycles at the start of a hyperperiod of the computer system. The hyperperiod corresponds to the operating period of system 1, which is the least common multiple of the respective operating periods of each computer in the plurality of computers. The operating period of a computer is the period during which its operations are repeated.

[0063] In this embodiment, the preceding calculation cycle and the current calculation cycle are considered to be contained within a plurality of successive calculation cycles. The first calculation cycle of the plurality of calculation cycles is defined as being prior to the current calculation cycle and is called the "initial calculation cycle".

[0064] In this embodiment, the process 100 then includes, as illustrated in Figure 2, before determining the corrected computation time, the implementation of a step 120 for interrupting the initial computation cycle after an initial computation time. This initial computation time elapses from the initialization of the initial computation cycle and is such that the counter has a value corresponding to the beginning of a hyper-period of the computer system at the time of the interruption of the initial computation cycle.

[0065] In one embodiment, the initial calculation time, denoted T init , is determined such that T init = (2 * ^ - (t0mod(T1)')') * f Oc , where 7 is the hyperperiod of the computer system, mod(Tf) corresponds to the modulo of the hyperperiod T 1; t0 is the value of the counter at the initialization of the initial calculation cycle and f Occorresponds to the initial timer frequency expressed in the time base of the counter. For example, the initial timer frequency expressed in the time base of the counter is equal to the timer frequency (defined in the timer's time base) or to a frequency determined via a calibration mechanism, such as the one shown below.

[0066] In one embodiment, the method 100 includes a calibration step 110 prior to implementing the interruption of the initial calculation cycle in order to determine the initial timer frequency expressed in the time base of the counter. This calibration includes implementing an interruption after a predefined duration. The predefined duration is such that it is the same in the time base of the counter and in the time base of the timer. The initial timer frequency expressed in the time base of the counter f Oc is thus determined such that f Oc = fo where fo is the timer frequency in the time base of the ' T 0.C timer, T0, re is the predefined duration and T0,c is the duration evaluated via the counter at the interrupt triggered by the timer at the end of the predefined duration.

[0067] The predefined duration is a duration defined prior to the calibration, or even before the implementation of process 100. Preferably, this duration is sufficiently long, relative to the initial calculation time, to accurately determine the timer frequency expressed in the counter's time base. The predefined duration is, for example, greater than or equal to five times the initial calculation time, or greater than or equal to ten times, or even greater than or equal to twenty times this duration. For example, the predefined duration is greater than or equal to 100 ms, or greater than or equal to 150 ms, or even greater than or equal to 200 ms.

[0068] In one embodiment, the initial timer frequency expressed in the time base of the counter is determined prior to the implementation of process 100. In this case, this timer frequency expressed in the time base of the counter may have been determined previously, by a known method, or by a previous implementation of process 100. In the latter case, the timer frequency expressed in the time base of the counter corresponds to a timer frequency expressed in the time base of the counter calculated during the previous implementation of process 100, typically the last timer frequency expressed in the time base of the counter, such as the last calculated corrected frequency expressed in the time base of the counter.

[0069] Another aspect of the invention relates to one of the computers 10, 20, or 30 of the plurality of computers. This computer is specifically configured to implement the method 100 according to the invention. Typically, the computer includes a memory containing instructions which, when executed by a processor of the computer, cause that processor to implement the method 100.

[0070] Another aspect of the invention relates to a computer system such as that described above. In particular, in this computer system, each computer in the plurality of computers it comprises is configured to implement the method 100 according to the invention, as described above.

[0071] As an illustration, Figure 3 provides an example of the implementation of method 100, which aims to synchronize the four electric motors M1, M2, M3, and M4 of a drone 50. The four motors M1 to M4 are synchronized via method 100 implemented on the respective computer, C1 to C4, of each of these motors. Connecting the computers via network 40 allows the actuation signals Act_M1 to Act_M4 to be synchronized, here with a frequency between 1 kHz and 10 kHz, for example, 5 kHz. Thus, thanks to the implementation of the method on these computers, the motor actuation is synchronized within a time window Ws of duration less than or equal to 1 ps.

[0072] For illustrative purposes, an implementation of process 100 is shown in Figure 4. Initially, calibration step 110 is implemented and a calculation cycle is initiated, to be interrupted after the predefined duration T OrefThe initial timer frequency expressed in the time base of the counter f O c is thus determined from this predefined duration T Oref and the duration T Oc evaluated via the meter.

[0073] Next, step 120 is implemented, interrupting the initial calculation cycle after the initial calculation time T. init .

[0074] The first calculation cycle is then performed. At its initialization, step 130 is implemented, as described previously, to determine the corrected calculation time T C 1 of this first calculation cycle, considering the theoretical calculation time T th as a reference duration T ref .

[0075] The second calculation cycle is then performed. At its initialization, step 130 is implemented, as described previously, to determine the corrected calculation time T c>2of this second calculation cycle, considering the previous calculation time T t c l (i.e., the previous calculation time evaluated by the counter and corresponding to the first calculation cycle) as the reference time T ref .

[0076] Thus, generally, at the initialization of a calculation cycle n, step 130 is implemented, as described previously, to determine the corrected calculation time T Cn of this nth calculation cycle, considering the previous calculation time T t>c>n- (i.e., the previous calculation time evaluated by the counter and corresponding to calculation cycle n-1) as the reference time T ref It is also noted that the corrected calculation time T c nor is the duration of this calculation cycle n-1 determined by considering the previous calculation time T t>cn-2 (i.e., the previous calculation time evaluated by the counter and corresponding to calculation cycle n-2) as the reference time Tref .

Claims

DEMANDS

1. A method (100) for synchronizing calculation cycles of a computer (10, 20, 30) among a plurality of computers (10, 20, 30) of a computer system (1), the computer (10, 20, 30) comprising: - a counter (12, 22, 32) of a real-time clock synchronized with a counter (12, 22, 32) of a real-time clock of at least one other computer (10, 20, 30) of the plurality of computers (10, 20, 30), the counter (12, 22, 32) counting in a time base called the counter's time base, and - a timer (13, 23, 33) running at a timer frequency in a time base called the timer's frequency, the process (100) comprising: - initialize, by the timer (13, 23, 33), a current calculation cycle following an interruption of a previous calculation cycle by said timer (13, 23, 33), the current calculation cycle being initialized at the end of a duration, called the calculation time, elapsed in the timer's time base since an initialization of the previous calculation cycle, - determine a correction for the timer frequency expressed in the time base of the counter by comparing a previous calculation duration with a reference duration, the previous calculation duration corresponding to the duration evaluated by the counter (12, 22, 32) from the initialization until the interruption by the timer (13, 23, 33) of the previous calculation cycle, - determine (130) at the initialization of the current calculation cycle a corrected calculation time elapsed in the timer's time base since the initialization of the current calculation cycle as a function of the timer frequency correction expressed in the counter's time base, - interrupt, by the timer (13, 23, 33), the current calculation cycle, the current calculation cycle being interrupted at the end of the corrected calculation time.

2. Method (100) according to claim 1, wherein the timer frequency f tc expressed in the time base of the counter is obtained by f tc = f ref * where f ref is a reference frequency corresponding to the frequency of timer in the time base of the counter determined at the initialization of the previous calculation cycle, T ref is the reference duration and T tc the previous calculation period.

3. Method (100) according to claim 2, wherein the corrected computation time T c is obtained by T c = T P * f tc , where T p is the corrected calculation time expressed in the time base of the counter, the corrected calculation time expressed in the time base of the counter corresponding to a prediction, at the initialization of the current cycle, of the corrected calculation time evaluated in the time base of the counter.

4. Method (100) according to claim 3, wherein T p = t tfl init - init + T th where t th ' init is a expected value of the counter (12, 22, 32) at the initialization of the current calculation cycle, t init being an effective value of the counter (12, 22, 32) at the initialization of the current calculation cycle, and T th being a theoretical calculation time.

5. A method (100) according to any one of the preceding claims, wherein the previous calculation cycle and the current calculation cycle are included in a plurality of successive calculation cycles, the first calculation cycle of the plurality of calculation cycles being prior to the current calculation cycle and being called the initial calculation cycle, the method comprising, before the determination (130) of the corrected calculation time, the implementation of an interruption (120) of the initial calculation cycle after an initial calculation time elapsed since an initialization of the initial calculation cycle, such that the counter (12, 22, 32) has a value corresponding to a hyper-period of the computer system at the interruption of the initial calculation cycle.

6. Method (100) according to claim 5, wherein the initial calculation time T init is determined by T init = (2 * l - (t0[7 ])) * fo,c> where is the hyper-period of the computer system, t0 is the value of the counter (12, 22, 32) at the initialization of the initial calculation cycle, and f Oc corresponds to the initial timer frequency expressed in the time base of the counter.

7. A method (100) according to any one of claims 5 to 6, wherein the initial timer frequency expressed in the time base of the counter is determined by a calibration (110) prior to implementing the interruption of the initial calculation cycle, the calibration (110) comprising implementing an interruption after a predefined duration, the predefined duration being the same in the time base of the counter and in the time base of the timer, the initial timer frequency f Oc expressed in the time base of the counter being determined by f Oc = f Q * where f Q is the timer frequency expressed in the time base of the To, c timer, T Oref is the predefined duration and T Oc the duration evaluated by the counter (12, 22, 32) at the interruption after the predefined duration. [Claims] Calculator (10, 20, 30) configured to implement the method (100) according to any one of the preceding claims. [Claims] Computer system (1) comprising a plurality of computers (10, 20, 30), each computer (10, 20, 30) of the plurality of computers (10, 20, 30) being configured to implement the method (100) according to any one of claims 1 to 7.

10. A computer-readable recording medium comprising instructions which, when executed by a computer, cause the computer to carry out the method (100) according to any one of claims 1 to 7.

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