A signal processing circuit for quadrature amplitude modulation receiver

Abstract

The invention is a signal processing circuit for enhancing signal-to-noise ratio (SNR) in a quadrature amplitude modulation (QAM) receiver and quadrature amplitude modulation (QAM) receiver having the signal processing circuit arranged between a front-end and a demodulation stage of the receiver.

Description

[0001] DESCRIPTION

[0002] A SIGNAL PROCESSING CIRCUIT FOR QUADRATURE AMPLITUDE MODULATION RECEIVER

[0003] Technical Field

[0004] The invention is related to a signal processing circuit for enhancing signal-to-noise ratio (SNR) in a quadrature amplitude modulation (QAM) receiver and quadrature amplitude modulation (QAM) receiver having the signal processing circuit arranged between a front-end and a demodulation stage of the receiver.

[0005] Prior Art

[0006] In the field of wireless communication systems, various methodologies have been developed to enhance the signal-to-noise ratio (SNR) during signal reception. One such method involves the use of hardware-based matched filters, which are designed to maximize SNR by correlating the received signal with a known reference. While effective in certain applications, these filters often introduce challenges related to design complexity and increased latency and depend on a reference known signal.

[0007] Alternative approaches have incorporated redundant data transmission for channel estimation purposes. This technique involves sending auxiliary signals alongside the primary data to facilitate accurate channel characterization. However, the inclusion of redundant signals can lead to decreased spectral efficiency and reduced overall data throughput.

[0008] Coding schemes represent another strategy employed to improve SNR. By adding structured redundancy to the transmitted data, these schemes enable error detection and correction at the receiver end. Despite their effectiveness in enhancing signal integrity, coding schemes can significantly increase system complexity and computational demands, potentially impacting real-time processing capabilities.

[0009] Using array antenna at receiver and transmitter another hardware technique which enhance the SNR at receiver, in spite of it is effective approach but the complexity is significant high.

[0010] These existing methods, while addressing specific aspects of noise reduction, often do so at the expense of other critical performance metrics such as latency, spectral efficiency, complexity, and data rate. Consequently, there remains a need for a noise reduction solution that effectivelyenhances SNR without introducing additional complexity or compromising other system parameters.

[0011] As a result, all the problem mentioned above has made it necessary to provide a novelty in the related field.

[0012] Objects of the Invention

[0013] The present invention introduces a novel hardware-based signal processing circuit designed to significantly enhance the signal-to-noise ratio (SNR) in communication systems. Unlike traditional matched filter methodologies, which often involve complex designs and increased latency, this invention achieves over 40 dB SNR improvement through an innovative mechanism that eliminates the need for redundant signals or intricate coding systems. This advancement directly addresses the prevalent issue of noise interference that compromises data quality and reliability in communication channels.

[0014] The invention's primary objectives encompass increasing data transmission rates, ensuring consistent and accurate data delivery, expanding coverage areas for broader accessibility, and reducing system complexity and computational demands. By achieving higher data rates without additional bandwidth consumption and improving spectrum efficiency, the invention facilitates reliable long-distance communication with reduced latency. This is particularly beneficial for applications requiring real-time responsiveness, such as remote surgeries and unmanned vehicle operations. Furthermore, the streamlined design contributes to cost-effective and efficient system performance, meeting the growing demand for robust, high-speed communication technologies in an increasingly connected world.

[0015] Description of the Figures of the Invention

[0016] The figures and related descriptions necessary for the subject matter of the invention to be understood better are given below.

[0017] Figure 1. A schematic view of the circuit of invention.

[0018] Figure 2. A graphic of signals step by step

[0019] Reference Numbers

[0020] The parts and components are given in the figures are referenced for the subject matter of the invention to be understood better.1. Input terminal

[0021] 2. Local oscillator

[0022] 3. Phase shifter

[0023] 4. First multiplier

[0024] 5. Second multiplier

[0025] 6. First DC filter

[0026] 7. Second DC filter

[0027] 8. Third multiplier

[0028] 9. Fourth multiplier

[0029] 10. Operational Amplifier

[0030] Rf. Feedback resistance

[0031] Ri. Input resistance

[0032] Detailed Description of the Invention

[0033] The invention is related to a signal processing circuit for enhancing signal-to-noise ratio (SNR) in a quadrature amplitude modulation (QAM) receiver and quadrature amplitude modulation (QAM) receiver having the signal processing circuit arranged between a front-end and a demodulation stage of the receiver

[0034] Referring to Figure 1 and Figure 2; the circuit of the present invention comprises an input terminal (1) for receiving a modulated signal includes in-phase (I) and quadrature (Q) components.

[0035] Preferably, the form of the modulated signal includes in-phase (I) and quadrature (Q) components is

[0036] I sin(wct) + Q cos(wct), wherein

[0037] I is inphase component of QAM signal and Q is the Quadrature component, wcis the local oscillator angular velocity and t is the time in second.Also, the circuit comprises a local oscillator (2) which can generate a carrier frequency signal. Preferably, the form of the carrier frequency signal

[0038] [2 sin(wct)].

[0039] The carrier frequency signal is generated for multiplying the modulated input signal received by the input terminal (1). The multiplying step is carried out by a first and a second multipliers (4,5).

[0040] The local oscillator (2) provides two outputs. One of the outputs is connected to the first multiplier (4) and other output is connected to the second multiplier (5) via a phase shifter (3). A phase shifter (3) is configured to shift phase of the carrier frequency signal. Preferably, the phase shifter (3) is configured to shift phase of carrier frequency signal by π / 2 radians.

[0041] Preferably, the form of output of the phase shifter (3) is

[0042] 2 cos(wct).

[0043] The first multiplier (4) configured to multiply carrier frequency signal provided by the local oscillator (2) and the input signal received by the input terminal (1). The second multiplier (5) configured to multiply carrier frequency signal shifted by the phase shifter (3) and the input signal received by the input terminal (1).

[0044] Preferably, the form of output of the first multiplier (4) is

[0045] I − I cos( 2wct) + Q sin(2wct),

[0046] the form of output of the second multiplier (5) is

[0047] I sin(2wct) + Q + Q cos(2 wct).

[0048] The first multiplier (4) and the second multiplier (5) are connected to the filter elements. More clearly, the both multiplied signals provided by the first and the second multipliers (4,5) filtered to remove their DC component by a first and second DC filters (6, 7). The DC filters (6, 7) are preferably coupling capacitors. However, any component which has function to filter DC components of the signal can be used as DC filter (6, 7).

[0049] Preferably, the form of output of the first DC filter (6) is—I cos( 2wct) + Q sin(2wct),

[0050] the form of output of the second DC filter (7) is

[0051] I sin(2wct) + Q cos(2 wct).

[0052] Another multiplying steps is applied for both filtered signals provided by the first and the second DC filters (6, 7). Accordingly, the outputs of the first and the second DC filters (6, 7) are connected to a third and a fourth multipliers (8, 9), respectively. Also, the output of the local oscillator (2) is connected directly to the fourth multiplier (9) and the output of the phase shifter (3) is connected to the third multiplier (8). Thus, the third multiplier (8) multiply the carrier frequency signal shifted by the phase shifter (3) and output of the first DC filter (6); the fourth multiplier (9) multiply the carrier frequency signal provided by the local oscillator (2) and output of the second DC filter (7).

[0053] Preferably, the form of output of the third multiplier (8) is

[0054] —I cos(wct) + Q sin(wct) — I cos(3wct) + Q sin(3wct),

[0055] the form of output of the fourth multiplier (9) is

[0056] I cos(wct) — Q sin(wct) — I cos(3wct) + Q sin(3wct).

[0057] Multiplying step at the third and fourth multipliers (8,9) provides the inphase (I) and Quadrature (Q) components of the signal to be out of phase (n) in respect to each other, while the noise and signals with (3wc) to be in phase. The signals which are out of phase are I cos (wct) & Q sin (wct) as seen they are the transmitted signals while the signals which are inphase are I cos(3wct) & Q sin(3wct) as well as the noise.

[0058] The outputs of the third multiplier (8) and the fourth multiplier (9) are connected to an operational amplifier (10). Preferably, output of the third multiplier (8) connected the negative terminal of the operational amplifier (10) and output of the fourth multiplier (9) connected the positive terminal of the operational amplifier (10).

[0059] The operational amplifier (10) is provided with feedback resistances (Rf) and input resistances (Ri). The one of feedback resistances (Rf) connected to the positive terminal of the operational amplifier (10) and to the input resistance (Ri) and the other terminal of (Rf) is connected toground. Other feedback resistances (Rf) connected to the negative terminal of the operational amplifier (10) and to the input resistance (Ri) and the other terminal of (Rf) is connected to output of the operational amplifier (10). The operational amplifier (10) having a common-mode rejection ratio (CMRR). Common Mode Rejection Ratio (CMRR), defined as the ratio of the Differential Mode Gain (Avd) to the Common Mode Gain (Avc). CMRR is high for typically operational amplifier. That’s mean high capability of reject in phase signals and highly amplification of out of phase signals between two inputs of operation amplifier

[0060] CMRR = [Avd] / [Avc]

[0061] This signal processing circuit ensures that transmitted signals are shifted out of phase while noise remains in phase. As a result, the transmitted signals are amplified and at the same time, the in-phase noise is effectively rejected. This process enables SNR improvement of at least 40 dB relative to the received signal at the input terminal.

[0062] Gain is calculated according to formula;

[0063] Gain = (Rf1 / Ri1) + (1+ Rf2 / Ri2) and

[0064] If the feedback resistances (Rf) are equal and input resistances (Ri) are equal to each other, approximately:

[0065] Gain = 2*(Rf / Ri).

[0066] In a preferred embodiment, the gain is 200. This embodiment enhances the Signal-to-Noise Ratio (SNR) by 70 dB by assuming the typical value of CMRR is also 70 dB. Furthermore, it should be understood that the primary objective of the invention is to improve the signal-to-noise ratio (SNR). The gain value of 200 is a design choice made for illustrative purposes and should not be construed as the only possible option or a limiting feature of the invention.

[0067] In an alternative embodiment, the processing circuit comprises one DC filter, instead of two as explained before. In this case,

[0068] 1- Only one DC filter can be connected between first multiplier (4) and third multiplier (8)

[0069] Preferably, the form of output of the third multiplier (8) is

[0070] —I cos(wct) + Q sin(wct) — I cos(3wct) + Q sin(3wct),the form of output of the second third multiplier (9) which is without DC filter is

[0071] I cos(wct) + Q sin(wct) — I cos(3wct) + Q sin(3wct).

[0072] It is obvious only the [ I cos(wct)] of received signal [I sin(wct) + Q cos(wct)] is amplified while the all remaining three parts as well as the noise is council.

[0073] 2- Only DC filter can be connected between second multiplier (5) and fourth multiplier (9).

[0074] Preferably, the form of output of the third multiplier (8) is

[0075] I cos(wct) + Q sin(wct) — I cos(3wct) + Q sin(3wct),

[0076] the form of output of the second third multiplier (9) is

[0077] I cos(wct) — Q sin(wct) — I cos(3wct) + Q sin(3wct).

[0078] It is obvious only the [ Q sin(wct)] of received signal [I sin(wct) + Q cos(wct)] is amplified while the all remaining three parts as well as the noise is council.

[0079] for the previous two cases, signal-to-noise ratio (SNR) can be still achieved but, for one part of received signal, that’s it, one DC filter embodiment only enhances either the in-phase component or the quadrature component (in QAM), but not both simultaneously. The improvement in this example circuit is still more than 40 dB but, just for one part.

Claims

CLAIMS1. A signal processing circuit for enhancing signal-to-noise ratio (SNR) in a quadrature amplitude modulation (QAM) receiver, characterized by• an input terminal (1) configured to receive a modulated signal comprising inphase (I) and quadrature (Q) components,• a local oscillator (2) configured to generate a carrier frequency signal,• a phase shifter (3) configured to shift the carrier frequency signal to generate a phase-shifted carrier frequency signal by π / 2,• a first multiplier (4) configured to multiply the received signal of the input terminal (1) with the carrier frequency signal;• a second multiplier (5) configured to multiply the received signal of the input terminal (1) with the phase-shifted carrier frequency signal;• at least one DC filter (6, 7) configured to remove the DC component from the output of the first multiplier (4) or the second multiplier (5), respectively;• a third multiplier (8) configured to multiply the output of the first coupling capacitor (6) with the phase-shifted carrier frequency signal;• a fourth multiplier (9) configured to multiply the output of the second coupling capacitor (7) with the carrier frequency signal;• an operational amplifier (10) having a Common Mode Rejection Ratio (CMRR), defined as the ratio of the Differential Mode Gain (Avd) to the Common Mode Gain (Avc) andhaving feedback resistances (Rf) and input resistances (Ri) andconfigured to receive output of the third and fourth multiplier (8,9).

2. A signal processing circuit according to Claim 1, wherein ratio of feedback resistance (Rf) and input resistance (Ri) are same for positive and negative terminals.

3. A signal processing circuit according to Claim 1, wherein ratio of feedback resistance (Rf) and input resistance (Ri) is 100.

4. A signal processing circuit according to Claim 1, wherein output of the third multiplier (8) is connected to negative terminal of the operational amplifier (10) via an inputresistance and output of the fourth multiplier (9) is connected to positive terminal of the operational amplifier (10) via an input resistance.

5. A signal processing circuit according to Claim 1, wherein the first and second DC filters (6,7) are coupling capacitors.

6. A signal processing circuit according to Claim 1, wherein comprises two DC filter as a first and second DC filter (6, 7) configured to remove the DC component from the output of the first multiplier (4) and the second multiplier (5), respectively.

7. A signal processing circuit according to claim 1, wherein• the input terminal (1) configured to receive a modulated signal comprising in-phase (I) and quadrature (Q) components in form of I sin(wct) + Q cos(wct),• the local oscillator (2) and the phase shifter (3) configured to generate a carrier frequency signal and phase-shifted carrier frequency signal in form of 2 sin(wct), and 2cos(wct), respectively.• the first multiplier (4) configured to form a signal in form of I — / cos(2wct) + Q sin(2wct),• the second multiplier (5) configured to form a signal in form of I sin(2 wct) + Q + Q cos(2 wct)• the first and second coupling capacitor (6, 7) configured to form a signal in form of —I cos( 2wct) + Q sin(2wct) and I sin(2wct) + Q cos(2 wct), respectively,• the third multiplier (8) configured to form a signal in form of -I cos(wct) + Q sin(wct) — I cos(3wct) + Q sin(3wct),• the fourth multiplier (9) configured to form a signal in form of I cos(wct) − Qsin(wct) − Icos(3wct) + Qsin(3wct);• the operational amplifier (10) configured form a signal in form ofQ sin(wct) — I cos(3wct) + Q sin(3wct)], whereinI is inphase component of QAM signal and Q is the Quadrature component, wcis the local oscillator angular velocity and t is the time, Rfis feedback resistances and Riis input resistances8. A signal processing circuit according to any of preceding claims, wherein the operational amplifier configured to the output signal exhibits an SNR improvement of at least 40 dB relative to the received signal.

9. A quadrature amplitude modulation (QAM) receiver having the circuit according to any preceding claims which is arranged between a front-end and a demodulation stage of the receiver.

10. A method for reducing noise in a QAM receiver signal, the method comprising:• receiving an in-phase (I) and quadrature (Q) modulated signal,• multiplying the received signal with a carrier frequency signal to generate a first intermediate signal,• multiplying the received signal with a π / 2 phase-shifted carrier frequency signal to generate a second intermediate signal,• removing DC components from the first and the second intermediate signals to obtain third and fourth intermediate, respectively;• multiplying the third intermediate signal each intermediate signal with corresponding carrier signals to isolate higher-order and fundamental frequency components;• applying the resulting signals to a differential amplifier,• amplifying out-of-phase components while suppressing in-phase harmonic and noise components to provide the output signal.

11. A method according to Claim 10, wherein amplifying in such a way that the output signal exhibits an SNR improvement at least 40 dB relative to the received signal.

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