Semiconductor device and method for producing semiconductor device

Abstract

Provided is a semiconductor device that can be miniaturized or highly integrated. The present invention comprises first to third transistors and first to fourth insulating layers. The first to third transistors are all vertical transistors, share some components, and are stacked in this order. The third transistor has two gates. The first insulating layer is provided between one of a source and a drain of the first transistor and a gate of the first transistor. The second insulating layer is provided between the gate of the first transistor and one of a source and a drain of the third transistor. The third insulating layer is provided between one of the source and the drain of the third transistor and one gate of the third transistor. The fourth insulating layer is provided between the one gate of the third transistor and the other of the source and the drain of the third transistor.

Description

Semiconductor device and method for manufacturing a semiconductor device.

[0001] One aspect of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a transistor and a method for manufacturing a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices having the same, methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] In recent years, the development of semiconductor devices has progressed, and for example, large-scale integrated circuits (LSIs) are being used in semiconductor devices. For example, central processing units (CPUs) and memory are used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memory) formed into chips by processing semiconductor wafers, and electrodes that serve as connection terminals are formed on them.

[0005] Semiconductor circuits such as CPUs and memory are mounted on circuit boards, such as printed circuit boards, and used as components in various electronic devices.

[0006] Furthermore, the technology of constructing transistors using semiconductor thin films formed on substrates with insulating surfaces is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors are attracting attention as other materials.

[0007] Transistors using oxide semiconductors are known to have extremely low leakage current in the non-conductive state. For example, Patent Document 1 discloses a low-power CPU that takes advantage of the low leakage current characteristic of transistors using oxide semiconductors. Also, for example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by taking advantage of the low leakage current characteristic of transistors using oxide semiconductors.

[0008] Furthermore, in recent years, with the miniaturization and weight reduction of electronic devices, there has been a growing demand for even higher density integrated circuits. There is also a need to improve the productivity of semiconductor devices, including integrated circuits. For example, Patent Document 3 and Non-Patent Document 1 disclose a technology for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film, thereby superimposing multiple memory cells.

[0009] Furthermore, if transistors can be oriented vertically, the density of integrated circuits can be increased. For example, Patent Document 4 discloses a vertical transistor in which the side surface of an oxide semiconductor is covered by a gate electrode via a gate insulating layer.

[0010] Japanese Patent Publication No. 2012-257187, Japanese Patent Publication No. 2011-151383, International Publication No. 2021 / 053473, Japanese Patent Publication No. 2013-211537

[0011] M. Oota et. al, “3D-Stacked CAAC-In-Ga-Zn Oxide FETs with Gate Length of 72nm”, IEDM Tech. Dig. , 2019, pp. 50-53

[0012] Various measures can be taken to achieve miniaturization and high integration of memory devices, such as reducing the number of transistors and other elements that make up the memory device, miniaturizing the elements themselves, and devising the layout of the elements. On the other hand, there are cases where these measures have a trade-off relationship with the performance of the memory device (for example, data retention characteristics, operating speed, power consumption, etc.).

[0013] For example, DRAM (Dynamic Random Access Memory), which consists of one transistor and one capacitive element, is a well-known memory device with a small number of elements. However, due to its configuration, DRAM requires a refresh operation because both data writing and reading must be performed by a single transistor, which presents challenges in terms of power consumption.

[0014] For example, SRAM (Static Random Access Memory) is a well-known memory device that offers low power consumption and high-speed operation. However, SRAM requires at least six transistors to be configured, posing a challenge in terms of miniaturization.

[0015] One aspect of the present invention aims to provide a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a transistor with a large on-current. Alternatively, one aspect of the present invention aims to provide a transistor with good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a semiconductor device or memory device with low power consumption. Alternatively, one aspect of the present invention aims to provide a semiconductor device or memory device with a fast operating speed. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device, memory device, or transistor.

[0016] Alternatively, one aspect of the present invention aims to provide a method for manufacturing a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated. Alternatively, one aspect of the present invention aims to provide a method for manufacturing a transistor with a large on-current. Alternatively, one aspect of the present invention aims to provide a method for manufacturing a transistor with good electrical characteristics. Alternatively, one aspect of the present invention aims to provide a method for manufacturing a semiconductor device or memory device with low power consumption. Alternatively, one aspect of the present invention aims to provide a method for manufacturing a semiconductor device or memory device with a high operating speed. Alternatively, one aspect of the present invention aims to provide a novel method for manufacturing a semiconductor device, memory device, or transistor.

[0017] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0018] To solve the aforementioned problems and realize a memory device that is miniaturized, highly integrated, and high-performance (excellent retention characteristics, fast read speed, low power consumption, etc.), it is preferable to miniaturize and arrange the transistors that constitute the memory device, and to use different transistors for each operation of the memory device (data writing, data reading selection / deselection, and data reading). Furthermore, from the viewpoint of reducing the number of manufacturing steps and costs, it is preferable for each transistor to share some of its components with one another.

[0019] Based on the above, one aspect of the present invention comprises a first conductive layer to a fifth conductive layer, a semiconductor layer, and a first insulating layer to a seventh insulating layer, wherein the first insulating layer is located on top of the first conductive layer, the second conductive layer is located on top of the first insulating layer, the second insulating layer is located on top of the second conductive layer, the third conductive layer is located on top of the second insulating layer, the fourth conductive layer is located on top of the third insulating layer, and the first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, the third insulating layer, the fourth conductive layer, and the fourth insulating layer. The edge layer has an opening that reaches the first conductive layer, the fifth insulating layer is located on the side of the opening of the second conductive layer, the sixth insulating layer is located on the side of the opening of the fourth conductive layer, the semiconductor layer is in contact with the upper surface of the first conductive layer, the side of the first insulating layer, the side of the fifth insulating layer, the side of the second insulating layer, the side of the third conductive layer, the side of the third insulating layer, the side of the sixth insulating layer, and the side of the fourth insulating layer within the opening, the seventh insulating layer is located on the semiconductor layer, the fifth conductive layer is located on the seventh insulating layer, and the fifth conductive layer is located on the opening and has a second region located on the opening and in contact with the semiconductor layer.

[0020] Furthermore, in the above, the first conductive layer and the third conductive layer each contain a first element and oxygen, the second conductive layer and the fourth conductive layer each contain a second element, and the fifth insulating layer and the sixth insulating layer each contain a second element and oxygen, wherein the first element is preferably one or more of indium, tin, and silicon, and the second element is preferably one or more of tantalum, tungsten, and aluminum.

[0021] Furthermore, in the above, it is preferable that the height of the upper surface of the seventh insulating layer in the region where the surface to be formed is parallel to the upper surface of the first conductive layer is higher than the height of the upper surface of the second conductive layer.

[0022] Furthermore, in the above, it is preferable that the semiconductor layer contains indium and oxygen, and that the first insulating layer, second insulating layer, third insulating layer, and fourth insulating layer each contain silicon and oxygen.

[0023] Furthermore, in the above, it is preferable to have a first layer between the seventh insulating layer and the first region, and the height of the upper surface of the first layer is higher than the height of the upper surface of the second conductive layer.

[0024] Furthermore, in the above, it is preferable that the semiconductor layer contains indium and oxygen, and that the first insulating layer, second insulating layer, third insulating layer, and fourth insulating layer each contain silicon and oxygen.

[0025] Furthermore, in the above, the semiconductor layer preferably has a third region located inside the opening and a fourth region located outside the opening, and the second region is in contact with the upper surface of the fourth region.

[0026] Furthermore, in the above, it is preferable that the semiconductor layer contains indium and oxygen, and that the first insulating layer, second insulating layer, third insulating layer, and fourth insulating layer each contain silicon and oxygen.

[0027] Furthermore, one aspect of the present invention is a method for manufacturing a semiconductor device, in which a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, a fourth conductive layer, and a fourth insulating layer are formed in this order, each having an overlapping region; an opening reaching the first conductive layer is formed in the first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, the third insulating layer, the fourth conductive layer, and the fourth insulating layer; and a first treatment is performed to oxidize the side surface of the second conductive layer and the side surface of the fourth conductive layer within the opening, thereby forming a fifth insulating layer on the side surface of the second conductive layer and a sixth insulating layer on the side surface of the fourth conductive layer.

[0028] Furthermore, in the above, the first treatment is preferably a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere.

[0029] Furthermore, in the above, after the formation of the fifth insulating layer and the sixth insulating layer, a semiconductor film is formed in contact with the opening and the upper surface of the fourth insulating layer, respectively, and a first insulating film and a first conductive film are formed on the semiconductor film in this order. A portion of each of the first conductive film, the first insulating film, and the semiconductor film is removed to expose the upper surface of the fourth insulating layer, and a fifth conductive layer is formed from the first conductive film, a seventh insulating layer from the first insulating film, and a semiconductor layer from the semiconductor film, respectively. Preferably, the sixth conductive layer is formed on the fifth conductive layer, on the seventh insulating layer, and on the semiconductor layer so as to have a region that overlaps with the opening.

[0030] Furthermore, in the above, after the formation of the fifth insulating layer and the sixth insulating layer, a semiconductor film is formed in contact with the opening and the upper surface of the fourth insulating layer, respectively, and a first insulating film and a first film are formed on the semiconductor film in this order, and a part of the first film, the first insulating film and the semiconductor film is removed to expose the upper surface of the fourth insulating layer, and a first layer is formed from the first film, a seventh insulating layer from the first insulating film and a semiconductor layer from the semiconductor film, respectively, a resist mask is formed on the fourth insulating layer so as not to overlap with the first layer, a part of the first layer is removed to form a second layer whose upper surface height is higher than the upper surface height of the second conductive layer, the resist mask is removed, and a first conductive film is formed on the second layer, the seventh insulating layer, the semiconductor layer and the fourth insulating layer so as to fill the opening, and a part of the first conductive film is removed to form a seventh conductive layer having a region that overlaps with the opening.

[0031] Furthermore, in the above, after the formation of the fifth insulating layer and the sixth insulating layer, a semiconductor film is formed in contact with the inside of the opening and the upper surface of the fourth insulating layer, respectively, and a portion of the semiconductor film is removed to form a first semiconductor layer having a region that overlaps with the opening and is in contact with the upper surface of the fourth insulating layer. A first insulating film and a first conductive film are formed on the first semiconductor layer in this order, and a portion of the first conductive film, the first insulating film, and the first semiconductor layer is removed to form an eighth conductive layer, a seventh insulating layer, and a second semiconductor layer, respectively, whose heights are roughly the same outside the opening. It is preferable to form a ninth conductive layer having a region that overlaps with the second semiconductor layer on the eighth conductive layer, the seventh insulating layer, and the second semiconductor layer.

[0032] According to one aspect of the present invention, a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a transistor with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a transistor with good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device or memory device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device or memory device with a fast operating speed can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device, memory device, or transistor can be provided.

[0033] Alternatively, according to one aspect of the present invention, a method for manufacturing a semiconductor device, memory device, or transistor that can be miniaturized or highly integrated can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a transistor with a large on-current can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a transistor with good electrical characteristics can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a semiconductor device or memory device with low power consumption can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a semiconductor device or memory device with a high operating speed can be provided. Alternatively, according to one aspect of the present invention, a method for manufacturing a novel semiconductor device, memory device, or transistor can be provided.

[0034] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0035] Figure 1A is a plan view showing an example of a semiconductor device. Figures 1B and 1C are cross-sectional views showing an example of a semiconductor device. Figure 1D is a circuit diagram illustrating a semiconductor device. Figure 2A is a cross-sectional view showing an example of a semiconductor device. Figure 2B is a plan view showing an example of a semiconductor device. Figures 3A, 3B, 3C, and 3D are cross-sectional views showing an example of a semiconductor device. Figure 4A is a plan view showing an example of a semiconductor device. Figures 4B and 4C are cross-sectional views showing an example of a semiconductor device. Figure 5A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 5B and 5C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 6A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 6B and 6C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 7A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 7B and 7C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 8A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 8B and 8C are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figure 9A is a plan view showing an example of a method for manufacturing a semiconductor device. Figures 9B and 9C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 10A is a plan view showing an example of a semiconductor device manufacturing method. Figures 10B and 10C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 11A is a plan view showing an example of a semiconductor device manufacturing method. Figures 11B and 11C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 12A is a plan view showing an example of a semiconductor device manufacturing method. Figures 12B and 12C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 13A is a plan view showing an example of a semiconductor device manufacturing method. Figures 13B and 13C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 14A is a plan view showing an example of a semiconductor device manufacturing method. Figures 14B and 14C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 15A is a plan view showing an example of a semiconductor device manufacturing method. Figures 15B and 15C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 16A is a plan view showing an example of a semiconductor device manufacturing method. Figures 16B and 16C are cross-sectional views showing an example of a semiconductor device manufacturing method.Figure 17A is a plan view showing an example of a semiconductor device manufacturing method. Figures 17B and 17C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 18A is a plan view showing an example of a semiconductor device manufacturing method. Figures 18B and 18C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 19A is a plan view showing an example of a semiconductor device manufacturing method. Figures 19B and 19C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 20A is a plan view showing an example of a semiconductor device manufacturing method. Figures 20B and 20C are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 21A is a block diagram showing an example of a memory device configuration. Figure 21B is a circuit diagram showing an example of a memory cell configuration. Figure 21C is a timing chart explaining the operation of a memory cell. Figure 22A is a plan view showing an example of a memory device configuration. Figure 22B is a perspective view showing an example of a memory device configuration. Figures 23A and 23B are cross-sectional views showing an example of a memory device configuration. Figure 24 is a cross-sectional view showing an example of a memory device configuration. Figure 25 is a cross-sectional view showing an example of a memory device configuration. Figures 26A and 26B show examples of electronic components. Figures 27A, 27B, and 27C show examples of large-scale computers. Figure 27D shows an example of space equipment. Figure 27E shows an example of a storage system applicable to data centers.

[0036] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0037] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0038] Furthermore, the position, size, and extent of each component shown in the drawings may not represent the actual position, size, and extent for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and extent disclosed in the drawings. For example, in the actual manufacturing process, layers or resist masks may be unintentionally reduced due to processes such as etching, but this may not be reflected in the drawings for the sake of ease of understanding.

[0039] In this specification, the ordinal numbers "first," "second," etc., are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Also, the ordinal numbers attached to components in one part of this specification may not be the same as the ordinal numbers attached to those components in other parts of this specification or in the claims.

[0040] Furthermore, a transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors in this specification include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0041] Furthermore, in this specification, a transistor is defined as an element having at least three terminals, including a gate (sometimes called a gate terminal or gate electrode), a drain (sometimes called a drain terminal, drain region, or drain electrode), and a source (sometimes called a source terminal, source region, or source electrode). It also has a region where a channel is formed between the drain and the source (also called a channel-forming region), and current can flow between the source and the drain through this channel-forming region. In this specification, the channel-forming region refers to the region through which current primarily flows.

[0042] Furthermore, the functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably.

[0043] In semiconductors, impurities refer to elements other than the main components that make up the semiconductor. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor or a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that alter the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specifically, these include, for example, hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Water can also function as an impurity. Furthermore, for example, the inclusion of impurities can cause oxygen vacancies (V) in the oxide semiconductor. Ｏ It can also be written as ).

[0044] Furthermore, in this specification, the terms "film" and "layer" can be interchanged depending on the context. For example, the term "conductive layer" can be changed to the term "conductive film," and vice versa. Similarly, the term "insulating film" can be changed to the term "insulating layer," and vice versa.

[0045] Furthermore, in this specification, "parallel" means a state in which two lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0046] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0047] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0048] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0049] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0050] Furthermore, in this specification, the term "node" can be replaced with "terminal," "wiring," "electrode," "conductive layer," "conductor," or "impurity region," depending on the circuit configuration and device structure. Also, terminals, wiring, etc., can be replaced with "node."

[0051] Furthermore, in this specification, "voltage" and "potential" may be used interchangeably as appropriate. "Voltage" is the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be replaced with "potential." Note that the ground potential does not necessarily mean 0V. Also, potential is relative, and as the reference potential changes, the potential applied to the wiring, the potential applied to the circuit, and the potential output from the circuit also change.

[0052] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, if two wires are described as "functioning as wires that supply a high-level potential," the high-level potentials provided by each wire do not have to be equal. Similarly, if two wires are described as "functioning as wires that supply a low-level potential," the low-level potentials provided by each wire do not have to be equal.

[0053] In this specification, unless otherwise specified, on-current refers to the drain current (also written as Id) when the transistor is in the ON state (also called the conducting state). Unless otherwise specified, the ON state refers to the state in an n-channel transistor where the voltage between the gate and source (gate voltage, also written as Vg or Vgs) is equal to or greater than the threshold voltage (also written as Vth), and in a p-channel transistor where it is less than or equal to the threshold voltage.

[0054] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conducting state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage Vgs between the gate and source is lower than the threshold voltage Vth (in a p-channel transistor, it is higher than Vth).

[0055] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0056] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it refers to a region in which the angle between the inclined side surface and the substrate surface or the surface to be formed (also called the taper angle) is less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0057] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0058] In this specification, terms such as "top," "bottom," "left," and "right" are used for convenience to explain the positional relationships between components with reference to the drawings. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms used are not limited to those described in this specification and can be appropriately rephrased depending on the situation.

[0059] In this specification, "approximately equal height" refers to a configuration in which the height from a reference surface (for example, a flat surface such as the substrate surface) is approximately equal in a cross-sectional view. For example, when a planarization treatment (typically chemical mechanical polishing (CMP) treatment) is performed, the treated surface will have approximately equal height. However, even after planarization, the height may not be exactly the same depending on the film material, but in this specification, this is also considered to be "approximately equal height".

[0060] In this specification, "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also called oxide semiconductors or simply OS), etc. For example, when a metal oxide is used in the semiconductor layer of a transistor, the metal oxide may be called an oxide semiconductor. In other words, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or oxide semiconductor. Metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be called metal oxide nitrides.

[0061] (Embodiment 1) This embodiment describes a semiconductor device, a method for manufacturing a semiconductor device, and the like according to one aspect of the present invention.

[0062] One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer.

[0063] The first to third transistors all have a vertical transistor structure (a transistor structure in which the source and drain are located at different heights relative to the substrate surface, and the drain current flows in the vertical direction). Therefore, miniaturization and reduction in occupied area can be achieved compared to planar transistors in which the source and drain are located on the same plane.

[0064] Herein, for each of the first to third transistors, the terminal located on the lower side (substrate side) of the source or drain will be referred to as "one of the source or drain terminals," and the terminal located on the upper side will be referred to as "the other of the source or drain terminals."

[0065] The first to third transistors are stacked in this order, sharing some components. Therefore, the overall footprint of the semiconductor device can be reduced compared to when each transistor is placed adjacent to another on the same plane. Furthermore, because some components are shared among the transistors, the number of manufacturing steps and costs associated with the overall semiconductor device can be reduced compared to when each transistor is placed individually.

[0066] Of the first to third transistors, the first transistor is a vertical transistor with a GAA (Gate All Around) structure in which, in a plan view, the gate surrounds a semiconductor layer that functions as a channel formation region. The second transistor is a vertical transistor with a CAA (Channel All Around) structure in which, in a plan view, a semiconductor layer that functions as a channel formation region surrounds the gate. The third transistor is a vertical transistor having two gates (a first gate and a second gate), with a structure in which, in a plan view, a semiconductor layer that functions as a channel formation region surrounds the first gate, and the second gate surrounds the said semiconductor layer.

[0067] The other source or drain of the first transistor is connected to one source or drain of the second transistor. The other source or drain of the second transistor is connected to one source or drain of the third transistor. The gate of the second transistor is connected to the first gate of the third transistor and the other source or drain of the third transistor.

[0068] The first insulating layer has a region sandwiched between the source or drain of the first transistor and the gate of the first transistor. The second insulating layer has a region sandwiched between the gate of the first transistor and the other source or drain of the second transistor (which is also the source or drain of the third transistor). The third insulating layer has a region sandwiched between the other source or drain of the second transistor and the second gate of the third transistor. The fourth insulating layer has a region overlapping the second gate of the third transistor.

[0069] The first insulating layer, the gate of the first transistor, the second insulating layer, the other of the source or drain of the second transistor, the third insulating layer, the second gate of the third transistor, and the fourth insulating layer are provided with openings that reach either the source or the drain of the first transistor.

[0070] Within the opening, an insulating layer (the fifth insulating layer) formed by oxidation of the gate of the first transistor is provided on the side surface of the gate of the first transistor. Also within the opening, an insulating layer (the sixth insulating layer) formed by oxidation of the gate of the second gate of the third transistor is provided on the side surface of the second gate of the third transistor. The fifth insulating layer functions as the gate insulating layer of the first transistor, and the sixth insulating layer functions as the second gate insulating layer of the third transistor.

[0071] Furthermore, within the opening, a semiconductor layer is provided in contact with each of the following surfaces: the upper surface of one source or drain of the first transistor, the side surface of the first insulating layer, the side surface of the fifth insulating layer, the side surface of the second insulating layer, the other side surface of the source or drain of the second transistor, the side surface of the third insulating layer, the side surface of the sixth insulating layer, and the side surface of the fourth insulating layer. The semiconductor layer has regions that function as channel formation regions for each of the first to third transistors. For example, silicon can be used as the semiconductor layer. Alternatively, for example, an oxide semiconductor can be used. By using an oxide semiconductor, the short-channel effect is less likely to occur even in minute transistors, and transistors with extremely low off-currents can be realized compared to those using silicon.

[0072] Short-channel effects refer to the degradation of electrical characteristics that becomes apparent with the miniaturization of transistors (reduction of channel length). Specific examples of short-channel effects include a shift of the threshold voltage towards the normally-on characteristic, a decrease in the on-off ratio (ratio of on-current to off-current), an increase in the subthreshold swing value (sometimes denoted as the S value), and an increase in off-current. Here, the S value refers to the change in gate voltage in the subthreshold region where the drain current is changed by an order of magnitude while the drain voltage remains constant.

[0073] An insulating layer is provided on the semiconductor layer, which functions as a gate insulating layer for the second transistor and a first gate insulating layer for the third transistor. A conductive layer is provided on the insulating layer, which functions as the gate for the second transistor and the first gate for the third transistor, so as to fill the opening.

[0074] Here, the height of the bottom surface of the conductive layer (height as seen from the substrate surface) is higher than the height of the top surface of the gate of the first transistor. Furthermore, the conductive layer has a region located outside the opening, and in this region, the conductive layer and the aforementioned semiconductor layer are in contact.

[0075] A semiconductor device according to one aspect of the present invention has the above-described configuration, thereby realizing a storage device in which the third transistor functions as a data writing transistor, the second transistor as a data reading selection / deselection transistor, and the first transistor as a data reading transistor.

[0076] One aspect of the present invention is a semiconductor device composed of three transistors (first to third transistors), which is more transistors than a DRAM. However, vertical transistors can be applied to each transistor, and they can be stacked. Therefore, even when the semiconductor device according to one aspect of the present invention is used as a memory device, the occupied area can be kept to the same level as a DRAM. Furthermore, since the three transistors in the semiconductor device according to one aspect of the present invention share some of their respective components, the number of manufacturing processes and costs for the entire semiconductor device can be reduced compared to when each transistor is provided independently.

[0077] Furthermore, oxide semiconductors can be used in the semiconductor layers of the three transistors in one embodiment of the present invention. As described above, by using an oxide semiconductor layer as a semiconductor layer that functions as a channel formation region, a transistor with extremely low off-current can be realized. Therefore, by using such a transistor in a memory device, a memory device with extremely excellent data retention characteristics can be made. Consequently, refreshing can be eliminated or the frequency of refreshing can be reduced, and a memory device with extremely low power consumption can be realized. For example, power consumption can be reduced to the same level as SRAM.

[0078] Thus, by applying a semiconductor device according to one aspect of the present invention to a storage device, it is possible to realize an extremely high-performance storage device that not only possesses the advantages of conventional storage devices such as DRAM and SRAM, but also overcomes their disadvantages.

[0079] In the following, a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0080] <Example of Semiconductor Device Configuration 1> Figure 1A shows a plan view (also called a top view) of the semiconductor device 100. Figure 1B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 1A. Figure 1C shows a cross-sectional view along the dashed line A3-A4 shown in Figure 1A. Figure 1D shows an equivalent circuit diagram of the semiconductor device 100. Note that in Figure 1A, some components of the semiconductor device 100 (such as the insulating layer) are omitted. In subsequent drawings of semiconductor devices, some components may also be omitted, similar to Figure 1A.

[0081] The semiconductor device 100 is provided on a substrate 102. Although not shown in Figure 1B, etc., an insulating layer that functions as an underlay can also be provided between the substrate 102 and the semiconductor device 100. The semiconductor device 100 includes transistor 10_1, transistor 10_2, transistor 10_3, insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110d.

[0082] Transistors 10_1, 10_2, and 10_3 are stacked in this order. Transistors 10_1 to 10_3 have overlapping regions. Also, transistors 10_1 to 10_3 share some components.

[0083] The transistor 10_1 has a conductive layer 112a, a semiconductor layer 108, an insulating layer 116a, and a conductive layer 114a. The conductive layer 112a functions as either a source or a drain. The semiconductor layer 108 has a region that functions as either a source or a drain (first region), a region that functions as a channel forming region (second region), and a region that functions as the other source or drain (third region). The insulating layer 116a functions as a gate insulating layer. The conductive layer 114a functions as a gate. Note that the insulating layer 116a is an insulating layer formed by the oxidation of a part of the conductive layer 114a.

[0084] The transistor 10_2 has a semiconductor layer 108, a conductive layer 112b, an insulating layer 106, and a conductive layer 104. The semiconductor layer 108 has a region that functions as either the source or the drain (third region), a region that functions as a channel forming region (fourth region), and a region that functions as the other of the source or the drain (fifth region). The conductive layer 112b functions as the other of the source or the drain. The insulating layer 106 functions as a gate insulating layer. The conductive layer 104 functions as the gate. In Figure 1B, etc., an example is shown in which the conductive layer 104 is composed of a conductive layer 104a and a conductive layer 104b on the conductive layer 104a.

[0085] Here, the third region of the semiconductor layer 108 functions as the other of the source or drain of transistor 10_1, as described above, and also functions as one of the source or drain of transistor 10_2.

[0086] Transistor 10_3 has a conductive layer 112b, a conductive layer 104, an insulating layer 106, a semiconductor layer 108, an insulating layer 116b, and a conductive layer 114b. The conductive layer 112b functions as either a source or a drain. The conductive layer 104 functions as either a source or a drain, and also functions as a first gate. The insulating layer 106 functions as a first gate insulating layer. The semiconductor layer 108 has a region that functions as either a source or a drain (a fifth region), a region that functions as a channel forming region (a sixth region), and a region that functions as either a source or a drain (a seventh region). The insulating layer 116b functions as a second gate insulating layer. The conductive layer 114b functions as a second gate. Note that the insulating layer 116b is an insulating layer formed by the oxidation of a part of the conductive layer 114b.

[0087] Here, the fifth region of the semiconductor layer 108 is a region that functions as either the source or the drain of transistor 10_2, as described above, and also functions as either the source or the drain of transistor 10_3.

[0088] Furthermore, as described above, the conductive layer 112b functions as the other source or drain of transistor 10_2, and also functions as one of the source or drain of transistor 10_3.

[0089] An insulating layer 110a is provided on the conductive layer 112a. A conductive layer 114a is provided on the insulating layer 110a. An insulating layer 110b is provided on the conductive layer 114a. A conductive layer 112b is provided on the insulating layer 110b. An insulating layer 110c is provided on the conductive layer 112b. A conductive layer 114b is provided on the insulating layer 110c. An insulating layer 110d is provided on the conductive layer 114b. A conductive layer 104b is provided on the insulating layer 110d.

[0090] Figures 1A to 1C show examples in which conductive layers 112a and 112b are provided extending in the Y direction, respectively. Also shown are examples in which conductive layers 114a and 114b are provided extending in the X direction, respectively. When multiple conductive layers are stacked in this manner, it is preferable to provide them so that the extension directions of each conductive layer intersect with each other. This allows for wider spacing between conductive layers with the same extension direction compared to, for example, a case where all conductive layers extend in the same direction. Therefore, parasitic capacitance between each conductive layer can be reduced, and the adverse effects of such parasitic capacitance on the operation of the semiconductor device (e.g., slower operation speed) can be suppressed.

[0091] The conductive layer 112a, insulating layer 110a, conductive layer 114a, insulating layer 110b, conductive layer 112b, insulating layer 110c, conductive layer 114b, insulating layer 110d, and conductive layer 104b have overlapping regions. The insulating layer 110a, conductive layer 114a, insulating layer 110b, conductive layer 112b, insulating layer 110c, conductive layer 114b, and insulating layer 110d have openings 120 that reach the conductive layer 112a.

[0092] The top surface shape of the opening 120 can be, for example, circular or elliptical. The top surface shape of the opening 120 can also be a polygon such as a triangle, quadrilateral (including rectangle, rhombus, and square), or a polygon with rounded corners. As shown in Figure 1A, the top surface shape of the opening 120 is preferably circular. By making the top surface shape of the opening 120 circular, the processing accuracy when forming the opening 120 can be improved, and a fine-sized opening 120 can be formed. In this specification, the term "circular" is not limited to a perfect circle.

[0093] In Figure 1B, etc., the film thickness in the region of the conductive layer 112a that overlaps with the opening 120 is shown to be approximately equal to the film thickness in the region that does not overlap with the opening 120, but this is not always the case. Depending on the material used for the conductive layer 112a, the processing conditions of the opening 120, etc., the film thickness in the region of the conductive layer 112a that overlaps with the opening 120 may be thinner than the film thickness in the region that does not overlap with the opening 120.

[0094] An insulating layer 116a is provided on the side of the conductive layer 114a facing the opening 120, and an insulating layer 116b is provided on the side of the conductive layer 114b facing the opening 120. The insulating layer 116a is provided so as to be sandwiched between insulating layers 110a and 110b, and the insulating layer 116b is provided so as to be sandwiched between insulating layers 110c and 110d. The insulating layer 116a is an insulating layer formed by the oxidation of a part of the conductive layer 114a, and the insulating layer 116b is an insulating layer formed by the oxidation of a part of the conductive layer 114b. That is, the insulating layer 116a has the elements and oxygen that the conductive layer 114a has, and the insulating layer 116b has the elements and oxygen that the conductive layer 114b has. It is preferable to use conductive materials for each of the conductive layers 114a and 114b that have low electrical resistance, are easy to process, and whose surfaces can be oxidized relatively easily. For example, conductive layers 114a and 114b can be made from materials such as tantalum, tungsten, or aluminum. When tantalum is used for conductive layers 114a and 114b, insulating layers 116a and 116b will be made from tantalum oxide. Insulating layers 116a and 116b can be formed by oxidizing the side surface of conductive layer 114a on the side of the opening 120 and the side surface of conductive layer 114b on the side of the opening 120 after the opening 120 has been formed. For example, insulating layers 116a and 116b can be formed by heat treatment in an oxygen-containing atmosphere or by plasma treatment (oxygen plasma treatment) in an oxygen-containing atmosphere. The formation of insulating layers 116a and 116b will also be explained in <Example of Semiconductor Device Manufacturing Method 1>.

[0095] It is preferable to use conductive materials for conductive layers 112a and 112b that are different from conductive layers 114a and 114b, specifically conductive materials that are resistant to oxidation, or conductive materials that can maintain low electrical resistance even if oxidized. For example, conductive layers 112a and 112b can be made from materials such as titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, oxides containing indium and tin (also called indium tin oxide, ITO), or oxides containing indium, tin and silicon (also called ITSO). This prevents oxidation of the surfaces of conductive layers 112a and 112b even when processing (heat treatment, oxygen plasma treatment, etc.) is performed to form the insulating layers 116a and 116b after the formation of the opening 120. Alternatively, even if oxidation occurs, the electrical resistance of the conductive layer 112a and the conductive layer 112b can be kept low.

[0096] Within the opening 120, a semiconductor layer 108 is provided in contact with the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the insulating layer 116a, the side surface of the insulating layer 110b, the side surface of the conductive layer 112b, the side surface of the insulating layer 110c, the side surface of the insulating layer 116b, and the side surface of the insulating layer 110d. As described above, the semiconductor layer 108 has a first region to a seventh region.

[0097] The first region is a region that functions as either the source or the drain of transistor 10_1.

[0098] The second region is a region that functions as the channel formation region for transistor 10_1.

[0099] The third region functions as either the source or the drain of transistor 10_1, and also functions as either the source or the drain of transistor 10_2.

[0100] The fourth region is a region that functions as the channel formation region for transistor 10_2.

[0101] The fifth region functions as either the source or the drain of transistor 10_2, and also functions as either the source or the drain of transistor 10_3.

[0102] The sixth region is a region that functions as the channel formation region for transistor 10_3.

[0103] The seventh region is the region that functions as either the source or the drain of transistor 10_3.

[0104] The source region, drain region, and channel formation region of transistors 10_1 to 10_3, as well as the channel length and channel width, are explained in detail in Figures 2A and 2B.

[0105] The semiconductor material used in the semiconductor layer 108 is not particularly limited. For example, a semiconductor made of a single element or a compound semiconductor can be used. Examples of semiconductors made of single elements include silicon and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. It is also possible to have these semiconductor materials contain impurities that act as dopants.

[0106] The crystallinity of the semiconductor material used in the semiconductor layer 108 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0107] For example, silicon can be used for the semiconductor layer 108. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon for the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon for the channel formation region have high field-effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon for the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speed.

[0108] It is preferable to use an oxide semiconductor for the semiconductor layer 108. Transistors using oxide semiconductors (OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. In addition, OS transistors have significantly lower off-currents compared to transistors using silicon (Si transistors). Therefore, for example, by using an OS transistor as a writing transistor in a memory device, the written data can be retained for a long period of time. Furthermore, this eliminates the need for refreshing or reduces the frequency of refreshing, thereby reducing the power consumption of the memory device. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0109] Each of the insulating layers 110a, 110b, 110c, and 110d may be an inorganic insulating layer, an organic insulating layer, or both. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. It is preferable that each of the insulating layers 110a, 110b, 110c, and 110d has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0110] Each of the insulating layers 110a, 110b, 110c, and 110d has a region that is in contact with the semiconductor layer 108. When an oxide semiconductor is used for the semiconductor layer 108, it is preferable that the regions of each of the insulating layers 110a, 110b, 110c, and 110d that are in contact with the semiconductor layer 108 contain oxygen. It is also preferable that oxygen is released when heat is applied. As a result, oxygen is supplied to the semiconductor layer 108 from each of the insulating layers 110a, 110b, 110c, and 110d, and oxygen deficiencies (V) in the semiconductor layer 108 are reduced. Ｏ ), and defects in which hydrogen enters the oxygen vacancy (hereinafter referred to as V Ｏ This can reduce the amount of H. Therefore, it is preferable to use one or more of the above-mentioned oxides and oxiditrides in the regions of insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110d that are in contact with the semiconductor layer 108.

[0111] An insulating layer 106 is provided on the semiconductor layer 108. The insulating layer 106 has a shape that reflects the shape of the semiconductor layer 108 provided within the opening 120.

[0112] Figure 1B and others show an example in which the upper surface height of the insulating layer 106 in the region where the surface to be formed is parallel to the upper surface of the conductive layer 112a is approximately the same as the upper surface height of the conductive layer 114a (preferably higher than the upper surface height of the conductive layer 114a).

[0113] A conductive layer 104a is provided on the insulating layer 106. Preferably, the height of the bottom surface of the conductive layer 104a is set to be higher than the height of the top surface of the conductive layer 114a. Furthermore, preferably, the height of the bottom surface of the conductive layer 104a is set to be lower than the height of the bottom surface of the conductive layer 112b. In other words, it is preferable that the conductive layer 104, which functions as the gate of transistors 10_2 and 10_3 respectively, and the channel formation region of transistor 10_1 do not overlap in a cross-sectional view (Z direction). This reduces the effect of the electric field from the conductive layer 104 on the carriers in the channel formation region of transistor 10_1, thereby reducing adverse effects on the operation of transistor 10_1 (for example, malfunction).

[0114] The conductive layer 104a is provided so as to fill the opening 120. The upper surface of the conductive layer 104a, the upper end of the insulating layer 106 (the highest part when viewed from the substrate surface), the upper end of the semiconductor layer 108 (the highest part when viewed from the substrate surface), and the upper surface of the insulating layer 110d are all approximately the same height.

[0115] A conductive layer 104b is provided on the conductive layer 104a, the insulating layer 106, the semiconductor layer 108, and the insulating layer 110d. The conductive layer 104b is provided so as to have a region that overlaps with the opening 120. Furthermore, as shown in Figure 1A, the conductive layer 104b is provided so as to have a region that is located outside the opening 120 in a plan view. The conductive layer 104b has regions that are in contact with the upper surface of the conductive layer 104a, the upper end of the insulating layer 106, the upper end of the semiconductor layer 108, and the upper surface of the insulating layer 110d. Unlike the conductive layers 112a, 114a, 112b, and 114b mentioned above, the conductive layer 104b does not extend in any direction in a plan view, but is provided in an island-like manner.

[0116] In terms of the circuit configuration of the semiconductor device 100, as shown in Figure 1D, the other source or drain of transistor 10_1 is connected to one source or drain of transistor 10_2 (corresponding to the third region of semiconductor layer 108). Also, the other source or drain of transistor 10_2 is connected to one source or drain of transistor 10_3 (in Figure 1D, the wiring drawn out from this connection point is shown as conductive layer 112b). Furthermore, the other source or drain of transistor 10_3 is connected to the first gate of transistor 10_3 and the gate of transistor 10_2 (in Figure 1D, the wiring connecting each of these is shown as conductive layer 104).

[0117] For example, by using transistor 10_3 as a data writing transistor, transistor 10_2 as a data reading selection / deselection transistor, and transistor 10_1 as a data reading transistor, the semiconductor device 100 can be operated as a memory device.

[0118] This memory device can utilize vertical transistors for all three transistors (transistors 10_1 to 10_3), and can be stacked and arranged with some components shared. Therefore, the number of manufacturing steps and costs associated with the memory device can be reduced compared to the case where each transistor is provided independently.

[0119] Furthermore, since OS transistors can be used as the three transistors in the memory device, the off-current can be made much smaller than that of Si transistors. Therefore, it is possible to realize an extremely high-performance memory device that achieves both excellent retention characteristics and low power consumption.

[0120] Further details regarding specific configuration examples, operation examples, and other aspects when a semiconductor device according to one aspect of the present invention is applied as a memory device will be described in Embodiment 3.

[0121] In the following, the channel length and channel width of transistors 10_1, 10_2, and 10_3 will be described with reference to Figures 2A and 2B. Figure 2A is an enlarged cross-sectional view of the semiconductor device 100 in the XZ plane shown in Figure 1B. Figure 2B is an enlarged plan view of the semiconductor device 100 shown in Figure 1A.

[0122] The region of the semiconductor layer 108 that is in contact with the conductive layer 112a functions as either the source region or the drain region of the transistor 10_1. In other words, this region corresponds to the first region of the semiconductor layer 108.

[0123] The region of the semiconductor layer 108 that faces the conductive layer 114a via the insulating layer 116a functions as the channel formation region of the transistor 10_1. In other words, this region corresponds to a second region of the semiconductor layer 108.

[0124] The region of the semiconductor layer 108 located at the height between the upper surface of the conductive layer 114a and the lower surface of the conductive layer 104a functions as either the source region or the drain region of transistor 10_1, and also functions as either the source region or the drain region of transistor 10_2. In other words, this region functions as a third region of the semiconductor layer 108.

[0125] At the height between conductive layer 114a and conductive layer 112b, the region of semiconductor layer 108 facing conductive layer 104a via insulating layer 106 functions as a channel formation region of transistor 10_2. In other words, this region functions as a fourth region of semiconductor layer 108.

[0126] The region of the semiconductor layer 108 that is in contact with the conductive layer 112b functions as either the source region or the drain region of transistor 10_2, and also functions as either the source region or the drain region of transistor 10_3. In other words, this region functions as a fifth region of the semiconductor layer 108.

[0127] The region of the semiconductor layer 108 that faces the conductive layer 114b via the insulating layer 116b functions as the channel formation region of the transistor 10_3. In other words, this region corresponds to a sixth region of the semiconductor layer 108.

[0128] The region of the semiconductor layer 108 that is in contact with the conductive layer 104b functions as the other of the source region or drain region of the transistor 10_3. In other words, this region corresponds to a seventh region of the semiconductor layer 108.

[0129] Furthermore, transistor 10_3 has regions that do not belong to the source region, drain region, or channel formation region. Specifically, these are the regions located at the height between conductive layer 112b and conductive layer 114b, and the regions located at the height between conductive layer 114b and conductive layer 104b in the semiconductor layer 108. These regions are high-resistance regions that can function as offset regions of transistor 10_3 and may obstruct the flow of current between the source and drain of transistor 10_3. However, in transistor 10_3, the conductive layer 104 can also function as a gate electrode, so when an electric field is applied from the conductive layer 104, another channel formation region (also called a back channel formation region) of transistor 10_3 can be formed in the entire region of the semiconductor layer 108 facing the conductive layer 104 (here, conductive layer 104a). As a result, even though transistor 10_3 has the above-mentioned offset region structure, it is possible to pass current between the source and drain through this channel formation region.

[0130] The channel length of transistor 10_1 can be considered as the length of the channel formation region of transistor 10_1 (the second region of the semiconductor layer 108). Therefore, the channel length of transistor 10_1 can be said to be the length of the region of the semiconductor layer 108 facing the conductive layer 114a. In Figure 2A, the channel length L1 of transistor 10_1 is indicated by a dashed double arrow.

[0131] The channel length of transistor 10_2 can be considered as the length of the channel formation region (the fourth region of the semiconductor layer 108) of transistor 10_2. Therefore, the channel length of transistor 10_2 can be said to be the length of the region of the semiconductor layer 108 that faces the conductive layer 104a at the height between the conductive layer 114a and the conductive layer 112b. In Figure 2A, the channel length L2 of transistor 10_2 is indicated by a dashed double arrow.

[0132] The channel length of transistor 10_3 can be considered as the length of the channel formation region (the sixth region of the semiconductor layer 108) of transistor 10_3. Therefore, the channel length of transistor 10_3 can be said to be the length of the region of the semiconductor layer 108 facing the conductive layer 114b. In Figure 2A, the channel length L3 of transistor 10_3 is indicated by a dashed double arrow.

[0133] In the case of planar transistors, the minimum achievable channel length is limited by the exposure limit of photolithography during transistor fabrication. In contrast, the three transistors in the semiconductor device 100 according to one aspect of the present invention are all vertical transistors, and the channel length of each transistor can be set by the respective film thicknesses of the conductive layer 114a, the insulating layer 110b, and the conductive layer 114b. Therefore, the channel length of each transistor can be reduced to an extremely small value that exceeds the exposure limit of photolithography (for example, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, or 5 nm to 10 nm). Consequently, the on-current of the transistor can be increased, and the frequency characteristics can be improved. For example, by applying the semiconductor device 100 according to one aspect of the present invention to a memory device, a memory device with a high operating speed can be realized.

[0134] Furthermore, OS transistors can be used for the three transistors in the semiconductor device 100 according to one aspect of the present invention. Therefore, even with a configuration having an extremely short channel length as described above, the short-channel effect is less likely to occur compared to Si transistors. Consequently, even when the channel length is extremely short, the transistor can maintain good electrical characteristics.

[0135] Furthermore, OS transistors have a much smaller off-current than Si transistors. Therefore, by applying a semiconductor device 100 according to one aspect of the present invention to a memory device, an extremely high-performance memory device that achieves both excellent retention characteristics and low power consumption can be realized.

[0136] The channel width of transistor 10_1 can be considered as the length of the channel formation region of transistor 10_1 (the second region of the semiconductor layer 108) in a plan view. Similarly, the channel width of transistor 10_2 can be considered as the length of the channel formation region of transistor 10_2 (the fourth region of the semiconductor layer 108) in a plan view. Furthermore, the channel width of transistor 10_3 can be considered as the length of the channel formation region of transistor 10_3 (the sixth region of the semiconductor layer 108) in a plan view.

[0137] In other words, the channel widths of transistors 10_1, 10_2, and 10_3 can be described as the length of the contour of the aperture 120 in a plan view, where the semiconductor layer 108 is provided.

[0138] For example, if the upper surface shape of the opening 120 is a circle with a diameter D, as shown by the double-headed arrow in Figure 2B, and the opening 120 has a constant opening diameter (D) in the depth direction (Z direction), as shown in Figure 2A, then the channel widths of transistors 10_1, 10_2, and 10_3 can be said to correspond to D × π. In Figure 2B, the channel widths W1 of transistor 10_1, W2 of transistor 10_2, and W3 of transistor 10_3 (all D × π) are shown by the double-headed arrows.

[0139] Note that Figures 2A and 2B show an example configuration where the aperture 120 has a constant aperture diameter in the depth direction and the channel widths of transistors 10_1, 10_2, and 10_3 are all the same, but this is not limited to this configuration. If the aperture 120 has different aperture diameters depending on the position in the depth direction, the channel widths of transistors 10_1, 10_2, and 10_3 may be different.

[0140] The channel length L1 of transistor 10_1 is preferably smaller than the channel width W1. Similarly, the channel length L2 of transistor 10_2 is preferably smaller than the channel width W2. Similarly, the channel length L3 of transistor 10_3 is preferably smaller than the channel width W3. For example, the channel length of each transistor is preferably 0.1 times or more and 0.99 times or less than the channel width, and more preferably 0.5 times or more and 0.8 times or less. This makes it possible to realize a transistor that achieves both good electrical characteristics and high reliability.

[0141] The following describes the materials that can be used for each component of the semiconductor device 100. Note that some of the descriptions for certain components may overlap with those previously mentioned.

[0142] [Semiconductor Layer 108] The semiconductor material that can be used for the semiconductor layer 108 is not particularly limited. For example, a single-element semiconductor or a compound semiconductor can be used. For example, silicon or germanium can be used as a single-element semiconductor. For example, gallium arsenide and silicon germanium can be used as compound semiconductors. For example, organic materials having semiconductor properties or metal oxides having semiconductor properties (also called oxide semiconductors) can be used as compound semiconductors. In addition, these semiconductor materials can also be configured to include impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron).

[0143] The crystallinity of the semiconductor material used in the semiconductor layer 108 is not particularly limited, and either an amorphous semiconductor or a crystalline semiconductor (single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a crystalline semiconductor is preferable because it can suppress the degradation of transistor characteristics.

[0144] Silicon can be used for the semiconductor layer 108. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is LTPS.

[0145] Transistors using amorphous silicon for the semiconductor layer 108 can be formed on large glass substrates and can be manufactured at low cost. Transistors using polycrystalline silicon for the semiconductor layer 108 have high field-effect mobility and can operate at high speeds. Furthermore, transistors using microcrystalline silicon for the semiconductor layer 108 have higher field-effect mobility than transistors using amorphous silicon and can operate at high speeds.

[0146] The semiconductor layer 108 preferably has a metal oxide (oxide semiconductor).

[0147] Examples of metal oxides that can be used in the semiconductor layer 108 include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium, and tin. Gallium is more preferred for element M.

[0148] For example, the semiconductor layer 108 can be made of indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also written as IWO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. Alternatively, indium tin oxide containing silicon can be used.

[0149] For the formation of metal oxides, suitable formation methods include sputtering, atomic layer deposition (ALD), or vacuum deposition. However, when forming metal oxides by sputtering, the atomic ratio of the target material may differ from that of the metal oxide. In particular, with zinc, the atomic ratio of the metal oxide may be lower than that of the target material. Specifically, the atomic ratio of zinc in the metal oxide may be between 40% and 90% of that of the target material.

[0150] When forming metal oxides by ALD, it is preferable to use a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD). Thermal ALD is preferred because it exhibits extremely high step coverage. PEALD is also preferred because, in addition to exhibiting high step coverage, it allows for low-temperature film formation.

[0151] The composition of the metal oxide in the semiconductor layer 108 significantly affects the electrical characteristics and reliability of transistors 10_1, 10_2, and 10_3, respectively.

[0152] For example, by increasing the indium content of the metal oxide, a transistor with a high on-current can be realized. Also, for example, by using a metal oxide that does not contain gallium or has a low gallium content, a transistor with high reliability against positive bias application can be realized. Also, for example, by using a metal oxide with a low content of element M, a transistor with high reliability against positive bias application can be realized. Also, for example, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be realized.

[0153] Details of the metal oxide composition that can be used in the semiconductor layer 108 will be described later.

[0154] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 108. For example, a metal oxide layer having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, or a nanocrystalline (nc: nano-crystal) structure can be used. By using a crystalline metal oxide layer for the semiconductor layer 108, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable transistor can be realized. The CAAC structure is a crystalline structure in which multiple nanocrystals (typically multiple IGZO nanocrystals) have c-axis orientation, and in the a-b plane, the multiple nanocrystals are linked without orientation. In the CAAC structure, the crystal grains are not as clearly visible in the a-b plane as in the polycrystalline structure, thus enabling the realization of a highly reliable transistor.

[0155] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 108, the lower the defect level density in the semiconductor layer 108 can be. On the other hand, by using a metal oxide layer with low crystallinity, it is possible to realize a transistor that can carry a large current.

[0156] The semiconductor layer 108 can be a single layer or a stacked structure of two or more layers.

[0157] The thickness of the semiconductor layer 108 is preferably, for example, 1 nm to 20 nm, 3 nm to 15 nm, 5 nm to 12 nm, or 5 nm to 10 nm.

[0158] Here, we will explain the oxygen vacancies that may be formed in the semiconductor layer 108.

[0159] As described above, when an oxide semiconductor is used for the semiconductor layer 108, the hydrogen contained in the oxide semiconductor reacts with the oxygen bonded to the metal atoms to form water, creating oxygen vacancies (V) in the oxide semiconductor. Ｏ ) may be formed. Furthermore, a defect called V is formed when hydrogen is placed in the oxygen vacancy. Ｏ H can function as a donor, generating electrons as carriers. Additionally, some hydrogen can combine with oxygen atoms bonded to metal atoms, also generating electrons. Therefore, transistors using oxide semiconductors with high hydrogen content tend to exhibit fluctuating threshold voltages (for example, n-channel transistors are prone to normally-on characteristics). Furthermore, because hydrogen in oxide semiconductors is easily affected by stresses such as heat and electric fields, a high hydrogen content in the oxide semiconductor may degrade the reliability of the transistor.

[0160] V Ｏ H can function as a donor in oxide semiconductors. However, it is difficult to quantitatively evaluate such defects. Therefore, in oxide semiconductors, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration assuming no electric field is applied may be used as a parameter for oxide semiconductors, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration".

[0161] Based on the above, when an oxide semiconductor is used for the semiconductor layer 108, V in the semiconductor layer 108 Ｏ It is preferable to reduce H as much as possible to achieve high-purity intrinsic or substantially high-purity intrinsic. In this way, V ＯTo obtain an oxide semiconductor in which H is sufficiently reduced, removing impurities such as water and hydrogen in the oxide semiconductor (sometimes referred to as dehydration or dehydrogenation treatment) and supplying oxygen to the oxide semiconductor to form oxygen vacancies (V Ｏ ) are important to be repaired. V Ｏ By using an oxide semiconductor with sufficiently reduced defects such as H in a channel formation region of a transistor, stable electrical characteristics can be imparted. Note that supplying oxygen to the oxide semiconductor to repair oxygen vacancies (V Ｏ ) may be referred to as oxygenation treatment.

[0162] In the case where an oxide semiconductor is used for the semiconductor layer 108, the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region is preferably 1×10 １８ cm −３ or less, more preferably less than 1×10 １７ cm −３ , still more preferably less than 1×10 １６ cm −３ , still more preferably less than 1×10 １３ cm −３ , still more preferably less than 1×10 １２ cm −３ . Note that there is no particular limitation on the lower limit of the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region, and for example, it can be 1×10 −９ cm −３ .

[0163] A transistor including an oxide semiconductor (OS transistor) has extremely high field-effect mobility as compared with a transistor including amorphous silicon. In addition, the OS transistor has extremely low off-state current.

[0164] Therefore, the OS transistor is preferably applied to a memory device. For example, by applying the semiconductor device of one embodiment of the present invention including the OS transistor to a memory device, a memory device with smaller off-state current and extremely low power consumption can be realized as compared with the case of applying a semiconductor device including amorphous silicon.

[0165] OS transistors exhibit small fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0166] [Insulating Layer] In a transistor according to one aspect of the present invention, and in a semiconductor device to which a transistor according to one aspect of the present invention is applied, an inorganic insulating material or an organic insulating material can be used as the insulating layer (insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d, insulating layer 106, insulating layer 116a, and insulating layer 116b). Furthermore, a laminated structure of an inorganic insulating material and an organic insulating material can also be used as the insulating layer.

[0167] As the inorganic insulating material, one or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used.

[0168] In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content. The term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, silicon oxide-nitride refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride oxide refers to a material in which the nitrogen content is greater than the oxygen content.

[0169] For the analysis of oxygen and nitrogen content, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing elemental content, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0170] Furthermore, for evaluating the film density of insulating layers, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR) can be used. Differences in film density can also sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Even when applying the same material to the insulating layer, differences in film density can sometimes be observed as differences in contrast at the boundaries between these densities in the cross-sectional TEM image.

[0171] The nitrogen content of an insulating layer can be confirmed, for example, by energy-dispersive X-ray spectroscopy (EDX). For example, when silicon nitride, silicon oxynitride, etc. are used for the insulating layer, the nitrogen content can be evaluated using the ratio of the peak height of nitrogen to the peak height of silicon. In EDX, the peak of a given element refers to the point where the count number of that element reaches its maximum value in a spectrum where the energy of the characteristic X-ray is shown on the horizontal axis and the count number (detection value) of the characteristic X-ray is shown on the vertical axis. Alternatively, the difference in nitrogen content can be confirmed by using the count number at the characteristic X-ray energy specific to that element and comparing it with the count number of nitrogen to the count number of silicon. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0172] The hydrogen concentration in the insulating layer can be evaluated, for example, using SIMS.

[0173] When hydrogen diffuses into the semiconductor layer 108, it reacts with oxygen atoms contained in the oxide semiconductor to form water, creating oxygen vacancies (V) in the semiconductor layer 108. Ｏ ) may be formed in the semiconductor layer 108. Furthermore, V Ｏ H may be formed, and the carrier concentration in the semiconductor layer 108 may increase. By using a barrier film that suppresses hydrogen diffusion as an insulating layer in contact with the semiconductor layer 108, or as an insulating layer located around the semiconductor layer 108, oxygen vacancies (V) in the semiconductor layer 108 can be suppressed. Ｏ ) and V Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0174] Oxygen vacancies (V) in the channel formation regions of transistors 10_1, 10_2, and 10_3, respectively. Ｏ ) and V Ｏ H is preferably low. In particular, when the channel length is short, oxygen deficiency (V) in the channel formation region is preferable. Ｏ ) and V ＯThe effect of H on the electrical characteristics and reliability of each transistor becomes significant. For example, if V flows from the source region or drain region to the channel formation region... Ｏ When H diffuses, the carrier concentration in the channel formation region increases, which may cause fluctuations in the threshold voltage of each transistor or a decrease in reliability. Ｏ The effect of H diffusion on the electrical characteristics and reliability of each transistor increases as the channel length decreases. Semiconductor layer 108, in particular, oxygen vacancies (V) in the channel formation region. Ｏ ) and V Ｏ By reducing H, it is possible to realize transistors with short channel lengths that have good electrical characteristics and high reliability.

[0175] By using an insulating layer that releases oxygen as an insulating layer in contact with the semiconductor layer 108, or an insulating layer located around the semiconductor layer 108 (for example, insulating layer 106, insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d, etc.), oxygen can be supplied from the insulating layer to the semiconductor layer 108. By supplying oxygen to the channel formation region of the semiconductor layer 108, oxygen vacancies (V) in the semiconductor layer 108 can be reduced. Ｏ ) and V Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable. Other methods for supplying oxygen to the semiconductor layer 108 include heating in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.

[0176] It is preferable that the insulating layer in contact with the semiconductor layer 108, or the insulating layer located around the semiconductor layer 108, releases little impurities (e.g., water and hydrogen) from itself. The impurities referred to here are those that diffuse into the semiconductor layer 108, causing oxygen vacancies (V) in the semiconductor layer 108. Ｏ ) and V Ｏ This refers to substances that can adversely affect the electrical characteristics of a transistor, such as by generating hydrogen (H). By reducing the release of impurities, the diffusion of these impurities into the semiconductor layer 108 is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0177] In some cases, oxygen may be removed from the semiconductor layer 108 due to heat applied in a process after the formation of the semiconductor layer 108. However, oxygen is supplied to the semiconductor layer 108 from the insulating layer in contact with the semiconductor layer 108, or from the insulating layer located around the semiconductor layer 108, thereby preventing oxygen deficiencies (V) in the semiconductor layer 108. Ｏ ) and V Ｏ This makes it possible to suppress the increase in H. Furthermore, it increases the degree of freedom in the processing temperature during processes after the formation of the semiconductor layer 108. Specifically, the processing temperature can be increased even during processes after the formation of the semiconductor layer 108. Therefore, it is possible to form transistors that exhibit good electrical characteristics and high reliability.

[0178] [Insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d] Insulating layers 110a, 110b, 110c, and 110d can each be made of an inorganic insulating material or an organic insulating material. Insulating layers 110a, 110b, 110c, and 110d can each be made of a laminated structure of an inorganic insulating material and an organic insulating material.

[0179] Inorganic insulating materials can be suitably used as insulating layers 110a, 110b, 110c, and 110d. One or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used as inorganic insulating materials. For example, one or more silicon oxide, silicon oxidized nitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon oxide nitride, and aluminum nitride can be used as insulating layers 110a, 110b, 110c, and 110d, respectively.

[0180] It is preferable that insulating layers 110a, 110b, 110c, and 110d are insulating layers that release oxygen upon heating. It is also preferable that they are insulating layers with a high oxygen diffusion coefficient. This allows oxygen to be supplied to the semiconductor layer 108 from each of the insulating layers 110a, 110b, 110c, and 110d, and when an oxide semiconductor layer is used for the semiconductor layer 108, oxygen vacancies (V) in the semiconductor layer 108 are reduced. Ｏ ) and V Ｏ H can be reduced. For example, it is preferable to use an oxide or oxidized nitride such as silicon oxide or silicon oxidnitride as the insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110d.

[0181] In Figure 1B, etc., insulating layers 110a, 110b, 110c, and 110d are shown as single-layer structures, but this is not limited to them. Insulating layers 110a, 110b, 110c, and 110d can each be made into a laminated structure of two or more layers.

[0182] For example, when insulating layers 110a, 110b, 110c, and 110d are each arranged in a three-layer laminated structure, it is preferable to use an oxide or oxiditride such as silicon oxide or silicon oxiditride for the second insulating layer.

[0183] On the other hand, it is preferable to use insulating layers that have barrier properties against oxygen and hydrogen (barrier insulating layers) for the first and third insulating layers, respectively. It is also preferable that they release little impurity (e.g., water and hydrogen). For example, it is preferable to use oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, or gallium oxide, zinc gallium oxide, silicon nitride, silicon oxide nitride, etc. for the first and third insulating layers. Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), etc.

[0184] By forming a three-layer laminated structure with insulating layers 110a, 110b, 110c, and 110d, each made of the aforementioned insulating material, oxygen can be supplied from the second insulating layer to the semiconductor layer 108. Furthermore, the release of oxygen from the second insulating layer to the outside through the first and third barrier insulating layers can be suppressed. This allows for efficient supply of oxygen from the second insulating layer to the semiconductor layer 108. Additionally, the diffusion of oxygen from the second insulating layer to the conductive layers 112a, 114a, 112b, and 114b via the first and third barrier insulating layers can be suppressed, preventing oxidation of these conductive layers and increasing their electrical resistance. Furthermore, the diffusion of impurities such as hydrogen from outside the semiconductor device to the semiconductor layer 108 through the first and third barrier insulating layers can be suppressed.

[0185] In this specification, the term "barrier insulating layer" refers to an insulating layer that possesses barrier properties. Furthermore, "barrier property" refers to the property of making it difficult for the corresponding substance to diffuse (also referred to as the property of making it difficult for the corresponding substance to permeate, the property of having low permeability to the corresponding substance, or the function of suppressing the diffusion of the corresponding substance). The function of capturing or fixing the corresponding substance (also called gettering) can be rephrased as "barrier property." When hydrogen is described as the corresponding substance, it refers to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − This refers to at least one substance that is bonded with hydrogen, such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N). ２ O, NO, NO ２ This refers to at least one of the following: copper atoms, etc. Furthermore, when oxygen is mentioned as a corresponding substance, it refers to at least one of the following: oxygen atoms, oxygen molecules, etc. Specifically, oxygen barrier properties refer to the property that at least one of the following—oxygen atoms, oxygen molecules, etc.—is difficult to diffuse.

[0186] The insulating layers 110a, 110b, 110c, and 110d are preferably formed by a film deposition method such as sputtering, ALD, or plasma CVD (Chemical Vapor Deposition).

[0187] In particular, by using the sputtering method and a deposition method that does not use a hydrogen-containing gas as the deposition gas, it is possible to create a film with an extremely low hydrogen content. Therefore, the supply of hydrogen to the semiconductor layer 108 can be suppressed, and the electrical characteristics of transistors 10_1, 10_2, and 10_3 can be stabilized. When depositing silicon oxide by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing an oxygen-containing gas. Similarly, when depositing silicon nitride by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing a nitrogen-containing gas. Furthermore, when depositing aluminum oxide by sputtering, for example, the film can be deposited using an aluminum target in an atmosphere containing an oxidizing gas.

[0188] Furthermore, silicon oxide and silicon nitride can be deposited using, for example, the PEALD method. Aluminum oxide and hafnium oxide can also be deposited using, for example, the thermal ALD method. By depositing an insulating layer using the PEALD method and the thermal ALD method, a dense insulating film can be formed, thereby improving barrier properties against oxygen and hydrogen.

[0189] When insulating layers 110a, 110b, 110c, and 110d are arranged in the aforementioned three-layer laminated structure, it is preferable to use materials with a higher nitrogen content for the first and third barrier insulating layers than for the second insulating layer. Increasing the nitrogen content of the insulating layers can improve the barrier properties against oxygen and hydrogen.

[0190] [Insulating Layer 106] The insulating layer 106, which functions as a gate insulating layer, preferably has a low defect density. A low defect density in the insulating layer 106 allows for a transistor that exhibits good electrical characteristics. Furthermore, the insulating layer 106 preferably has a high dielectric breakdown voltage. A high dielectric breakdown voltage in the insulating layer 106 allows for a highly reliable transistor.

[0191] Furthermore, it is preferable that the insulating layer 106 is an insulating layer containing oxygen. It is also preferable that it is an insulating layer that releases oxygen upon heating. This allows, for example, when a metal oxide is used for the semiconductor layer 108, the oxygen contained in the insulating layer 106 to be supplied to the metal oxide. This allows oxygen deficiencies in the metal oxide to be repaired, thereby improving the electrical characteristics and reliability of transistors 10_1, 10_2, and 10_3, respectively.

[0192] For example, one or more insulating oxides, oxiditrides, nitride oxides, and nitrides can be used for the insulating layer 106. For example, one or more silicon oxide, silicon oxiditride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxiditride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxiditride, gallium oxide, gallium oxiditride, yttrium oxide, yttrium oxiditride, and Ga-Zn oxide can be used for the insulating layer 106. It is preferable to use the same materials for the insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110d described above for the insulating layer 106. For example, it is preferable to use silicon oxide or silicon oxiditride for the insulating layer 106. The insulating layer 106 can be a single layer structure or a laminated structure of two or more layers. The insulating layer 106 can also be a laminated structure of oxide and nitride, for example.

[0193] In miniature transistors, if the thickness of the gate insulating layer becomes thin, the leakage current through the gate insulating layer (also called gate leakage current) may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0194] It is preferable that the insulating layer 106 releases little impurities (e.g., water and hydrogen) from itself. By reducing the release of impurities from the insulating layer 106, the diffusion of such impurities into the semiconductor layer 108 is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0195] The insulating layer 106 is formed on the semiconductor layer 108. Therefore, it is preferable that the insulating layer 106 is a film formed under conditions that minimize damage to the semiconductor layer 108. For example, it is preferable to form it under conditions where the deposition rate (also called the deposition rate) is sufficiently slow. For example, when forming an insulating film that will become the insulating layer 106 by plasma CVD, forming it under low power conditions can reduce the damage to the semiconductor layer 108.

[0196] Here, we will specifically explain the insulating layer 106, using a configuration in which a metal oxide is used for the semiconductor layer 108 as an example.

[0197] To improve the interfacial properties with the semiconductor layer 108, it is preferable to use one or more oxides and oxidized nitrides on at least the side of the insulating layer 106 that is in contact with the semiconductor layer 108. For example, silicon oxide and one or more silicon oxidized nitrides can be suitably used for the insulating layer 106. Furthermore, it is even more preferable to use a film that releases oxygen when heated for the insulating layer 106.

[0198] Furthermore, the insulating layer 106 can also be a laminated structure. The insulating layer 106 can be a laminated structure of an oxide film or oxynitride film on the side in contact with the semiconductor layer 108 and a nitride film on the side in contact with the conductive layer 104a. For example, silicon oxide and one or more silicon oxynitride films can be suitably used as the oxide film or oxynitride film. For example, silicon nitride can be suitably used as the nitride film.

[0199] The thickness of the insulating layer 106 is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. It is preferable that the insulating layer 106 has at least a portion of the above-mentioned thickness region.

[0200] [Conductive layer 112a, conductive layer 112b, conductive layer 104] The conductive layers 112a, 112b, and 104, which function as source and drain electrodes, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the aforementioned metals. Low-resistance conductive materials containing one or more of copper, silver, gold, or aluminum can be suitably used for conductive layers 112a, 112b, and 104, respectively. Copper or aluminum are particularly preferred due to their excellent mass-producibility.

[0201] Furthermore, metal oxide films (also called oxide conductors) can be used for conductive layers 112a, 112b, and 104, respectively. Examples of oxide conductors (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0202] Here, we will explain oxide conductors (OCs). For example, when an oxygen vacancy is formed in a metal oxide with semiconductor properties, and hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0203] The conductive layers 112a, 112b, and 104 can each be a laminated structure of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0204] The conductive layers 112a, 112b, and 104 can each be coated with a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, processing can be performed by wet etching, which helps to reduce manufacturing costs.

[0205] As mentioned above, the conductive layer 104 functions as the other of the source electrode or drain electrode of transistor 10_3, as well as the gate electrode of transistor 10_2 and the first gate electrode of transistor 10_3. Therefore, the conductive layers 112a and 112b and the conductive layer 104 can be made of the same material, or they can be made of different materials.

[0206] Furthermore, in the case of semiconductor device 100, the conductive layer 104 is composed of conductive layer 104a and conductive layer 104b. Of these, conductive layer 104b has a region in contact with semiconductor layer 108 and therefore mainly functions as the other of the source electrode or drain electrode of transistor 10_3, while conductive layer 104a has a region facing semiconductor layer 108 via insulating layer 106 and therefore mainly functions as the gate electrodes of transistors 10_2 and 10_3, respectively. Therefore, it is not necessarily required to use the same material for conductive layer 104a and conductive layer 104b, and different materials can be used for each. For example, in conductive layer 104, conductive layer 104b can use the same material as conductive layers 112a and 112b, respectively, while conductive layer 104a can use the same material as conductive layers 114a and 114b, respectively. The materials that can be used for conductive layer 114a and conductive layer 114b will be explained in [Conductive layer 104, conductive layer 114a, conductive layer 114b].

[0207] Here, we will take a configuration in which a metal oxide (oxide semiconductor) is used for the semiconductor layer 108 as an example and specifically explain the conductive layer 112a, conductive layer 112b, and conductive layer 104.

[0208] When an oxide semiconductor is used for semiconductor layer 108, the oxygen contained in semiconductor layer 108 may oxidize conductive layer 112a, conductive layer 112b, and conductive layer 104, potentially increasing their resistance. The oxygen contained in insulating layer 106 may oxidize conductive layer 104, potentially increasing its resistance. The oxygen contained in insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110d may oxidize conductive layer 112a, conductive layer 112b, and conductive layer 104, potentially increasing their resistance.

[0209] Furthermore, the oxygen contained in the semiconductor layer 108 oxidizes the conductive layer 112a, conductive layer 112b, and conductive layer 104, respectively, resulting in oxygen vacancies (V) in the semiconductor layer 108. ＯIn some cases, the amount of oxygen supplied from the insulating layer 106 to the semiconductor layer 108 may increase. In some cases, the amount of oxygen supplied from the insulating layer 106 to the semiconductor layer 108 may decrease due to the oxidation of the conductive layer 104 by the oxygen contained in insulating layers 110a, 110b, 110c, and 110d, respectively. In some cases, the amount of oxygen supplied from insulating layers 110a, 110b, 110c, and 110d to the semiconductor layer 108 may decrease due to the oxidation of the conductive layer 112a, 112b, and 104, respectively.

[0210] Therefore, it is preferable to use conductive materials that are resistant to oxidation for conductive layers 112a, 112b, and 104. It is also preferable to use conductive materials that can maintain low electrical resistance even when oxidized. For example, among the metals, alloys, or metal oxides mentioned above, it is particularly preferable to use materials such as titanium, ruthenium, ruthenium oxide, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, ITO, and ITSO. Alternatively, it is preferable to use nitride conductors such as tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, and ruthenium nitride. Note that conductive layers 112a, 112b, and 104 can each have a laminated structure of the aforementioned materials.

[0211] For example, by using materials that are resistant to oxidation for each of the conductive layers 112a, 112b, and 104, it is possible to suppress the oxidation of these materials by oxygen contained in the semiconductor layer 108, oxygen contained in the insulating layer 106, or oxygen contained in the insulating layers 110a, 110b, 110c, and 110d, which would increase the resistance. In addition, oxygen vacancies (V) in the semiconductor layer 108 can be suppressed. Ｏ The increase in ) is suppressed, and the amount of oxygen supplied to the semiconductor layer 108 from each of the insulating layers 106, 110a, 110b, 110c, and 110d can be increased.

[0212] [Conductive layer 104, conductive layer 114a, conductive layer 114b] The conductive layers 104, 114a, and 114b, which function as gate electrodes, can each be formed using, for example, one or more of the following: chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy composed of one or more of the aforementioned metals. Alternatively, the conductive layers 104, 114a, and 114b can each be made from the materials described in [Conductive layer 112a, conductive layer 112b, conductive layer 104] above.

[0213] Here, as mentioned above, conductive layer 114a is a conductive layer that functions as the gate electrode of transistor 10_1, and after the formation of the opening 120, it is necessary to form an insulating layer 116a that functions as a gate insulating layer by oxidizing the side surface of conductive layer 114a on the opening 120 side. Similarly, conductive layer 114b is a conductive layer that functions as the gate electrode (second gate electrode) of transistor 10_3, and after the formation of the opening 120, it is necessary to form an insulating layer 116b that functions as a gate insulating layer (second gate insulating layer) by oxidizing the side surface of conductive layer 114b on the opening 120 side. Therefore, it is preferable to use conductive materials for conductive layer 114a and conductive layer 114b that have low electrical resistance, are easy to process, and whose surfaces can be oxidized relatively easily. For example, it is preferable to use materials such as tantalum, tungsten, or aluminum for conductive layer 114a and conductive layer 114b.

[0214] For example, when tantalum is used for both conductive layer 114a and conductive layer 114b, insulating layers 116a and 116b made of tantalum oxide can be formed by oxidizing the sides of conductive layer 114a and conductive layer 114b on the opening 120 side. Alternatively, when aluminum is used for both conductive layer 114a and conductive layer 114b, insulating layers 116a and 116b made of aluminum oxide can be formed by oxidizing the sides of conductive layer 114a and conductive layer 114b on the opening 120 side.

[0215] Furthermore, as mentioned above, in the conductive layer 104 of the semiconductor device 100, conductive layer 104b can be considered to mainly function as the other of the source electrode or drain electrode of transistor 10_3, and conductive layer 104a can be considered to mainly function as the gate electrodes of transistors 10_2 and 10_3, respectively. Therefore, it is not necessarily required to use the same material for conductive layer 104a and conductive layer 104b, and different materials can be used for each. For example, in conductive layer 104, only conductive layer 104a can be made of the same material as conductive layers 114a and 114b, respectively, while conductive layer 104b can be made of the material described above in [conductive layer 112a, conductive layer 112b, conductive layer 104].

[0216] In Figure 1B, etc., the conductive layer 104a and conductive layer 104b are shown as single-layer structures, but this is not limited to this. For example, the conductive layer 104a and conductive layer 104b can each be made into a laminated structure of two or more layers.

[0217] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or organic resin substrates can be used as the substrate 102. In addition, substrates on which semiconductor elements are provided can also be used as the substrate 102. The shape of the semiconductor substrate and insulating substrate can be circular or rectangular.

[0218] A flexible substrate can be used as the substrate 102, and the semiconductor device 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the semiconductor device 100, etc. The release layer can be used to separate the semiconductor device from the substrate 102 after it has been partially or completely completed on it, and to transfer it to another substrate. In this case, the semiconductor device 100, etc., can be transferred to a substrate with poor heat resistance or to a flexible substrate.

[0219] [Composition of the metal oxide in the semiconductor layer 108] The following describes in detail the composition of the metal oxide that can be used in the semiconductor layer 108.

[0220] The composition of the metal oxide in the semiconductor layer 108 significantly affects the electrical characteristics and reliability of transistors 10_1, 10_2, and 10_3, respectively.

[0221] For example, by increasing the indium content of the metal oxide, it is possible to realize a transistor with a large on-current.

[0222] When using an In-Zn oxide for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, metal oxides with atomic ratios of metal elements of In:Zn = 1:1, In:Zn = 2:1, In:Zn = 3:1, In:Zn = 4:1, In:Zn = 5:1, In:Zn = 7:1, or In:Zn = 10:1, or close to these ratios, can be used.

[0223] When using an In-Sn oxide for the semiconductor layer 108, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than that of tin. For example, metal oxides with atomic ratios of metal elements of In:Sn = 1:1, In:Sn = 2:1, In:Sn = 3:1, In:Sn = 4:1, In:Sn = 5:1, In:Sn = 7:1, or In:Sn = 10:1, or close to these ratios, can be used.

[0224] When using an In-M-Zn oxide for the semiconductor layer 108, a metal oxide can be applied in which the atomic ratio of indium to the total number of metal elements is higher than the atomic ratio of element M. Furthermore, it is even more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M. For example, in the semiconductor layer 108, the atomic ratio of metal elements can be In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1 Metal oxides with the following ratios can be used: 6, In:M:Zn = 10:1:3, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, or near these ratios.

[0225] Furthermore, if element M contains multiple metallic elements, the sum of the atomic ratios of those metallic elements can be used as the atomic ratio of element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as elements M, the sum of the atomic ratios of gallium and aluminum can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as elements M, the sum of the atomic ratios of gallium and tin can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges.

[0226] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the total number of metal elements contained in the metal oxide is 30 atomic% to 100 atomic%, preferably 30 atomic% to 95 atomic%, more preferably 35 atomic% to 95 atomic%, more preferably 35 atomic% to 90 atomic%, more preferably 40 atomic% to 90 atomic%, more preferably 45 atomic% to 90 atomic%, more preferably 50 atomic% to 80 atomic%, more preferably 60 atomic% to 80 atomic%, and more preferably 70 atomic% to 80 atomic. For example, when using In-Ga-Zn oxide for the semiconductor layer 108, it is preferable that the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is within the aforementioned range.

[0227] In this specification, the ratio of indium atoms to the total number of atoms of other metal elements may be referred to as the indium content. The same applies to other metal elements.

[0228] By increasing the indium content of the metal oxide, a transistor with a high on-current can be created. Applying this transistor to a transistor requiring a high on-current results in a semiconductor device with excellent electrical characteristics.

[0229] For the analysis of the composition of metal oxides, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may not be detected.

[0230] In this specification, the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when describing an atomic ratio of In:M:Zn = 4:2:3 or a composition near that, it includes cases where the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Also, when describing an atomic ratio of In:M:Zn = 5:1:6 or a composition near that, it includes cases where the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, when describing an atomic ratio of In:M:Zn = 1:1:1 or a composition near that, it includes cases where the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is greater than 0.1 and 2 or less.

[0231] The following describes an example of a semiconductor device configuration different from semiconductor device 100, according to one aspect of the present invention.

[0232] <Example of Semiconductor Device Configuration 2> Figures 3A and 3B show an example of the configuration of a semiconductor device 100A, which is different from the semiconductor device 100 shown in Figures 1A to 1C. Figure 3A is a cross-sectional view of the semiconductor device 100A corresponding to the dashed line A1-A2 of the semiconductor device 100 shown in Figure 1A. Figure 3B is a cross-sectional view of the semiconductor device 100A corresponding to the dashed line A3-A4 of the semiconductor device 100 shown in Figure 1A. For a plan view of the semiconductor device 100A, refer to the plan view of the semiconductor device 100 shown in Figure 1A.

[0233] The semiconductor device 100A includes transistor 10A_1, transistor 10A_2, transistor 10A_3, insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d, and layer 115.

[0234] The semiconductor device 100A differs from the semiconductor device 100 mainly in that it has a layer 115 and the conductive layer 104 is composed of only one conductive layer.

[0235] The semiconductor device 100A has a configuration in which a layer 115 is provided in a recess of an insulating layer 106 located within the opening 120, and a conductive layer 104 is provided on the layer 115 so as to fill the recess. Furthermore, the conductive layer 104 is not composed of two conductive layers, conductive layer 104a and conductive layer 104b, as in the semiconductor device 100, but is composed of only one conductive layer.

[0236] Figures 3A and 3B show an example in which the height of the upper surface of layer 115 is higher than the height of the upper surface of conductive layer 114a. It is preferable that the height of the upper surface of layer 115 be higher than the height of the upper surface of conductive layer 114a. Furthermore, it is preferable that the height of the upper surface of layer 115 be lower than the height of the bottom surface of conductive layer 112b. In other words, it is preferable that the conductive layer 104, which functions as the gate of transistor 10A_2 and transistor 10A_3 respectively, and the channel formation region of transistor 10A_1 do not overlap in a cross-sectional view (Z direction). This reduces the effect of the electric field from conductive layer 104 on the carriers in the channel formation region of transistor 10A_1, thereby reducing adverse effects on the operation of transistor 10A_1 (for example, malfunctions).

[0237] For example, an insulating material can be used for layer 115. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 115. In particular, it is preferable that layer 115 be formed using an insulating material, and it is especially preferable that it be formed using an organic insulating material. Examples of organic insulating materials that can be used for layer 115 include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Furthermore, layer 115 can also be a laminated structure of an inorganic insulating film and an organic insulating film.

[0238] In the case of the semiconductor device 100, it is necessary to adjust the thickness of the insulating layer 106 so that, in a cross-sectional view, there is no overlap between the conductive layer 104 and the channel formation region of the transistor 10_1. Therefore, it is necessary to deposit the insulating layer 106 to a certain thickness, which increases the time required for deposition. Also, depending on the ratio of the aperture diameter to the depth (aspect ratio) of the opening 120, the opening 120 may be filled with the insulating layer 106, leaving no space to subsequently place the conductive layer 104 within the opening 120.

[0239] In contrast, in the case of semiconductor device 100A, since the conductive layer 104 is provided on the layer 115 after forming the layer 115 in the aperture 120, the thickness of the layer 115 can be adjusted so that there is no overlapping region between the conductive layer 104 and the channel formation region of the transistor 10A_1 in cross-sectional view. Therefore, it is possible to form the insulating layer 106 thinner than that of semiconductor device 100, and semiconductor devices can be manufactured with a good yield regardless of the aspect ratio of the aperture 120.

[0240] Furthermore, depending on the aspect ratio of the aperture 120, it may be possible to manufacture the semiconductor device 100 with a good yield. In this case, since it is not necessary to form layer 115, it may be possible to reduce the time required for manufacturing or the number of manufacturing steps compared to semiconductor device 100A.

[0241] Furthermore, in semiconductor device 100A, since the conductive layer 104 can be provided in the remaining space within the opening 120 after the layer 115 has been formed within the opening 120, it is not necessary to form the conductive layer 104 with two conductive layers (conductive layer 104a and conductive layer 104b) as in semiconductor device 100, and it has the advantage of being able to be formed with only one conductive layer. The method for forming the layer 115 and the conductive layer 104 of semiconductor device 100A will be explained in <Example of Semiconductor Device Manufacturing Method 2>.

[0242] Regarding semiconductor device 100A, other than the points mentioned above, you can refer to the content described for semiconductor device 100.

[0243] <Example of Semiconductor Device Configuration 3> Figures 3C and 3D show an example of the configuration of a semiconductor device 100B, which is different from the semiconductor device 100 shown in Figures 1A and 1C. Figure 3C is a cross-sectional view of the semiconductor device 100B corresponding to the dashed line A1-A2 of the semiconductor device 100 shown in Figure 1A. Figure 3D is a cross-sectional view of the semiconductor device 100B corresponding to the dashed line A3-A4 of the semiconductor device 100 shown in Figure 1A. For a plan view of the semiconductor device 100B, refer to the plan view of the semiconductor device 100 shown in Figure 1A.

[0244] The semiconductor device 100B includes transistor 10B_1, transistor 10B_2, transistor 10B_3, insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110d.

[0245] The semiconductor device 100B differs from the semiconductor device 100 mainly in that the aperture 120 has a tapered shape.

[0246] In semiconductor device 100, the side walls of the opening 120 (the sides of the insulating layer 110a, insulating layer 116a, insulating layer 110b, conductive layer 112b, insulating layer 110c, insulating layer 116b, and insulating layer 110d within the opening 120) are shown to be perpendicular to the bottom of the opening 120 (in this case, the upper surface of the conductive layer 112a). In contrast, in semiconductor device 100B, the side walls of the opening 120 are provided at an inclination with respect to the bottom of the opening 120 (i.e., they have a tapered shape).

[0247] In the case of semiconductor device 100B, since the aperture 120 has a tapered shape, the aperture diameter of the aperture 120 in a plan view becomes smaller towards the bottom of the aperture 120. Therefore, even without increasing the thickness of the insulating layer 106, the area near the bottom of the aperture 120 can be filled with the insulating layer 106 alone, as shown in Figures 3C and 3D. Consequently, it is sometimes possible to manufacture semiconductor devices with a good yield regardless of the aspect ratio of the aperture 120 (here, the ratio of the maximum aperture diameter to the depth of the aperture 120).

[0248] Furthermore, the semiconductor device 100B has the advantage that the tapered shape of the opening 120 improves the coverage of the film (for example, the semiconductor layer 108) whose surface is formed on the side wall of the opening 120.

[0249] The taper angle of the opening 120 (the angle between the side wall of the opening 120 and the upper surface of the conductive layer 112a) can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less. The smaller the taper angle, the better the coverage of the film with the side wall of the opening 120 as the surface to be formed.

[0250] On the other hand, in the case of semiconductor device 100B, depending on the aspect ratio of the aperture 120, the maximum diameter of the aperture 120 may become large, which can be disadvantageous for miniaturization. In contrast, in semiconductor device 100, the aperture diameter in a plan view of the aperture 120 is constant regardless of the depth direction (Z direction), so it has the advantage that the aperture diameter can be reduced without worrying about the aspect ratio of the aperture 120. Therefore, semiconductor device 100 may be able to achieve miniaturization more effectively than semiconductor device 100B.

[0251] Regarding semiconductor device 100B, other than the points mentioned above, you can refer to the content described for semiconductor device 100.

[0252] <Example of semiconductor device configuration 4> Figures 4A to 4C show an example of the configuration of a semiconductor device 100C that is different from the semiconductor device 100 shown in Figures 1A to 1C. Figure 4A is a plan view of the semiconductor device 100C. Figure 4B is a cross-sectional view of the semiconductor device 100C along the dashed line A1-A2 shown in Figure 4A. Figure 4C is a cross-sectional view of the semiconductor device 100C along the dashed line A3-A4 shown in Figure 4A.

[0253] The semiconductor device 100C includes transistor 10C_1, transistor 10C_2, transistor 10C_3, insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d, and insulating layer 106s.

[0254] The semiconductor device 100C differs from the semiconductor device 100 mainly in that a portion of the semiconductor layer 108 is also provided outside the opening 120, and that it has an insulating layer 106s.

[0255] In semiconductor device 100, as shown in Figures 1B and 1C, the semiconductor layer 108, insulating layer 106, and conductive layer 104a are provided so that they are located only inside the opening 120. In contrast, in semiconductor device 100C, as shown in Figures 4B and 4C, a portion of each of the semiconductor layer 108, insulating layer 106, and conductive layer 104a has a region that is located outside the opening 120. Of these, the semiconductor layer 108 has an end that extends beyond the opening 120 in a plan view, as shown in Figure 4A, and a portion of its upper end is in contact with the upper surface of the insulating layer 110d, as shown in Figures 4B and 4C. In addition, an insulating layer 106s is provided in the region on the insulating layer 110d where the semiconductor layer 108 is not provided.

[0256] The upper surface of the conductive layer 104a, the upper end of the insulating layer 106, a portion of the upper surface of the semiconductor layer 108 (the upper surface in the highest region as viewed from the substrate surface), and the upper surface of the insulating layer 106s are all roughly the same in height. The conductive layer 104b is provided in contact with the upper surface of the conductive layer 104a, the upper end of the insulating layer 106, and a portion of the upper surface of the semiconductor layer 108.

[0257] In semiconductor device 100C, the contact area between the semiconductor layer 108 and the conductive layer 104b is larger than that of semiconductor device 100. Therefore, the contact resistance between the semiconductor layer 108 and the conductive layer 104b can be reduced in semiconductor device 100C than in semiconductor device 100. Consequently, the transistor 10C_3 in semiconductor device 100C may be able to have a higher on-current than the transistor 10_3 in semiconductor device 100. In addition, in semiconductor device 100C, the possibility of poor contact between the semiconductor layer 108 and the conductive layer 104b is lower than in semiconductor device 100. Therefore, it is possible to suppress problems such as difficulty in applying voltage (gate voltage) to the conductive layer 104a, which functions as the source electrode or drain electrode of transistor 10C_3, the gate electrode (first gate electrode) of transistor 10C_3, and the gate electrode of transistor 10C_2, via the semiconductor layer 108 and the conductive layer 104b.

[0258] As shown in Figure 4A and other figures, it is preferable that the conductive layer 104b be provided so as to be enclosed within the semiconductor layer 108 in a plan view. This is preferable because it allows for a larger contact area between the conductive layer 104 and the semiconductor layer 108 compared to the case where a portion of the conductive layer 104b overlaps with the semiconductor layer 108 in a plan view.

[0259] In Figure 4A, etc., an example is shown in which the conductive layer 104b has a smaller area than the semiconductor layer 108, and is provided so that the conductive layer 104b is enclosed within the semiconductor layer 108 in a plan view. However, this is not limited to this configuration. For example, the conductive layer 104b has a larger area than the semiconductor layer 108, and can be configured so that the conductive layer 104b encloses the semiconductor layer 108 in a plan view. In this case, the upper surface of the semiconductor layer 108 is not exposed, so it is possible to suppress the adhesion of impurities such as water and hydrogen to the upper surface of the semiconductor layer 108.

[0260] The insulating layer 106s is formed when a portion of the insulating film that becomes the insulating layer 106 remains on the outside of the semiconductor layer 108 during the process of manufacturing the semiconductor layer 108, the insulating layer 106, and the conductive layer 104a. Therefore, it can be said that the insulating layer 106 and the insulating layer 106s are made of the same material. The method for forming the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 of the semiconductor device 100C will be explained in <Example of Semiconductor Device Manufacturing Method 3>.

[0261] Furthermore, if the contact resistance between the semiconductor layer 108 and the conductive layer 104 is sufficiently low, adopting the configuration of semiconductor device 100 is preferable to semiconductor device 100C because it reduces the number of manufacturing steps and costs.

[0262] Regarding semiconductor device 100C, other than the points mentioned above, you can refer to the content described for semiconductor device 100.

[0263] <Example 1 of Semiconductor Device Manufacturing Method> Below, an example of a semiconductor device manufacturing method according to one aspect of the present invention will be described with reference to the drawings. Here, the semiconductor device 100 shown in Figures 1A to 1C will be used as an example.

[0264] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, CVD, vacuum deposition, pulsed laser deposition (PLD), and ALD.

[0265] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0266] CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. Furthermore, depending on the source gas used, they can be divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD).

[0267] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices can become charged by receiving charge from the plasma. This accumulated charge can damage the wiring, electrodes, or components in the semiconductor device. In contrast, thermal CVD, which does not use plasma, avoids this plasma damage, resulting in a higher yield for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0268] As ALD methods, thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants, can be used.

[0269] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable, for example, for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0270] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers, because time required for transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0271] Furthermore, the ALD method allows for the deposition of films with any desired composition by using multiple different types of precursors. Alternatively, when using multiple different types of precursors, films with any desired composition can be deposited by controlling the number of cycles for each precursor.

[0272] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0273] Thin films constituting semiconductor devices can be processed using methods such as photolithography. In addition, thin films can also be processed using nanoimprint lithography, sandblasting, and lift-off methods. Furthermore, island-like thin films can be directly formed using deposition methods that utilize shielding masks such as metal masks.

[0274] Photolithography typically involves two main methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, followed by exposure and development, to process the thin film into the desired shape.

[0275] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0276] For etching thin films, methods such as dry etching, wet etching, or sandblasting can be used.

[0277] For planarization of thin films, polishing methods such as the CMP method are typically suitable. Alternatively, the reflow method, which involves heat treatment of the conductive layer to fluidize it, can also be suitably used. Furthermore, a combination of the reflow method and the CMP method can be employed.

[0278] Furthermore, a process can be used in which a planarization film is formed on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching (e.g., dry etching) on ​​the planarization film, or a process in which a planarization film and a photoresist are formed in that order on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching on the planarization film and the photoresist, thereby filling only the planarization film into the depressions and flattening the entire top surface (these processes are sometimes called etch-back processes). When using an etch-back process, high-temperature heating (e.g., around 800°C) like that used in reflow methods is not required, so there is no need to worry about damage to the device during fabrication caused by such heating. In addition, an etch-back process is suitable because it can be applied to devices on large substrates that are difficult to process with the CMP method due to the effects of bending, etc.

[0279] Other thin film planarization treatments that can be used include dry etching and plasma treatment. Polishing, dry etching, and plasma treatment can be performed multiple times, or they can be combined. When combining treatments, the order of the processes is not particularly limited and is preferably set appropriately according to the surface irregularities of the treated surface.

[0280] To precisely process a thin film to a desired thickness, for example, the CMP method can be used. In this method, first, the thin film is polished at a constant processing speed until a portion of its upper surface is exposed. Then, by polishing at a slower processing speed until the thin film reaches the desired thickness, high-precision processing becomes possible.

[0281] Methods for detecting the end point of polishing include optical methods that involve irradiating the surface of the workpiece with light and detecting changes in the reflected light, physical methods that involve detecting changes in the polishing resistance that the processing equipment receives from the workpiece, and methods that use changes in magnetic field lines caused by eddy currents generated when magnetic field lines are applied to the workpiece.

[0282] After the upper surface of the thin film is exposed, the thickness of the thin film can be precisely controlled by performing a polishing process at a slow processing speed while monitoring its thickness using an optical method such as a laser interferometer. If necessary, the polishing process can be repeated multiple times until the thin film reaches the desired thickness.

[0283] Figures 5A to 12C illustrate the method for manufacturing the semiconductor device 100. Figure (A) shows a plan view corresponding to Figure 1A. Figure (B) shows a cross-sectional view along the dashed line A1-A2 in the plan view shown in Figure 1A. Figure (C) shows a cross-sectional view along the dashed line A3-A4 in the plan view shown in Figure 1A.

[0284] First, a conductive film that will become the conductive layer 112a is formed on the substrate 102, and a portion of the conductive film is removed to form the conductive layer 112a. The conductive film can be made from any of the materials previously described that can be used for the conductive layer 112a. For example, sputtering can be used to form the conductive film. Furthermore, either wet etching or dry etching, or both, can be used to process the conductive film.

[0285] Next, an insulating layer 110a is formed on the conductive layer 112a and the substrate 102 (Figures 5A to 5C).

[0286] The insulating layer 110a can be made from the materials described above as appropriate.

[0287] For example, silicon oxide, silicon oxide, silicon nitride, and the like can be suitably used as the insulating layer 110a.

[0288] Specifically, as the insulating layer 110a, for example, silicon oxide can be deposited using a sputtering method. Alternatively, for example, silicon oxide can be deposited using a PECVD method. Alternatively, for example, silicon oxynitride can be deposited using a PECVD method.

[0289] Furthermore, for example, silicon oxide deposited using the sputtering method and silicon oxide or silicon oxidnitride deposited using the PECVD method can be used in a layered configuration.

[0290] Furthermore, for example, silicon nitride or silicon nitride oxide deposited using the PECVD method can be used in a layered manner, with silicon oxide or silicon oxynitride deposited using the PECVD method and silicon nitride or silicon nitride oxide deposited using the PECVD method.

[0291] After forming the insulating layer 110a, a process can be performed to flatten the upper surface of the insulating layer 110a. For example, the upper surface of the insulating layer 110a can be flattened by using a process such as the CMP method. Flattening the upper surface of the insulating layer 110a is preferable because it can improve the coverage of the structure formed on top of the insulating layer 110a. However, if there is no problem with the coverage of the structure formed on top of the insulating layer 110a, the above flattening process is not necessarily required.

[0292] After forming the insulating layer 110a, a heat treatment can also be performed. By performing the heat treatment, water and hydrogen can be removed from the surface and within the film of the insulating layer 110a.

[0293] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate 102, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can also be used as the atmosphere containing nitrogen or oxygen. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a content of hydrogen, water, etc. kept to a minimum, it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating layer 110a as much as possible. Heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. Using an RTA device can shorten the heat treatment time.

[0294] After the above heat treatment, a step of supplying oxygen to the insulating layer 110a can also be performed. For example, after the insulating layer 110a is formed, oxygen can be supplied to the insulating layer 110a by forming a metal oxide layer on the insulating layer 110a. Alternatively, the heat treatment can be performed after the formation of the metal oxide layer. By performing the heat treatment after the formation of the metal oxide layer, oxygen can be effectively supplied from the metal oxide layer to the insulating layer 110a, and oxygen can be contained in the insulating layer 110a. The oxygen supplied to the insulating layer 110a is supplied to the semiconductor layer 108 in a later step, thereby eliminating oxygen vacancies (V) in the semiconductor layer 108. Ｏ ) and V Ｏ H can be reduced.

[0295] After forming the metal oxide layer, or after the aforementioned heat treatment, oxygen can be further supplied to the insulating layer 110a through the metal oxide layer. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. As the plasma treatment, a device that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that convert gas into plasma using high-frequency power include plasma etching devices and plasma ashing devices.

[0296] The metal oxide layer may be an insulating layer or a conductive layer. The metal oxide layer may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0297] It is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108 as the metal oxide layer. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. This allows the metal oxide layer to be formed using the same sputtering target as the semiconductor layer 108, thereby reducing manufacturing costs.

[0298] When using a metal oxide material containing indium and gallium in the metal oxide layer, a material with a higher gallium composition (content) than the semiconductor layer 108 can be used. By using a material with a higher gallium composition (content) in the metal oxide layer, the barrier properties against oxygen can be further enhanced. This is preferable because it can suppress the detachment of oxygen contained in the insulating layer 110a to the outside through the metal oxide layer.

[0299] The metal oxide layer is preferably formed in an atmosphere containing oxygen, for example. In particular, it is preferable to form it by sputtering in an atmosphere containing oxygen. This allows for a suitable supply of oxygen to the insulating layer 110a during the formation of the metal oxide layer.

[0300] Next, the metal oxide layer is removed. For example, a wet etching method can be suitably used to remove the metal oxide layer.

[0301] The process of supplying oxygen to the insulating layer 110a is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atom ions, oxygen molecular ions, etc., can be supplied to the insulating layer 110a by ion doping, ion implantation, plasma treatment, etc. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating layer 110a, and then oxygen can be supplied to the insulating layer 110a through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.

[0302] Next, a conductive film that will become the conductive layer 114a is formed on the insulating layer 110a, and the conductive layer 114a is formed by removing a portion of the conductive film. The conductive film can be made from any material that can be used for the conductive layer 114a as described above. For example, sputtering can be used to form the conductive film. For processing the conductive film, either or both of the wet etching method and the dry etching method can be used. The conductive layer 114a is formed to have a region that overlaps with the conductive layer 112a.

[0303] Next, an insulating layer 110b is formed on the conductive layer 114a and the insulating layer 110a (Figures 6A to 6C).

[0304] Regarding materials that can be used for the insulating layer 110b, forming methods, etc. (including planarization treatment, heat treatment, oxygen supply treatment, etc. after formation), refer to the description relating to the insulating layer 110a above.

[0305] Next, a conductive film that will become the conductive layer 112b is formed on the insulating layer 110b, and a portion of the conductive film is removed to form the conductive layer 112b. For materials that can be used for the conductive layer 112b, a method of forming it, etc., refer to the description of the conductive layer 112a above. The conductive layer 112b is formed to have regions that overlap with the conductive layer 112a and the conductive layer 114a, respectively.

[0306] Next, an insulating layer 110c is formed on the conductive layer 112b and the insulating layer 110b (Figures 7A to 7C).

[0307] Regarding materials and formation methods that can be used for the insulating layer 110c (including planarization treatment, heat treatment, oxygen supply treatment, etc. after formation), refer to the description relating to the insulating layer 110a above.

[0308] Next, a conductive film that will become the conductive layer 114b is formed on the insulating layer 110c, and a portion of the conductive film is removed to form the conductive layer 114b. For materials that can be used for the conductive layer 114b, and for the formation method, refer to the description of the conductive layer 114a above. The conductive layer 114b is formed to have regions that overlap with the conductive layers 112a, 114a, and 112b.

[0309] Next, an insulating layer 110d is formed on the conductive layer 114b and the insulating layer 110c (Figures 8A to 8C).

[0310] Regarding materials that can be used for the insulating layer 110d, forming methods, etc. (including planarization treatment, heat treatment, oxygen supply treatment, etc. after formation), refer to the description relating to the insulating layer 110a above.

[0311] Next, a portion of each of the insulating layer 110a, conductive layer 114a, insulating layer 110b, conductive layer 112b, insulating layer 110c, conductive layer 114b, and insulating layer 110d is removed to form an opening 120 that reaches the conductive layer 112a (Figures 9A to 9C). For this formation, for example, a dry etching method can be suitably used.

[0312] Next, the conductive layers 114a and 114b within the opening 120 are oxidized to form an insulating layer 116a on the side of the conductive layer 114a facing the opening 120, and an insulating layer 116b on the side of the conductive layer 114b facing the opening 120 (Figures 10A to 10C). For this process, for example, heat treatment can be used. For the temperature and equipment used for the heat treatment, refer to the description of the heat treatment that can be performed on the insulating layer 110a, etc., mentioned above. Alternatively, by supplying oxygen into the opening 120, the conductive layers 114a and 114b can be oxidized, and insulating layers 116a and 116b can be formed. For this treatment, refer to the description of the oxygen supply treatment that can be performed on the insulating layer 110a, etc., mentioned above.

[0313] Next, a semiconductor film 108f, which will become the semiconductor layer 108, is formed in contact with the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the insulating layer 116a, the side surface of the insulating layer 110b, the side surface of the conductive layer 112b, the side surface of the insulating layer 110c, the side surface of the insulating layer 116b, the side surface of the insulating layer 110d, and the upper surface of the insulating layer 110d, within the opening 120.

[0314] The semiconductor film 108f can be made from any material that can be used for the semiconductor layer 108 described above.

[0315] For example, sputtering can be used to form the semiconductor film 108f. For instance, when a metal oxide is used for the semiconductor layer 108, it can be formed by sputtering using a metal oxide target. Sputtering is preferable because it allows for the relatively easy formation of films with low hydrogen content.

[0316] Furthermore, when a metal oxide is used for the semiconductor layer 108, it can also be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0317] For example, when forming In-Ga-Zn oxide, three precursors can be used: an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor. Alternatively, two precursors can be used: an indium-containing precursor and precursors containing both gallium and zinc.

[0318] Indium-containing precursors that can be used include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, and indium(III) chloride.

[0319] Furthermore, gallium-containing precursors such as trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, and diethylchlorogallium can be used.

[0320] Furthermore, zinc-containing precursors such as dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride can be used.

[0321] For example, ozone, oxygen, and water can be used as oxidizing agents.

[0322] Methods for controlling the composition of the resulting film include adjusting the flow ratio of the source gases, the duration of the source gas flow, and the order in which the source gases are flowed. By adjusting these factors, it is also possible to deposit films with continuously changing compositions. Furthermore, it becomes possible to deposit films with different compositions in succession.

[0323] Using the ALD method to form the semiconductor film 108f is preferable because it allows the semiconductor film 108f to be formed with a uniform thickness on the side walls of the opening 120 (the sides of the insulating layer 110a, the sides of the insulating layer 116a, the sides of the insulating layer 110b, the sides of the conductive layer 112b, the sides of the insulating layer 110c, the sides of the insulating layer 116b, and the sides of the insulating layer 110d).

[0324] The semiconductor film 108f can also be subjected to heat treatment after deposition. Heat treatment reduces the amount of water and hydrogen contained in the semiconductor film 108f and allows oxygen to be supplied to the semiconductor film 108f from each of the insulating layers 110a, 110b, 110c, and 110d. Note that the heat treatment can also be performed after processing the semiconductor film.

[0325] The substrate temperature during the formation of the semiconductor film 108f is preferably between room temperature (25°C) and 200°C, and more preferably between room temperature and 130°C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when using a large-area glass substrate. It is also possible to set the substrate temperature during the formation of the semiconductor film 108f to a temperature higher than 200°C.

[0326] The higher the substrate temperature (stage temperature) during metal oxide layer formation, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the oxygen flow rate ratio, the more crystalline the metal oxide layer can be formed.

[0327] Next, an insulating film 106f, which will become an insulating layer 106, is formed on the semiconductor film 108f.

[0328] For the insulating film 106f, any material that can be used for the insulating layer 106 described above can be used as appropriate.

[0329] For example, the ALD method can be used to form the insulating film 106f. The ALD method is preferable because it allows for good coverage of the insulating film 106f formed over the semiconductor film 108f that covers the opening 120. However, if the semiconductor film 108f can be sufficiently covered, methods other than the ALD method can be used to form the insulating film 106f. For example, the PECVD method or sputtering method can be used. This allows for a faster deposition rate of the insulating film 106f than when using the ALD method, thereby increasing productivity.

[0330] As mentioned above, in the semiconductor device 100, the upper surface height of the insulating layer 106 in the region where the surface to be formed is parallel to the upper surface of the conductive layer 112a is higher than the upper surface of the conductive layer 114a. Therefore, the insulating layer 106 in the region where the surface to be formed is parallel to the upper surface of the conductive layer 112a is required to have a certain film thickness. Therefore, from the viewpoint of shortening the film formation time, it may be preferable to use a film formation method such as the PECVD method or sputtering method, which have a faster film formation rate than the ALD method.

[0331] Next, a conductive film 104f, which will become the conductive layer 104a, is formed on the insulating film 106f (Figures 11A to 11C).

[0332] Any material that can be used for the conductive layer 104 described above can be appropriately used for the conductive film 104f.

[0333] For forming the conductive film 104f, sputtering, CVD, molecular beam epitaxy (MBE), PLD, ALD, etc., can be used as appropriate. Here, it is preferable that the conductive film 104f is formed in contact with the insulating film 106f facing the side wall of the opening 120. Therefore, it is preferable to use a formation method that provides good coverage or embedding properties for forming the conductive film 104f, and it is more preferable to use the CVD or ALD method.

[0334] Next, a portion of the conductive film 104f, insulating film 106f, and semiconductor film 108f is removed to form the conductive layer 104a, insulating layer 106, and semiconductor layer 108 (Figures 12A to 12C).

[0335] For removing a portion of the conductive film 104f, insulating film 106f, and semiconductor film 108f, for example, the CMP method can be used. Alternatively, techniques such as etch-back processing can also be used.

[0336] The conductive film 104f, the insulating film 106f, and the semiconductor film 108f are each removed in areas located outside the opening 120. For example, if the CMP method is used for this removal, the conductive film 104f, the insulating film 106f, and the semiconductor film 108f are polished until the upper surface of the insulating layer 110d is exposed. As a result, as shown in Figures 12B and 12C, conductive layer 104a, insulating layer 106, and semiconductor layer 108 can be formed within the opening 120, with their upper surface (or upper end) heights being approximately the same.

[0337] Next, a conductive film that will become the conductive layer 104b is formed on the conductive layer 104a, the insulating layer 106, the semiconductor layer 108, and the insulating layer 110d, and a portion of the conductive film is removed to form the conductive layer 104b. The conductive layer 104b is formed to have a region that overlaps with the opening 120.

[0338] For the conductive film that forms the conductive layer 104b, any material that can be used for the conductive layer 104 described above can be used as appropriate. Furthermore, for the formation of the conductive film, for example, a sputtering method can be used. For processing the conductive film, either a wet etching method or a dry etching method, or both, can be used.

[0339] By following the above steps, the semiconductor device 100 can be manufactured (Figures 1A to 1C).

[0340] <Example 2 of Semiconductor Device Manufacturing Method> Below, an example of a manufacturing method for the semiconductor device 100A shown in Figures 3A and 3B will be explained with reference to the drawings. Here, we will mainly explain the differences from the example of a manufacturing method for the semiconductor device 100 explained in <Example 1 of Semiconductor Device Manufacturing Method>.

[0341] Up to the formation of insulating layers 116a and 116b, you can refer to the description of the example of the semiconductor device 100 manufacturing method described above (Figures 5A to 10C).

[0342] Next, the semiconductor film 108f and the insulating film 106f are formed in this order within the opening 120. For details of this formation, please refer to the description of the semiconductor device 100 shown in Figures 11A to 11C.

[0343] Next, a film 115f, which will become layer 115, is formed on the insulating film 106f (Figures 13A to 13C). Any material that can be used for layer 115 as described above can be used for film 115f. When an inorganic insulating material is used for film 115f, sputtering, CVD, or other methods can be used to form film 115f as appropriate. When an organic insulating material is used for film 115f, methods such as spin coating can be used to form film 115f as appropriate.

[0344] Next, a portion of each of the film 115f, insulating film 106f, and semiconductor film 108f is removed to form layer 115e, insulating layer 106, and semiconductor layer 108 (Figures 14A to 14C).

[0345] For removing parts of the film 115f, insulating film 106f, and semiconductor film 108f, for example, the CMP method can be used. Alternatively, techniques such as etch-back processing can also be used.

[0346] The film 115f, the insulating film 106f, and the semiconductor film 108f are each removed in areas located outside the opening 120. For example, if the CMP method is used for this removal, the film 115f, the insulating film 106f, and the semiconductor film 108f are polished until the upper surface of the insulating layer 110d is exposed. As a result, as shown in Figures 14B and 14C, layers 115e, the insulating layer 106, and the semiconductor layer 108, each with approximately the same height of their upper surfaces (or upper edges), can be formed within the opening 120.

[0347] Next, a resist mask 190 is formed on the insulating layer 110d using photolithography (Figures 15A to 15C). The resist mask 190 is formed so as not to overlap with layer 115e. Either a positive or negative type photoresist can be used for the resist mask 190 material (photoresist). It is preferable to use a material for the resist mask 190 that has a high etching selectivity ratio with respect to layer 115e (a material that is less likely to be etched when layer 115e is etched).

[0348] Next, a portion of layer 115e is removed using the resist mask 190 as a mask to form layer 115 (Figures 16A to 16C). The removal of a portion of layer 115e can be performed, for example, by using an etch-back process. Layer 115 is formed such that the height of its upper surface is greater than the height of the upper surface of the conductive layer 114a.

[0349] Next, remove the resist mask 190.

[0350] Next, a conductive film 104f, which will become the conductive layer 104, is formed on the layer 115, the insulating layer 106, the semiconductor layer 108, and the insulating layer 110d, so as to fill the opening 120 (Figures 17A to 17C). For details on the formation of the conductive film 104f, refer to the description relating to the semiconductor device 100 shown in Figures 11A to 11C.

[0351] It is preferable that the conductive film 104f is formed to have a region located outside the opening 120. The conductive film 104f has a region embedded in the opening 120 and a region located outside the opening 120. Outside the opening 120, the conductive film 104f has regions that are in contact with the upper end of the insulating layer 106, the upper end of the semiconductor layer 108, and the upper surface of the insulating layer 110d, respectively.

[0352] Next, it is preferable to perform a process to flatten the upper surface of the conductive film 104f. This process can be carried out, for example, by using methods such as the CMP method or etch-back process. Flattening the upper surface of the conductive film 104f is preferable because it can improve the coverage of the structure formed on the upper layer of the conductive film 104f. However, if the upper surface of the conductive film 104f has a flatness that does not cause problems in subsequent processes, it is not necessarily required to perform the above process. This is preferable because it can reduce the number of processes.

[0353] Next, a portion of the conductive film 104f is removed to form a conductive layer 104. The conductive layer 104 is formed to have a region that overlaps with the opening 120. In addition, either or both of the wet etching method and the dry etching method can be used to form the conductive layer 104.

[0354] By following the above steps, the semiconductor device 100A can be manufactured (Figures 3A and 3B).

[0355] <Example 3 of Semiconductor Device Manufacturing Method> Below, an example of a manufacturing method for the semiconductor device 100C shown in Figures 4A to 4C will be explained with reference to the drawings. Here, we will mainly explain the differences from the example of a manufacturing method for the semiconductor device 100 explained in <Example 1 of Semiconductor Device Manufacturing Method>.

[0356] Up to the formation of insulating layers 116a and 116b, you can refer to the description of the example of the semiconductor device 100 manufacturing method described above (Figures 5A to 10C).

[0357] Next, a semiconductor film 108f is formed within the opening 120. For details on the formation of the semiconductor film 108f, please refer to the description of the semiconductor device 100 shown in Figures 11A to 11C.

[0358] Next, a portion of the semiconductor film 108f is removed by etching to form a semiconductor layer 108e (Figures 18A to 18C). The semiconductor layer 108e is formed to have a region that overlaps with the opening 120. The semiconductor layer 108e has regions that are in contact with the upper surface of the conductive layer 112a, the side surface of the insulating layer 110a, the side surface of the insulating layer 116a, the side surface of the insulating layer 110b, the side surface of the conductive layer 112b, the side surface of the insulating layer 110c, the side surface of the insulating layer 116b, the side surface of the insulating layer 110d, and the upper surface of the insulating layer 110d, all within the opening 120.

[0359] Next, an insulating film 106f is formed on the semiconductor layer 108e and the insulating layer 110d. Details of the formation of the insulating film 106f can be found in the description of the semiconductor device 100 shown in Figures 11A to 11C. The insulating film 106f has regions that are in contact with the upper and side surfaces of the semiconductor layer 108e and the upper surface of the insulating layer 110d, respectively.

[0360] Next, a conductive film 104f is formed on the insulating film 106f (Figures 19A to 19C). For details on the formation of the conductive film 104f, refer to the description of the semiconductor device 100 shown in Figures 11A to 11C.

[0361] Next, a portion of the conductive film 104f, insulating film 106f, and semiconductor layer 108e is removed to form the conductive layer 104a, insulating layer 106, insulating layer 106s, and semiconductor layer 108, respectively (Figures 20A to 20C).

[0362] For removing a portion of the conductive film 104f, the insulating film 106f, and the semiconductor layer 108e, for example, the CMP method can be used. Alternatively, techniques such as etch-back processing can be used. This removal is carried out until at least the upper surface of the semiconductor layer 108e is exposed.

[0363] For example, when using the CMP method for removal, the upper surfaces of the conductive film 104f, the insulating film 106f, and the semiconductor layer 108e are polished until at least the upper surface of the semiconductor layer 108e is exposed. However, it is preferable that the polishing be completed before the insulating layer 110d is exposed. That is, it is preferable to complete the polishing while a portion of each of the semiconductor layer 108e and the insulating film 106f remains on the insulating layer 110d. This ensures a sufficient contact area between the conductive layer 104b and the semiconductor layer 108, which will be formed later.

[0364] As a result of this removal, a conductive layer 104a is formed from the conductive film 104f, and a semiconductor layer 108 is formed from the semiconductor layer 108e. In addition, a separate insulating layer 106 and insulating layer 106s are formed from the insulating film 106f. It can be said that a portion of each of the conductive layer 104a, insulating layer 106, and semiconductor layer 108 is located within the opening 120. Furthermore, outside the opening 120, the upper surface of the conductive layer 104a, the upper end of the insulating layer 106, the upper surface of the semiconductor layer 108, and the upper surface of the insulating layer 106s are approximately the same height.

[0365] Next, a conductive film that will become the conductive layer 104b is formed on the conductive layer 104, the insulating layer 106, the semiconductor layer 108, and the insulating layer 106s, and a part of the conductive film is removed to form the conductive layer 104b. The conductive layer 104b is formed to have a region that overlaps with the upper surface of the semiconductor layer 108. Preferably, the conductive layer 104b is formed so that it is enclosed by the semiconductor layer 108 in a plan view. This ensures a sufficient contact area between the conductive layer 104b and the semiconductor layer 108, and reduces the contact resistance between the conductive layer 104b and the semiconductor layer 108.

[0366] By following the above steps, the semiconductor device 100C can be manufactured (Figures 4A to 4C).

[0367] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0368] (Embodiment 2) In this embodiment, an indium oxide film that can be used in the semiconductor layer (semiconductor layer 108) of an n-channel type transistor, one of the two transistors in a semiconductor device according to one aspect of the present invention, will be described.

[0369] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0370] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0371] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0372] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single-crystal indium oxide.

[0373] The range of suitable carrier (in this case, electrons) concentrations for the channel formation region of a transistor (in this case, an n-channel transistor) is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0374] Indium oxide can contain elements that lower carrier concentrations. Examples of such elements include magnesium, calcium, zinc, cadmium, and copper. These elements can lower carrier concentrations by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower carrier concentrations by substituting for oxygen.

[0375] Elements that reduce carrier concentration can also be called elements that confer p-type properties. Adding elements that reduce carrier concentration to an indium oxide film can make the indium oxide film i-type or substantially i-type. In this case, the concentration of the above-mentioned carrier-reducing element in the indium oxide film is 1 × 10⁻⁶. １６ atoms / cm ３ The above 8 x 10 ２０ atoms / cm ３ The following is preferable: 1 × 10 １６ atoms / cm ３ The above 4 x 10 ２０ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 8 x 10 １９ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following is even more preferable. By using such concentrations, the carrier concentration can be reduced while maintaining the crystal structure of indium oxide.

[0376] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm−３ is a range including, for example, 1×10 １９ cm −３ or more and 1×10 ２２ cm −３ or less. By sufficiently increasing the carrier concentration, the resistivity can be expected to be reduced to 1×10 −４ Ω·cm or less.

[0377] An element that increases the carrier concentration can be contained in indium oxide. For example, it is preferable to contain an element common to the source electrode and the drain electrode of a transistor. Examples of the element that increases the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. In particular, it is more preferable to use an element whose oxide has conductivity or semiconductivity.

[0378] The element that increases the carrier concentration can also be referred to as an element that imparts n-type properties. The concentration of the element that increases the carrier concentration in the indium oxide film is 1×10 １６ atoms / cm ３ or more and 8×10 ２０ atoms / cm ３ or less is preferable, 1×10 １６ atoms / cm ３ or more and 4×10 ２０ atoms / cm ３ or less is more preferable, 1×10 １６ atoms / cm ３ or more and 8×10 １９ atoms / cm ３ or less is more preferable, and 1×10 １６ atoms / cm ３ or more and 5×10 １９ atoms / cm ３ or less is even more preferable. By setting such a concentration, the carrier concentration can be increased while maintaining the crystal structure of indium oxide. Note that antimony may also function as an element that increases the carrier concentration.

[0379] As described above, indium oxide is an oxide whose valence electrons can be controlled, so that the threshold voltage of a transistor using a semiconductor layer containing indium oxide can be controlled. In addition, a region with a low carrier concentration can be used for a channel formation region of a transistor, and a region with a high carrier concentration can be used for a source region and a drain region of the transistor. Accordingly, a so-called n-i-n junction (a junction of an n-type region, an i-type region, and an n-type region) can be formed. Note that valence electron control in a transistor using silicon is generally known. On the other hand, valence electron control in a transistor using indium oxide is a novel technical idea that is not usually conceivable. By using this technical idea, a transistor with high mobility, low off-state current, normally-off operation capability, and high reliability can be realized.

[0380] The indium oxide film preferably has crystallinity. In particular, the indium oxide film is preferably a polycrystalline film, more preferably a single crystal film. A single crystal film does not have a crystal grain boundary (also referred to as a grain boundary). By using the single crystal film, carrier scattering and the like at crystal grain boundaries can be suppressed, and a transistor exhibiting high field-effect mobility can be realized. In addition, an excellent effect of suppressing variation in transistor characteristics caused by the crystal grain boundaries can be achieved.

[0381] In addition, a polycrystalline film is preferable because it can reduce carrier scattering and exhibits high field-effect mobility as compared with a microcrystalline film or an amorphous film. When a polycrystalline film is used, it is preferable to use a film having crystal grains as large as possible and having few crystal grain boundaries. Note that in a transistor to which a polycrystalline film is applied, when a channel formation region has no crystal grain boundary or no crystal grain boundary is observed, the channel formation region is located in a single crystal region included in the polycrystalline film, so that the transistor can be regarded as a transistor to which a single crystal film is applied.

[0382] Note that the crystallinity of indium oxide can be analyzed by, for example, X-ray diffractometry (XRD: X-Ray Diffractometry), TEM, or electron diffractometry (ED: Electron Diffraction). Alternatively, a plurality of these techniques may be combined for analysis.

[0383] Further, in this specification and the like, a semiconductor layer in which no grain boundary is observed in a channel formation region, a semiconductor layer whose channel formation region is included in one crystal grain, or a semiconductor layer in which the crystal axis directions are the same in at least two regions within the channel formation region can be regarded as a single crystal film.

[0384] Note that the channel formation region refers to a region of the semiconductor layer that overlaps with (or faces) the gate electrode with the gate insulating layer interposed therebetween, and is located between a region in contact with the source electrode and a region in contact with the drain electrode. Crystal grains, crystal grain boundaries, crystal axes, crystal orientations, and the like in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, the source electrode, and the drain electrode.

[0385] Impurities in the indium oxide film can act as carrier scattering sources, and thus can be a factor reducing field-effect mobility and a factor inhibiting crystal growth. Examples of impurities for the indium oxide film include boron, silicon, and the like. In the channel formation region, the lower the concentration of these impurities in the indium oxide film, the more preferable. For example, the concentration of each of the above impurity elements is 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that carbon, hydrogen, and the like are elements that can be contained in a deposition gas or a precursor during film formation, and may remain in the indium oxide film in a larger amount than the above impurities.

[0386] Note that the indium oxide film may contain an element that can be a trivalent cation same as indium, as long as the crystal thereof maintains a cubic structure (bixbyite type). Examples include Group 13 elements of the periodic table such as gallium and aluminum, Group 3 elements of the periodic table, and the like. Since these elements have a stronger bonding force with oxygen than indium, adding these elements to the indium oxide film can reduce oxygen vacancies (V ＯThis can suppress the formation of ions. Furthermore, since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of the indium oxide film can be kept low. Therefore, it becomes possible to shift the threshold voltage of the transistor to the positive side. Also, normally-off operation becomes possible. Thus, a transistor with good electrical characteristics can be provided.

[0387] The concentration of the above elements in the indium oxide film is 1 × 10⁻⁶ １６ atoms / cm ３ The above 8 x 10 ２０ atoms / cm ３ The following is preferable: 1 × 10 １６ atoms / cm ３ The above 4 x 10 ２０ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 8 x 10 １９ atoms / cm ３ The following is more preferable: 1 × 10 １６ atoms / cm ３ The above 5 x 10 １９ atoms / cm ３ The following are even more preferable.

[0388] Furthermore, the elements that impart n-type, p-type, and trivalent cations mentioned above can be added to the indium oxide film by methods such as ion doping, ion implantation, and thermal diffusion. Alternatively, the elements that impart n-type, p-type, and trivalent cations mentioned above can be added to the sputtering target, deposition gas, ALD deposition precursor, etc., when depositing the indium oxide film. Alternatively, the elements that impart n-type, p-type, and trivalent cations mentioned above can be auto-doped from the chamber used when depositing the indium oxide film. Auto-doping refers to the automatic addition of elements contained in the chamber components, etc., into the indium oxide film during deposition.

[0389] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm ２ / (V·s) or more, more preferably 250 cm ２ / (V・s) or more is possible.

[0390] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0391] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0392] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0393] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Additionally, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a vertical transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) is less than or equal to 1aA (1 × 10) under room temperature (25°C) conditions. −１８ A) Less than or equal to, or 1zA (1 × 10 −２１ A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0394] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This can improve the crystallinity of the indium oxide film. A substrate (for example, a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0395] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0396] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0397] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0398] Furthermore, the crystal structure of the seed layer and the crystal structure of the indium oxide film do not necessarily have to be the same in terms of crystal system or crystal orientation. For example, a film with a hexagonal or trigonal crystal structure can be used beneath an indium oxide film with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the underside of the indium oxide film to

[111] , the requirements related to crystal orientation necessary for epitaxial growth can be met. Examples of hexagonal or trigonal crystals include wurtzite-type structures and YbFe. ２ O ４ Type structure, Yb ２ Fe ３ O ７ These include type structures and their modified forms. YbFe ２ O ４ Type structure or Yb ２ Fe ３ O ７ An example of a crystal having a type structure is IGZO.

[0399] This embodiment can be implemented in appropriate combination with other embodiments described herein, at least in part.

[0400] (Embodiment 3) In this embodiment, a storage device 50 to which a semiconductor device according to one aspect of the present invention described in Embodiment 1 can be applied will be described.

[0401] Figure 21A is a block diagram showing an example configuration of the storage device 50. The storage device 50 includes a storage unit 20, a word line drive circuit 11, a bit line drive circuit 13, and a power supply circuit 15. The storage unit 20 has a plurality of memory cells 21 arranged in a matrix. Note that the power supply circuit 15 can also be provided outside the storage device 50.

[0402] The word line driving circuit 11 is connected to the memory cell 21 via wiring 31. The wiring 31 extends, for example, in the row direction of the matrix. The wiring 31 functions as a word line. In Figure 21A, wiring 31R and wiring 31W are shown as wiring 31.

[0403] The bit line driving circuit 13 is connected to the memory cell 21 via wiring 33. The wiring 33 extends, for example, in the column direction of the matrix. The wiring 33 functions as a bit line.

[0404] In Figure 21A, as shown in the figure, the direction in which wiring 31, which functions as a word line, extends is defined as the X direction, and the direction in which wiring 33, which functions as a bit line, extends is defined as the Y direction. As mentioned above, wiring 31 extends in the row direction of the matrix, and wiring 33 extends in the column direction of the matrix. Therefore, the X direction can be defined as the row direction, and the Y direction as the column direction. The X and Y directions can be directions that intersect each other, specifically, directions that are perpendicular to each other. In addition, the direction that intersects both the X and Y directions, specifically, the direction that is perpendicular to both the X and Y directions, can be defined as the Z direction. In subsequent drawings, directions will also be indicated as the X, Y, and Z directions, but the definitions may be the same as or different from those in Figure 21A. Also, in Figure 21A, the X, Y, and Z directions are indicated by arrows, but unless explicitly stated, there is no distinction between forward and reverse directions. The same applies to subsequent drawings.

[0405] The power supply circuit 15 is connected to the memory cell 21 via wiring 35. Figure 21A shows an example where the wiring 35 extends in the column direction of the matrix. The wiring 35 functions as a power line.

[0406] In Figure 21A, wires 31, 33, and 35 are shown as straight lines. However, a single straight line does not necessarily represent a single wire; multiple wires may be represented by a single straight line. In subsequent block diagrams, circuit diagrams, etc., multiple wires may also be represented by a single straight line. Furthermore, multiple wires other than wires 31, 33, and 35 may also be represented by a single straight line.

[0407] The word line drive circuit 11 has the function of selecting a memory cell 21 to write data to, row by row. The word line drive circuit 11 also has the function of selecting a memory cell 21 to read data from, specifically a memory cell 21 that outputs data to the wiring 33, row by row. The word line drive circuit 11 can select a memory cell 21 to write data to or a memory cell 21 to read data from by supplying a signal to the wiring 31. Specifically, the word line drive circuit 11 has the function of selecting a memory cell 21 to write data to by supplying a signal to the wiring 31W. The word line drive circuit 11 also has the function of selecting a memory cell 21 to read data from, specifically a memory cell 21 that outputs data to the wiring 33, by supplying a signal to the wiring 31R. Here, the wiring 31W is also called the write word line, and the wiring 31R is also called the read word line. The signal supplied from the word line drive circuit 11 to the wiring 31W is also called the write selection signal, and the signal supplied to the wiring 31R is also called the read selection signal.

[0408] Based on the above, the word line drive circuit 11 has the function of controlling the writing of data to the memory cell 21 by supplying a write selection signal to the wiring 31W. In addition, the word line drive circuit 11 has the function of controlling the reading of data from the memory cell 21 by supplying a read selection signal to the wiring 31R.

[0409] Specifically, the bit line drive circuit 13 has the function of writing data to the memory cell 21 selected by the word line drive circuit 11 using a write selection signal, via the wiring 33. The bit line drive circuit 13 also has the function of reading data held in the memory cell 21. Specifically, the bit line drive circuit 13 has the function of amplifying the potential corresponding to the data to a potential that can be handled by other circuits. Furthermore, the bit line drive circuit 13 has the function of pre-charging the wiring 33 before reading data from the memory cell 21.

[0410] Based on the above, the bit line driving circuit 13 has the function of writing data to the memory cell 21 via the wiring 33. Furthermore, the bit line driving circuit 13 has the function of reading the data via the wiring 33.

[0411] The power supply circuit 15 has the function of supplying power potential to the wiring 35, specifically, the function of supplying a constant potential to the wiring 35. The power supply circuit 15 also has the function of generating a high potential or a low potential and supplying it to the wiring 35. The power supply circuit 15 can also be configured to have the function of supplying power potential to one or both of the word line drive circuit 11 and the bit line drive circuit 13.

[0412] Figure 21B shows an example of a circuit configuration that can be applied to the memory cell 21. The memory cell 21 shown in Figure 21B has transistor M1, transistor M2, and transistor M3.

[0413] Transistor M1 functions as a data writing transistor. Transistor M2 functions as a data reading selection / deselection transistor. Transistor M3 functions as a data reading transistor. In this specification, a memory device having a gain cell type memory cell using an OS transistor for transistor M1 is called NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory).

[0414] Transistor M1 has two gates (a first gate and a second gate). The first gate of the transistor is connected to wiring 31W. The second gate of transistor M1 is connected to the first terminal of transistor M1 (one of a source and a drain) and the gate of transistor M2. The second terminal of transistor M1 (the other of the source and the drain) is connected to wiring 33. Note that in FIG. 21B, the junction point of the second gate of transistor M1, the first terminal of transistor M1, and the gate of transistor M2 is shown as node SN.

[0415] The first terminal of transistor M2 (one of a source and a drain) is connected to the first terminal of transistor M3 (one of a source and a drain). The second terminal of transistor M2 (the other of the source and the drain) is connected to wiring 33.

[0416] The gate of transistor M3 is connected to wiring 31R. The second terminal of transistor M3 (the other of the source and the drain) is connected to wiring 35.

[0417] Here, it can be said that the memory cell 21 shown in FIG. 21B has the same circuit configuration as the semiconductor device 100 shown in FIG. 1D. For example, the transistor 10_3 in the semiconductor device 100 can be made to correspond to transistor M1 in the memory cell 21, the transistor 10_2 in the semiconductor device 100 can be made to correspond to transistor M2 in the memory cell 21, and the transistor 10_1 in the semiconductor device 100 can be made to correspond to transistor M3 in the memory cell 21.

[0418] In this case, the conductive layer 114b in the semiconductor device 100 corresponds to the first gate of transistor M1 in the memory cell 21. Further, the conductive layer 104 in the semiconductor device 100 corresponds to the second gate of transistor M1, the first terminal of transistor M1, and the gate of transistor M2 in the memory cell 21. Further, the conductive layer 112b in the semiconductor device 100 corresponds to the second terminal of transistor M1 and the second terminal of transistor M2 in the memory cell 21.

[0419] Furthermore, the conductive layer 114a in the semiconductor device 100 corresponds to the gate of transistor M3 in the memory cell 21. Also, the conductive layer 112a in the semiconductor device 100 corresponds to the second terminal of transistor M3 in the memory cell 21.

[0420] Therefore, when the semiconductor device 100 is applied to the memory cell 21, the conductive layer 114b is connected to the wiring 31W, the conductive layer 114a is connected to the wiring 31R, the conductive layer 112b is connected to the wiring 33, and the conductive layer 112a is connected to the wiring 35.

[0421] Thus, the semiconductor device 100 according to one aspect of the present invention can be applied as a memory cell 21 constituting a storage device 50. Furthermore, the semiconductor devices 100A, 100B, and 100C described in Embodiment 1 can also be applied as memory cells 21.

[0422] By applying a semiconductor device according to one aspect of the present invention to a memory cell 21, a low-cost, extremely miniaturized, and highly integrated storage device 50 can be realized. Furthermore, a storage device 50 with excellent data retention characteristics and extremely low power consumption can be realized.

[0423] The following describes a specific example of the operation of the memory cell 21.

[0424] Figure 21C shows an example of a timing chart illustrating the operation of the memory cell 21. While this timing chart assumes that each period has the same length, this is not mandatory. The memory cell can also be operated with different lengths for each period.

[0425] In the following explanation, it is assumed that either a high potential H or a low potential L is applied to wiring 31W, wiring 31R, and wiring 33. Note that the potential H applied to each wiring is not necessarily the same magnitude, nor is the potential L applied to each wiring. Of the two potentials applied to each wiring, the higher potential is assumed to be potential H, and the lower potential is assumed to be potential L.

[0426] Furthermore, the potential H applied to the wiring 31W is the potential that turns transistor M1 into the ON state, and the potential L applied to the wiring 31W is the potential that turns transistor M1 into the OFF state.

[0427] Similarly, the potential H applied to the wiring 31R is the potential that turns on transistor M3, and the potential L applied to the wiring 31R is the potential that turns off transistor M3.

[0428] Furthermore, the memory cell 21 is a binary memory cell, where the potential H applied to the wiring 33 corresponds to data 1, and the potential L applied to the wiring 33 corresponds to data 0.

[0429] Furthermore, when data 1 is held in node SN, a potential that turns transistor M2 ON is applied to the gate of transistor M2, and when data 0 is held in node SN, a potential that turns transistor M2 OFF is applied to the gate of transistor M2.

[0430] Furthermore, if node SN holds data 1, a potential of the magnitude corresponding to data 1 will be applied to the second gate of transistor M1, but transistor M1 will remain in the off state. In other words, transistor M1 will only turn on when a potential H is applied to the first gate of transistor M1 from wiring 31W, and transistor M1 will not turn on due to the potential applied to the second gate of transistor M1 (which may be a potential of the magnitude corresponding to data 1 or a potential of the magnitude corresponding to data 0).

[0431] Furthermore, although only one type of potential (shown as potential L in Figure 21C) is applied to the wiring 35 at all times, this potential only needs to be smaller than the potential applied to the first terminal of transistor M3 (for example, 0V), and the second terminal of transistor M3 is assumed to be permanently fixed by this potential.

[0432] It should be assumed that data 0 was written to node SN prior to period T1.

[0433] First, during period T1, when a potential H is applied to wiring 31W, transistor M1 turns ON. At the same time, when a potential H is applied to wiring 33, data 1 is written from wiring 33 to node SN via transistor M1 (Figure 21C shows how the potential of node SN rises from potential L to potential H during period T1). Therefore, the operation during period T1 is the writing operation of data 1.

[0434] Next, during period T2, when potential L is applied to wiring 31W, transistor M1 turns off. As a result, data 1 is held at node SN (Figure 21C shows that the potential of node SN is maintained at potential H during period T2).

[0435] Next, during period T3, a potential H is applied to wiring 33. At this time, the potential of wiring 31W remains at potential L, so transistor M1 remains in the off state. Therefore, data 1 continues to be held at node SN. The operation during period T3 is the pre-charging of wiring 33 in preparation for the subsequent data readout operation.

[0436] Next, during period T4, while maintaining the potential of wiring 31W at potential L, potential H is applied to wiring 31R. As a result, transistor M1 remains in the off state, while transistor M3 turns on. Wiring 33 is in a floating state (neither potential H nor potential L is applied). At this time, since node SN holds data 1, transistor M2 also turns on. Therefore, since both transistors M2 and M3 are turned on, the connection between wiring 33 and wiring 35 becomes conductive, and current flows from wiring 33 to wiring 35. Consequently, the potential of wiring 33, which is in a floating state (potential H, precharged in period T3), drops to the potential applied to wiring 35 (potential L) (Figure 21C shows how the potential of wiring 33 decreases from potential H to potential L during period T4). Here, the bit line drive circuit connected to wiring 33 can recognize that data 1 is being held in node SN by detecting that the potential of wiring 33 has changed (in this case decreased) from the potential after precharging (potential H) performed in period T3. Therefore, the operation in period T4 is a data 1 read operation.

[0437] Next, during period T5, while maintaining the potential of wiring 31W at potential L, potential L is applied to wiring 31R. As a result, transistor M3 turns off, and the connection between wiring 33 and wiring 35 becomes non-conductive. At this time, transistor M1 also remains off. Therefore, data 1 continues to be held at node SN.

[0438] Next, during period T6, a potential H is applied to wiring 31W, and transistor M1 turns ON. At the same time, a potential L is applied to wiring 33, and data 0 is written from wiring 33 to node SN via transistor M1 (Figure 21C shows how the potential of node SN decreases from potential H (corresponding to data 1) to potential L (corresponding to data 0) during period T6). Therefore, the operation during period T6 is the writing operation of data 0.

[0439] Next, during period T7, when potential L is applied to wiring 31W, transistor M1 turns off. As a result, data 0 is held at node SN (Figure 21C shows that the potential of node SN is maintained at potential L during period T7).

[0440] Next, during period T8, a potential H is applied to wiring 33. At this time, the potential of wiring 31W remains at potential L, so transistor M1 remains in the off state. Therefore, the data 0 continues to be held at node SN. The operation during period T8 is the pre-charging of wiring 33 in preparation for the subsequent data readout operation.

[0441] Next, during period T9, while maintaining the potential of wiring 31W at potential L, potential H is applied to wiring 31R. As a result, transistor M3 turns ON while transistor M1 remains OFF. Wiring 33 is also left floating. At this time, since node SN holds data 0, transistor M2 is OFF. That is, although transistor M3 is ON, transistor M2 is OFF, so the connection between wiring 33 and wiring 35 is non-conductive, and no current flows between wiring 33 and wiring 35. Therefore, the potential of wiring 33, which is floating (potential H precharged in period T8), does not change during period T9. Here, the bit line drive circuit connected to wiring 33 can recognize that data 0 is held at node SN by detecting that the potential of wiring 33 does not change during period T9 from the potential after precharging in period T8 (potential H). Therefore, the operation during period T9 is a data 0 read operation.

[0442] Next, during period T10, while maintaining the potential of wiring 31W at potential L, potential L is applied to wiring 31R. This turns off transistor M3. Also, potential L is applied to wiring 33 from its floating state. As a result, the potential of wiring 33 decreases from the pre-charged potential H state in period T8 to potential L. At this time, the data 0 is continuously held at node SN.

[0443] As described above, for example, by performing the operations described in periods T1 to T10, the memory cell 21 can perform a series of operations such as writing data 1, holding data 1, reading data 1, writing data 0, holding data 0, and reading data 0.

[0444] <Example of Memory Device Configuration 1> Below, an example of the configuration of multiple memory cells 21 will be described. Specifically, an example of the configuration of a 4x4 memory cell 21 will be described using a plan view. Note that some reference numerals may be omitted in this plan view.

[0445] Figure 22A is a plan view showing an example configuration in which memory cells 21 (corresponding to, for example, the semiconductor device 100 shown in Figures 1A to 1D) are arranged in a matrix.

[0446] As shown in Figure 22A, the conductive layer 112b, which functions as wiring 33, and the conductive layer 112a, which functions as wiring 35, both have regions that extend in the Y direction and are shared by the memory cells 21 arranged in the Y direction. In other words, memory cells 21 in the same row share the same conductive layer 112b and conductive layer 112a, respectively. This prevents current from flowing from multiple wirings 33, which function as read bit lines, into a single wiring 35, which functions as a power line, when reading data held in the memory cell 21. This reduces the current flowing through the wiring 35. Here, according to Ohm's law, the voltage drop ΔV across the wiring is the product of the wiring resistance R and the current I (ΔV = R × I). Therefore, by reducing the current flowing through the wiring 35, it is possible to suppress a decrease in the potential supplied as the power potential, especially in memory cells 21 with a long wiring distance from the power supply circuit 15 shown in Figure 21A. This prevents, for example, data held in the memory cell 21 from being read incorrectly. Thus, it is possible to provide memory cells and semiconductor devices with high read accuracy.

[0447] In the example shown in Figure 22A, each conductive layer 114b, which functions as wiring 31W, has a region extending in the X direction and is shared by memory cells 21 arranged in the X direction. In other words, memory cells 21 in the same row share the same conductive layer 114b. Similarly, each conductive layer 112b, which functions as wiring 33, has a region extending in the Y direction and is shared by memory cells 21 arranged in the Y direction. In other words, memory cells 21 in the same column share the same conductive layer 112b.

[0448] Figures 23A and 23B show cross-sectional views of a 4x4 memory cell 21, the same configuration as shown in the plan view in Figure 22A. Figure 23A is a cross-sectional view in the XZ plane, and Figure 23B is a cross-sectional view in the YZ plane. As shown in the plan view of Figure 22A and the cross-sectional views of Figures 23A and 23B, a semiconductor device according to one embodiment of the present invention can have a configuration in which memory cells 21, each consisting of three transistors stacked, with source electrodes and drain electrodes provided at different heights relative to the substrate surface, are densely arranged in the XY plane. Therefore, not only can the area occupied by individual memory cells in a plan view be reduced, but a semiconductor device with highly integrated multiple memory cells can also be realized.

[0449] Furthermore, as will be described later in Figure 24 and other figures, one embodiment of the present invention can also be configured such that the memory cells 21 are stacked not only in the XY plane but also in the Z direction. By adopting this configuration, further integration of the semiconductor device can be achieved.

[0450] <Example of Memory Device Configuration 2> Below, an example of a memory device configuration in which multiple layers containing the memory cell 21 shown in <Example of Memory Device Configuration 1> are stacked will be explained with reference to the drawings.

[0451] Figure 22B is a perspective view showing an example configuration of the storage device 50. The storage device 50 has a drive circuit layer 61 and n layers (where n is an integer of 1 or more) of storage layers 63. The drive circuit layer 61 is provided with the word line drive circuit 11 and the bit line drive circuit 13 described above. Alternatively, the drive circuit layer 61 may also be configured to include the power supply circuit 15 described above. Memory cells 21 are arranged in a matrix in the storage layers 63. In this embodiment, the n layers of storage layers 63 are distinguished by being referred to as storage layers 63_1 to 63_n. In Figure 22B, storage layers 63_1, 63_2, 63_3, 63_4, and 63_n are shown as storage layers 63.

[0452] In the storage device 50 shown in Figure 22B, an n-layer storage layer 63 is provided on the drive circuit layer 61. This reduces the occupied area of ​​the storage device 50 and increases the storage capacity per unit area.

[0453] Figure 24 is a cross-sectional view showing an example configuration of memory layers 63_1 to 63_4, which are among the memory layers 63_1 to 63_n shown in Figure 22B, and is shown in the XZ plane. As shown in Figure 24, memory layer 63_1 is provided on the substrate 102, memory layer 63_2 is provided on memory layer 63_1, memory layer 63_3 is provided on memory layer 63_2, and memory layer 63_4 is provided on memory layer 63_3. As mentioned above, memory cells 21 are provided in memory layer 63. Figure 24 shows an example configuration of a memory cell array in which two memory cells 21 are integrated in the X direction and four memory cells 21 are integrated in the Z direction.

[0454] In Figure 24, a memory cell 21 provided in memory layer 63_1 (corresponding to, for example, semiconductor device 100) is shown as memory cell 21_1 (in this case, semiconductor device 100_1), a memory cell 21 provided in memory layer 63_2 is shown as memory cell 21_2 (in this case, semiconductor device 100_2), a memory cell 21 provided in memory layer 63_3 is shown as memory cell 21_3 (in this case, semiconductor device 100_3), and a memory cell 21 provided in memory layer 63_4 is shown as memory cell 21_4 (in this case, semiconductor device 100_4).

[0455] An insulating layer 139, which functions as an interlayer insulating layer, is provided on the memory cell 21. In Figure 24, the insulating layer 139 provided on memory cell 21_1 is shown as insulating layer 139_1, the insulating layer 139 provided on memory cell 21_2 is shown as insulating layer 139_2, the insulating layer 139 provided on memory cell 21_3 is shown as insulating layer 139_3, and the insulating layer 139 provided on memory cell 21_4 is shown as insulating layer 139_4. For example, the insulating layer 139 (insulating layers 139_1 to 139_4) can be made of the same material as the insulating layer 110a, insulating layer 110b, insulating layer 110c, and insulating layer 110d shown in the above embodiment.

[0456] Figure 25 is a cross-sectional view showing an example configuration of a drive circuit layer 61, a storage layer 63_1 on the drive circuit layer 61, and a storage layer 63_2 on the storage layer 63_1. Figure 25 is a cross-sectional view obtained by omitting storage layers 63_3 and 63_4 from Figure 24 and adding the drive circuit layer 61. In Figure 25, transistor 300 is shown as a transistor in the drive circuit layer 61.

[0457] The transistor 300 is provided on a substrate 311 and has a conductive layer 316 that functions as a gate electrode, an insulating layer 315 that functions as a gate insulating layer, a semiconductor region 313 that includes a part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 can be either a p-channel type transistor or an n-channel type transistor. For example, a single-crystal silicon substrate can be used as the substrate 311.

[0458] In Figure 25, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, a conductive layer 316 covers the side and top surfaces of the semiconductor region 313 via an insulating layer 315. The conductive layer 316 can also be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor due to its shape, which utilizes the convex portion of the semiconductor substrate. It is also possible to have an insulator that contacts the upper part of the convex portion and functions as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, it is also possible to form a semiconductor film with a convex shape by processing an SOI substrate.

[0459] Note that the transistor 300 shown in Figure 25 is just one example, and its structure is not limited to that example. It is preferable to use an appropriate transistor depending on the circuit configuration or driving method.

[0460] Between each structure, a wiring layer may be provided, which may include an interlayer insulating layer, wiring, plugs, etc. Furthermore, multiple wiring layers may be provided depending on the design. In this specification, the wiring and the plugs connecting to the wiring may also be integrated into a single unit. That is, a portion of the conductor may function as both wiring and a plug.

[0461] For example, on the transistor 300, insulating layers 320, 322, 324, and 326 are sequentially stacked as interlayer insulating layers. A conductive layer 328 is embedded in insulating layers 320 and 322, for example. A conductive layer 330 is embedded in insulating layers 324 and 326, for example. The conductive layers 328 and 330 function as contact plugs or wiring.

[0462] Furthermore, the insulating layer, which functions as an interlayer insulating layer, can also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulating layer 322 can be planarized by a planarizing treatment using the CMP method or the like to improve its flatness.

[0463] A wiring layer can also be provided on the insulating layer 326 and the conductive layer 330. For example, in Figure 25, insulating layers 350, 352, and 354 are sequentially laminated on the insulating layer 326 and the conductive layer 330. A conductive layer 356 is provided on insulating layers 350, 352, and 354. The conductive layer 356 functions as a contact plug or wiring.

[0464] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0465] (Embodiment 4) In this embodiment, an example of an application of a semiconductor device according to one aspect of the present invention will be described with reference to Figures 26A to 27E.

[0466] A semiconductor device according to one aspect of the present invention can be used, for example, in electronic components, large computers, space equipment, data centers (also referred to as DCs), and various electronic devices. By using a semiconductor device according to one aspect of the present invention, it is possible to achieve lower power consumption and higher performance in electronic components, large computers, space equipment, data centers, and various electronic devices.

[0467] Furthermore, a display device having a semiconductor device according to one aspect of the present invention can be used in the display units of various electronic devices. A display device having a semiconductor device according to one aspect of the present invention can be easily made higher resolution and higher definition.

[0468] Examples of electronic devices include television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0469] In particular, a display device according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and mixed reality (MR) devices.

[0470] A display device according to one aspect of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels). In particular, a resolution of 4K, 8K, or higher is preferred. Furthermore, the pixel density (detail) of the display device according to one aspect of the present invention is preferably 100 ppi or more, 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, 5000 ppi or more, or 7000 ppi or more. By using a display device having one or both of these high resolution and / or high detail, it is possible to further enhance the sense of presence and depth. Furthermore, there are no particular limitations on the aspect ratio of the display device according to one embodiment of the present invention. For example, the display device can support various aspect ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0471] The electronic device of this embodiment may have sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0472] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, or text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0473] [Electronic Components] Figure 26A shows a perspective view of a substrate (mounted substrate 1989) on which electronic component 1980 is mounted. The electronic component 1980 shown in Figure 26A has a semiconductor device 1981 inside a mold 1984. Some details are omitted in Figure 26A to show the inside of the electronic component 1980. The electronic component 1980 has a land 1985 on the outside of the mold 1984. The land 1985 is connected to an electrode pad 1986, and the electrode pad 1986 is connected to the semiconductor device 1981 via a wire 1987. The electronic component 1980 is mounted, for example, on a printed circuit board 1988. Multiple such electronic components are combined and connected on the printed circuit board 1988 to complete the mounted substrate 1989.

[0474] Furthermore, the semiconductor device 1981 has a drive circuit layer 1982 and a storage layer 1983. The storage layer 1983 has a configuration in which multiple memory cell arrays are stacked. The configuration in which the drive circuit layer 1982 and the storage layer 1983 are stacked can be a monolithic stack configuration. In a monolithic stack configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding. By monolithically stacking the drive circuit layer 1982 and the storage layer 1983, for example, a so-called on-chip memory configuration can be achieved in which memory is directly formed on the processor. By using an on-chip memory configuration, it is possible to speed up the operation of the interface portion between the processor and the memory.

[0475] Furthermore, by using an on-chip memory configuration, the size of connection wiring can be reduced compared to technologies using through-hole electrodes such as TSVs, making it possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, which in turn improves the memory bandwidth (also called memory bandwidth).

[0476] Furthermore, it is preferable to form the multiple memory cell arrays of the memory layer 1983 using OS transistors and to stack these multiple memory cell arrays monolithically. By configuring the multiple memory cell arrays in a monolithic stack, it is possible to improve either or both of the memory bandwidth and / or the memory access latency. Bandwidth is the amount of data transferred per unit time, and access latency is the time from access to the start of data exchange. In the case of a configuration using Si transistors in the memory layer 1983, it is difficult to create a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0477] The semiconductor device 1981 may also be referred to as a die. In this specification, a die refers to a chip piece obtained in the semiconductor chip manufacturing process by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) and cutting it into cubes. Examples of semiconductor materials that can be used for dies include silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon die.

[0478] Next, a perspective view of the electronic component 1990 is shown in Figure 26B. The electronic component 1990 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). The electronic component 1990 has an interposer 1991 provided on a package substrate 1992 (printed circuit board), and a semiconductor device 1994 and a plurality of semiconductor devices 1981 are provided on the interposer 1991.

[0479] Electronic component 1990 shows an example of using semiconductor device 1981 as a high-bandwidth memory (HBM). Furthermore, semiconductor device 1994 can be used in integrated circuits such as CPUs, GPUs (Graphics Processing Units), or FPGAs (Field Programmable Gate Arrays).

[0480] The package substrate 1992 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 1991 can be, for example, a silicon interposer or a resin interposer.

[0481] The interposer 1991 has multiple wirings and functions to connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 1991 also has the function of connecting integrated circuits provided on the interposer 1991 to electrodes provided on the package substrate 1992. For these reasons, the interposer is sometimes called a "redistribution substrate" or "intermediate substrate". In addition, through electrodes may be provided on the interposer 1991, and these through electrodes may be used to connect the integrated circuits and the package substrate 1992. Furthermore, in silicon interposers, TSVs can also be used as through electrodes.

[0482] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0483] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0484] On the other hand, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space is required, such as the width of the terminal pitch. Therefore, when attempting to reduce the size of electronic component 1990, the width of the terminal pitch becomes a problem, and it may become difficult to provide the many wires necessary to achieve a wide memory bandwidth. For this reason, as mentioned above, a monolithic stacked configuration using OS transistors is preferable. A composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array may also be used.

[0485] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 1990. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 1991. For example, in the electronic component 1990 shown in this embodiment, it is preferable to align the heights of the semiconductor device 1981 and the semiconductor device 1994.

[0486] To mount the electronic component 1990 onto another substrate, electrodes 1993 may be provided at the bottom of the package substrate 1992. Figure 26B shows an example in which the electrodes 1993 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 1992, BGA (Ball Grid Array) mounting can be realized. Alternatively, the electrodes 1993 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 1992, PGA (Pin Grid Array) mounting can be realized.

[0487] The electronic component 1990 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0488] [Large-scale computer] Next, Figure 27A shows a perspective view of the large-scale computer 5600. The large-scale computer 5600 shown in Figure 27A has multiple rack-mount type computers 5620 housed in rack 5610. The large-scale computer 5600 may also be called a supercomputer.

[0489] The computer 5620 can have the configuration shown in the perspective view in Figure 27B, for example. In Figure 27B, the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into a slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0490] The PC card 5621 shown in Figure 27C is an example of a processing board equipped with a CPU, GPU, storage device, etc. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Although Figure 27C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, you can refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below for details on these semiconductor devices.

[0491] The connector 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and functions as an interface for connecting the PC card 5621 and the motherboard 5630. Examples of standards for the connector 5629 include PCIe.

[0492] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, power supply and signal input to the PC card 5621. They can also serve as interfaces for, for example, outputting signals calculated by the PC card 5621. Examples of standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, examples of standards include HDMI (registered trademark).

[0493] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0494] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be connected by soldering these terminals to the wiring provided on the board 5622, for example, using a reflow soldering method. Examples of semiconductor devices 5627 include FPGAs, GPUs, and CPUs. For example, an electronic component 1990 can be used as the semiconductor device 5627.

[0495] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be connected by soldering these terminals to the wiring on the board 5622, for example, using a reflow soldering method. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 1990 can be used as the semiconductor device 5628.

[0496] The 5600 mainframe computer can also function as a parallel computer. By using the 5600 mainframe computer as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0497] [Space Equipment] A semiconductor device according to one aspect of the present invention can be suitably used in space equipment.

[0498] One embodiment of the present invention includes an OS transistor. Compared to Si transistors, OS transistors exhibit smaller fluctuations in electrical properties due to radiation exposure. In other words, they have high resistance to radiation, making them highly reliable and suitable for use in environments where radiation may be incident. For example, OS transistors are suitable for use in outer space. Specifically, OS transistors can be used in transistors constituting semiconductor devices installed in space shuttles, artificial satellites, or space probes. Examples of radiation include X-rays and neutrons. Outer space refers, for example, to an altitude of 100 km or higher, but outer space as described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0499] Figure 27D shows an example of space equipment, specifically a satellite 6800. The satellite 6800 comprises a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 27D, a planet 6804 is shown as an example in outer space.

[0500] Furthermore, although not shown in Figure 27D, a battery management system (also known as a BMS) or a battery control circuit may be provided with the secondary battery 6805. Using an OS transistor in the aforementioned battery management system or battery control circuit is preferable because it consumes little power and has high reliability even in outer space.

[0501] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.

[0502] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel is not exposed to sunlight, or if the amount of sunlight shining on the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to equip the satellite 6800 with a secondary battery 6805. Note that solar panels are sometimes called solar cell modules.

[0503] The artificial satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another artificial satellite. By receiving the signal transmitted by the artificial satellite 6800, the position of the receiver that received the signal can be measured. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0504] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 6807.

[0505] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected after hitting an object on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0506] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes.

[0507] As explained above, OS transistors have superior advantages compared to Si transistors, such as the ability to achieve a wider memory bandwidth and higher radiation resistance.

[0508] [Data Center] One embodiment of the present invention is suitably used in storage systems applied to data centers, for example. Data centers are required to manage data over the long term, such as by ensuring the immutability of the data. Managing data over the long term requires the installation of storage and servers to store vast amounts of data, securing a stable power supply to hold the data, or securing cooling equipment required for data storage, which necessitates the construction of larger buildings.

[0509] By using a semiconductor device according to one aspect of the present invention in a storage system applied to a data center, it is possible to reduce the power required for data retention and miniaturize the semiconductor device that holds the data. Therefore, it is possible to miniaturize the storage system, the power supply for data retention, and the cooling equipment. This, in turn, contributes to space savings in the data center.

[0510] Furthermore, since the semiconductor device according to one aspect of the present invention has low power consumption, heat generation from the circuit can be reduced. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using the semiconductor device according to one aspect of the present invention, a data center that operates stably even in high-temperature environments can be realized. Therefore, the reliability of the data center can be improved.

[0511] Figure 27E shows a storage system applicable to a data center. The storage system 7010 shown in Figure 27E has multiple servers 7001sb as hosts 7001 (indicated as Host Computer) and multiple storage devices 7003md as storage 7003 (indicated as Storage). The host 7001 and storage 7003 are connected via a storage area network 7004 (SAN) and a storage control circuit 7002 (indicated as Storage Controller).

[0512] Host 7001 corresponds to a computer that accesses data stored in storage 7003. The hosts 7001 may be connected to each other via a network.

[0513] Although storage 7003 uses flash memory to shorten data access speed, that is, the time required for data storage and retrieval, this time is significantly longer than the time required for DRAM, which can be used as cache memory within the storage. In storage systems, cache memory is usually provided within the storage to shorten the time required for data storage and retrieval in order to solve the access speed problem of storage 7003.

[0514] The aforementioned cache memory is used within the storage control circuit 7002 and storage 7003. Data exchanged between the host 7001 and storage 7003 is stored in the cache memory within the storage control circuit 7002 and storage 7003, and then output to the host 7001 or storage 7003.

[0515] By using OS transistors as the transistors for storing the aforementioned cache memory data, and configuring them to maintain a potential corresponding to the data, the frequency of refresh can be reduced, thereby lowering power consumption. Furthermore, miniaturization is possible by stacking the memory cell arrays.

[0516] Furthermore, by applying a semiconductor device according to one aspect of the present invention to one or more selected from electronic components, large computers, space equipment, data centers, and electronic devices, power consumption can be reduced. Therefore, as energy demand is expected to increase with the performance or integration of semiconductor devices, using a semiconductor device according to one aspect of the present invention can reduce carbon dioxide (CO2) emissions. ２ It is also possible to reduce greenhouse gas emissions, such as those represented by [specific examples of greenhouse gas emissions]. Furthermore, because the semiconductor device according to one aspect of the present invention consumes little power, it is also effective as a measure against global warming.

[0517] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0518] 10_1: Transistor, 10_2: Transistor, 10_3: Transistor, 10A_1: Transistor, 10A_2: Transistor, 10A_3: Transistor, 10B_1: Transistor, 10B_2: Transistor, 10B_3: Transistor, 10C_1: Transistor, 10C_2: Transistor, 10C_3: Transistor, 11: Word line drive circuit, 13: Bit line drive circuit, 15: Power supply circuit, 20: Memory unit, 21: Memory cell, 21_1: Memory cell, 21_2: Memory cell, 21_3: Memory cell, 21_4: Memory cell, 31: Wiring, 31R: Wiring, 31W: Wiring, 33: Wiring, 35: Wiring, 50: Memory device, 61: Drive circuit layer, 63: Memory layer, 63_1: Memory layer, 63_2: Memory layer, 63_3: Memory layer, 63_4: Memory layer, 63_n: Memory layer, 100: Semiconductor device, 100_1: Semiconductor device, 100_2: Semiconductor device, 100_3: Semiconductor device, 100_4: Semiconductor device, 100A: Semiconductor device, 100B: Semiconductor device, 100C: Semiconductor device, 102: Substrate, 104: Conductive layer, 104a: Conductive layer, 104b: Conductive layer, 104f: Conductive film, 106: Insulating layer, 106f: Insulating film, 1 06s: insulating layer, 108: semiconductor layer, 108e: semiconductor layer, 108f: semiconductor film, 110a: insulating layer, 110b: insulating layer, 110c: insulating layer, 110d: insulating layer, 112a: conductive layer, 112b: conductive layer, 114a: conductive layer, 114b: conductive layer, 115: layer, 115e: layer, 115f: film, 116a: insulating layer, 116b: insulating layer, 120: opening, 139: insulating layer, 139_1: insulating layer, 139_2: insulating layer, 139_3: insulating layer, 139_4: insulating layer, 190: resist mask, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resist 314b: Low-resistance region, 315: Insulating layer, 316: Conductive layer, 320: Insulating layer, 322: Insulating layer, 324: Insulating layer, 326: Insulating layer, 328: Conductive layer, 330: Conductive layer, 350: Insulating layer, 352: Insulating layer, 354: Insulating layer, 356: Conductive layer, 1980: Electronic component, 1981: Semiconductor device, 1982: Drive circuit layer, 1983: Memory layer, 1984: Mold, 1985: Land, 1986: Electrode pad, 1987: Wire, 1988: Printed circuit board, 1989: Mounted circuit board, 1990: Electronic component, 1991: Interposer, 1992: Package circuit board,1993: Electrode, 1994: Semiconductor equipment, 5600: Mainframe computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connector, 5624: Connector, 5625: Connector, 5626: Semiconductor equipment, 5627: Semiconductor equipment, 5628: Semiconductor equipment, 5629: Connector, 5630: Motherboard, 5631: Slot, 6800: Satellite, 6801: Aircraft body, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Secondary battery, 6807: Control device, 7001: Host, 7001sb: Server, 7002: Storage control circuit, 7003: Storage, 7003md: Memory device, 7004: Storage area network, 7010: Storage system

Claims

It comprises a first conductive layer to a fifth conductive layer, a semiconductor layer, and a first insulating layer to a seventh insulating layer. The first insulating layer is located overlapping the first conductive layer, The second conductive layer is located on top of the first insulating layer, The second insulating layer is located overlapping the second conductive layer, The third conductive layer is located on top of the second insulating layer, The third insulating layer is located overlapping the third conductive layer, The fourth conductive layer is located on top of the third insulating layer, The fourth insulating layer is positioned overlapping the fourth conductive layer, The first insulating layer, the second conductive layer, the second insulating layer, the third conductive layer, the third insulating layer, the fourth conductive layer, and the fourth insulating layer each have an opening that reaches the first conductive layer. The fifth insulating layer is located on the side of the second conductive layer facing the opening, The sixth insulating layer is located on the side of the fourth conductive layer facing the opening, The semiconductor layer is in contact with the upper surface of the first conductive layer, the side surface of the first insulating layer, the side surface of the fifth insulating layer, the side surface of the second insulating layer, the side surface of the third conductive layer, the side surface of the third insulating layer, the side surface of the sixth insulating layer, and the side surface of the fourth insulating layer, respectively, within the opening. The seventh insulating layer is located on the semiconductor layer, The fifth conductive layer is located on the seventh insulating layer, The fifth conductive layer has a first region located within the opening and a second region located on the opening and in contact with the semiconductor layer. Semiconductor equipment. 　 In claim 1, The first conductive layer and the third conductive layer each contain a first element and oxygen, The second conductive layer and the fourth conductive layer each contain the second element, The fifth insulating layer and the sixth insulating layer each contain the second element and oxygen. The first element is one or more of indium, tin, and silicon. The second element is one or more of tantalum, tungsten, and aluminum. Semiconductor equipment. 　 In claim 1 or claim 2, In the seventh insulating layer, the height of the upper surface in the region where the surface to be formed is parallel to the upper surface of the first conductive layer is higher than the height of the upper surface of the second conductive layer. Semiconductor equipment. 　 In claim 3, The semiconductor layer comprises indium and oxygen. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer each contain silicon and oxygen. Semiconductor equipment. 　 In claim 1 or claim 2, A first layer is provided between the seventh insulating layer and the first region. The height of the upper surface of the first layer is greater than the height of the upper surface of the second conductive layer. Semiconductor equipment. 　 In claim 5, The semiconductor layer comprises indium and oxygen. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer each contain silicon and oxygen. Semiconductor equipment. In claim 1 or claim 2, The semiconductor layer has a third region located within the opening and a fourth region located outside the opening. The second region is in contact with the upper surface of the fourth region. Semiconductor equipment. 　 In claim 7, The semiconductor layer comprises indium and oxygen. The first insulating layer, the second insulating layer, the third insulating layer, and the fourth insulating layer each contain silicon and oxygen. Semiconductor equipment. 　 A first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a third conductive layer, a third insulating layer, a fourth conductive layer, and a fourth insulating layer are formed in this order, each having an overlapping region. An opening reaching the first conductive layer is formed in the first insulating layer, the second conductive layer, the third conductive layer, the third insulating layer, the fourth conductive layer, and the fourth insulating layer. A first treatment is performed to oxidize the side surface of the second conductive layer and the side surface of the fourth conductive layer within the opening, thereby forming a fifth insulating layer on the side surface of the second conductive layer and a sixth insulating layer on the side surface of the fourth conductive layer. Method for manufacturing semiconductor devices. 　 In claim 9, the first treatment is a heating treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere. Method for manufacturing semiconductor devices. 　 In claim 9 or claim 10, After the formation of the fifth insulating layer and the sixth insulating layer, a semiconductor film is formed in contact with the opening and the upper surface of the fourth insulating layer, respectively. A first insulating film and a first conductive film are formed on the semiconductor film in this order. A portion of the first conductive film, the first insulating film, and the semiconductor film is removed to expose the upper surface of the fourth insulating layer, and a fifth conductive layer is formed from the first conductive film, a seventh insulating layer from the first insulating film, and a semiconductor layer from the semiconductor film. A sixth conductive layer is formed on the fifth conductive layer, the seventh insulating layer, and the semiconductor layer, such that it has a region overlapping with the aforementioned opening. Method for manufacturing semiconductor devices. 　 In claim 9 or claim 10, After the formation of the fifth insulating layer and the sixth insulating layer, a semiconductor film is formed in contact with the opening and the upper surface of the fourth insulating layer, respectively. A first insulating film and a first film are formed on the semiconductor film in this order. A portion of the first film, the first insulating film, and the semiconductor film is removed to expose the upper surface of the fourth insulating layer, and a first layer is formed from the first film, a seventh insulating layer from the first insulating film, and a semiconductor layer from the semiconductor film. A resist mask is formed on the fourth insulating layer so as not to overlap with the first layer. A portion of the first layer is removed to form a second layer whose upper surface height is greater than that of the second conductive layer. Remove the aforementioned resist mask, A first conductive film is formed on the second layer, the seventh insulating layer, the semiconductor layer, and the fourth insulating layer so as to fill the opening. A portion of the first conductive film is removed to form a seventh conductive layer having a region that overlaps with the opening. Method for manufacturing semiconductor devices. 　 In claim 9 or claim 10, After the formation of the fifth insulating layer and the sixth insulating layer, a semiconductor film is formed in contact with the opening and the upper surface of the fourth insulating layer, respectively. A portion of the semiconductor film is removed to form a first semiconductor layer having a region that overlaps with the opening and is in contact with the upper surface of the fourth insulating layer. A first insulating film and a first conductive film are formed on the first semiconductor layer in this order. By removing a portion of the first conductive film, the first insulating film, and the first semiconductor layer, an eighth conductive layer, a seventh insulating layer, and a second semiconductor layer are formed, respectively, whose heights are approximately the same outside the opening. A ninth conductive layer is formed on the eighth conductive layer, the seventh insulating layer, and the second semiconductor layer, having a region that overlaps with the second semiconductor layer. Method for manufacturing semiconductor devices.

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