Semiconductor device and production method for semiconductor device

Abstract

The present invention provides a semiconductor device that has a transistor that has high field-effect mobility. A semiconductor device according to the present invention has a semiconductor layer, a conductive layer, a first insulating layer, and a second insulating layer. The semiconductor layer has a region that contacts an upper surface of the first insulating layer. The semiconductor layer includes indium oxide. The semiconductor layer includes fluorine. The semiconductor layer has a first region that coincides with the conductive layer with the second insulating layer therebetween and a pair of second regions that sandwich the first region. The second regions include an impurity element. The impurity element is at least one of hydrogen, boron, phosphorus, and fluorine. The second regions have a higher concentration of the impurity element than the first region.

Description

Semiconductor device and method for manufacturing a semiconductor device.

[0001] One aspect of the present invention relates to a display device and a method for manufacturing the same. Another aspect of the present invention relates to a transistor and a method for manufacturing the same. Another aspect of the present invention relates to a display device having a transistor.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), devices having such circuits, etc. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have a semiconductor device.

[0004] In recent years, there has been a growing demand for high-definition display devices. Devices requiring high-definition display capabilities include those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), all of which are being actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also called light-emitting devices). Examples of light-emitting elements include organic EL (Electroluminescence) elements and light-emitting diodes (LEDs). Patent document 1 discloses a high-definition display device using organic EL elements.

[0006] Technology related to transistors using semiconductor thin films is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also attracting attention as other materials.

[0007] Examples of oxide semiconductors applicable to transistors include indium oxide and indium gallium zinc oxide. Non-patent document 1 discloses a thin-film transistor using polycrystalline indium hydrogenate formed by low-temperature solid-phase crystallization.

[0008] International Publication No. 2016 / 038508

[0009] Y. Magari et al. , “High-mobility hydrogenated polycrystalline In▲2▼O▲3▼(In▲2▼O▲3▼:H) thin-film transistors”, nature COMMUNICATIONS, 13, 1078 (2022)

[0010] One aspect of the present invention aims to provide a semiconductor device having a transistor with high field-effect mobility. Alternatively, it aims to provide a semiconductor device having a transistor with a large on-current. Alternatively, it aims to provide a semiconductor device having a transistor of a very small size. Alternatively, it aims to provide a semiconductor device having a transistor with a short channel length. Alternatively, it aims to provide a semiconductor device having a transistor with good electrical characteristics. Alternatively, it aims to provide a semiconductor device that operates at high speed. Alternatively, it aims to provide a semiconductor device with a small footprint. Alternatively, it aims to provide a semiconductor device with low wiring resistance. Alternatively, it aims to provide a semiconductor device or display device with low power consumption. Alternatively, it aims to provide a transistor, semiconductor device, or display device with high reliability. Alternatively, it aims to provide a high-definition display device. Alternatively, it aims to provide a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Alternatively, it aims to provide a method for manufacturing a transistor, semiconductor device, or display device with high productivity. Alternatively, it aims to provide a novel transistor, semiconductor device, display device, or method for manufacturing the same.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0012] One aspect of the present invention is a semiconductor device having a semiconductor layer, a conductive layer, a first insulating layer, and a second insulating layer. The semiconductor layer has a region in contact with the upper surface of the first insulating layer. The semiconductor layer contains indium oxide. The semiconductor layer contains fluorine. The semiconductor layer has a first region that overlaps with the conductive layer via the second insulating layer, and a pair of second regions that sandwich the first region. The second regions contain impurity elements. The impurity elements are one or more of hydrogen, boron, phosphorus, and fluorine. The concentration of the impurity elements in the second regions is higher than the concentration of the impurity elements in the first region.

[0013] In the aforementioned semiconductor device, the first insulating layer preferably contains fluorine.

[0014] One aspect of the present invention is a semiconductor device having a semiconductor layer, a conductive layer, a first insulating layer, and a second insulating layer. The semiconductor layer has a region in contact with the upper surface of the first insulating layer. The semiconductor layer contains indium, element M, and oxygen. Element M is one or more of gallium, aluminum, and tin. The semiconductor layer contains fluorine. The semiconductor layer has a first region that overlaps with the conductive layer via the second insulating layer, and a pair of second regions that sandwich the first region. The second regions contain impurity elements. The impurity elements are one or more of hydrogen, boron, phosphorus, and fluorine. The concentration of the impurity elements in the second regions is higher than the concentration of the impurity elements in the first region.

[0015] In the aforementioned semiconductor device, the first insulating layer preferably contains fluorine.

[0016] In the aforementioned semiconductor device, the indium content in the semiconductor layer is preferably 60% to 99%.

[0017] In the aforementioned semiconductor device, the semiconductor layer preferably comprises a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. The second metal oxide layer preferably has a region with a higher hydrogen concentration than the first metal oxide layer and the third metal oxide layer, respectively.

[0018] In the aforementioned semiconductor device, the second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ Preferably, the following regions are present: The first metal oxide layer and the third metal oxide layer each preferably have a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer.

[0019] In the semiconductor device described above, it is preferable that the second metal oxide layer has a region with a lower film density than the first metal oxide layer and the third metal oxide layer, respectively.

[0020] In the aforementioned semiconductor device, it is preferable that the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer and the thickness of the third metal oxide layer.

[0021] One aspect of the present invention is a method for manufacturing a semiconductor device comprising: forming a first insulating layer; performing plasma treatment on the first insulating layer using a gas containing fluorine; forming a metal oxide film on the first insulating layer; performing heat treatment on the first insulating layer and the metal oxide film; processing the metal oxide film into island shapes to form a semiconductor layer; forming a second insulating layer on the semiconductor layer; forming a conductive layer on the second insulating layer; and using the conductive layer as a mask, supplying impurity elements to regions of the semiconductor layer that do not overlap with the conductive layer, wherein the impurity elements are one or more types of hydrogen, boron, phosphorus, and fluorine.

[0022] In the aforementioned method for fabricating semiconductor devices, it is preferable to use nitrogen trifluoride gas as the gas.

[0023] In the aforementioned method for manufacturing semiconductor devices, it is preferable to use a plasma CVD apparatus for plasma processing.

[0024] In the aforementioned method for manufacturing semiconductor devices, it is preferable to use a plasma CVD apparatus for forming the first insulating layer. After forming the first insulating layer, it is preferable to perform continuous plasma processing in a vacuum.

[0025] One aspect of the present invention can provide a semiconductor device having a transistor with high field-effect mobility. Or, a semiconductor device having a transistor with high on-current can be provided. Or, a semiconductor device having a transistor of a very small size can be provided. Or, a semiconductor device having a transistor with a short channel length can be provided. Or, a semiconductor device having a transistor with good electrical characteristics can be provided. Or, a semiconductor device that operates at high speed can be provided. Or, a semiconductor device with a small footprint can be provided. Or, a semiconductor device with low wiring resistance can be provided. Or, a semiconductor device or display device with low power consumption can be provided. Or, a transistor, semiconductor device, or display device with high reliability can be provided. Or, a high-definition display device can be provided. Or, a method for manufacturing the aforementioned transistor, semiconductor device, or display device can be provided. Or, a method for manufacturing a transistor, semiconductor device, or display device with high productivity can be provided. Or, a novel transistor, semiconductor device, display device, or method for manufacturing them can be provided.

[0026] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0027] Figure 1A is a top view showing an example of a semiconductor device. Figures 1B and 1C are cross-sectional views showing an example of a semiconductor device. Figure 2A is a top view showing an example of a semiconductor device. Figures 2B and 2C are cross-sectional views showing an example of a semiconductor device. Figures 3A and 3B are cross-sectional views showing an example of a semiconductor device. Figures 4A, 4B, 4C, and 4D are cross-sectional views showing an example of a semiconductor device. Figure 5A is a top view showing an example of a semiconductor device. Figure 5B is a cross-sectional view showing an example of a semiconductor device. Figures 6A, 6B, and 6C are cross-sectional views showing an example of a semiconductor device. Figures 7A and 7B are cross-sectional views showing an example of a semiconductor device. Figures 8A and 8B are cross-sectional views showing an example of a semiconductor device. Figure 9A is a top view showing an example of a semiconductor device. Figures 9B and 9C are cross-sectional views showing an example of a semiconductor device. Figures 10A, 10B, 10C, 10D, 10E, and 10F are cross-sectional views showing an example of a method for manufacturing a semiconductor device. Figures 11A, 11B, 11C, 11D, and 11E are cross-sectional views showing an example of a semiconductor device manufacturing method. Figures 12A, 12B, 12C, 12D, and 12E are cross-sectional views showing an example of a semiconductor device manufacturing method. Figure 13A is a perspective view showing an example of a display device. Figures 13B and 13C are circuit diagrams showing an example of a sub-pixel. Figures 14A and 14B are circuit diagrams showing an example of a sub-pixel. Figures 15A and 15B are cross-sectional views showing an example of a display device. Figure 16 is a cross-sectional view showing an example of a display device. Figure 17 is a cross-sectional view showing an example of a display device. Figures 18A, 18B, and 18C are cross-sectional views showing an example of a display device. Figures 19A and 19B are cross-sectional views showing an example of a display device. Figure 20 is a cross-sectional view showing an example of a display device. Figure 21 is a cross-sectional view showing an example of a display device. Figure 22 is a cross-sectional view showing an example of a display device. Figures 23A, 23B, 23C, and 23D are diagrams showing an example of an electronic device. Figures 24A, 24B, 24C, 24D, 24E, and 24F show examples of electronic devices. Figures 25A, 25B, 25C, 25D, 25E, 25F, and 25G show examples of electronic devices.

[0028] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0029] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for parts that are identical or have similar functions, and repeated explanations are omitted. In addition, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0030] The position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0031] In this specification, ordinal numbers such as "first," "second," etc., are used to avoid confusion of components and do not limit the number of components or the order of components (e.g., process order or stacking order). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0032] In this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". Furthermore, when describing a common matter for multiple elements with identifying numerals, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0033] The words "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0034] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0035] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source terminal and drain terminal, or source electrode and drain electrode, depending on the situation.

[0036] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as gate electrode and back gate electrode, etc., depending on the context.

[0037] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A and B refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0038] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0039] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0040] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0041] In this specification, unless otherwise specified, on-current refers to the drain current (also called the conduction state) when the transistor is in the on state. Unless otherwise specified, the on state refers to the state in an n-channel transistor where the voltage between the gate and source (gate voltage, also called Vg or Vgs) is equal to or greater than the threshold voltage (also called Vth), and in a p-channel transistor where it is less than or equal to the threshold voltage.

[0042] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0043] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0044] In this specification, the top surface shape of a component refers to the contour shape of the component when viewed from above (also called a plan view). Furthermore, a top view refers to viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0045] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in this case, it may also be said that the "matching or roughly matching top shapes" apply. Furthermore, when the top shapes match or roughly match, it can also be said that the "edges match or roughly match," or "the edges are aligned or roughly aligned."

[0046] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed is sometimes referred to as the taper angle.

[0047] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step).

[0048] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0049] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (Metal Mask) structured devices. Furthermore, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (Metal Maskless) structured devices.

[0050] In this specification, a structure in which different light-emitting layers are created using light-emitting devices with different emission wavelengths is sometimes referred to as an SBS (Side By Side) structure.

[0051] In this specification, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0052] In this specification, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element includes a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other as a common electrode.

[0053] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, regardless of whether it is elastic or able to return to its original shape.

[0054] For example, flexible electronic devices, flexible display devices (also called flexible displays, etc.), flexible batteries (also called flexible batteries, etc.), and flexible substrates (also called flexible substrates, etc.) can each be deformed in response to external forces. Flexible electronic devices, flexible display devices, flexible batteries, and flexible substrates can each be used fixed in a deformed state, used after repeated deformation, or used in an undeformed state. The phrase "deforms in response to external forces" above means that it can be deformed by the average adult's hand without requiring excessive force. Flexibleness can be evaluated using testing machines capable of stress-strain measurement (tensile testing machines, compression testing machines, etc.). In stress-strain measurement, the flexibility of an object can be quantified by applying an external force to the object and measuring the strain of the object caused by the resulting stress.

[0055] In this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may have parts that are not flexible.

[0056] (Embodiment 1) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to Figures 1A to 12E. The semiconductor device according to one aspect of the present invention can be suitably used, for example, in one or both of the pixel circuit and the drive circuit of a display device.

[0057] <Configuration Example 1> Figure 1A shows a top view (also called a plan view) of a semiconductor device 10, which is one embodiment of the present invention. Figure 1B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 1A, and Figure 1C shows a cross-sectional view of the cross-section along the dashed-dotted line B1-B2. Note that in Figure 1A, some of the components of the semiconductor device 10 (such as the gate insulating layer) are omitted. In the top view of the semiconductor device, as in Figure 1A, some of the components are omitted in the following drawings as well.

[0058] The semiconductor device 10 has a transistor 100. The transistor 100 has an insulating layer 105 on a substrate 102, a semiconductor layer 108 on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108, and a conductive layer 104 on the insulating layer 106. The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. The conductive layer 104 functions as the gate electrode of the transistor 100, and the insulating layer 106 functions as a gate insulating layer. An insulating layer 195 is provided on the conductive layer 104 and the insulating layer 106.

[0059] The semiconductor layer 108 has a region 108i that overlaps with the conductive layer 104 via the insulating layer 106, and a pair of regions (region 108P and region 108Q) that sandwich region 108i. Regions 108P and 108Q do not overlap with the conductive layer 104. In the transistor 100, region 108i functions as a channel formation region, region 108P functions as one of the source region and drain region, and region 108Q functions as the other of the source region and drain region.

[0060] The semiconductor layer 108 preferably has a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties. The band gap of the metal oxide is preferably 2.0 eV or more, and more preferably 2.5 eV or more. Transistors using oxide semiconductors (hereinafter also referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably low off-current and can retain the charge stored in a capacitor connected in series with the transistor for a long period of time. In addition, the power consumption of semiconductor devices can be reduced by applying OS transistors. When an oxide semiconductor is used for the semiconductor layer, the semiconductor layer can be called an oxide semiconductor layer or a metal oxide layer.

[0061] Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. Furthermore, it is preferable that the metal oxide contains at least indium. Alternatively, it is preferable that the metal oxide contains either or both indium and element M. Alternatively, it is preferable that the metal oxide contains either or both indium and zinc. Alternatively, it is preferable that the metal oxide has one or more elements selected from indium, element M, and zinc. Element M is a metallic or metalloid element with a high bond energy to oxygen; for example, a metallic or metalloid element with a higher bond energy to oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have high bonding energy with oxygen and their ionic radii are similar to those of indium or zinc. Furthermore, tin is more preferred because its tetravalent state can increase carrier mobility. In this specification, metallic elements and metalloid elements are sometimes collectively referred to as "metallic elements," and the "metallic elements" described in this specification may include metalloid elements.

[0062] The semiconductor layer 108 preferably contains indium and oxygen. For example, indium oxide (also written as IO) can be suitably used as the semiconductor layer 108. Alternatively, the semiconductor layer 108 preferably contains indium, element M, and oxygen. Typically, gallium can be suitably used as element M. For example, indium gallium oxide (In-Ga oxide, also written as IGO) can be suitably used as the semiconductor layer 108. Note that transistors using indium oxide in the channel formation region are sometimes referred to as IO transistors, and transistors using indium gallium oxide are sometimes referred to as IGO transistors. Furthermore, gallium may be used as an example of element M in the explanation.

[0063] By increasing the indium content in the metal oxide, the field-effect mobility of the transistor can be increased. Furthermore, a transistor with a high on-current can be realized. The atomic ratio of indium in the metal oxide is preferably equal to or greater than the atomic ratio of element M. The indium content in the metal oxide is preferably 50% to 100%, more preferably 60% to 100%, more preferably 60% to 99%, more preferably 70% to 99%, more preferably 80% to 99%, more preferably 80% to 98%, more preferably 80% to 96%, more preferably 86% to 94%, and more preferably 80% to 92%. However, the indium content is not limited to the above ranges.

[0064] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0065] A metal oxide containing indium and element M can be used for the semiconductor layer 108. The presence of element M allows for oxygen vacancies (V) in the metal oxide. ＯThe formation of ) is suppressed, and carrier generation due to oxygen vacancies is suppressed. As a result, the threshold voltage of the transistor is suppressed, the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage (Vg) is 0V can be reduced, and a normally-off transistor can be made. In addition, a transistor with a small off-current can be made. Fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved. For example, fluctuations in electrical characteristics due to photo-negative bias (hereinafter also referred to as photo-negative bias degradation) can be suppressed.

[0066] However, if the content of element M in the metal oxide is too high, the content of indium will decrease, which may result in a low field-effect mobility. Therefore, it is preferable that the atomic ratio of element M in the metal oxide is less than or equal to the atomic ratio of indium, and even more preferably lower than the atomic ratio of indium.

[0067] The composition of the metal oxide applied to the semiconductor layer 108 can be used to alter the electrical characteristics and reliability of the transistor. Therefore, it is preferable to select the content of indium and element M according to the electrical characteristics and reliability required for the transistor. Typically, it is preferable to use indium gallium oxide with an indium content of 60% to 99% for the semiconductor layer 108. This makes it possible to create a transistor that achieves both high field-effect mobility and high reliability.

[0068] When the metal oxide is an In-M oxide, it is preferable to use metal oxides with atomic ratios of the metal elements such as In:M = 99:1, In:M = 98:2 (49:1), In:M = 97:3, In:M = 95:5 (19:1), In:M = 10:1, In:M = 5:1, In:M = 4:1, In:M = 3:1, In:M = 2:1, or close to these. Typically, metal oxides with any of these atomic ratios and in which element M is Ga can be suitably used.

[0069] The semiconductor layer 108 preferably contains a first element. At least the region 108i preferably contains the first element. As the first element, a halogen (e.g., chlorine, fluorine, and bromine) can be used.

[0070] As described above, by using a metal oxide with a high indium content for the semiconductor layer 108, a transistor with high field-effect mobility can be obtained. However, a metal oxide with a high indium content is prone to oxygen vacancies, and the number of oxygen vacancies in the semiconductor layer 108 may increase in some cases. In addition, a defect in which hydrogen enters an oxygen vacancy (hereinafter referred to as V Ｏ H) functions as a donor and may generate electrons that serve as carriers. This may cause a shift in the threshold voltage of the transistor. In addition, the reliability of the transistor may be reduced. Particularly in a transistor with a short channel length, the influence of oxygen vacancies and V in the channel formation region on electrical characteristics is greater, and the transistor tends to be normally-on. Ｏ H has a greater effect on electrical characteristics, and the device tends to be normally-on.

[0071] When the region 108i contains the first element, the first element can compensate for oxygen vacancies and reduce the number of oxygen vacancies. Accordingly, V in the region 108i functioning as a channel formation region Ｏ H can be prevented from increasing, and a shift in the threshold voltage can be suppressed. V contained in the region 108i Ｏ H is V Ｏ By becoming F, V ＯH can be reduced. In addition, oxygen substituted with the first element in the metal oxide can trap electrons. As a result, a negative charge (also called a negative fixed charge) is formed at and near the interface between the channel formation region and the gate insulating layer, which can shift the threshold voltage of the transistor to the positive side. Therefore, the cutoff current can be reduced even in transistors with short channel lengths, and a normally-off transistor can be made. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved. When the first element fills the oxygen vacancy, the higher the electronegativity of the first element, the higher the bonding energy with the metal and the more stably it can exist. Fluorine can be suitably used as the first element. In the following, fluorine may be used as an example of the first element. Note that multiple elements can also be used as the first element. In addition, the concentration of the first element in the semiconductor layer 108 may not be uniform. For example, the semiconductor layer 108 may have a gradient where the concentration is higher on the insulating layer 105 side and decreases towards the insulating layer 106 side.

[0072] For analyzing the concentration of the first element in the semiconductor layer 108, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is sometimes also called ESCA (Electron Spectrometry for Chemical Analysis). Furthermore, multiple analytical methods can be used. For example, a combined analysis using both SIMS and XPS can be performed. The same applies to other analyses.

[0073] In the semiconductor layer 108, the first element may be bonded to a metal element that constitutes the metal oxide present in the semiconductor layer 108. When the semiconductor layer 108 contains indium and the first element is fluorine, the semiconductor layer 108 may have both In-O bonds and In-F bonds.

[0074] XPS can be used, for example, to analyze the bonding state between atoms. The following explanation will use an example of using XPS to analyze bonding states, but the analytical method is not particularly limited.

[0075] In XPS, for example, In3d is a peak that indicates the energy originating from the In bond. ５／２ Peaks originating from energy levels (hereinafter referred to as In3d) ５／２ (Also written as peak), In3D ３／２ Peaks originating from energy levels, In3p ３／２ Peaks originating from energy levels, and In3p １／２ Peaks originating from energy levels can be cited. In XPS measurement of semiconductor layer 108, peaks originating from In bonding (e.g., In3d ５／２ The peaks may include peaks originating from In-O bonds (hereinafter also referred to as In-O peaks) and peaks originating from In-F bonds (hereinafter also referred to as In-F peaks). Furthermore, even for the same element, the binding energy differs depending on its bonding state (hereinafter also referred to as chemical shift). As a result, the In3d obtained by XPS measurement ５／２ The peak can be separated into an In-O peak and an In-F peak. Because fluorine has a higher electronegativity than oxygen, the binding energy of the In-F bond is greater than that of the In-O bond. In XPS spectra, where the horizontal axis is binding energy and the vertical axis is photoelectron intensity, the binding energy at which the photoelectron intensity reaches its maximum value (the peak peak, or the maximum value at the peak) is sometimes denoted as the peak energy, and the intensity at the peak energy is sometimes denoted as the peak height. In addition, binding energy is sometimes denoted as bond energy.

[0076] In XPS measurements, for example, Kα rays from monochromatic aluminum can be used as X-rays. For peak separation (hereinafter also referred to as peak separation), it is preferable to use the XPS spectrum obtained by narrow-scan measurement. It is also preferable to subtract and remove the background from the spectrum obtained by measurement (hereinafter also referred to as background processing). For background processing, for example, the Shirley method, the linear method, or the Tougaard method can be used. It is preferable to use the spectrum after background processing (hereinafter also referred to as the analytical spectrum) for peak separation.

[0077] Next, the In3D of the spectrum for analysis. ５／２ Peak separation is performed. For peak separation, for example, a Gaussian function, a Lorentz function, a Voigt function, or a pseudo-Voigt function can be used. The Voigt function is obtained by convolution of a Gaussian function and a Lorentz function. The pseudo-Voigt function is obtained by summing a Gaussian function and a Lorentz function. Parameters for these functions include peak energy, peak height, and peak width. If available, XPS measurements can be performed using certified reference materials (CRMs) as standard samples, and the obtained peak energy and peak width can be used as parameters. If suitable certified reference materials are not available, commercially available or synthesized materials may be used as standard samples. Also, for peak energy, for example, values ​​from an XPS database can be used. One example of a database is the X-ray Photoelectron Spectroscopy Database of the NIST (National Institute of Standards and Technology). According to this database, In ２ O ３ In3D ５／２ The peak energy of the peak is 444.80 eV, InF ３ In3D ５／２The peak energy of the peak is 446.35 eV.

[0078] The sum of the function corresponding to the In-O peak and the function corresponding to the In-F peak (hereinafter also referred to as the calculated value) is fitted to the analytical spectrum value (hereinafter also referred to as the measured value) to minimize the difference, and the parameters of each function are determined. This allows for peak separation. For example, the least squares method can be used for fitting. Furthermore, if the difference between the calculated value fitted with the sum of the functions corresponding to the In-O peak and the measured value is smaller (or the fitting is more accurate) compared to the difference between the calculated value fitted with only the function corresponding to the In-O peak and the measured value, then it can be said that an In-F peak exists. Note that if the concentration of the first element in the semiconductor layer 108 is low, the In-F bond may not be detectable.

[0079] Although the present invention shows a configuration in which the semiconductor layer 108 contains the first element, the present invention is not limited to this. The first element may also be present at the interface between the semiconductor layer 108 and the insulating layer 105. In other words, the lower surface of the semiconductor layer 108 may contain the first element. In this case, the first element may be detected at and near the interface between the semiconductor layer 108 and the insulating layer 105 in SIMS analysis. In this case as well, the semiconductor layer 108 can be considered to contain the first element.

[0080] When forming a metal oxide film that will become a semiconductor layer 108 on an insulating layer 105, components contained in the insulating layer 105 (for example, hydrogen) are mixed into the metal oxide film, causing oxygen vacancies and V2 defects in the semiconductor layer 108, particularly on the insulating layer 105 side. Ｏ H may be more likely to occur. Because the lower surface of the semiconductor layer 108 has the first element, oxygen deficiency and V Ｏ It can effectively reduce H and is therefore preferable.

[0081] A first element is supplied (also called added or injected) to the insulating layer 105, and then a metal oxide film is formed, and the metal oxide film is processed into island shapes. It is preferable to perform a heat treatment after forming the metal oxide film or after processing the metal oxide film into island shapes. The heat treatment causes the first element to diffuse from the insulating layer 105, and a semiconductor layer 108 having the first element can be formed. As a result, not only region 108i, but also regions 108P and 108Q have the first element. Furthermore, the heat treatment can increase the crystallinity of the semiconductor layer 108 and reduce defects (e.g., defects within crystal grains). By reducing defects within crystal grains, the influence of scattering factors within crystal grains is reduced, making it possible to create a transistor with high field-effect mobility. In addition, the heat treatment can remove impurities (e.g., atmospheric components) contained in or adsorbed on the surface of the semiconductor layer 108.

[0082] The insulating layer 105 preferably contains a first element. The first element supplied to the insulating layer 105 diffuses into the semiconductor layer 108 and also diffuses into the insulating layer 105 by heat treatment. When the transistor is turned on, electrons are injected into the semiconductor layer 108 by supplying a potential to the gate electrode. The fluorine in the insulating layer 105 traps these electrons, and the fluorine that has trapped the electrons may function as a negative fixed charge. In this way, the fluorine in the insulating layer 105 functions as a negative fixed charge, which can shift the threshold voltage of the transistor to the positive side. This makes it possible to create a normally-off transistor. However, the concentration of the first element in the insulating layer 105 may not be uniform. For example, the concentration of the first element may be higher on the semiconductor layer 108 side and decrease towards the substrate 102 side, creating a gradient.

[0083] In the insulating layer 105, the first element may be bonded to elements other than the first element constituting the insulating layer 105. If the insulating layer 105 contains a silicon oxide or oxiditride and the first element is fluorine, the insulating layer 105 may have both Si-O bonds and Si-F bonds. XPS can be used to analyze these bonds, for example. For XPS analysis, please refer to the above description. Note that if the concentration of the first element in the insulating layer 105 is low, Si-F bonds may not be detectable.

[0084] As a method for supplying the first element, for example, ion implantation or plasma treatment can be used.

[0085] Ion implantation allows for highly precise control of the concentration profile in the depth direction by adjusting the ion acceleration energy and dose. The acceleration energy can be adjusted by the acceleration voltage during ion implantation. Furthermore, by using an ion implantation method that ionizes the source gas and supplies the ions by mass separation, it is possible to supply ions of a specific mass and increase the purity of the supplied ions. Alternatively, productivity can be increased by using an ion implantation method that supplies ions without mass separation. Unless otherwise specified in this specification, the presence or absence of mass separation is not limited. Note that the method of supplying ions by mass separation is sometimes called ion implantation, and the method of supplying ions without mass separation is sometimes called ion doping. By using a gas containing a first element as the source gas, the first element can be supplied. The amount of the first element supplied can be adjusted, for example, by adjusting the ion acceleration energy and dose.

[0086] For plasma processing, an apparatus that converts a gas into plasma using high-frequency power can be suitably used. Examples of such apparatus include plasma CVD apparatus, plasma etching apparatus, and plasma ashing apparatus. The first element can be supplied by performing plasma processing in an atmosphere containing a gas with the first element. The amount of the first element supplied can be adjusted, for example, by the concentration of the first element in the atmosphere during plasma processing, the power, and the processing time.

[0087] Examples of gases containing the element fluorine include fluorine (F ２ ), nitrogen trifluoride (NF ３ ), carbon tetrafluoride (CF ４ ), C ２ F ６ , C ４ F ６ , C ４ F ８ , C ５ F ８ CHF ３ and SF ６ One or more types can be used. Typically, NF ３ This can be suitably used. Multiple gases containing the first element can also be mixed and used. Alternatively, a gas containing the first element (for example, NF ３ ) can also be used in mixture with a gas that does not contain the first element (for example, argon and nitrogen).

[0088] For the heat treatment, for example, a device that heats by heat conduction or thermal radiation from a heating element can be used. For example, an oven or a rapid thermal annealing (RTA) device can be used for the heat treatment. As an RTA device, an LRTA (Lamp RTA) device can be used, which heats the object to be treated by radiation of light (electromagnetic waves) emitted from a lamp. Examples of such lamps include halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Alternatively, as an RTA device, a GRTA (Gas RTA) device can be used, which heats the object to be treated using high-temperature gas.

[0089] The temperature for the heat treatment is preferably 100°C or higher and below the strain point of the substrate, more preferably 100°C to 450°C, more preferably 150°C to 450°C, more preferably 200°C to 450°C, more preferably 300°C to 450°C, and more preferably 350°C to 450°C. It is preferable that the temperature of the substrate during the heat treatment falls within the above temperature range. However, the temperature of the substrate during the heat treatment is not limited to the above range.

[0090] The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can be used as the atmosphere containing nitrogen or oxygen. It is preferable to carry out the heat treatment in an atmosphere containing oxygen. Performing the heat treatment in an atmosphere containing oxygen may enhance effects such as reducing defects and increasing the grain size. CDA can be suitably used as the atmosphere for the heat treatment. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a content of hydrogen, water, etc. kept to a minimum, it is possible to prevent hydrogen, water, etc. from being incorporated into the semiconductor layer 108 as much as possible.

[0091] Alternatively, a metal oxide film can be formed on the insulating layer 105, and the first element can be supplied to the metal oxide film. Then, by processing the metal oxide film into island shapes, a semiconductor layer 108 having the first element can be formed. Alternatively, the semiconductor layer 108 having the first element can also be formed by processing the metal oxide film into island shapes and then supplying the first element. For the method of supplying the first element, please refer to the above description.

[0092] Alternatively, island-shaped metal oxide layers that will become semiconductor layers 108 are formed, and an insulating film that will become insulating layers 106 is deposited on the metal oxide layers. Then, the first element is supplied to the insulating film and heat treatment is performed so that the first element diffuses from the insulating film, forming a semiconductor layer 108 having the first element.

[0093] The method for supplying the first element is not limited to ion implantation and plasma treatment; for example, heat treatment can be used. The first element can be supplied by performing heat treatment in an atmosphere containing a gas with the first element. The amount of the first element supplied can be adjusted, for example, by the concentration of the first element in the atmosphere during the heat treatment, the heating temperature, and the treatment time.

[0094] Alternatively, a semiconductor layer 108 containing the first element can be formed by depositing a metal oxide film containing the first element and processing the metal oxide film into island-like structures. A gas containing the first element can be used as the film-forming gas for the metal oxide film.

[0095] By increasing the thickness T108 in the channel formation region of the semiconductor layer 108, the on-current of the transistor can be increased. However, if the thickness T108 is too thick, oxygen vacancies and V will form in the semiconductor layer 108. Ｏ If the amount of H increases, the transistor may become normally on. Also, reliability may decrease. The thickness T108 is preferably 1 nm to 50 nm, more preferably 1 nm to 40 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 1 nm to 10 nm. By setting the thickness T108 within the above range, a transistor with good electrical characteristics and high reliability can be obtained. In a cross-sectional view, the thickness T108 can be the shortest distance between the surface of the semiconductor layer 108 where it is formed (here, the upper surface of the insulating layer 105) and the upper surface of the semiconductor layer 108 in the region where it overlaps with the conductive layer 104. In Figure 1C, the thickness T108 is shown by a solid arrow. Note that the thickness T108 is not limited to the above range.

[0096] The crystallinity of the semiconductor material used in the semiconductor layer 108 is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystallinity other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used.

[0097] The semiconductor layer 108 is preferably crystalline. Using a crystalline oxide semiconductor for the semiconductor layer 108 is preferable because it suppresses the degradation of transistor characteristics. The semiconductor layer 108 is preferably highly crystalline, and is preferably polycrystalline or single-crystal. For example, it is preferable to use a polycrystalline In-Ga oxide film as the semiconductor layer 108, and more preferably a single-crystal In-Ga oxide film. Alternatively, it is preferable to use a polycrystalline indium oxide film as the semiconductor layer 108, and more preferably a single-crystal indium oxide film. Note that In-Ga oxide having crystal grains may be written as crystalline In-Ga oxide (Crystal IGO) or crystalline In-Ga oxide (Crystalline IGO), and indium oxide having crystal grains may be written as crystalline indium oxide (Crystal IO) or crystalline indium oxide (Crystalline IO).

[0098] Single-crystal films are particularly preferred because they do not have grain boundaries, thus suppressing carrier scattering at grain boundaries and enabling transistors with high field-effect mobility. Compared to microcrystalline and amorphous films, polycrystalline films can reduce carrier scattering and enable transistors with high field-effect mobility. When a polycrystalline film is used for the semiconductor layer 108, it is preferable that the grain size of the crystal grains contained in the semiconductor layer 108 is large. By using a polycrystalline film with large grain size, the number of crystal grain boundaries located in the channel formation region can be reduced, and the length of the crystal grain boundaries located in the channel formation region can be shortened, thus enabling transistors with high field-effect mobility. Furthermore, it is preferable that there are few crystal grain boundaries in the channel formation region that intersect with the direction in which the drain current flows (also known as the channel length direction). Note that even with a polycrystalline film, if there are no crystal grain boundaries located in the channel formation region, the same effects as a single-crystal film can be achieved.

[0099] When a non-single-crystal (e.g., polycrystalline) film is used as the semiconductor layer 108, it is preferable that the barrier height at the grain boundaries is low. A low barrier height at the grain boundaries reduces the effect of grain boundary scattering, thus enabling a transistor with high field-effect mobility. Generally, the barrier height at the grain boundaries of low-temperature polysilicon (LTPS) is 60 meV to 80 meV. When a polycrystalline metal oxide is used for the semiconductor layer 108, it is preferable that the barrier height at the grain boundaries is lower than that of LTPS. For example, the barrier height at the grain boundaries of a metal oxide is preferably less than 60 meV, more preferably 55 meV or less, and even more preferably 50 meV or less. Since a low barrier height at the grain boundaries is preferred, no lower limit is set. Note that the barrier height at the grain boundaries of a metal oxide is not limited to the above range.

[0100] For example, Kelvin probe force microscopy (KFM) can be used to measure the barrier height at grain boundaries. KFM is a type of scanning probe microscopy (SPM) measurement mode in which the potential distribution on the sample surface can be evaluated by scanning the sample surface with a conductive probe and detecting the electrostatic force between the probe and the sample surface.

[0101] Due to the low barrier height at the grain boundaries of metal oxides, OS transistors have high field-effect mobility and can operate at high speeds. Furthermore, OS transistors have high saturation (also known as high constant current) and low electrical hysteresis. Therefore, OS transistors can be suitably used as both selector and drive transistors in pixel circuits. By using OS transistors with high saturation and high current controllability as drive transistors, a display device with high display quality can be created. Additionally, using transistors with low hysteresis can further enhance display quality.

[0102] In this specification, the term "high saturation" may be used to describe a transistor where the change in current in the saturation region of the Id-Vd characteristic is small.

[0103] As the semiconductor layer 108, an amorphous film or a film having a crystalline region in part can be used. For example, it is preferable to use an amorphous In-Ga oxide film or an In-Ga oxide film having a crystalline region in part as the semiconductor layer 108. This reduces the number of grain boundaries located in the channel formation region, thereby reducing the influence of grain boundaries on the electrical characteristics of the transistor. Therefore, variations in transistor characteristics can be suppressed. In addition, since the semiconductor layer 108 can be formed by processing a metal oxide film with low crystallinity, processing becomes easier, and the productivity of semiconductor devices can be increased.

[0104] Furthermore, lowering the indium content may result in lower crystallinity of the semiconductor layer 108. For example, increasing the gallium content may result in lower crystallinity of the semiconductor layer 108. In addition, in a semiconductor layer 108 having indium gallium oxide, if the gallium content is low, the crystal structure of the semiconductor layer 108 may be cubic.

[0105] The metal oxide film that will become the semiconductor layer 108 can be deposited using sputtering, atomic layer deposition (ALD), or chemical vapor deposition (CVD).

[0106] Metal oxide films can also be formed using conditions that result in low crystallinity. After forming a metal oxide film with low crystallinity, heat treatment is performed to crystallize it, thereby increasing the grain size. When forming a metal oxide film, a gas containing hydrogen (e.g., H) can be used. ２ or H ２It is preferable to use O). This reduces the number of crystal grains generated during the formation of the metal oxide film, and lowers the crystallinity of the metal oxide film at the time of formation. In addition, the inclusion of hydrogen in the metal oxide film can cause the grain boundaries to be terminated with hydrogen (hereinafter also referred to as hydrogen termination), which can have the effect of lowering the barrier height at the grain boundaries. However, if the amount of hydrogen in the metal oxide film (especially in the channel formation region) is too high, oxygen vacancies and V in the channel formation region may occur. Ｏ An increase in H may cause a shift in the transistor's threshold voltage. The ratio of hydrogen gas flow rate to the total deposition gas flow rate when depositing a metal oxide film (hereinafter also referred to as the hydrogen flow rate ratio) is preferably higher than 0% and 20% or less, more preferably higher than 0% and 15% or less, and even more preferably higher than 0% and 10% or less. By setting the hydrogen flow rate ratio within the above range, a transistor with high field-effect mobility can be obtained. Note that the hydrogen flow rate ratio is not limited to the above range.

[0107] By using oxygen gas as the deposition gas for the metal oxide film, the occurrence of oxygen vacancies in the metal oxide film can be suppressed. Furthermore, oxygen can be supplied to the insulating layer 105 during the deposition of the metal oxide film. This allows oxygen to be supplied from the insulating layer 105 to the semiconductor layer 108 in subsequent processes, thus suppressing oxygen vacancies and V2 in the semiconductor layer 108. Ｏ H can be reduced. Also, the amount of oxygen contained in the metal oxide film can be increased, which promotes crystallization in subsequent heat treatment. However, if the ratio of the flow rate of oxygen gas to the total film formation gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow rate ratio) is too high, there is a risk that the number of crystal grains contained in the metal oxide film will increase at the stage when the metal oxide film is formed. The oxygen flow rate ratio is preferably higher than 0% and 10% or less, more preferably higher than 0% and 5% or less, and even more preferably higher than 0% and 3% or less. By setting the oxygen flow rate ratio within the above range, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ This method can reduce H content and lower the crystallinity of the metal oxide film at the deposition stage. Note that the oxygen flow rate ratio is not limited to the aforementioned range.

[0108] It is preferable to use hydrogen gas, oxygen gas, and argon gas as the film-forming gases for the metal oxide film. This makes it possible to obtain a semiconductor layer 108 with large grain sizes and few defects.

[0109] When a polycrystalline film is used for the semiconductor layer 108, the grain size of the crystal grains contained in the semiconductor layer 108 is preferably 0.1 μm or larger, more preferably 0.2 μm or larger, more preferably 0.3 μm or larger, more preferably 0.4 μm or larger, more preferably 0.5 μm or larger, more preferably 0.6 μm or larger, and more preferably 0.7 μm or larger. Since a larger grain size is preferable, no particular upper limit is set for the grain size. Note that the grain size of the crystal grains is not limited to the above range.

[0110] The crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD), transmission electron microscopy (TEM), or electron diffraction (ED). Alternatively, a combination of these methods can be used for the analysis.

[0111] The grain size of the crystal grains contained in the semiconductor layer 108 can be analyzed, for example, by transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), or electron backscatter diffraction (EBSD or EBSP). Alternatively, a combination of these methods can be used for analysis. For example, the average grain size of multiple crystal grains can be used as the grain size. Furthermore, the grain size of a crystal grain can be defined as, for example, the diameter of a circle with the same area as the crystal grain. This diameter is sometimes called the equivalent diameter of a circle.

[0112] In this specification, a grain boundary refers to, for example, the boundary between adjacent grains with different crystal orientations. Therefore, in this specification, boundaries between adjacent grains with the same crystal orientation are not included in grain boundaries. For example, even if a boundary is observed between two grains in a TEM image, if the crystal orientations of those two grains are the same or approximately the same, the boundary may not be called a grain boundary. Also, in EBSD, if the difference in crystal orientation between adjacent measurement points is small (for example, if the difference in crystal orientation is less than 5 degrees), these measurement points can be considered to belong to the same grain.

[0113] In this specification, space groups are denoted using the international notation (or Hermann-Mauguin notation) Short notation. In addition, space group numbers from the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be included. Furthermore, Miller indices are used to indicate crystal planes and crystal directions. In crystallography, space groups, crystal planes, and crystal directions are indicated by a bar above the number, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a bar above it. In addition, individual orientations indicating directions within a crystal are indicated by [ ], collective orientations indicating all equivalent directions are indicated by < >, individual planes indicating crystal planes are indicated by ( ), and collective planes with equivalent symmetry are indicated by {}. Note that even with the same space group number, the notation for the space group may differ depending on how the crystal axis is defined.

[0114] In ２ O ３ The crystals of, for example, have a cubic structure (bixbite type). Also, cubic (Cubic) In ２ O ３ The crystal structure belongs to space group Ia-3 (space group number 206).

[0115] The grain size of the crystal grains can also be confirmed, for example, using an optical microscope or a scanning electron microscope (SEM). Furthermore, by creating irregularities on the surface of the semiconductor layer 108 using etchants with different etching rates depending on the crystal plane or crystallinity, the crystal grains can be more easily observed using an optical microscope or SEM. When an indium oxide film is used as the semiconductor layer 108, the crystal grains of indium oxide can be more easily observed by using an etchant containing an acid. Examples of such acids include one or more types of phosphoric acid, oxalic acid, hydrofluoric acid, nitric acid, and hydrochloric acid. However, if the etching amount is too large, a portion of the semiconductor layer 108 may disappear, making it difficult to observe the crystal grains. Therefore, it is preferable to adjust the etching amount by the type, concentration, temperature, and processing time of the etchant so that the semiconductor layer 108 does not disappear but its thickness is reduced (also called half-etching). Half-etching allows for easy observation of the crystal grains.

[0116] Furthermore, if the thickness T108 is thin, it may not be possible to evaluate the crystallinity and grain size of the semiconductor layer 108.

[0117] As mentioned above, by using a metal oxide with a high indium content in the semiconductor layer, a transistor with a large on-current can be made. Therefore, a semiconductor device that operates at high speed can be made. When a semiconductor device according to one aspect of the present invention is applied to a display device, a display device that operates at high speed and has high display quality can be made. Furthermore, because transistors using metal oxides with a high indium content have high field-effect mobility, a large on-current can be obtained even with a small channel width. Therefore, the area occupied by the transistor can be reduced, and thus the area occupied by the semiconductor device can be reduced. When a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be made. Furthermore, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of the gate line drive circuit and the source line drive circuit), the area occupied by the drive circuit can be reduced, and a narrow-bezel display device can be made.

[0118] In the semiconductor layer 108, the length of the region located between the source region and the drain region, and overlapping with the conductive layer 104 via the insulating layer 106, is the channel length L of the transistor 100. In Figures 1A and 1B, the channel length L is indicated by a dashed double arrow. Furthermore, the width of the region where the semiconductor layer 108 and the conductive layer 104 overlap in a direction perpendicular to the channel length direction is the channel width W of the transistor 100. In Figures 1A and 1C, the channel width W is indicated by a solid double arrow.

[0119] Figure 1B and others show a configuration in which the edge of the insulating layer 106 coincides with the edge of the conductive layer 104. The edge of the insulating layer 106 is located on the semiconductor layer 108. Furthermore, the insulating layer 106 does not overlap with either region 108P or region 108Q. It can also be said that the upper surface shape of the insulating layer 106 coincides with, or roughly coincides with, the conductive layer 104. The insulating layer 106 can be formed, for example, by processing it using a resist mask for processing the conductive layer 104.

[0120] The insulating layer 195 has regions that are in contact with the top and side surfaces of the semiconductor layer 108, the side surfaces of the insulating layer 106, and the top and side surfaces of the conductive layer 104. The insulating layer 195 has regions that are in contact with region 108P and region 108Q, and has an opening 147a that reaches region 108P and an opening 147b that reaches region 108Q. Conductive layers 112a and 112b are formed to cover openings 147a and 147b. Conductive layer 112a is in contact with region 108P at opening 147a and is connected to region 108P. Conductive layer 112b is in contact with region 108Q at opening 147b and is connected to region 108Q. Conductive layer 112a functions as one of the source electrode and drain electrode of transistor 100, and conductive layer 112b functions as the other of the source electrode and drain electrode.

[0121] Transistor 100 is a so-called top-gate type transistor, having a gate electrode above the semiconductor layer 108. Furthermore, by supplying impurities to the semiconductor layer 108 using the conductive layer 104, which functions as the gate electrode, as a mask, regions 108P and 108Q, which function as the source and drain regions, can be formed in a self-aligned manner. Transistor 100 can be described as a TGSA (Top Gate Self-Aligned) type transistor.

[0122] In a TGSA-type transistor, the physical distance between the conductive layers 112a and 112b, which function as the source and drain electrodes, and the conductive layer 104, which functions as the gate electrode, can be increased, thereby reducing the parasitic capacitance between them.

[0123] Regions 108P and 108Q contain impurities. By supplying impurities to the semiconductor layer 108, the electrical resistance of regions 108P and 108Q can be lowered. The elements contained in the impurities (hereinafter also referred to as the second element or impurity element) can be hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and one or more noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of hydrogen, boron, phosphorus, and fluorine as the second element. The concentrations of the second element in regions 108P and 108Q are higher than the concentrations of the second element in region 108i. For information on how to supply the second element, please refer to the description of how to supply the first element. For analysis of the concentration of the second element in the semiconductor layer 108, for example, SIMS or XPS can be used.

[0124] By supplying the second element, an oxygen vacancy is created in the semiconductor layer 108. Furthermore, V Ｏ The generation of H allows for the formation of regions 108P and 108Q with low electrical resistance. Furthermore, when an element that readily bonds with oxygen is used as the second element, the second element removes oxygen from the semiconductor layer 108 and exists in a state bonded with oxygen. When an element that becomes stable when bonded with oxygen is used as the second element, the second element in the semiconductor layer 108 exists stably in an oxidized state, making it less susceptible to desorption due to heat applied during the semiconductor device manufacturing process, thus keeping the electrical resistance of regions 108P and 108Q low. For this reason, it is preferable to use an element as the second element whose oxide can exist as a solid at least at the temperature during the manufacturing process. Boron and phosphorus, or both, can be suitably used as the second element.

[0125] When boron is used as the second element, the boron contained in regions 108P and 108Q can exist in a state bonded with oxygen. This is evident in XPS analysis, B ２ O ３This can be confirmed by observing peaks caused by bonding. Furthermore, in XPS analysis, peaks caused by the element boron in its elemental state may not be observed, or their peak intensity may be extremely low, almost at background levels.

[0126] Hydrogen, when supplied, causes an oxygen deficiency, and when it enters the oxygen deficiency, V Ｏ Because H is generated, the electrical resistance of regions 108P and 108Q can be efficiently reduced. Therefore, hydrogen can be suitably used as the second element.

[0127] In supplying the second element, it is preferable to adjust the supply conditions so that the concentration of the second element is highest on the surface of the semiconductor layer 108 or in a region close to the surface.

[0128] For supplying the second element, for example, a gas containing the second element can be used as the raw material. When supplying boron, typically B ２ H ６ Gas, or BF ３ One or more gases can be used. Also, when supplying phosphorus, typically pH ３ Gases can be used. Furthermore, gases obtained by diluting these raw material gases with noble gases can also be used. Note that the raw materials are not limited to gases; solids or liquids can also be vaporized and used.

[0129] When using ion implantation to supply the second element, it is preferable to set conditions such as acceleration voltage and dose amount considering the composition, density, and thickness of the insulating layer 106 and the semiconductor layer 108. Furthermore, since the second element is supplied to regions of the insulating layer 105 that do not overlap with the conductive layer 104, these regions may also contain the second element.

[0130] The method of supplying the second element is not particularly limited; for example, plasma treatment or treatment utilizing thermal diffusion by heating can be used. In the case of plasma treatment, the second element can be supplied by generating plasma in a gas atmosphere containing the second element to be supplied and performing plasma treatment. As the apparatus for generating the plasma, dry etching apparatus, ashing apparatus, plasma CVD apparatus, high-density plasma CVD apparatus, etc., can be used.

[0131] A plasma CVD apparatus can be used to supply the second element to regions 108P and 108Q, and to deposit the insulating layer 195. This allows the supply of the second element and the deposition of the insulating layer 195 to be performed continuously within the plasma CVD apparatus, thereby increasing productivity. For example, by performing plasma processing in an atmosphere containing a hydrogen gas using a plasma CVD apparatus, hydrogen can be supplied as the second element to regions of the semiconductor layer 108 that do not overlap with the conductive layer 104.

[0132] An insulating layer 218 is provided on the conductive layer 112a, the conductive layer 112b, and the insulating layer 195. The insulating layer 195 and the insulating layer 218 each function as protective layers for the transistor 100.

[0133] [Semiconductor Layer 108] The metal oxides that can be used in the semiconductor layer 108 will be described in detail. Examples of semiconductor layers 108 include indium oxide, gallium oxide, zinc oxide, indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), and aluminum zinc oxide. Indium tin oxide (Al-Zn oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc., can be used. Alternatively, silicon-containing indium tin oxide (In-Sn-Si oxide, also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc., can be used.

[0134] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the metal element orbitals, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, these metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0135] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0136] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and its reliability can be improved.

[0137] When the metal oxide is an In-M-Zn oxide, it is preferable that the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:1, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, and In:M Compositions such as Zn=5:1:9, In:M:Zn=6:1:6, In:M:Zn=10:1:1, In:M:Zn=10:1:3, In:M:Zn=10:1:4, In:M:Zn=10:1:6, In:M:Zn=10:1:7, In:M:Zn=10:1:8, In:M:Zn=5:2:5, In:M:Zn=10:1:10, In:M:Zn=20:1:10, In:M:Zn=40:1:10, and compositions near these. In this specification, "nearby composition" includes a range of ±30% of the desired atomic ratio. Increasing the atomic ratio of indium in the metal oxide can increase the on-current or field-effect mobility of the transistor.

[0138] In an In-M-Zn oxide, the atomic ratio of In can be less than the atomic ratio of element M. Examples of such atomic ratios of metal elements in an In-M-Zn oxide include In:M:Zn = 1:3:2, In:M:Zn = 1:3:3, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, and compositions close to these. Increasing the proportion of M atoms in the metal oxide can suppress the formation of oxygen vacancies.

[0139] A metal oxide that does not contain element M can be applied to the semiconductor layer 108. When the metal oxide is an In-Zn oxide, examples of atomic ratios of the metal elements include In:Zn=1:1, In:Zn=2:1, In:Zn=1:2, In:Zn=3:1, In:Zn=3:2, In:Zn=2:3, In:Zn=4:1, In:Zn=4:3, In:Zn=5:1, In:Zn=5:2, In:Zn=5:3, In:Zn=5:4, In:Zn=5:6, In:Zn=5:7, In:Zn=5:8, In:Zn=5:9, In:Zn=7:1, In:Zn=10:1, In:Zn=10:3, In:Zn=10:7, and compositions near these. Furthermore, it is more preferable that the atomic ratio of In is greater than or equal to the atomic ratio of Zn. By increasing the atomic ratio of indium in a metal oxide, the on-current or field-effect mobility of a transistor can be increased.

[0140] When the metal oxide is an In-M-Zn oxide, it is preferable to use a metal oxide with an atomic ratio of metal elements of, for example, In:M:Zn = 40:1:10, or close to that ratio. Typically, a metal oxide with any of these atomic ratios and in which element M is Ga can be suitably used.

[0141] For analyzing the composition of the semiconductor layer 108, for example, energy-dispersive X-ray spectroscopy (EDX), X-ray photoelectron spectroscopy (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectroscopy (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and then identify and quantify the elements. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of the analysis accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may be below the detection limit.

[0142] The semiconductor layer 108 can be a single layer or a stacked structure of two or more layers. When the semiconductor layer 108 has a stacked structure, the aforementioned metal oxides can be suitably used in each layer of the semiconductor layer 108. The same material can be used for each layer of the semiconductor layer 108. Alternatively, different materials can be used for one or more layers of the semiconductor layer 108.

[0143] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0144] Sputtering or ALD (Advanced Laser Deposition) can be suitably used to deposit metal oxide films. However, when depositing metal oxide films by sputtering, the composition of the deposited metal oxide film may differ from that of the sputtering target. In particular, the zinc content in the deposited metal oxide film may decrease to about 50% of the content in the sputtering target. Similarly, the content of other elements in the deposited metal oxide film may differ from that in the sputtering target.

[0145] It is preferable to use a crystalline metal oxide for the semiconductor layer 108. Examples of crystalline metal oxide structures include CAAC (c-axis aligned crystal) structure, polycrystalline structure, microcrystalline structure, and nanocrystalline (nc: nano-crystal) structure. By using a crystalline metal oxide, the defect level density in the semiconductor layer 108 can be reduced, and a highly reliable semiconductor device can be realized.

[0146] It is preferable to use CAAC-OS or nc-OS for the semiconductor layer 108.

[0147] CAAC-OS has multiple layered crystals. The c-axis of these crystals is oriented in the direction normal to the surface to be formed. Preferably, the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the surface to be formed. Preferably, the semiconductor layer 108 has layered crystals that are parallel or approximately parallel to the upper surface of the insulating layer 105, which is the surface to be formed. With this configuration, the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, so that a transistor with a large on-current can be made.

[0148] OS transistors exhibit minimal fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton beams, and neutron beams).

[0149] The semiconductor layer 108 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0150] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a channel-forming region is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) are some examples.

[0151] [Insulating layer 106, insulating layer 105] It is preferable that insulating layer 106 and insulating layer 105 each have one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride.

[0152] In this specification, the term "oxidogenic nitride" refers to a material whose composition contains more oxygen than nitrogen. The term "nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0153] The insulating layer 106 has a region that is in contact with the semiconductor layer 108. When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 106 that is in contact with the semiconductor layer 108 contains oxygen in order to improve the interfacial characteristics between the semiconductor layer 108 and the insulating layer 106. Specifically, it is preferable that the region of the insulating layer 106 that is in contact with the channel-forming region contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the insulating layer 106 that is in contact with the channel-forming region. The same applies to the insulating layer 105. For example, it is preferable that the insulating layer 106 and the insulating layer 105 each contain silicon and oxygen, respectively. Silicon oxide or silicon oxiditride can be suitably used for the insulating layer 106 and the insulating layer 105, respectively.

[0154] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxiditrides having aluminum and hafnium, oxides having silicon and hafnium, oxiditrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0155] In Figure 1B and other figures, the insulating layer 106 and insulating layer 105 are shown as single-layer structures, but the present invention is not limited to this. One or both of the insulating layer 106 and insulating layer 105 can be made into a laminated structure of two or more layers. When the insulating layer 106 is made into a laminated structure, it is preferable that the insulating layer on the semiconductor layer 108 side has an oxide or oxidizride. Similarly, when the insulating layer 105 is made into a laminated structure, it is preferable that the insulating layer on the semiconductor layer 108 side has an oxide or oxidizride. For example, silicon oxide, silicon oxidizride, or aluminum oxide can be suitably used as the insulating layer on the semiconductor layer 108 side.

[0156] It is preferable to use a material that is difficult for substances to permeate in one or more of the layers constituting the insulating layer 106. This layer can also be said to function as a barrier film. By providing a layer that functions as a barrier film, it is possible to suppress the diffusion of metal components contained in the conductive layer 104 and impurities (e.g., water and hydrogen) contained in the layers formed on the transistor 100 into the semiconductor layer 108 via the insulating layer 106. Furthermore, it is possible to suppress the diffusion of oxygen contained in the semiconductor layer 108 into the conductive layer 104 side via the insulating layer 106. This suppresses the formation of oxygen vacancies in the semiconductor layer 108. In addition, it is possible to suppress the oxidation of the conductive layer 104 by the oxygen contained in the semiconductor layer 108, which increases the electrical resistance of the conductive layer 104. As a result, a transistor with good electrical characteristics and high reliability can be obtained. Similarly, it is preferable to provide a layer that functions as a barrier film in one or more of the layers constituting the insulating layer 105.

[0157] In this specification, the term "barrier film" refers to a film that possesses barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for the target substance to diffuse, thereby suppressing the permeation of the substance through the film (also known as low permeability), and a function that captures or fixes the substance (also known as gettering).

[0158] The barrier film can be, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, an oxidized nitride having silicon, and an oxide nitride having silicon. Typically, the barrier film can preferably be one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, silicon oxidized nitride, and silicon oxide nitride. The barrier film of the insulating layer 106 can be one or more of oxides and oxidized nitrides, for example, aluminum oxide can be preferably used. Also, the barrier film of the insulating layer 105 can be one or more of nitrides and oxide nitrides, for example, silicon nitride can be preferably used.

[0159] The insulating layer 106 can be, for example, a laminated structure of a silicon oxidizide film and a silicon nitride film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of a silicon oxidizide film and an aluminum oxide film on the silicon oxidizide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon oxidizide film on the aluminum oxide film. Alternatively, the insulating layer 106 can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film. Here, an example is shown in which the insulating layer 106 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 106 can also have a laminated structure of three or more layers.

[0160] The insulating layer 105 can, for example, be a laminated structure of a silicon nitride film and a silicon oxynitride film on the silicon nitride film. Here, an example is shown in which the insulating layer 105 has a two-layer laminated structure, but the present invention is not limited to this. The insulating layer 105 can also have a laminated structure of three or more layers.

[0161] [Conductive layer 112a, conductive layer 112b, conductive layer 104] Conductive layer 112a, conductive layer 112b, and conductive layer 104 can each be a single layer or a laminated structure of two or more layers. Materials that can be used for conductive layer 112a, conductive layer 112b, and conductive layer 104 include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Conductive layers 112a, conductive layer 112b, and conductive layer 104 can preferably be conductive materials with low electrical resistivity that include one or more of copper, silver, gold, and aluminum. Copper or aluminum are particularly preferred because they are easy to mass-produce.

[0162] Conductive layers 112a, 112b, and 104 can each be made of a conductive metal oxide (also called an oxide conductor (OC)). Examples of oxide conductors include indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, ITSO, In-Sn-Zn oxide, Ga-Zn oxide, and In-Ga-Zn oxide. Oxide conductors containing indium are particularly preferred due to their high conductivity.

[0163] When oxygen vacancies are formed in a metal oxide with semiconductor properties, and hydrogen is added to these vacancies, donor levels are formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can also be called an oxide conductor.

[0164] The conductive layer 112a, conductive layer 112b, and conductive layer 104 can each have a laminated structure consisting of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0165] The conductive layer 112a, conductive layer 112b, and conductive layer 104 can each be made of a nitride conductor. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0166] The conductive layers 112a, 112b, and 104 can each be made of a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). Using a Cu-X alloy film allows for processing by wet etching, thus reducing manufacturing costs.

[0167] The conductive layer 112a, conductive layer 112b, and conductive layer 104 may be made of the same material. Alternatively, at least one of them may be made of a different material.

[0168] [Insulating layer 195] The insulating layer 195 preferably has one or more inorganic insulating layers. The inorganic insulating layer can be made from the materials listed for insulating layer 106 and insulating layer 105.

[0169] The insulating layer 195 preferably functions as a barrier film. This effectively suppresses the diffusion of impurities (e.g., water and hydrogen) into the transistor from the outside, thereby improving the reliability of the semiconductor device. For example, silicon nitride and silicon nitride oxide, or both, can be suitably used as the insulating layer 195. Refer to the above description for details regarding the barrier film.

[0170] [Insulating layer 218] As the insulating layer 218, either an inorganic insulating layer or an organic insulating layer, or both, can be used. The inorganic insulating layer can be made from the materials listed for insulating layer 106 and insulating layer 105. Examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin. The organic insulating layer functions as a planarizing layer that reduces irregularities caused by the transistor.

[0171] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatments. For example, single-crystal semiconductor substrates, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or resin substrates made of silicon or silicon carbide can be used as the substrate 102. In addition, a substrate on which semiconductor elements are provided can be used as the substrate 102. A substrate with an insulating film formed on its surface can be used as the substrate 102. The shape of the substrate 102 is not particularly limited and can be circular or rectangular, for example.

[0172] A flexible substrate can be used as the substrate 102, and transistors 100, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the transistors 100, etc. By providing a release layer, after partially or completely completing the semiconductor device on it, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistors 100, etc., can also be transferred to a substrate with low heat resistance or a flexible substrate.

[0173] The following describes a configuration example that differs in some aspects from the aforementioned <Configuration Example 1>. Note that in the following, explanations of parts that overlap with <Configuration Example 1> may be omitted. Also, in the drawings shown below, parts having the same function as those in Configuration Example 1 may use the same hatching pattern and may not be labeled.

[0174] Furthermore, the structure of the transistor that can be applied to a semiconductor device according to one aspect of the present invention is not particularly limited.

[0175] <Configuration Example 2> Figure 2A shows a top view of a semiconductor device 10A, which is one embodiment of the present invention. Figure 2B shows a cross-sectional view of the cross-section along the dashed-dotted line A1-A2 shown in Figure 2A, and Figure 2C shows a cross-sectional view of the cross-section along the dashed-dotted line B1-B2.

[0176] The semiconductor device 10A has a transistor 100A. Transistor 100A differs from transistor 100 shown in Figure 1B, etc., in that it has a conductive layer 103.

[0177] The conductive layer 103 is provided between the substrate 102 and the insulating layer 105. The conductive layer 103 functions as the back gate electrode of the transistor 100A. The conductive layer 103 has a region that overlaps with the conductive layer 104 via the insulating layer 105, the semiconductor layer 108, and the insulating layer 106. The insulating layer 105 functions as the back gate insulating layer of the transistor 100A.

[0178] By providing a back gate electrode, the potential on the back gate electrode side (also called the back channel side) of the semiconductor layer 108 is fixed, which can improve the saturation in the Id-Vd characteristics. Furthermore, by fixing the potential on the back channel side of the semiconductor layer 108, the threshold voltage shift can be suppressed. Therefore, a transistor with a small cutoff current can be made, resulting in a semiconductor device with low power consumption.

[0179] The conductive layer 103 preferably has a region that protrudes from the edge of the conductive layer 104. This enhances the effect of making it difficult for electric fields generated outside the transistor to act on the channel formation region (also known as the electric field shielding effect).

[0180] The conductive layer 103 can be configured to be connected to either the conductive layer 112a or the conductive layer 112b. For example, by providing openings in the insulating layer 195, insulating layer 106, and insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 112a so as to cover these openings, the conductive layer 103 and the conductive layer 112a can be in contact. By connecting the conductive layer 112a and the conductive layer 103, the source electrode and the drain electrode and the back gate electrode can be brought to the same potential. For example, when the conductive layer 112a functions as the source electrode, a shift in the threshold voltage of the transistor 100A can be suppressed. Furthermore, the reliability of the transistor 100A can be improved.

[0181] The conductive layer 103 can be configured to be connected to the conductive layer 104. For example, by providing openings in the insulating layer 106 and the insulating layer 105 that reach the conductive layer 103, and providing the conductive layer 104 so as to cover the openings, the conductive layer 103 and the conductive layer 104 can be in contact. By connecting the gate electrode and the back gate electrode, the back gate electrode and the gate electrode can be brought to the same potential, and the on-current of the transistor 100A can be increased.

[0182] The conductive layer 103 can be made from the materials listed for conductive layer 104, conductive layer 112a, and conductive layer 112b.

[0183] <Configuration Example 3> Figures 3A and 3B show cross-sectional views of a semiconductor device 10B, which is one embodiment of the present invention. A top view of the semiconductor device 10B can be found in Figure 2A. Figure 3A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 3B is a cross-sectional view of the section along the dashed line B1-B2.

[0184] The semiconductor device 10B has a transistor 100B. Transistor 100B differs from transistor 100A shown in Figure 2B, etc., in that its insulating layer 105 has a multilayer structure.

[0185] Figures 3A and 3B show an example in which the insulating layer 105 has an insulating layer 105a and an insulating layer 105b on top of the insulating layer 105a.

[0186] The insulating layer 105b has a region that is in contact with the semiconductor layer 108. As mentioned above, it is preferable that the insulating layer 105b in contact with the semiconductor layer 108 contains oxygen.

[0187] The insulating layer 105a located on the substrate 102 and conductive layer 103 side preferably functions as a barrier film. By providing a barrier film, the diffusion of components (e.g., metals) contained in the substrate 102 and conductive layer 103 into the semiconductor layer 108 can be suppressed, resulting in a highly reliable semiconductor device. The barrier film can be described in the above description. The insulating layer 105a preferably contains nitrogen.

[0188] The insulating layer 105a preferably contains silicon and nitrogen. The insulating layer 105b preferably contains silicon and oxygen. For example, silicon nitride can be suitably used for the insulating layer 105a and silicon oxynitride can be suitably used for the insulating layer 105b.

[0189] <Configuration Example 4> Figures 4A and 4B show cross-sectional views of a semiconductor device 10C, which is one embodiment of the present invention. A top view of the semiconductor device 10C can be found in Figure 2A. Figure 4A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 4B is a cross-sectional view of the section along the dashed line B1-B2.

[0190] The semiconductor device 10C has a transistor 100C. Transistor 100C differs from transistor 100A shown in Figure 2B, etc., in that the insulating layer 106 has regions in contact with regions 108P and 108Q.

[0191] The insulating layer 106 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108 and the upper surface of the insulating layer 105. An insulating layer 195 is provided on the insulating layer 106 and the conductive layer 104. The insulating layer 195 and the insulating layer 106 have openings 147a and 147b. Conductive layers 112a and 112b are formed so as to cover openings 147a and 147b.

[0192] Region 108i overlaps with the conductive layer 104 via the insulating layer 106. Regions 108P and 108Q do not overlap with either the conductive layer 104 or the insulating layer 106, respectively. Regions 108R and 108S overlap with the insulating layer 106 but do not overlap with the conductive layer 104, respectively.

[0193] After forming a conductive layer 104 on an insulating layer 106, the conductive layer 104 can be used as a mask to supply a second element to the semiconductor layer 108 via the insulating layer 106. In this case, the second element may be supplied to regions of the insulating layer 106 that do not overlap with the conductive layer 104, thereby resulting in those regions containing the second element. For example, ion implantation can be suitably used to supply the second element.

[0194] <Configuration Example 5> Figures 4C and 4D show cross-sectional views of a semiconductor device 10D, which is one embodiment of the present invention. A top view of the semiconductor device 10D can be found in Figure 2A. Figure 4C is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 4D is a cross-sectional view of the section along the dashed line B1-B2.

[0195] The semiconductor device 10D has a transistor 100D. Transistor 100D differs from transistor 100A shown in Figure 2B, etc., in that the insulating layer 106 has a region that protrudes more than the conductive layer 104.

[0196] The edges of the insulating layer 106 are located on the semiconductor layer 108, and the edges of the conductive layer 104 are located on the insulating layer 106. It can also be said that the edges of the insulating layer 106 are located outside the edges of the conductive layer 104. The insulating layer 106 has a region that overlaps with the conductive layer 104 and a region that does not overlap with the conductive layer 104 on the semiconductor layer 108.

[0197] The semiconductor layer 108 has a region 108i, a pair of regions (region 108R and region 108S) flanking region 108i, and a pair of regions (region 108P and region 108Q) located outside of these. Regions 108R and 108S overlap with the insulating layer 106 but do not overlap with the conductive layer 104. Region 108R is located between region 108i and region 108P, and region 108S is located between region 108i and region 108Q.

[0198] Regions 108R and 108S function as buffer regions to mitigate the drain electric field. Since regions 108R and 108S do not overlap with the conductive layer 104, channels are hardly formed in these regions even when a gate voltage is applied to the conductive layer 104. It is preferable that the carrier concentration in regions 108R and 108S is higher than that in the channel formation region. This allows regions 108R and 108S to function as LDD (Lightly Doped Drain) regions.

[0199] Regions 108R and 108S can also be described as regions with similar or lower electrical resistance, similar or higher carrier concentration, similar or higher oxygen deficiency density, and similar or higher concentration of the second element compared to the channel-forming region.

[0200] Regions 108R and 108S can also be described as regions with similar or higher electrical resistance, similar or lower carrier concentration, similar or lower oxygen deficiency density, and similar or lower concentration of the second element, compared to regions 108P and 108Q.

[0201] The insulating layer 195 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108, the upper and side surfaces of the insulating layer 106, and the upper and side surfaces of the conductive layer 104.

[0202] <Configuration Example 6> Figure 5A shows a top view of a semiconductor device 10E, which is one embodiment of the present invention. Figure 5B shows a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 5A. For a cross-sectional view of the section along the dashed line B1-B2, refer to Figure 4B.

[0203] The semiconductor device 10E has a transistor 100E. Transistor 100E differs from transistor 100D shown in Figure 4C, etc., in that conductive layers 112a and 112b are formed in the same process as conductive layer 104.

[0204] The insulating layer 106 has openings 147a and 147b that reach the semiconductor layer 108. Conductive layers 112a and 112b are provided so as to cover a portion of opening 147a and a portion of opening 147b. Conductive layer 112a has a region that contacts the semiconductor layer 108 at opening 147a, and conductive layer 112b has a region that contacts the semiconductor layer 108 at opening 147b.

[0205] Conductive layers 104, 112a, and 112b can be formed using the same material and the same process. For example, an insulating film is deposited on a semiconductor layer 108, and the insulating film is processed to form an insulating layer 106 having openings 147a and 147b. Then, a conductive film is deposited to cover the insulating layer 106, openings 147a and 147b, and the conductive film is processed to form conductive layers 104, 112a, and 112b. By forming conductive layers 112a and 112b using the same process as conductive layer 104, the number of processes can be reduced.

[0206] By supplying a second element to the semiconductor layer 108 using conductive layers 104, 112a, and 112b as masks, regions 108P and 108Q can be formed in a self-aligned manner. Regions 108P and 108Q are formed in regions of the semiconductor layer 108 that do not overlap with conductive layers 104, 112a, 112b, or the insulating layer 106. In addition, regions 108R and 108S are formed in regions of the semiconductor layer 108 that do not overlap with conductive layers 104, 112a, or 112b, but overlap with the insulating layer 106.

[0207] The region of the semiconductor layer 108 that is in contact with the conductive layer 112a, and the region 108P in contact with said region, function as one of the source region and the drain region. The region of the semiconductor layer 108 that is in contact with the conductive layer 112b, and the region 108Q in contact with said region, function as the other of the source region and the drain region.

[0208] An insulating layer 195 is provided on the transistor 100E. Although Figure 5B shows an example configuration in which an insulating layer 218 is not provided, the present invention is not limited to this. An insulating layer 218 can also be provided on the insulating layer 195.

[0209] <Configuration Example 7> Figures 6A and 6B show cross-sectional views of a semiconductor device 10F, which is one embodiment of the present invention. A top view of the semiconductor device 10F can be found in Figure 2A. Figure 6A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 6B is a cross-sectional view of the section along the dashed line B1-B2.

[0210] The semiconductor device 10F has a transistor 100F. Transistor 100F differs from transistor 100C shown in Figure 4A, etc., in that its semiconductor layer 108 has a stacked structure.

[0211] Figure 6B and others show a configuration in which the semiconductor layer 108 has a three-layer structure consisting of semiconductor layer 108a, semiconductor layer 108b on semiconductor layer 108a, and semiconductor layer 108c on semiconductor layer 108b. Semiconductor layer 108b is in contact with and sandwiched between semiconductor layers 108a and 108c.

[0212] The semiconductor layers 108a, 108b, and 108c can each be made from the materials listed for semiconductor layer 108. The semiconductor layers 108a, 108b, and 108c can each be made from the same material. Indium oxide can be suitably used for each of the semiconductor layers 108a, 108b, and 108c. Alternatively, different materials can be used for one or more of the semiconductor layers 108a, 108b, and 108c.

[0213] In some cases, the boundaries between semiconductor layer 108a and semiconductor layer 108b, and between semiconductor layer 108b and semiconductor layer 108c, cannot be clearly identified. Therefore, in Figure 6B and other diagrams, these boundaries are shown with dashed lines. In some cases, one or both of these boundaries can be identified.

[0214] It is preferable that the conductivity of semiconductor layer 108b is higher than that of either semiconductor layer 108a or semiconductor layer 108c. This ensures that the main current path in transistor 100F is semiconductor layer 108b. On the other hand, in semiconductor layer 108, it is preferable that semiconductor layer 108a, which is in contact with insulating layer 105, and semiconductor layer 108c, which is in contact with insulating layer 106, are denser and have fewer defects than semiconductor layer 108b.

[0215] Trap levels caused by impurities or defects may form at the interface between the insulating layer 106, which functions as a gate insulating layer, and the semiconductor layer 108, and at the interface between the insulating layer 105, which functions as a back gate insulating layer, and the semiconductor layer 108, and at the interface at the interface at the interface at the interface. Furthermore, when the insulating layer 106 is deposited, damage may be inflicted on the interface between the insulating layer 106 and the semiconductor layer 108, causing trap levels to form at the interface

[0216] Here, when a high potential is applied to the conductive layer 104, which functions as the gate electrode, trap levels may be formed at and near the interface between the insulating layer 106 and the semiconductor layer 108. Similarly, when a high potential is applied to the conductive layer 103, which functions as the back gate electrode, trap levels may be formed at and near the interface between the insulating layer 105 and the semiconductor layer 108. If electrons are trapped in these trap levels, the threshold voltage of the transistor may shift to the positive side, potentially reducing reliability. By providing a semiconductor layer 108c with few defects in contact with the insulating layer 106, the formation of trap levels at and near the interface between the insulating layer 106 and the semiconductor layer 108 can be suppressed. Similarly, by providing a semiconductor layer 108a with few defects in contact with the insulating layer 105, the formation of trap levels at and near the interface between the insulating layer 105 and the semiconductor layer 108 can be suppressed. This makes it possible to create a highly reliable transistor.

[0217] In this way, by sandwiching the highly conductive semiconductor layer 108b between the less defective semiconductor layers 108a and 108c, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a semiconductor device can be made that achieves both high-speed operation and high reliability.

[0218] In the channel formation region, it is preferable that the carrier mobility of semiconductor layer 108b is higher than that of semiconductor layer 108a and semiconductor layer 108c. Here, when a non-single-crystal (e.g., polycrystalline) metal oxide is used for the semiconductor layer, the carrier mobility can be increased by increasing the carrier concentration. It is preferable that the carrier concentration of semiconductor layer 108b is higher than that of semiconductor layer 108a and semiconductor layer 108c. As a result, the conductivity of semiconductor layer 108b, which is the main current path, is increased, and a transistor with high field-effect mobility can be made.

[0219] It is preferable that semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c each have an element that increases the carrier concentration (hereinafter also referred to as the third element). As the third element, for example, one or more of hydrogen, carbon, and nitrogen can be used. Hydrogen can be suitably used as the third element. Hydrogen reacts with oxygen bonded to the metal atoms of the metal oxide to form water, thereby forming oxygen vacancies in the metal oxide. Furthermore, a defect (V) is formed when hydrogen enters the oxygen vacancy. Ｏ H) functions as a donor, generating electrons, which are carriers, thereby increasing the carrier concentration in the metal oxide. Note that in the following explanation, hydrogen may be used as an example of a third element.

[0220] In the channel formation region, it is preferable that semiconductor layer 108b has a region with a higher concentration of the third element compared to semiconductor layer 108a and semiconductor layer 108c. Typically, it is preferable that semiconductor layer 108b has a region with a higher hydrogen concentration compared to semiconductor layer 108a and semiconductor layer 108c. In the channel formation region, semiconductor layer 108b has a concentration of the third element (for example, hydrogen) of 1 × 10⁻¹⁶. １９ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 1 × 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３It is preferable to have the following regions. If the concentration of the third element in the semiconductor layer 108b is too low, the carrier concentration will be low, and there is a risk that the carrier mobility will be low. On the other hand, if the concentration of the third element in the semiconductor layer 108b is too high, the V of the channel formation region Ｏ An increase in the amount of H may cause a shift in the threshold voltage and a larger cutoff current. By setting the concentration of the third element in the semiconductor layer 108b within the aforementioned range, a transistor can be made that achieves both high field-effect mobility and a small cutoff current. Note that the concentration of the third element in the semiconductor layer 108 may have a gradient in the thickness direction of the semiconductor layer 108. It is preferable that the maximum value of the concentration of the third element in the semiconductor layer 108b is within the aforementioned range. Note that the concentration of the third element in the semiconductor layer 108b is not limited to the aforementioned range.

[0221] In the channel formation region, it is preferable that semiconductor layer 108a and semiconductor layer 108c each have regions where the concentration of the third element is lower compared to semiconductor layer 108b. In the channel formation region, it is preferable that semiconductor layer 108a and semiconductor layer 108c each have regions where the concentration of the third element (e.g., hydrogen) is 1 / 100 to 1 / 2 of the concentration of the third element in semiconductor layer 108b, more preferably 1 / 100 to 1 / 4, more preferably 1 / 100 to 1 / 6, more preferably 1 / 100 to 1 / 8, and more preferably 1 / 100 to 1 / 10. If the concentration of the third element in semiconductor layer 108a and semiconductor layer 108c is too high, the film density will be low, and there is a risk of many defects. On the other hand, if the concentration of the third element in semiconductor layer 108a and semiconductor layer 108c is too low, the carrier concentration will be low, resulting in low carrier mobility, which may lead to low field-effect mobility. By setting the concentration of the third element in semiconductor layer 108a and semiconductor layer 108c within the aforementioned range, a transistor can be made that achieves both high field-effect mobility and high reliability. As mentioned above, the concentration of the third element in semiconductor layer 108 may have a gradient in the thickness direction of semiconductor layer 108. It is preferable that the minimum value of the concentration of the third element in semiconductor layer 108a and the minimum value of the concentration of the third element in semiconductor layer 108c are within the aforementioned range. However, the concentration of the third element in semiconductor layer 108a and semiconductor layer 108c is not limited to the aforementioned range.

[0222] For example, SIMS or XPS can be used to analyze the concentration of the third element in the semiconductor layer 108. For example, SIMS can be suitably used to analyze the hydrogen concentration. However, the reliability of the measured values ​​may be low at the interface between the semiconductor layer 108 and the layer in contact with the semiconductor layer 108, and in its vicinity, due to the matrix effect. For example, when measuring in the direction from the insulating layer 106 towards the semiconductor layer 108, the reliability of the measured values ​​may be low at the interface between the insulating layer 106 and the semiconductor layer 108, and in its vicinity. Measured values ​​in areas with low reliability should not be treated as the concentration of the third element in the semiconductor layer 108. Furthermore, the accuracy of the analysis of the concentration of the third element in the semiconductor layer 108 can sometimes be improved by combining measurements in the direction from the insulating layer 106 towards the semiconductor layer 108 with measurements in the direction from the insulating layer 105 towards the semiconductor layer 108.

[0223] In concentration analysis, the intensity of the constituent elements of the metal oxide can sometimes be used to estimate the location of the interface between the insulating layer 106 and the semiconductor layer 108, and the location of the interface between the insulating layer 105 and the semiconductor layer 108. For example, the range in which the intensity of the constituent elements of the metal oxide present in the semiconductor layer 108 is 1 / 2 or more of its maximum value can be defined as the semiconductor layer 108. When a metal oxide containing indium is used in the semiconductor layer 108 and SIMS is used to analyze the concentration of a third element, the range in which the secondary ion intensity of indium is 1 / 2 or more of its maximum value can be defined as the semiconductor layer 108, and the range in which it is less than 1 / 2 of its maximum value can be defined as layers other than the semiconductor layer 108 (e.g., insulating layer 105 and insulating layer 106). Alternatively, the range in which the secondary ion intensity of an indium-containing cluster (e.g., an indium-oxygen cluster) is 1 / 2 or more of its maximum value can be defined as the semiconductor layer 108, and the range in which it is less than 1 / 2 of its maximum value can be defined as layers other than the semiconductor layer 108 (e.g., insulating layer 105 and insulating layer 106).

[0224] Preferably, the film density of semiconductor layer 108a and semiconductor layer 108c is higher than the film density of semiconductor layer 108b. This reduces defects in semiconductor layer 108a and semiconductor layer 108c. Furthermore, by providing a semiconductor layer 108c with a high film density on semiconductor layer 108b, damage to semiconductor layer 108b during the deposition of the insulating layer 106 can be suppressed. For example, film density can be evaluated using Rutherford backscattering spectrum (RBS) or X-ray reflectivity (XRR).

[0225] Differences in film density can sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (darker) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Therefore, even when the same material, such as indium oxide, is used for semiconductor layers 108a, 108b, and 108c, differences in film density among these layers can sometimes be observed as differences in contrast in cross-sectional TEM observations. Specifically, in the TE image, semiconductor layers 108a and 108c may have darker (darker) regions compared to semiconductor layer 108b. Also, semiconductor layer 108b may have lighter (brighter) regions compared to semiconductor layers 108a and 108c.

[0226] Furthermore, the film densities of semiconductor layer 108a and semiconductor layer 108c can be configured to be the same as, or lower than, the film densities of semiconductor layer 108b.

[0227] Even when using the same material, the etching rate may be slower if the film is denser and has a higher film density. It is preferable that the etching rate in one etchant of semiconductor layer 108a and semiconductor layer 108c is slower than the etching rate of semiconductor layer 108b. It is also preferable to provide a semiconductor layer 108c with a slow etching rate on top of semiconductor layer 108b. This makes it possible to suppress the disappearance of semiconductor layer 108c in the etching process after the formation of semiconductor layer 108, and to suppress the thinning of the thickness of semiconductor layer 108.

[0228] The semiconductor layer 108 can be formed by depositing a metal oxide film and processing the metal oxide film into island shapes. It is preferable to perform a heat treatment to crystallize the metal oxide film after depositing it or after processing the metal oxide film into island shapes. By performing the heat treatment, the particle size of the crystal grains contained in the semiconductor layer 108 can be increased and the crystallinity of the semiconductor layer 108 can be improved. Furthermore, the heat treatment can reduce defects in the semiconductor layer 108. In addition, the heat treatment can remove impurities contained in the semiconductor layer 108 or adsorbed on its surface.

[0229] When the semiconductor layer 108 has a three-layer structure consisting of semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c, the metal oxide films are formed in the following order: a first metal oxide film to become semiconductor layer 108a, a second metal oxide film to become semiconductor layer 108b, and a third metal oxide film to become semiconductor layer 108c.

[0230] The first, second, and third metal oxide films are preferably deposited by sputtering using a metal target or a metal oxide target. Alternatively, the first, second, and third metal oxide films are preferably deposited by the ALD method. The ALD method allows for easy control of the deposition rate, enabling the deposition of thin films with high yield. Therefore, the ALD method is particularly suitable when the metal oxide film is thin. Alternatively, the CVD method can also be used.

[0231] Examples of power supplies used in sputtering apparatuses include DC (Direct Current) power supplies, RF (Radio Frequency) power supplies, and AC (Alternating Current) power supplies. A pulsed DC power supply that applies a pulsed voltage to the target can also be used. Furthermore, the magnetron sputtering method, which utilizes the magnetic field of a magnet, offers a high deposition rate, thus increasing productivity. The deposition of the first, second, and third metal oxide films can be suitably performed using sputtering methods, particularly magnetron sputtering. In the following, the magnetron sputtering method may be used as an example to describe the deposition methods for the first, second, and third metal oxide films.

[0232] When forming the first metal oxide film, the second metal oxide film, and the third metal oxide film, noble gases (for example, helium gas, argon gas, xenon gas, etc.) can be used.

[0233] It is preferable to deposit a second metal oxide film in a vacuum after depositing a first metal oxide film, without exposing the surface of the first metal oxide film to the atmosphere. Similarly, it is preferable to deposit a third metal oxide film in a vacuum after depositing a second metal oxide film, without exposing the surface of the second metal oxide film to the atmosphere. By depositing the first, second, and third metal oxide films in succession, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first and second metal oxide films. Examples of such impurities include water and organic matter.

[0234] When using the same material for two or more of the first, second, and third metal oxide films, the films can be deposited in the same processing chamber using the same sputtering target.

[0235] It is preferable that semiconductor layers 108a, 108b, and 108c use the same material. The first metal oxide film, the second metal oxide film, and the third metal oxide film can be deposited continuously in the same processing chamber using the same sputtering target. This increases the productivity of semiconductor devices and reduces manufacturing costs. Furthermore, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first metal oxide film and the second metal oxide film.

[0236] Alternatively, it is preferable to use one or more different materials for semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c. Two or more sputtering targets can be used to deposit the first metal oxide film, the second metal oxide film, and the third metal oxide film. In this case as well, it is preferable to deposit the metal oxide films continuously in a vacuum within the same apparatus without exposing the surface of the metal oxide films to the atmosphere. For example, it is preferable to deposit each metal oxide film in different processing chambers continuously in a vacuum within the same apparatus.

[0237] As mentioned above, there are cases where the boundary between semiconductor layer 108a and semiconductor layer 108b, and the boundary between semiconductor layer 108b and semiconductor layer 108c cannot be clearly identified. In particular, in configurations where the same material is used for semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c, these boundaries may not be clearly identified. Furthermore, by continuously depositing the first metal oxide film, the second metal oxide film, and the third metal oxide film in a vacuum, no interface may be formed between each metal oxide film, and these boundaries may not be identified. In such cases, semiconductor layer 108a, semiconductor layer 108b, and semiconductor layer 108c can be read as the first region, the second region, and the third region. Semiconductor layer 108 has a first region (corresponding to semiconductor layer 108a) on the insulating layer 105 side, a third region (corresponding to semiconductor layer 108c) on the insulating layer 106 side, and a second region (corresponding to semiconductor layer 108b) between the first region and the third region.

[0238] Preferably, the concentration of the third element in the second region is higher than the concentration of the third element in the first region and higher than the concentration of the third element in the third region. The concentration of the third element in the second region can be referenced from the description relating to the concentration of the third element in semiconductor layer 108b described above. The concentrations of the third element in the first region and the third region can be referenced from the descriptions relating to the concentrations of the third element in semiconductor layer 108a and semiconductor layer 108c described above, respectively. Note that the concentrations of the third element in the first region, the second region, and the third region are not limited to the ranges described above.

[0239] Preferably, the film density of the first region and the third region is higher than the film density of the second region. When observing the cross-section of the semiconductor layer 108 using TEM, the first region and the third region may have darker areas in the TE image compared to the second region. Also, the second region may have lighter areas compared to the first and third regions.

[0240] Here, by varying the deposition conditions for the metal oxide film, the film quality of the metal oxide film (later the semiconductor layer) can be varied. Examples of film quality include conductivity, band gap, defect amount, impurity concentration, and crystallinity. Examples of deposition conditions include power density, pressure, gas type, gas flow rate, substrate temperature, and the distance between the sputtering target and the substrate (also called T-S distance or TS distance). When varying the deposition conditions, one or more of the power density, pressure, gas type, gas flow rate, substrate temperature, and T-S distance can be varied. Note that changing the substrate temperature and T-S distance may take time. Therefore, when depositing two or more metal oxide films in the same processing chamber, it is preferable to keep the substrate temperature and T-S distance the same. Note that even when using the same material, the band gap may differ by varying the deposition conditions.

[0241] Preferably, the deposition conditions for the first metal oxide film (hereinafter also referred to as the first deposition conditions) are different from the deposition conditions for the second metal oxide film (hereinafter also referred to as the second deposition conditions). It is preferable that the deposition conditions for the third metal oxide film (hereinafter also referred to as the third deposition conditions) are different from the second deposition conditions. For example, one or both of the power density and the pressure under the first deposition conditions are preferably different from the power density and the pressure under the second deposition conditions. Similarly, one or both of the power density and the pressure under the third deposition conditions are preferably different from the power density and the pressure under the second deposition conditions. It is particularly preferable that the power density and the pressure under the first deposition conditions are different from the power density and the pressure under the second deposition conditions, and the power density and the pressure under the third deposition conditions are different from the power density and the pressure under the second deposition conditions.

[0242] It is preferable that the power densities under the first deposition conditions and the third deposition conditions are each higher than the power density under the second deposition conditions. By increasing the power density, the semiconductor layer 108a and the semiconductor layer 108c which are dense and have few defects can be obtained. The power densities under the first deposition conditions and the third deposition conditions are each 0.3 W / cm ２ or more and 2 W / cm ２ or less, more preferably 0.4 W / cm ２ or more and 2 W / cm ２ or less, more preferably 0.5 W / cm ２ or more and 2 W / cm ２ or less, more preferably 0.6 W / cm ２ or more and 2 W / cm ２ or less, more preferably 0.6 W / cm ２ or more and 1 W / cm ２ or less. If the power density is low, defects in the semiconductor layer 108a and the semiconductor layer 108c may increase, whereas if the power density is too high, the load on the apparatus may increase. By setting the power densities under the first deposition conditions and the third deposition conditions within the aforementioned ranges, the semiconductor layer 108a and the semiconductor layer 108c that are dense and have few defects can be obtained, and the load on the apparatus can be reduced. Note that the power densities under the first deposition conditions and the third deposition conditions are not limited to the aforementioned ranges, respectively.

[0243] Power density is calculated by dividing the power applied to the substrate by the magnet area. The magnet area is the area of ​​the surface of the magnet that overlaps with the sputtering target.

[0244] The power density under the second film deposition condition was 0.1 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.8W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.6W / cm or more ２ The following is preferable, and more preferably 0.3 W / cm². ２ 0.6W / cm or more ２ The following is preferable. Furthermore, it is preferable that the power density under the second film deposition condition is lower than the power density under the first and third film deposition conditions. If the power density is too high, the conductivity of the semiconductor layer 108b may be low, while if the power density is too low, the film deposition rate will be slow, which may reduce productivity. Also, if the power density is too low, the discharge may become unstable. By setting the power density under the second film deposition condition within the above range, it is possible to obtain a semiconductor layer 108b with high conductivity and to increase productivity. Note that the power density under the second film deposition condition is not limited to the above range.

[0245] The pressure in the first and third film deposition conditions is preferably lower than the pressure in the second film deposition condition. By lowering the pressure, dense semiconductor layers 108a and 108c with few defects can be obtained. The pressure in the first and third film deposition conditions is preferably 0.1 Pa or more and 0.8 Pa or less, more preferably 0.1 Pa or more and 0.6 Pa or less, more preferably 0.1 Pa or more and 0.4 Pa or less, and more preferably 0.1 Pa or more and 0.3 Pa or less. If the pressure is too high, there is a risk of an increase in defects in the semiconductor layer 108a and semiconductor layer 108c, while if the pressure is too low, it may take a long time to adjust the pressure in the processing chamber, which may reduce productivity. In addition, if the pressure is too low, arcing may occur, making it difficult to discharge. By setting the pressure in the first and third film deposition conditions within the aforementioned ranges, it is possible to produce dense semiconductor layers 108a and 108c with few defects, and to increase productivity. However, the pressure in the first and third film deposition conditions is not limited to the aforementioned ranges.

[0246] The pressure in the second film deposition condition is preferably 0.2 Pa or more and 1 Pa or less, more preferably 0.3 Pa or more and 1 Pa or less, more preferably 0.4 Pa or more and 1 Pa or less, and more preferably 0.4 Pa or more and 0.8 Pa or less. Furthermore, the pressure in the second film deposition condition is preferably higher than the pressure in the first and third film deposition conditions. If the pressure is too low, the conductivity of the semiconductor layer 108b may be low. On the other hand, if the pressure is too high, the film deposition rate will be slow, which may reduce productivity. Also, if the pressure is too high, discharge may become difficult. By setting the pressure in the second film deposition condition within the above range, it is possible to obtain a semiconductor layer 108b with high conductivity and increase productivity. Note that the pressure in the second film deposition condition is not limited to the above range.

[0247] It is particularly preferable that the power density under the first and third film deposition conditions is higher than the power density under the second film deposition condition, and that the pressure under the first and third film deposition conditions is lower than the pressure under the second film deposition condition. This makes it possible to increase the conductivity of the semiconductor layer 108b and to make the semiconductor layers 108a and 108c denser and reduce defects.

[0248] Here, a configuration is shown in which the power density and pressure in the first and third film deposition conditions are different from those in the second film deposition condition; however, the present invention is not limited to this. It is also possible to differ other parameters (for example, gas flow rate) between the first and third film deposition conditions and the second film deposition condition.

[0249] Furthermore, the first film deposition conditions and the third film deposition conditions can be the same or different. By making the first and third film deposition conditions the same, that is, by making the film quality of semiconductor layer 108a and semiconductor layer 108c the same, the number of film types that need to be controlled in the manufacturing of semiconductor devices can be reduced. This can increase productivity. Alternatively, the first and third film deposition conditions can be different, that is, by making the film quality of semiconductor layer 108a and semiconductor layer 108c different. Since damage may occur to the semiconductor layer 108c when depositing the insulating layer 106, it is preferable that the third film deposition conditions be denser and less prone to defects compared to the first film deposition conditions. For example, one or both of the power density and pressure in the third film deposition conditions can be different from the power density and pressure in the first film deposition conditions. Specifically, the power density under the third film deposition condition can be made higher than the power density under the first film deposition condition. Furthermore, the pressure under the third film deposition condition can be made lower than the pressure under the first film deposition condition.

[0250] Figure 6C shows an enlarged view of the semiconductor layer 108 and its vicinity, as shown in Figure 6B. In Figure 6C, the thicknesses T108a of semiconductor layer 108a, T108b of semiconductor layer 108b, and T108c of semiconductor layer 108c are indicated by solid arrows. Thicknesses T108a, T108b, and T108c are the thicknesses of each layer in the region of semiconductor layer 108 that overlaps with the conductive layer 104 in a cross-sectional view. Note that thicknesses T108a, T108b, and T108c can be controlled by the processing time (also referred to as deposition time) during the deposition of semiconductor layers 108a, 108b, and 108c, respectively.

[0251] A thickness T108b is preferable. A thickness T108b is preferable to both thickness T108a and thickness T108c. By increasing the thickness T108b of the semiconductor layer 108b, which is the main current path, a transistor with a large on-current can be made. However, if the thickness T108b is too thick, oxygen vacancies and V in the semiconductor layer 108b may occur. Ｏ An increase in the amount of H can cause a shift in the transistor's threshold voltage, potentially leading to a larger cutoff current. The thickness T108b is preferably 1 nm to 30 nm, more preferably 2 nm to 30 nm, more preferably 2 nm to 20 nm, more preferably 4 nm to 20 nm, and more preferably 4 nm to 10 nm. By setting the thickness T108b within the above range, a transistor with a large on-current can be made. Furthermore, by suppressing the shift in the threshold voltage, the cutoff current can be reduced, resulting in a normally-off transistor. Note that the thickness T108b is not limited to the above range.

[0252] It is preferable that thicknesses T108a and T108c are each thinner than thickness T108b. Furthermore, thicknesses T108a and T108c are preferably 0.5 nm to 10 nm, more preferably 0.5 nm to 6 nm, more preferably 0.5 nm to 4 nm, more preferably 0.5 nm to 3 nm, and more preferably 1 nm to 3 nm. If thickness T108c is too thick, the physical distance between the conductive layer 104, which functions as the first gate electrode, and the semiconductor layer 108b becomes longer, which may result in a decrease in field-effect mobility. On the other hand, if thickness T108c is too thin, the physical distance between the interface and vicinity of the interface between the insulating layer 106 and the semiconductor layer 108, where trap levels can be formed, and the semiconductor layer 108b, which is the main current path, becomes shorter, which may result in a decrease in field-effect mobility. In addition, reliability may decrease. The same applies to thickness T108a. By setting the thicknesses T108a and T108c within the aforementioned ranges, a transistor with high field-effect mobility and high reliability can be obtained. Note that the thicknesses T108a and T108c are not limited to the aforementioned ranges.

[0253] Here, the semiconductor layer 108 is shown as a three-layer stacked structure, but the present invention is not limited to this. The semiconductor layer 108 can be a single layer, a two-layer, or a four-layer or more stacked structure. When the semiconductor layer 108 has a stacked structure, it is preferable that the semiconductor layer 108 has at least one semiconductor layer 108b.

[0254] Figures 7A and 7B show cross-sectional views of a semiconductor device 10G according to one aspect of the present invention. A top view of the semiconductor device 10G can be found in Figure 2A. Figure 7A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 7B is a cross-sectional view of the section along the dashed line B1-B2.

[0255] The semiconductor device 10G has a transistor 100G. Transistor 100G differs from transistor 100F shown in Figure 6A, etc., in that its semiconductor layer 108 has a two-layer structure consisting of semiconductor layer 108a and semiconductor layer 108b. By omitting the semiconductor layer 108c, the manufacturing process can be simplified and productivity can be increased.

[0256] Figures 8A and 8B show cross-sectional views of a semiconductor device 10H according to one aspect of the present invention. A top view of the semiconductor device 10H can be found in Figure 2A. Figure 8A is a cross-sectional view of the section along the dashed line A1-A2 shown in Figure 2A, and Figure 8B is a cross-sectional view of the section along the dashed line B1-B2.

[0257] The semiconductor device 10H has a transistor 100H. Transistor 100H differs from transistor 100F shown in Figure 6A, etc., in that its semiconductor layer 108 has a two-layer structure consisting of semiconductor layer 108b and semiconductor layer 108c. By omitting the semiconductor layer 108a, the manufacturing process can be simplified and productivity can be increased.

[0258] As mentioned above, the same material can be used for each layer of the semiconductor layer 108. Alternatively, different materials can be used for one or more of the layers of the semiconductor layer 108.

[0259] An example of a configuration in which one or more layers of the semiconductor layer 108 are made of different materials will be described.

[0260] In the semiconductor layer 108 shown in Figures 7A and 7B, it is preferable that semiconductor layer 108a contains indium, element M, and oxygen. It is preferable that semiconductor layer 108b contains indium and oxygen. It is preferable that the content of element M in semiconductor layer 108a is higher than the content of element M in semiconductor layer 108b. For example, In-M oxide can be suitably used in semiconductor layer 108a and indium oxide in semiconductor layer 108b.

[0261] For element M, please refer to the description above. Gallium can be suitably used as element M, for example. In the following, gallium may be used as an example of element M in the explanation.

[0262] The semiconductor layer 108a preferably contains indium, gallium, and oxygen. The semiconductor layer 108b preferably contains indium and oxygen. The gallium content in the semiconductor layer 108a is preferably higher than the gallium content in the semiconductor layer 108b. For example, In-Ga oxide can be suitably used for the semiconductor layer 108a and indium oxide for the semiconductor layer 108b.

[0263] Because the semiconductor layer 108a has an element M with a high bonding energy with oxygen, oxygen vacancies and V are formed in the semiconductor layer 108. Ｏ The increase in H can be suppressed. On the conductive layer 103 side, which functions as a back gate electrode, oxygen deficiency and V Ｏ By providing a semiconductor layer 108a with a low H content, a highly reliable transistor can be made.

[0264] When forming a metal oxide film that will become a semiconductor layer 108 on an insulating layer 105, components contained in the insulating layer 105 (for example, hydrogen) become mixed into the metal oxide film, causing oxygen vacancies and V Ｏ H can be generated. This can lead to oxygen deficiency and V in the channel formation region. Ｏ If H becomes too high, the threshold voltage of the transistor may shift. Furthermore, the reliability of the transistor may decrease. This is especially true for transistors with short channel lengths, where oxygen deficiencies and V in the channel formation region can be problematic. Ｏ The influence of H on the electrical properties is greater, and it is more likely to become a normalion. Therefore, by using a metal oxide containing element M in the semiconductor layer 108a provided in contact with the insulating layer 105, oxygen vacancies and V are created in the semiconductor layer 108. Ｏ This suppresses the increase in H. As a result, even transistors with short channel lengths can be made into normally-off transistors. Furthermore, it can suppress variations in threshold voltage due to drain-induced barrier lowering (DIBL), resulting in highly reliable transistors.

[0265] Hydrogen contained in semiconductor layer 108a diffuses into semiconductor layer 108b, causing oxygen vacancies and V in the channel formation region of semiconductor layer 108b. Ｏ If the amount of H becomes too high, there is a risk that the threshold voltage of the transistor will shift. Here, the bond energy between gallium and hydrogen is higher than that between indium and hydrogen. Therefore, hydrogen mixed into the metal oxide film that becomes the semiconductor layer 108a can exist stably in the gallium-containing semiconductor layer 108a. As a result, the diffusion of hydrogen from semiconductor layer 108a to semiconductor layer 108b is suppressed, thus preventing oxygen vacancies and V in semiconductor layer 108b. Ｏ This allows for the suppression of the increase in H. As a result, it is possible to create a normally-off transistor and suppress variations in the threshold voltage.

[0266] It is preferable that the content of element M in semiconductor layer 108b is lower than the content of element M in semiconductor layer 108a. In other words, it is preferable that the indium content in semiconductor layer 108b is higher than the indium content in semiconductor layer 108a. By increasing the indium content in semiconductor layer 108b, which is the main current path, a transistor with high field-effect mobility can be made.

[0267] When using sputtering to deposit a first metal oxide film that will become semiconductor layer 108a and a second metal oxide film that will become semiconductor layer 108b, it is preferable to use different sputtering targets and deposit the metal oxide films continuously in a vacuum within the same apparatus without exposing the surface of the metal oxide films to the atmosphere. For example, it is preferable to deposit each metal oxide film in different processing chambers continuously in a vacuum within the same apparatus. For example, a sputtering target having indium, element M, and oxygen can be used to deposit the first metal oxide film. For example, an In-M oxide sputtering target can be used as the sputtering target. A sputtering target having indium and oxygen can be used to deposit the second metal oxide film. For example, an indium oxide sputtering target can be used as the sputtering target.

[0268] Alternatively, the first and second metal oxide films can be deposited using the same sputtering target, and element M (e.g., gallium) can be supplied to the first metal oxide film. For supplying element M, for example, ion implantation can be used. For details on ion implantation, please refer to the above description. For example, a sputtering target containing indium can be used for depositing the first metal oxide film and the second metal oxide film. As such a sputtering target, for example, an indium oxide sputtering target can be used. Since the first and second metal oxide films can be deposited continuously in the same processing chamber using the same sputtering target, the productivity of semiconductor devices can be increased. It is preferable to set the acceleration energy for supplying element M so that the concentration of element M is highest in the semiconductor layer 108a, or at or near the interface between the insulating layer 105 and the semiconductor layer 108a. Note that by supplying element M after depositing the first and second metal oxide films, the semiconductor layer 108b may also contain element M. In this case as well, it is preferable that the content of element M in semiconductor layer 108b is lower than the content of element M in semiconductor layer 108a. Alternatively, element M can be supplied after the first metal oxide film is formed, and then the second metal oxide film can be formed. Note that the supply of element M is not limited to ion implantation. For information on the supply of element M, please refer to the description of the supply of impurities mentioned above.

[0269] In the semiconductor layer 108 shown in Figures 8A and 8B, it is preferable that semiconductor layer 108c contains indium, element M, and oxygen. It is preferable that semiconductor layer 108b contains indium and oxygen. It is preferable that the content of element M in semiconductor layer 108c is higher than the content of element M in semiconductor layer 108b. For example, In-M oxide can be suitably used in semiconductor layer 108c and indium oxide in semiconductor layer 108b.

[0270] For example, the semiconductor layer 108c preferably contains indium, gallium, and oxygen. The semiconductor layer 108b preferably contains indium and oxygen. It is preferable that the gallium content in the semiconductor layer 108c is higher than the gallium content in the semiconductor layer 108b. For example, In-Ga oxide can be suitably used for the semiconductor layer 108c and indium oxide for the semiconductor layer 108b.

[0271] Because the semiconductor layer 108c has an element M with a high bonding energy with oxygen, oxygen vacancies and V are formed in the semiconductor layer 108. Ｏ The increase in H can be suppressed. On the conductive layer 104 side which functions as the gate electrode, oxygen deficiency and V Ｏ By providing a semiconductor layer 108c with a low H content, a highly reliable transistor can be made.

[0272] When forming an insulating layer 106 on a semiconductor layer 108, damage may be inflicted on the semiconductor layer 108, or components contained in the deposition gas for the insulating layer 106 (e.g., hydrogen) may be mixed into the semiconductor layer 108, resulting in oxygen deficiencies and V Ｏ H can occur. This may cause the threshold voltage of the transistor to shift. Also, the reliability of the transistor may decrease. Therefore, by using a metal oxide containing element M in the semiconductor layer 108c having a region in contact with the insulating layer 106, oxygen vacancies and V can be created in the semiconductor layer 108. Ｏ This suppresses the increase in H. As a result, even transistors with short channel lengths can be made into normally-off transistors. Furthermore, it can suppress threshold voltage variations due to drain-induced barrier drop (DIBL), resulting in highly reliable transistors.

[0273] Hydrogen contained in semiconductor layer 108c diffuses into semiconductor layer 108b, causing oxygen vacancies and V in the channel formation region of semiconductor layer 108b. ＯIf the amount of H becomes too high, there is a risk that the threshold voltage of the transistor will shift. However, hydrogen mixed into semiconductor layer 108c can exist stably in semiconductor layer 108c containing gallium. As a result, the diffusion of hydrogen from semiconductor layer 108c to semiconductor layer 108b is suppressed, thus preventing oxygen deficiencies and V in semiconductor layer 108b. Ｏ This allows for the suppression of the increase in H. As a result, it is possible to create a normally-off transistor and suppress variations in the threshold voltage.

[0274] It is preferable that the content of element M in semiconductor layer 108b is lower than the content of element M in semiconductor layer 108c. In other words, it is preferable that the indium content in semiconductor layer 108b is higher than the indium content in semiconductor layer 108c. By increasing the indium content in semiconductor layer 108b, which is the main current path, a transistor with high field-effect mobility can be made.

[0275] In the semiconductor layer 108 shown in Figures 8A and 8B, one of the semiconductor layer 108a and semiconductor layer 108c can be made of a different material than semiconductor layer 108b, while the other of semiconductor layer 108a and semiconductor layer 108c can be made of the same material as semiconductor layer 108b.

[0276] A different material can be used for semiconductor layer 108a than for semiconductor layer 108b, and the same material can be used for semiconductor layer 108c. For example, it is preferable that semiconductor layer 108a contains indium, element M, and oxygen. It is preferable that semiconductor layer 108b and semiconductor layer 108c each contain indium and oxygen. It is preferable that the content of element M in semiconductor layer 108a is higher than the content of element M in semiconductor layer 108b and semiconductor layer 108c. For example, In-M oxide can be suitably used for semiconductor layer 108a, and indium oxide can be suitably used for semiconductor layer 108b and semiconductor layer 108c.

[0277] For example, it is preferable that semiconductor layer 108a contains indium, gallium, and oxygen. It is preferable that semiconductor layer 108b and semiconductor layer 108c each contain indium and oxygen. It is preferable that the gallium content in semiconductor layer 108a is higher than the gallium content in semiconductor layer 108b and semiconductor layer 108c. For example, In-Ga oxide can be suitably used in semiconductor layer 108a, and indium oxide can be suitably used in semiconductor layer 108b and semiconductor layer 108c, respectively.

[0278] When the same material (e.g., indium oxide) is used for semiconductor layer 108b and semiconductor layer 108c, it is preferable that semiconductor layer 108b has a region with a higher concentration of the third element compared to semiconductor layer 108c in the channel formation region. Typically, it is preferable that semiconductor layer 108b has a region with a higher hydrogen concentration compared to semiconductor layer 108c. For semiconductor layer 108b and semiconductor layer 108c, please refer to the above description.

[0279] Alternatively, in the semiconductor layer 108 shown in Figures 8A and 8B, a different material can be used for semiconductor layer 108c than for semiconductor layer 108b, and the same material can be used for semiconductor layer 108a. For example, it is preferable that semiconductor layer 108c contains indium, element M, and oxygen. It is preferable that semiconductor layer 108b and semiconductor layer 108a each contain indium and oxygen. It is preferable that the content of element M in semiconductor layer 108c is higher than the content of element M in semiconductor layer 108b and semiconductor layer 108a. For example, In-M oxide can be suitably used for semiconductor layer 108c, and indium oxide can be suitably used for semiconductor layer 108b and semiconductor layer 108a, respectively.

[0280] For example, it is preferable that semiconductor layer 108c contains indium, gallium, and oxygen. It is preferable that semiconductor layer 108b and semiconductor layer 108a each contain indium and oxygen. It is preferable that the gallium content in semiconductor layer 108c is higher than the gallium content in semiconductor layer 108b and semiconductor layer 108a. For example, In-Ga oxide can be suitably used in semiconductor layer 108c, and indium oxide can be suitably used in semiconductor layer 108b and semiconductor layer 108a, respectively.

[0281] When the same material (for example, indium oxide) is used for semiconductor layer 108b and semiconductor layer 108a, it is preferable that semiconductor layer 108b has a region with a higher concentration of the third element compared to semiconductor layer 108a in the channel formation region. Typically, it is preferable that semiconductor layer 108b has a region with a higher hydrogen concentration compared to semiconductor layer 108a. For semiconductor layer 108a and semiconductor layer 108b, please refer to the above description.

[0282] Alternatively, in the semiconductor layer 108 shown in Figures 8A and 8B, different materials can be used for both semiconductor layer 108a and semiconductor layer 108c compared to semiconductor layer 108b. Furthermore, semiconductor layer 108a can be made of the same material as semiconductor layer 108c or a different material.

[0283] For example, it is preferable that semiconductor layer 108a and semiconductor layer 108c each contain indium, element M, and oxygen. It is preferable that semiconductor layer 108b contains indium and oxygen. It is preferable that the content of element M in semiconductor layer 108a and semiconductor layer 108c is higher than the content of element M in semiconductor layer 108b. For example, In-M oxide can be suitably used in semiconductor layer 108a and semiconductor layer 108c, and indium oxide can be suitably used in semiconductor layer 108b. Typically, gallium can be suitably used as element M.

[0284] <Configuration Example 8> Figure 9A shows a top view of a semiconductor device 10I, which is one embodiment of the present invention. Figure 9B shows a cross-sectional view of the cross-section along the dashed line A1-A2 shown in Figure 9A. For a cross-sectional view of the cross-section along the dashed line B1-B2, please refer to Figure 4D.

[0285] The semiconductor device 10I differs from the semiconductor device 10D shown in Figure 4C, etc., in that it has layers 121a and 121b. The semiconductor device 10I has a transistor 100I, layer 121a, and layer 121b.

[0286] Layers 121a and 121b are provided between the semiconductor layer 108 and the insulating layer 105, respectively. The semiconductor layer 108 has regions that are in contact with layers 121a, 121b, and the insulating layer 105.

[0287] The semiconductor layer 108 has a region 108i, a pair of regions (regions 108X and 108Y) flanking region 108i, and a pair of regions (regions 108P and 108Q) located outside of these. Region 108i overlaps with the conductive layer 104 via the insulating layer 106 and does not contact either layer 121a or layer 121b. Regions 108P and 108Q do not overlap with either the conductive layer 104 or the insulating layer 106, respectively. It is also preferable that regions 108P and 108Q contact either layer 121a or layer 121b, respectively. Regions 108X and 108Y contact the insulating layer 106 and either layer 121a or layer 121b, respectively. In transistor 100I, region 108P functions as one of the source region and drain region, and region 108Q functions as the other of the source region and drain region.

[0288] A conductive layer can be used as layer 121a and layer 121b. The conductive layer can be made from the materials listed for conductive layer 104, conductive layer 112a, and conductive layer 112b. Oxide conductors can be suitably used as layer 121a and layer 121b. By using an oxide conductor, the contact resistance between layer 121a and semiconductor layer 108, and the contact resistance between layer 121b and semiconductor layer 108 can be further reduced. Alternatively, a semiconductor layer can be used as layer 121a and layer 121b. The semiconductor layer can be made from the materials listed for semiconductor layer 108. Typically, ITO, ITSO, or In-Sn-Zn oxide can be suitably used as layer 121a and layer 121b.

[0289] It is preferable that the thicknesses of layers 121a and 121b are greater than the thickness T108 of the semiconductor layer 108. This allows for lower electrical resistance of layers 121a and 121b. However, if the thickness T108 of the semiconductor layer 108 is thin, the electrical resistance of regions 108P and 108Q may become high. Nevertheless, by lowering the electrical resistance of layers 121a and 121b, the electrical resistance of the source and drain regions can be lowered even when the thickness T108 is thin.

[0290] Figure 9B and other figures show a configuration in which layers 121a and 121b each have regions that overlap with the conductive layer 104. That is, regions 108X and 108Y each have regions that overlap with the conductive layer 104. In regions 108X and 108Y, the regions that overlap with the conductive layer 104 may function as channel-forming regions. Furthermore, if the electrical resistance of these regions is lower than that of the channel-forming regions, these regions can function as buffer regions to mitigate the drain electric field.

[0291] As shown in Figure 9C, the openings 147a and 147b can also penetrate the semiconductor layer 108 and reach the conductive layers 112a and 112b. The conductive layer 112a has a region in contact with layer 121a and region 108P at the opening 147a. The conductive layer 112b has a region in contact with layer 121b and region 108Q at the opening 147b. This makes it possible to lower the contact resistance between the source electrode and the source region, and the contact resistance between the drain electrode and the drain region, even when the thickness T108 is thin.

[0292] Although Figures 9A to 9C show a configuration in which layers 121a and 121b each have regions that overlap with the conductive layer 104, the present invention is not limited to this. It is also possible to have a configuration in which one or both of layers 121a and 121b do not overlap with the conductive layer 104.

[0293] A method for manufacturing a semiconductor device according to one aspect of the present invention will be described. Note that explanations regarding the materials and formation methods of each element may be omitted if they have already been described.

[0294] Thin films (insulating films, semiconductor films, and conductive films, etc.) that constitute semiconductor devices can be deposited using sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), ALD, and other methods. CVD methods include plasma enhanced chemical vapor deposition (PECVD) and thermal CVD. One type of thermal CVD method is metal-organic chemical vapor deposition (MOCVD).

[0295] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by wet deposition methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.

[0296] When processing thin films that constitute semiconductor devices, lithography or similar methods can be used. Alternatively, thin films can be processed by nanoimprint lithography, sandblasting, lift-off methods, etc. Furthermore, island-shaped thin films can be directly formed by deposition methods using shielding masks such as metal masks.

[0297] There are two main methods of lithography. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, then exposing and developing it to process the thin film into the desired shape.

[0298] In lithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other options include ultraviolet light, KrF laser light, or ArF laser light. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of the light source. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0299] For etching thin films, one or more of the following methods can be used: dry etching, wet etching, and sandblasting.

[0300] <Example of Manufacturing Method 1> Here, an example of a manufacturing method for the semiconductor device 10A shown in Figures 2A to 2C will be explained using Figures 10A to 11E. Figures 10A to 11E show side by side the cross-sectional view between the dashed lines A1 and A2 shown in Figure 2B and the cross-sectional view between the dashed lines B1 and B2 shown in Figure 2C.

[0301] First, a conductive film is formed on the substrate 102, and the conductive film is processed to form a conductive layer 103 (Figure 10A). The conductive film can be suitably formed using a sputtering method.

[0302] Next, an insulating layer 105 is formed on the conductive layer 103 and the substrate 102 (Figure 10A). The insulating layer 105 can preferably be formed using sputtering or plasma CVD.

[0303] Next, the first element is supplied to the insulating layer 105. The method for supplying the first element and the first element itself can be found in the previously mentioned description. Figure 10B schematically shows, with dashed arrows, how the first element is supplied to the insulating layer 105.

[0304] By using a plasma CVD apparatus for forming the insulating layer 105 and supplying the first element, the formation of the insulating layer 105 and the supply of the first element can be performed continuously within the apparatus, thereby increasing productivity. For example, after forming the insulating layer 105, NF ３ The processing chamber can be replaced with an atmosphere containing [a specific element], and plasma processing can be performed in the processing chamber. Furthermore, a halogen-containing gas (for example, NF) can be used as the cleaning gas in the processing chamber of the plasma CVD apparatus. ３ In some cases, a cleaning gas can be used as the source of the first element. This is preferable because it allows the reuse of existing equipment and does not require new capital investment.

[0305] If the power during plasma processing is too high, the insulating layer 105 may be etched, resulting in a reduction in its thickness. It is preferable to set the power and processing time during plasma processing so as to minimize the amount of etching of the insulating layer 105. For example, by lowering the power and shortening the processing time during plasma processing, the amount of etching of the insulating layer 105 can be reduced.

[0306] Next, a metal oxide film 108f, which will become the semiconductor layer 108, is deposited on the insulating layer 105 (Figure 10C). The metal oxide film 108f is preferably deposited by sputtering using a metal target or a metal oxide target. Alternatively, the metal oxide film 108f is preferably deposited by the ALD method. The ALD method allows for easy control of the deposition rate, enabling the deposition of thin films with a high yield. Therefore, the ALD method is particularly suitable when the thickness of the metal oxide film 108f is thin. Furthermore, the CVD method can be used to deposit the metal oxide film 108f.

[0307] A noble gas can be used when forming the metal oxide film 108f.

[0308] When forming the metal oxide film 108f, it is preferable to use conditions that result in a low crystallinity of the metal oxide film 108f. For example, hydrogen gas, oxygen gas, and argon gas can be suitably used as the film-forming gas for the metal oxide film 108f. For details on forming the metal oxide film 108f, please refer to the above description.

[0309] If the substrate temperature during the deposition of the metal oxide film 108f is too high, the indium content in the metal oxide film 108f may decrease. The substrate temperature during the deposition of the metal oxide film 108f is preferably between room temperature (e.g., 25°C) and 200°C, more preferably between room temperature and 150°C, more preferably between room temperature and 120°C, and more preferably between room temperature and 100°C. However, the substrate temperature during the deposition of the metal oxide film 108f is not limited to the above range.

[0310] By increasing the substrate temperature when forming the metal oxide film 108f, the crystallinity of the metal oxide film 108f is increased, and defects can be reduced. This results in a transistor with high field-effect mobility and high reliability. Typically, the substrate temperature can be set to 100°C.

[0311] By lowering the substrate temperature when depositing the metal oxide film 108f, the crystallinity of the metal oxide film 108f at the time of deposition can be reduced. This allows for an increase in grain size during subsequent heat treatment. In particular, it is preferable to deposit the metal oxide film 108f at room temperature or without heating the substrate.

[0312] When using the ALD method, it is preferable to use a film deposition method such as the thermal ALD method or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferred because it exhibits extremely high coverage. The PEALD method is preferred because, in addition to exhibiting high coverage, it allows for low-temperature film deposition.

[0313] The metal oxide film 108f can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.

[0314] For example, when forming an indium oxide film, a precursor containing indium can be used. When forming an In-Ga oxide film, two types of precursors can be used: one containing indium and another containing gallium. Alternatively, a precursor containing both indium and gallium can be used. Furthermore, by using a precursor containing a metal element and a first element, a metal oxide film 108f containing the first element can be formed.

[0315] Examples of indium precursors include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, indium(III) chloride, [3-(dimethylamino)propyl]dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]indium.

[0316] Examples of gallium-containing precursors include trimethylgallium, triethylgallium, gallium(III) chloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, and diethylchlorogallium.

[0317] Examples of aluminum-containing precursors include aluminum chloride and trimethylaluminum.

[0318] Examples of tin-containing precursors include tin(IV) chloride and tetrakis(dimethylamide)tin.

[0319] Examples of zinc-containing precursors include dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride.

[0320] Examples of oxidizing agents include ozone, oxygen, hydrogen peroxide, and water.

[0321] Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow rate ratio of the raw material gases, the duration for which the raw material gases are flowed, and the order in which the raw material gases are flowed. By adjusting these factors, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these factors, it is also possible to deposit a metal oxide film 108f with a continuously changing composition.

[0322] Before forming the metal oxide film 108f, it is preferable to perform at least one of the following: a treatment to desorb water, hydrogen, and organic matter adsorbed on the surface of the insulating layer 105, and a treatment to supply oxygen into the insulating layer 105. For example, a heat treatment can be performed in a vacuum at a temperature of 70°C to 200°C. Alternatively, a plasma treatment can be performed in an oxygen-containing atmosphere. Alternatively, nitrous oxide (N) can be used. ２ Plasma treatment in an atmosphere containing an oxidizing gas such as 0) can supply oxygen to the insulating layer 105. Plasma treatment in an atmosphere containing nitrous oxide gas can suitably remove organic matter from the surface of the insulating layer 105 while supplying oxygen. After such treatment, it is preferable to continuously form a metal oxide film 108f without exposing the surface of the insulating layer 105 to the atmosphere.

[0323] Next, the metal oxide film 108f is processed into island-like structures to form a metal oxide layer 108F (Figure 10D). A wet etching method can be suitably used to form the metal oxide layer 108F. At this time, a portion of the insulating layer 105 in areas that do not overlap with the metal oxide layer 108F may be etched and become thinner. However, by using a material with a high selectivity ratio for the insulating layer 105 during the etching of the metal oxide film 108f, the thinning of the insulating layer 105 can be suppressed.

[0324] Next, a heat treatment is performed. Through the heat treatment, the first element diffuses from the insulating layer 105 to the metal oxide layer 108F, forming a semiconductor layer 108 containing the first element (Figure 10E). The temperature, atmosphere, and apparatus used for the heat treatment can be found in the previously mentioned description.

[0325] Heat treatment can improve the crystallinity of the semiconductor layer 108 and reduce defects. Furthermore, heat treatment can supply oxygen from the insulating layer 105 to the metal oxide film 108f or the semiconductor layer 108.

[0326] When forming a metal oxide film 108f with low crystallinity, crystallization can be achieved through heat treatment. This allows for an increase in the grain size of the crystal grains contained in the semiconductor layer 108.

[0327] Note that heat treatment is not performed at this stage, and can be combined with heat treatment performed in a later step. In addition, a heat treatment in a later step (for example, a film formation step) may also serve as this heat treatment.

[0328] Next, an insulating film 106f is formed to cover the semiconductor layer 108 and the insulating layer 105, forming the insulating layer 106 (Figure 10F). For the formation of the insulating film 106f, plasma CVD, sputtering, or ALD methods can be suitably used, for example.

[0329] By increasing the temperature during the formation of the insulating film 106f, a gate insulating layer with fewer defects can be made. However, if the temperature during the formation of the insulating film 106f is high, oxygen will be detached from the semiconductor layer 108, resulting in oxygen vacancies and V in the semiconductor layer 108. Ｏ In some cases, H may increase. The substrate temperature when forming the insulating layer 106 is preferably 180°C to 450°C, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, and more preferably 300°C to 400°C. By setting the substrate temperature when forming the insulating film 106f within the above range, defects in the insulating layer 106 can be reduced, and the detachment of oxygen from the semiconductor layer 108 can be suppressed. Therefore, a transistor with good electrical characteristics and high reliability can be obtained.

[0330] Before depositing the insulating film 106f, the surface of the semiconductor layer 108 can be subjected to plasma treatment. This plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108. This reduces impurities at the interface between the semiconductor layer 108 and the insulating layer 106, enabling the realization of a highly reliable transistor. This is particularly suitable when the surface of the semiconductor layer 108 is exposed to the atmosphere between the formation of the semiconductor layer 108 and the deposition of the insulating film 106f. The plasma treatment can be performed in an atmosphere such as oxygen, ozone, nitrogen, nitrous oxide, or argon. Furthermore, it is preferable that the plasma treatment and the deposition of the insulating film 106f are performed continuously without exposure to the atmosphere.

[0331] After the insulating film 106f is formed, oxygen can be supplied to the insulating film 106f. As a method of supplying oxygen, for example, ion implantation or plasma treatment can be used. Plasma treatment is preferably performed in an atmosphere containing oxygen. For example, oxygen, nitrous oxide (N) ２ O), Nitrogen dioxide (NO) ２ It is preferable to perform the plasma treatment in an atmosphere containing one or more of the following: carbon monoxide and carbon dioxide. The amount of oxygen supplied can be adjusted, for example, by the power and treatment time in the plasma treatment.

[0332] It is preferable to deposit a film 139 on the insulating film 106f (Figure 10F). Sputtering is preferably used to deposit the film 139. By depositing the film 139 in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 106f.

[0333] The conductivity of the film 139 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139. For example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium gallium oxide, ITO, or ITSO can be used as the film 139.

[0334] It is preferable to use a metal oxide containing one or more of the same elements as the semiconductor layer 108 as the film 139. In particular, it is preferable to use a metal oxide that is applicable to the semiconductor layer 108. By using the same material for film 139 as for the semiconductor layer 108, the equipment used for forming film 139 and the metal oxide film 108f can be shared, thereby reducing manufacturing costs.

[0335] When forming the film 139, the higher the oxygen flow rate ratio of the film-forming gas introduced into the processing chamber of the film-forming apparatus, or the higher the oxygen partial pressure inside the processing chamber, the greater the amount of oxygen supplied to the insulating film 106f. The oxygen flow rate ratio is preferably 50% to 100%, more preferably 60% to 100%, more preferably 70% to 100%, more preferably 80% to 100%, and more preferably 90% to 100%. Typically, the oxygen flow rate ratio can be set to 100%. Note that the oxygen flow rate ratio can be interpreted as the ratio of the oxygen partial pressure to the pressure inside the processing chamber.

[0336] Thus, by depositing the film 139 by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 106f during film formation, and oxygen can be prevented from being released from the insulating film 106f. As a result, a large amount of oxygen can be trapped in the insulating film 106f. Then, a large amount of oxygen can be supplied to the semiconductor layer 108 by subsequent heat treatment. As a result, oxygen vacancies and V in the semiconductor layer 108 can be reduced. Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0337] Furthermore, if there is too much oxygen in the insulating layer 106, defect levels may easily form at and near the interface between the semiconductor layer 108 and the insulating layer 106. In this case, if a high potential is applied to the conductive layer 104 which functions as the gate electrode, electrons, which are carriers, may be trapped in these defect levels, causing the transistor's threshold voltage to shift to the positive side and potentially reducing reliability. In such cases, it is preferable to lower the oxygen flow rate ratio or oxygen partial pressure during film formation of the film 139 to reduce the amount of oxygen supplied to the insulating film 106f. The oxygen flow rate ratio is preferably, for example, 10% to 60%, more preferably 20% to 60%, more preferably 30% to 60%, and more preferably 30% to 50%. This suppresses fluctuations in the threshold voltage, resulting in a highly reliable transistor.

[0338] It is preferable to perform a heat treatment after forming the film 139. By performing a heat treatment after forming the film 139, oxygen can be effectively supplied from the insulating film 106f to the semiconductor layer 108. In addition, oxygen can be supplied from the film 139 to the insulating film 106f.

[0339] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA) can be used as the atmosphere containing nitrogen or oxygen. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a minimum content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 106f as much as possible. The heat treatment can be carried out using an oven, RTA device, etc.

[0340] After the film 139 is formed, or after the aforementioned heat treatment, oxygen can be supplied to the insulating film 106f via the film 139. For example, ion implantation or plasma treatment can be used as methods for supplying oxygen. A detailed explanation of plasma treatment is omitted here, as it can be found in the previous description.

[0341] Next, the film 139 is removed. Removing the film 139 exposes the insulating film 106f. There are no particular limitations on the method for removing the film 139, but a wet etching method can be preferably used. By using a wet etching method, etching of the insulating film 106f during the removal of the film 139 can be suppressed. This prevents the thickness of the insulating film 106f from becoming thinner, and the thickness of the insulating layer 106 can be made uniform.

[0342] The process of supplying oxygen to the insulating film 106f is not limited to the methods described above. For example, ion implantation or plasma treatment can be used. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 106f, and then oxygen can be supplied to the insulating film 106f through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.

[0343] Next, a conductive film is formed on the insulating film 106f. Then, the conductive film and the insulating film 106f are processed to form a conductive layer 104 and an insulating layer 106 (Figure 11A). The conductive film can be formed using, for example, sputtering, thermal CVD (including MOCVD), or ALD.

[0344] Next, the second element is supplied to the semiconductor layer 108 using the conductive layer 104 as a mask. As a result, regions 108P and 108Q are formed in the region of the semiconductor layer 108 that does not overlap with the conductive layer 104 (Figure 11B). Figure 11B schematically shows the supply of the second element to the semiconductor layer 108 with dashed arrows. When supplying the second element, it is preferable to determine the supply conditions for the second element by considering the material and thickness of the conductive layer 104 that acts as a mask, so that the second element is supplied as little as possible to the region of the semiconductor layer 108 that overlaps with the conductive layer 104. This makes it possible to lower the concentration of the second element in the region 108i of the semiconductor layer 108 that overlaps with the conductive layer 104.

[0345] Furthermore, the second element can be supplied before removing the resist mask used to form the conductive layer 104 and the insulating layer 106. By supplying the second element to the semiconductor layer 108 using the resist mask and the conductive layer 104 as a mask, regions 108P and 108Q can be formed. After that, the resist mask is removed.

[0346] In the transistor 100D shown in Figure 4C, etc., since an insulating layer 106 is provided on regions 108R and 108S, the amount of the second element supplied to these regions is less than the amount supplied to regions 108P and 108Q. In addition, in the transistor 100C shown in Figure 4A, etc., after forming the insulating layer 106 and the conductive layer 104, the conductive layer 104 can be used as a mask to supply the second element to the semiconductor layer 108. In this case, the second element is supplied to regions 108P and 108Q via the insulating layer 106.

[0347] Next, an insulating film 195f is formed to cover the conductive layer 104, the insulating layer 106, and the semiconductor layer 108, forming the insulating layer 195 (Figure 11C). Plasma CVD can be suitably used to form the insulating film 195f.

[0348] If the deposition temperature of the insulating film 195f is too high, the second element contained in regions 108P and 108Q may diffuse into the peripheral region including the channel-forming region. In addition, the electrical resistance of regions 108P and 108Q may increase. Therefore, it is preferable to determine the deposition temperature of the insulating film 195f taking into consideration the diffusion of the second element.

[0349] The deposition temperature for the insulating film 195f is preferably, for example, 150°C to 400°C, more preferably 180°C to 360°C, and more preferably 200°C to 250°C. By depositing the insulating film 195f at a low temperature, a transistor with good electrical characteristics can be obtained even with a short channel length.

[0350] A heat treatment can be performed after the formation of the insulating film 195f. This heat treatment may further reduce the electrical resistance of regions 108P and 108Q. A detailed explanation of the heat treatment is omitted as it can be found in the previous description. Note that if the heat treatment temperature is too high (for example, above 500°C), the second element may diffuse into the channel formation region, potentially leading to a decrease in the electrical characteristics and reliability of the transistor.

[0351] Note that this heat treatment is not required. Furthermore, the heat treatment at this stage can be omitted and combined with a heat treatment performed in a later step. Also, if there is a heat treatment in a later step (e.g., a film formation process), this heat treatment may be combined with that step.

[0352] Next, a portion of the insulating film 195f is removed to form openings 147a and 147b that reach regions 108P and 108Q (Figure 11D). This forms the insulating layer 195. For example, a dry etching method can be suitably used to form openings 147a and 147b.

[0353] Next, conductive layers 112a and 112b are formed to cover openings 147a and 147b (Figure 11E).

[0354] Next, an insulating layer 218 is formed on the insulating layer 195, conductive layer 112a, and conductive layer 112b (Figures 2B and 2C). Plasma CVD can be suitably used to form the insulating layer 218.

[0355] By following the above steps, a semiconductor device 10A according to one aspect of the present invention can be manufactured.

[0356] <Example of Manufacturing Method 2> Here, an example of a manufacturing method for the semiconductor device 10F shown in Figures 6A and 6B will be explained using Figures 12A to 12E. Figures 12A to 12E show side by side the cross-sectional view between the dashed lines A1 and A2 shown in Figure 6A and the cross-sectional view between the dashed lines B1 and B2 shown in Figure 6B. Note that explanations of parts that overlap with the above-mentioned <Example of Manufacturing Method 1> may be omitted.

[0357] First, the process is carried out in the same manner as in <Example of Manufacturing Method 1>, up to the deposition of the insulating layer 105. For details on the deposition of the insulating layer 105, please refer to the description in Figure 10A.

[0358] Next, a metal oxide film 108af, which will become the semiconductor layer 108a, is formed (Figure 12A).

[0359] Next, the first element is supplied to the metal oxide film 108af. Figure 12B schematically shows, with dashed arrows, how the first element is supplied to the metal oxide film 108af.

[0360] Next, a metal oxide film 108bf, which will become the semiconductor layer 108b, and a metal oxide film 108cf, which will become the semiconductor layer 108c, are formed (Figure 12C). As a result, a metal oxide film 108f having metal oxide films 108af, 108bf, and 108cf is formed on the insulating layer 105.

[0361] Next, the metal oxide film 108f is processed into an island shape to form a metal oxide layer 108F having metal oxide layers 108A, 108B, and 108C (Figure 12D).

[0362] Next, a heat treatment is performed. Through the heat treatment, the first element diffuses from the metal oxide layer 108A to the metal oxide layers 108B and 108C, forming semiconductor layers 108a, 108b, and 108c (semiconductor layer 108) containing the first element (Figure 12E).

[0363] Note that heat treatment is not performed at this stage, and can be combined with heat treatment performed in a later step. In addition, a heat treatment in a later step (for example, a film formation step) may also serve as this heat treatment.

[0364] Next, an insulating film 106f is formed to cover the semiconductor layer 108 and the insulating layer 105. For details after the formation of the insulating film 106f, please refer to the description in <Example of Manufacturing Method 1>.

[0365] By following the above steps, a semiconductor device 10F according to one aspect of the present invention can be manufactured.

[0366] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0367] (Embodiment 2) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 13A to 22.

[0368] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0369] The display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0370] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a flexible printed circuit board (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an integrated circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0371] The display device of this embodiment may also function as a touch panel. For example, the display device can be fitted with various detection elements (also called sensor elements) that can detect the proximity or contact of an object to be detected, such as a finger.

[0372] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0373] Examples of capacitance methods include surface capacitance and projected capacitance. Furthermore, projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0374] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell touch panel refers to a configuration in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0375] <Example of Display Device Configuration 1> Figure 13A shows a perspective view of the display device 50A.

[0376] The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 13A, substrate 152 is shown with a dashed line.

[0377] The display device 50A includes a display unit 162, a connection unit 140, a circuit unit 164, a conductive layer 165, etc. Figure 13A shows an example in which the IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 13A can also be described as a display module having the display device 50A, an IC, and an FPC.

[0378] The connection portion 140 is provided on the outside of the display unit 162. The connection portion 140 can be provided along one or more sides of the display unit 162. There may be one or more connection portions 140. Figure 13A shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit 162. The common electrode of the display element and the conductive layer are connected at the connection portion 140, and a potential can be supplied to the common electrode.

[0379] The circuit section 164 may include, for example, a scan line drive circuit (also called a gate driver). Alternatively, the circuit section 164 may include both a scan line drive circuit and a signal line drive circuit (also called a source driver).

[0380] The circuit section 164 can utilize various circuits, including shift register circuits, level shifter circuits, inverter circuits, latch circuits, analog switch circuits, demultiplexer circuits, and logic circuits. The circuit section 164 can also utilize transistors and capacitive elements. The transistors in the circuit section 164 can be formed using the same process as the transistors in the pixel circuit.

[0381] The conductive layer 165 has the function of supplying signals and power to the display unit 162 and the circuit unit 164. These signals and power are input to the conductive layer 165 from the outside via the FPC 172, or from the IC 173.

[0382] FIG. 13A shows an example in which an IC 173 is provided over a substrate 151 by a COG method. As the IC 173, for example, an IC including one or both of a scan line driver circuit and a signal line driver circuit can be applied. Note that the display device 50A and the display module may have a structure in which no IC is provided. Further, the IC may be mounted on an FPC by a COF method or the like.

[0383] The semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A. An oxide semiconductor (OS) can be suitably used for a channel formation region of a transistor included in the display device. By using an OS transistor, a display device with low power consumption can be obtained. Furthermore, the semiconductor device which is one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all transistors included in the display device can be OS transistors. When all the transistors included in the display device are OS transistors in this manner, an effect that manufacturing cost can be suppressed low is obtained.

[0384] For example, in the case where the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, so that a high-definition display device can be obtained. For another example, in the case where the semiconductor device of one embodiment of the present invention is applied to a driver circuit (e.g., one or both of a gate line driver circuit and a source line driver circuit) of a display device, the area occupied by the driver circuit can be reduced, so that a display device with a narrow frame can be obtained. In addition, since the semiconductor device of one embodiment of the present invention has favorable electrical characteristics, the reliability of the display device can be increased by using the semiconductor device in the display device.

[0385] The display portion 162 is a region where an image is displayed in the display device 50A, and includes a plurality of pixels 201 arranged periodically. FIG. 13A shows an enlarged view of one pixel 201.

[0386] There is no particular limitation on the arrangement of pixels in the display device of this embodiment, and a variety of methods can be applied. Examples of the pixel arrangement include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a pentile arrangement.

[0387] The pixel 201 illustrated in FIG. 13A includes a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that the sub-pixels 11R, 11G, and 11B may be collectively referred to as the sub-pixel 11 in some cases. Further, the number of sub-pixels included in one pixel is not particularly limited.

[0388] Each of the sub-pixels 11R, 11G, and 11B includes a display element and a pixel circuit that controls driving of the display element.

[0389] Various elements can be used as the display element, and examples thereof include a liquid crystal element and a light-emitting element. In addition, a display element or the like to which a shutter type or light interference type MEMS (Micro Electro Mechanical Systems) element, a microcapsule type, an electrophoretic type, an electrowetting type, or an electronic powder fluid (registered trademark) type or the like is applied can also be used. Further, a QLED (Quantum-dot LED) using a light source and a color conversion technology using a quantum dot material can also be used.

[0390] Examples of the display device using a liquid crystal element include a transmissive liquid crystal display device, a reflective liquid crystal display device, and a transflective liquid crystal display device.

[0391] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and Guest Host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0392] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, etc. Furthermore, either positive-type or negative-type liquid crystals may be used as the liquid crystal material, and can be selected according to the applied mode or design.

[0393] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0394] Examples of light-emitting materials for light-emitting devices include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0395] Examples of quantum dot materials include colloidal quantum dots, alloy quantum dots, core-shell quantum dots, and core quantum dots. Furthermore, quantum dot materials containing elemental groups of Group 2 and Group 16, Group 13 and Group 15, Group 13 and Group 17, Group 11 and Group 17, or Group 14 and Group 15 can be used. Alternatively, quantum dot materials containing elements such as cadmium (Cd), selenium (Se), zinc (Zn), sulfur (S), phosphorus (P), indium (In), tellurium (Te), lead (Pb), gallium (Ga), arsenic (As), and aluminum (Al) can be used.

[0396] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0397] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0398] Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0399] One embodiment of the present invention is a semiconductor device having a transistor with a high on-current. A suitable material for the channel formation region of the transistor can be an oxide semiconductor (OS), resulting in a transistor with a low off-current. This semiconductor device can be suitably used in either or both of the display unit 162 and the circuit unit 164. Furthermore, this semiconductor device can be used in both the display unit 162 and the circuit unit 164, meaning all transistors in the display device can be OS transistors. By using OS transistors for all transistors in the display device in this way, manufacturing costs can be kept low.

[0400] The transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, the transistors of one aspect of the present invention may be combined with transistors of other structures.

[0401] The display device of this embodiment may have, for example, one or more of planar transistors, staggered transistors, or inverse staggered transistors. The transistors in the display device of this embodiment may be top-gate or bottom-gate types. Alternatively, gates may be provided above and below the semiconductor layer in which the channel is formed.

[0402] The display device of this embodiment may have a transistor (also referred to as a Si transistor) using silicon in the channel formation region.

[0403] The transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 may all be the same or there may be two or more different structures. Similarly, the structures of the multiple transistors in the display unit 162 may all be the same or there may be two or more different structures.

[0404] All transistors in the display device may be OS transistors, all transistors in the display device may be Si transistors, or some of the transistors in the display device may be OS transistors and the rest may be Si transistors. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using LTPS in the channel formation region (also referred to as LTPS transistors) have high field-effect mobility and can operate at high speeds.

[0405] For example, by using both an LTPS transistor and an OS transistor in the display unit 162, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for transistors that function as switches to control conduction and non-conduction between wires, and an LTPS transistor is used for transistors that control current.

[0406] <Example of sub-pixel configuration> An example of the configuration of a sub-pixel 11 is shown in Figure 13B. The sub-pixel 11 includes a pixel circuit 51 and a light-emitting device 61.

[0407] The pixel circuit 51 includes a transistor 52A, a transistor 52B, and a capacitive element 53. The pixel circuit 51 is a 2Tr1C type pixel circuit having two transistors and one capacitive element. The pixel circuit that can be applied to the display device according to one embodiment of the present invention is not particularly limited.

[0408] The anode of the light-emitting device 61 is connected to one of the source and drain electrodes of transistor 52B and one electrode of the capacitive element 53. The other source and drain of transistor 52B is connected to wiring ANO. The gate of transistor 52B is connected to one of the source and drain electrodes of transistor 52A and the other electrode of the capacitive element 53. The other source and drain of transistor 52A is connected to wiring SL. The gate of transistor 52A is connected to wiring GL. The cathode of the light-emitting device 61 is connected to wiring VCOM.

[0409] Wiring VCOM is a wire that provides a potential for supplying current to the light-emitting device 61. Transistor 52A has the function of controlling the conduction or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO and VSS is supplied to wiring VCOM.

[0410] Transistor 52A functions as a selection transistor for controlling the selected state of the sub-pixel 11. Transistor 52B functions as a drive transistor for controlling the amount of current flowing to the light-emitting device 61. Capacitive element 53 has the function of holding the gate potential of transistor 52B. The intensity of the light emitted by the light-emitting device 61 is controlled according to the image signal supplied to the gate of transistor 52B. A semiconductor device according to one aspect of the present invention can be used in the pixel circuit 51. One or both of transistors 52A and transistor 52B can preferably be one or more of the aforementioned transistors.

[0411] For the drive transistor, a transistor with high saturation and high current controllability can be suitably used. This makes it possible to create a display device with high display quality. As the drive transistor, an OS transistor with high saturation can be suitably used.

[0412] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thereby allowing control of the current flowing to the light-emitting element. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0413] In terms of the saturation of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as the driving transistor, a stable current can be supplied to the light-emitting element even if there are variations in the current-voltage characteristics of the light-emitting element. In other words, when operating in the saturation region, OS transistors can stabilize the luminescence brightness of the light-emitting element because the change in source-drain current is small even when the source-drain voltage is changed.

[0414] To increase the luminescence brightness of a light-emitting element, it is necessary to increase the amount of current flowing through the element. To achieve this, the source-drain voltage of the driving transistor needs to be increased. Compared to Si transistors, OS transistors have a higher breakdown voltage between the source and drain, allowing a higher voltage to be applied to the source-drain of an OS transistor. Therefore, by using an OS transistor as the driving transistor, the amount of current flowing through the light-emitting element can be increased, thereby increasing the luminescence brightness of the element.

[0415] Because OS transistors have a low off-current, they can be suitably used as selection transistors. This allows the pixel gradation to be maintained even when the frame frequency is significantly low (e.g., 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying still images.

[0416] By using a transistor with high field-effect mobility as the selection transistor, the time required for charging and discharging the floating node FN can be shortened. Accordingly, the frame frequency in display can be increased, and a display device with high display quality can be obtained.

[0417] By using a plurality of transistors and capacitor elements in a pixel circuit, a high-performance display device can be obtained. By applying the semiconductor device which is one embodiment of the present invention, the occupied area can be reduced even when the number of transistors and capacitor elements is increased, and a high-performance and high-definition display device can be obtained. For example, a display device with a definition of 300 ppi or higher, 500 ppi or higher, 1000 ppi or higher, 2000 ppi or higher, or 3000 ppi or higher can be realized.

[0418] Since the semiconductor device of one embodiment of the present invention can reduce the occupied area, the aperture ratio of pixels can be increased in a bottom-emission structure display device. For example, a display device with an aperture ratio of 50% or higher, 55% or higher, or 60% or higher can be realized.

[0419] Note that in this specification and the like, the aperture ratio refers to the ratio of the area of a region from which light is emitted to the area of a pixel.

[0420] A structural example different from the sub-pixel 11 illustrated in FIG. 13B is illustrated in FIG. 13C. The sub-pixel 11 includes a pixel circuit 51A and a light-emitting device 61.

[0421] The pixel circuit 51A is mainly different from the pixel circuit 51 in that the transistor 52B is a p-channel transistor. One electrode of the capacitor element 53 is connected to the wiring ANO.

[0422] In the pixel circuit 51A, an n-channel OS transistor can be suitably used as the transistor 52A, and a p-channel LTPS transistor can be suitably used as the transistor 52B.

[0423] In the pixel circuit 51 shown in Figure 13B, transistors according to one aspect of the present invention (for example, an IO transistor and an IGO transistor) can be suitably used for both transistor 52A and transistor 52B. This allows transistors 52A and 52B to be formed in the same process. Therefore, compared to a configuration using LTPO, the process can be simplified and manufacturing costs can be reduced. Furthermore, as mentioned above, when increasing the luminescence brightness of a light-emitting element, it is necessary to increase the source-drain voltage of the driving transistor. When the source-drain voltage is high, the drain current of an LTPS transistor may increase due to the Kink effect. On the other hand, an OS transistor can be suitably used as a driving transistor because the increase in drain current is small even when the source-drain voltage is high. In addition, compared to an LTPS transistor, an OS transistor has smaller hysteresis and can be suitably used as a selection transistor and a driving transistor.

[0424] Figure 14A shows an example of a configuration different from the sub-pixel 11 shown in Figure 13B. The sub-pixel 11 has a pixel circuit 51B and a light-emitting device 61.

[0425] Pixel circuit 51B differs from pixel circuit 51 mainly in that it has a transistor 52C. Pixel circuit 51B has transistors 52A, 52B, 52C, and a capacitive element 53. Pixel circuit 51B is a 3Tr1C type pixel circuit having three transistors and one capacitive element.

[0426] Pixel circuit 51B has a configuration in which a transistor 52C is added to the pixel circuit 51 shown in Figure 13B. One of the source and drain of transistor 52C is connected to one of the source and drain of transistor 52B. The other of the source and drain of transistor 52C is connected to wiring V0. For example, a reference potential is supplied to wiring V0. The gate of transistor 52C is connected to wiring GL. Transistor 52C has the function of controlling the conduction or non-conduction state between one of the source and drain of transistor 52B and wiring V0 based on the potential of wiring GL.

[0427] The wiring V0 can be used to obtain current values ​​that can be used to set pixel parameters. Specifically, wiring V0 can function as a monitor line to output the current flowing through transistor 52B or the current flowing through light-emitting device 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit and output to the outside. Alternatively, it can be converted into a digital signal by an AD converter and output to the outside.

[0428] Figure 14B shows an example of a configuration different from that of the sub-pixel 11 shown in Figure 14A. The sub-pixel 11 has a pixel circuit 51C and a light-emitting device 61. The gate of transistor 52A is connected to wiring GL1. The gate of transistor 52C is connected to wiring GL2. Transistor 52C has the function of controlling the conduction or non-conduction state between the source and drain of transistor 52B and wiring V0 based on the potential of wiring GL2. By configuring the gates of transistor 52A and transistor 52C to be connected to different wirings, the operation of transistor 52A and the operation of transistor 52C can be controlled independently.

[0429] Back gates can be provided for some or all of the transistors included in the pixel circuit. For example, transistor 52B can have a back gate, and this back gate can be connected to either the source or the drain of transistor 52B. This can improve reliability. Alternatively, the back gate of transistor 52B can be connected to the gate of transistor 52B. This can increase the on-current of transistor 52B.

[0430] Figure 15A shows an example of a cross-section obtained by cutting a portion of the display device 50A, including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the end section.

[0431] The display device 50A shown in Figure 15A has transistors 205D, 205R, 205G, 205B, light-emitting elements 130R, 130G, 130B, etc. between substrates 151 and 152. Light-emitting element 130R is a display element of a sub-pixel 11R that emits red light, light-emitting element 130G is a display element of a sub-pixel 11G that emits green light, and light-emitting element 130B is a display element of a sub-pixel 11B that emits blue light.

[0432] The display device 50A employs an SBS structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0433] The display device 50A is a top-emission type. In the top-emission type, transistors and the like can be placed overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0434] Transistors 205D, 205R, 205G, and 205B are all formed on substrate 151. These transistors can be manufactured using the same process. Figure 15A shows an example configuration in which transistors 205R, 205G, 205B, and 205D are the same as transistor 100A shown in Figure 2B, etc. By using TGSA type transistors, the parasitic capacitance between the source electrode, drain electrode, and gate electrode can be reduced. Therefore, a decrease in display quality caused by parasitic capacitance can be suppressed. Note that transistors 205D, 205R, 205G, and 205B may be transistors with different structures.

[0435] In this embodiment, an example is shown in which OS transistors are used for transistors 205D, 205R, 205G, and 205B. Transistors according to one aspect of the present invention can be used for transistors 205D, 205R, 205G, and 205B. In other words, the display device 50A has transistors according to one aspect of the present invention in both the display unit 162 and the circuit unit 164. By using transistors according to one aspect of the present invention in the display unit 162, the pixel size can be reduced, resulting in a high-definition display device. Furthermore, by using transistors according to one aspect of the present invention in the circuit unit 164, the occupied area of ​​the circuit unit 164 can be reduced, and the bezel can be narrowed. For details on transistors according to one aspect of the present invention, refer to the description in the previous embodiment.

[0436] Specifically, transistors 205D, 205R, 205G, and 205B each have a conductive layer 104 that functions as a gate electrode, an insulating layer 106 that functions as a gate insulating layer, a conductive layer 103 that functions as a back gate electrode, an insulating layer 105 that functions as a back gate insulating layer, conductive layers 112a and 112b that function as source and drain electrodes, and a semiconductor layer 108 having a metal oxide. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film.

[0437] An insulating layer 218 is provided to cover transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided on top of the insulating layer 218. The details of the insulating layer 218 can be found in the previous description.

[0438] The insulating layer 235 preferably functions as a planarization layer, and an organic insulating layer is preferred. Alternatively, the insulating layer 235 can have a laminated structure of an organic insulating layer and an inorganic insulating layer. The outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This suppresses the formation of recesses in the insulating layer 235 during processing of pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be provided in the insulating layer 235 during processing of pixel electrodes 111R, 111G, and 111B, etc. Note that pixel electrodes 111R, 111G, and 111B are sometimes collectively referred to as pixel electrode 111.

[0439] Light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 235.

[0440] The light-emitting element 130R has a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 130R shown in Figure 15A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0441] The light-emitting element 130G has a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 130G shown in Figure 15A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0442] The light-emitting element 130B has a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 130B shown in Figure 15A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0443] In Figure 15A, the EL layers 113R, 113G, and 113B are all shown to be the same thickness, but this is not the only option. The thicknesses of the EL layers 113R, 113G, and 113B may be different. For example, it is preferable to set the thickness of the EL layers 113R, 113G, and 113B so that the optical path length is such that the light emitted by each layer is intensified. This makes it possible to realize a microcavity structure and improve the color purity of the light emitted from each light-emitting element.

[0444] The pixel electrode 111R is in contact with the conductive layer 112b of the transistor 205R at an opening provided in the insulating layer 218 and the insulating layer 235, and is connected to the conductive layer 112b. Similarly, the pixel electrode 111G is connected to the conductive layer 112b of the transistor 205G, and the pixel electrode 111B is connected to the conductive layer 112b of the transistor 205B.

[0445] Each end of the pixel electrodes 111R, 111G, and 111B is covered by an insulating layer 237. The insulating layer 237 functions as a partition. The insulating layer 237 can be provided in a single-layer or multi-layer structure using one or both inorganic insulating materials and / or organic insulating materials. For example, the materials listed for insulating layer 218 and insulating layer 235 can be applied to the insulating layer 237. The insulating layer 237 provides electrical insulation between the pixel electrodes and the common electrode. Furthermore, the insulating layer 237 provides electrical insulation between adjacent light-emitting elements.

[0446] The insulating layer 237 is provided at least on the display unit 162. The insulating layer 237 may be provided not only on the display unit 162, but also on the connection unit 140 and the circuit unit 164. Furthermore, the insulating layer 237 may extend to the end of the display device 50A.

[0447] The common electrode 115 is a continuous film provided in common to the light-emitting elements 130R, 130G, and 130B. The common electrode 115, which is shared by multiple light-emitting elements, is connected to a conductive layer 123 provided at the connection portion 140. It is preferable to use a conductive layer for the conductive layer 123 that is made of the same material and formed using the same process as the pixel electrodes 111R, 111G, and 111B.

[0448] In a display device according to one aspect of the present invention, among the pixel electrodes and common electrodes, the electrode that extracts light is preferably made of a conductive film that transmits visible light. Furthermore, it is preferable that the electrode that does not extract light is made of a conductive film that reflects visible light.

[0449] A conductive film that transmits visible light may also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0450] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other materials include ITO, ITSO, In-Zn oxide, and In-W-Zn oxide. Furthermore, such materials include aluminum alloys such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver alloys of silver and magnesium, and silver alloys of silver, palladium, and copper (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like.

[0451] It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is a semitransmitting / semi-reflective electrode that transmits and reflects visible light, and the other is a reflective electrode that reflects visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0452] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm) for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the electrical resistivity of these electrodes shall be 1 × 10⁻⁶ −２ A value of Ωcm or less is preferable.

[0453] The EL layers 113R, 113G, and 113B are each provided in an island-like manner. In Figure 15A, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 15A, but this is not the only case. In other words, adjacent EL layers may not overlap and may be separated from each other. Furthermore, in a display device, there may be both regions where adjacent EL layers overlap and regions where adjacent EL layers do not overlap and are separated.

[0454] Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

[0455] The light-emitting layer may contain one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). One or more of the organic compounds may be substances with high hole transport properties (hole transport material) and / or substances with high electron transport properties (electron transport material). Alternatively, one or more of the organic compounds may be bipolar substances (substances with high electron and hole transport properties) or TADF materials.

[0456] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration enables high efficiency, low-voltage operation, and a long lifespan for the light-emitting element.

[0457] The EL layer may have, in addition to the light-emitting layer, one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking properties (electron blocking layer), a layer containing a material with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). Furthermore, the EL layer may contain either or both a bipolar material and a TADF material.

[0458] The light-emitting element can be made of either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0459] The light-emitting element may be a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units). Each light-emitting unit has at least one light-emitting layer. The tandem structure is a configuration in which multiple light-emitting units are connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By using a tandem structure, a light-emitting element capable of high-brightness emission can be made. Furthermore, compared to a single structure, the tandem structure can reduce the current required to obtain the same brightness, thus improving reliability. The tandem structure can also be called a stack structure.

[0460] In Figure 15A, when a tandem light-emitting element is used, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0461] A protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B. The protective layer 131 and the substrate 152 are bonded together via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 152. For sealing the light-emitting elements, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 15A, the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided in a frame shape so as not to overlap with the light-emitting elements. Furthermore, the space may be filled with a resin different from the adhesive layer 142 provided in a frame shape.

[0462] The protective layer 131 is provided at least on the display section 162, and preferably so as to cover the entire display section 162. It is preferable that the protective layer 131 covers not only the display section 162, but also the connection section 140 and the circuit section 164. Furthermore, it is preferable that the protective layer 131 extends to the end of the display device 50A. On the other hand, in the connection section 197, there is an area where the protective layer 131 is not provided in order to connect the FPC 172 and the conductive layer 166.

[0463] By providing a protective layer 131 on the light-emitting elements 130R, 130G, and 130B, the reliability of the light-emitting elements can be improved.

[0464] The protective layer 131 can be a single layer or a laminated structure of two or more layers. Furthermore, the conductivity of the protective layer 131 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.

[0465] The presence of an inorganic film in the protective layer 131 prevents oxidation of the common electrode 115 and suppresses the intrusion of impurities (such as moisture and oxygen) into the light-emitting element, thereby suppressing degradation of the light-emitting element and improving the reliability of the display device.

[0466] The protective layer 131 preferably has one or more inorganic insulating layers. The protective layer 131 can be made from the materials listed for insulating layer 106 and insulating layer 105. In particular, the protective layer 131 preferably uses a nitride or nitride oxide, and more preferably uses a nitride.

[0467] The protective layer 131 may also be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO. The inorganic film is preferably highly resistive, specifically, more resistive than the common electrode 115. The inorganic film may further contain nitrogen.

[0468] When the light emitted from a light-emitting element is extracted via a protective layer 131, it is preferable that the protective layer 131 has high transmittance (also referred to as light transmission) to visible light. For example, ITO, IGZO, and aluminum oxide are preferred because they are inorganic materials with high transmittance to visible light.

[0469] As the protective layer 131, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. By using such a laminated structure, it is possible to suppress the penetration of impurities (water, oxygen, etc.) into the EL layer.

[0470] Furthermore, the protective layer 131 may have an organic film. For example, the protective layer 131 may have both an organic film and an inorganic film. Examples of organic films that can be used for the protective layer 131 include an organic insulating layer that can be used for the insulating layer 235.

[0471] A connection portion 197 is provided in the region of substrate 151 where substrate 152 does not overlap. At the connection portion 197, the conductive layer 165 is connected to the FPC 172 via the conductive layer 166 and the connection layer 242. Figure 15A shows an example in which the conductive layer 165 is formed by processing the same conductive film as conductive layers 112a and 112b, and the conductive layer 166 is formed by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B. The connection portion between conductive layer 165 and conductive layer 166 can be configured similarly to the connection portion between the pixel electrode 111 and conductive layer 112b. Specifically, Figure 15A shows an example in which an opening is provided in the upper layer of conductive layer 165, and the conductive layer 166 is in contact with the upper surface of conductive layer 165 at this opening. The conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection part 197 and the FPC 172 to be connected via the connection layer 242.

[0472] The display device 50A is of the top-emission type. The light emitted by the light-emitting element is emitted towards the substrate 152. It is preferable to use a material with high transmittance to visible light for the substrate 152. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.

[0473] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 that faces the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in connection portions 140, and in circuit portions 164, etc.

[0474] A colored layer, such as a color filter, may be provided on the surface of the substrate 152 facing the substrate 151, or on the protective layer 131. By placing a color filter on top of the light-emitting element, the color purity of the light emitted from the pixel can be increased.

[0475] A colored layer is a colored layer that selectively transmits light in a specific wavelength range and absorbs light in other wavelength ranges. For example, a red (R) color filter that transmits light in the red wavelength range, a green (G) color filter that transmits light in the green wavelength range, and a blue (B) color filter that transmits light in the blue wavelength range can be used. One or more of the following can be used for each colored layer: metal materials, resin materials, pigments, and dyes. The colored layers are formed at the desired positions using methods such as printing, inkjet printing, and photolithography etching.

[0476] Various optical components can be placed on the outside of the substrate 152 (the side opposite to the substrate 151). Examples of optical components include polarizing plates, phase difference plates, light diffusion layers (such as diffusion films), anti-reflective layers, and light-gathering films. In addition, surface protection layers such as an antistatic film to suppress the adhesion of dust, a water-repellent film to make it difficult for dirt to adhere, a hard coat film to suppress the occurrence of scratches during use, and a shock-absorbing layer may be placed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO ｘProviding a protective layer is preferable as it can suppress surface contamination and scratching. Alternatively, DLC (diamond-like carbon), aluminum oxide, polyester-based materials, or polycarbonate-based materials may be used as the surface protective layer. It is preferable to use a material with high transmittance to visible light for the surface protective layer. Furthermore, it is preferable to use a material with high hardness for the surface protective layer.

[0477] The substrates 151 and 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, etc., respectively. The substrate on the side that extracts light from the light-emitting element should be made of a material that transmits the light. If flexible materials are used for substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized. In addition, a polarizing plate may be used as at least one of substrates 151 and 152.

[0478] As substrates 151 and 152, various materials can be used, such as polyester resins like polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of substrates 151 and 152 may be made of glass of a thickness sufficient to provide flexibility.

[0479] Furthermore, when a circular polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy for the substrate of the display device. A substrate with high optical isotropy has low birefringence (or a small amount of birefringence). Examples of films with high optical isotropy include triacetylcellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

[0480] Various types of curing adhesives can be used as the adhesive layer 142, including UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins may also be used. Adhesive sheets may also be used.

[0481] As the connecting layer 242, an anisotropic conductive film (ACF), anisotropic conductive paste (ACP), etc., can be used.

[0482] <Example of Display Device Configuration 2> Figure 15B shows an example of a cross-section of the display unit 162 of the display device 50B. The display device 50B differs from the display device 50A in that each sub-pixel of each color uses a light-emitting element having a common EL layer 113 and a coloring layer (such as a color filter). The configuration shown in Figure 15B can be combined with the configuration of the region including the FPC 172, the circuit unit 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection unit 140, and the end portion shown in Figure 15A. Note that in the following description of the display device, parts that are the same as those described in the previously described display device may be omitted.

[0483] The display device 50B shown in Figure 15B includes light-emitting elements 130R, 130G, 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light, etc.

[0484] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0485] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0486] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0487] The light-emitting elements 130R, 130G, and 130B each share an EL layer 113 and a common electrode 115. Providing a common EL layer 113 for each sub-pixel of each color reduces the number of manufacturing steps compared to providing a different EL layer for each sub-pixel of each color.

[0488] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 15B emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0489] A light-emitting element that emits white light preferably includes two or more light-emitting layers. For example, a light-emitting element may have two light-emitting layers whose emitted colors are complementary, or three or more light-emitting layers whose emitted colors combine to produce white light as a whole.

[0490] The EL layer 113 preferably has, for example, an emissive layer having a light-emitting material that emits blue light, and an emissive layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 113 preferably has, for example, an emissive layer that emits yellow light and an emissive layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, an emissive layer that emits red light, an emissive layer that emits green light, and an emissive layer that emits blue light.

[0491] For light-emitting elements that emit white light, a tandem structure is preferable. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light in that order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, a light-emitting unit that emits red light, and a light-emitting unit that emits blue light in that order. For example, the number of layers and color order of the light-emitting unit can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, B, or a three-layer structure of B, X, B. The number of layers and color order of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, G, or a three-layer structure of R, G, R. In addition, other layers may be provided between the two light-emitting layers.

[0492] Furthermore, by applying a microcavity structure, a light-emitting element that normally emits white light may also emit light of specific wavelengths, such as red, green, or blue, with increased intensity.

[0493] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 15B emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. It is preferable to use a quantum dot material for the color conversion layer. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. Some of the light emitted by a light-emitting element may pass through without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via a colored layer, the color of light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light exhibited by the subpixel.

[0494] <Example of Display Device Configuration 3> The display device 50C shown in Figure 16 differs from the display device 50A in that it has a conductive layer 234p, a conductive layer 234a, a conductive layer 234b, and an insulating layer 239.

[0495] An insulating layer 239 is provided on the insulating layer 235, and light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 239.

[0496] The conductive layer 234p is provided so as to cover the openings provided in the insulating layer 218 and the insulating layer 235. The conductive layer 234p is in contact with the conductive layer 112b of the transistor 205R at the openings and is connected to the conductive layer 112b.

[0497] An insulating layer 239 is provided on the conductive layer 234p and the insulating layer 235. The insulating layer 239 can be made from the same materials as those used for the insulating layer 235.

[0498] The pixel electrode 111R is provided so as to cover an opening in the insulating layer 239. The pixel electrode 111R is in contact with the conductive layer 234p at the opening and is connected to the conductive layer 234p. In other words, the pixel electrode 111R is connected to the conductive layer 112b via the conductive layer 234p. The same applies to the pixel electrode 111G and the pixel electrode 111B.

[0499] The conductive layer 234a is provided so as to cover the openings provided in the insulating layer 218 and the insulating layer 235. The conductive layer 234a is in contact with the conductive layer 165 at the openings and is connected to the conductive layer 165.

[0500] The conductive layer 166 is provided so as to cover the opening provided in the insulating layer 239. The conductive layer 166 is in contact with the conductive layer 234a at the opening and is connected to the conductive layer 234a. In other words, the conductive layer 166 is connected to the conductive layer 165 via the conductive layer 234a.

[0501] Figure 16 shows a configuration in which the circuit section 164 has a conductive layer 234b. The conductive layer 234b can also be connected to the transistor 205D.

[0502] Conductive layers 234p, 234a, and 234b each function as wiring. Conductive layers 234p, 234a, and 234b are provided on different layers from conductive layers 112a, 112b, and 104. Therefore, wiring can be arranged on each layer, increasing the flexibility of the layout and reducing the circuit's footprint.

[0503] The conductive layers 234p, 234a, and 234b can be made from the materials listed for conductive layers 112a, 112b, and 104. The conductive layers 234p, 234a, and 234b can be formed in the same process. For example, the conductive layers 234p, 234a, and 234b can be formed by depositing a conductive film and then processing the conductive film.

[0504] <Example of Display Device Configuration 4> The display device 50D shown in Figure 17 differs from the display device 50B mainly in that it is a bottom-emission type display device.

[0505] The light emitted by the light-emitting element is emitted towards the substrate 151. It is preferable to use a material with high transmittance to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 is not a requirement.

[0506] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistors. Figure 17 shows an example in which a light-shielding layer 117 is provided on the substrate 151, an insulating layer 153 is provided on the light-shielding layer 117, and transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153. In addition, a colored layer 132R, a colored layer 132G, and a colored layer 132B are provided on the insulating layer 218, and an insulating layer 235 is provided on the colored layer 132R, a colored layer 132G, and a colored layer 132B.

[0507] The light-emitting element 130R, which overlaps with the colored layer 132R, has a pixel electrode 111R, an EL layer 113, and a common electrode 115.

[0508] The light-emitting element 130G, which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.

[0509] The light-emitting element 130B, which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.

[0510] The pixel electrodes 111R, 111G, and 111B are made of materials with high transmittance to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission type display device, a metal with low electrical resistivity can be used for the common electrode 115, thereby suppressing voltage drops caused by the electrical resistance of the common electrode 115 and achieving high display quality.

[0511] By applying a transistor according to one aspect of the present invention, the occupied area of ​​the pixel circuit can be reduced, thereby increasing the aperture ratio of the pixels or reducing the size of the pixels in a display device with a bottom emission structure.

[0512] <Example of Display Device Configuration 5> The display device 50E shown in Figure 18A differs from the display device 50A mainly in that it has a light-receiving element 130S.

[0513] The display device 50E has a light-emitting element and a light-receiving element in each pixel. In the display device 50E, it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be incorporated into a display device using an organic EL element.

[0514] In a display device 50E having light-emitting and light-receiving elements in its pixels, the pixels have a light-receiving function, allowing for the detection of contact or proximity of an object while displaying an image. Therefore, the display unit 162 has, in addition to an image display function, one or both of an imaging function and a sensing function. For example, the display device 50E can not only display an image using all of its subpixels, but some subpixels can also emit light as a light source, some other subpixels can perform light detection, and the remaining subpixels can display an image.

[0515] Therefore, it is not necessary to provide a light receiving unit and a light source separately from the display device 50E, and the number of components in the electronic device can be reduced. For example, there is no need to separately provide a biometric authentication device or a capacitive touch panel for scrolling, etc., which are provided in the electronic device. Therefore, by using the display device 50E, it is possible to provide an electronic device with reduced manufacturing costs.

[0516] When a light-receiving element is used as an image sensor, the display device 50E can capture an image using the light-receiving element. For example, the image sensor can be used to capture images for personal authentication, such as fingerprints, palm prints, irises, pulse patterns (including vein patterns and arterial patterns), or faces.

[0517] The light-receiving element can be used in touch sensors (also called direct touch sensors) or non-contact sensors (also called hover sensors, hover touch sensors, or touchless sensors). Touch sensors can detect an object (such as a finger, hand, or pen) by making direct contact between the display device and the object. Non-contact sensors, on the other hand, can detect an object even if the object does not come into contact with the display device.

[0518] The light-receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S. Light Lin is incident on the functional layer 113S from outside the display device 50E.

[0519] The pixel electrode 111S is in contact with the conductive layer 112b of the transistor 205S at an opening provided in the insulating layer 218 and the insulating layer 235, and is connected to the conductive layer 112b.

[0520] The ends of the pixel electrodes 111S are covered by an insulating layer 237.

[0521] The common electrode 115 is a continuous film provided in common to the light-receiving element 130S, the light-emitting element 130R (not shown), the light-emitting element 130G, and the light-emitting element 130B. The common electrode 115, which is shared by the light-emitting element and the light-receiving element, is connected to the conductive layer 123 provided at the connection portion 140.

[0522] The functional layer 113S has at least an active layer (also called a photoelectric conversion layer). The active layer contains a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In this embodiment, an example is shown in which an organic semiconductor is used as the semiconductor of the active layer. Using an organic semiconductor is preferable because the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), and the manufacturing equipment can be shared.

[0523] The functional layer 113S may further include layers other than the active layer, such as a material with high hole transport properties, a material with high electron transport properties, or a bipolar material. Furthermore, it may also further include layers containing a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material. For example, the functional layer 113S can be made from materials that can be used in the above-described light-emitting devices.

[0524] The photodetector can use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the photodetector can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0525] The display device 50E shown in Figures 18B and 18C has a layer 353 having a light-receiving element, a circuit layer 355, and a layer 357 having an light-emitting element between the substrate 151 and the substrate 152.

[0526] Layer 353 has, for example, a light-receiving element 130S. Layer 357 has, for example, light-emitting elements 130R, 130G, and 130B.

[0527] The circuit layer 355 includes a circuit for driving a light-receiving element and a circuit for driving a light-emitting element. The circuit layer 355 includes, for example, transistors 205R, 205G, and 205B. In addition, the circuit layer 355 may be provided with one or more of the following: switches, capacitors, resistors, wiring, and terminals.

[0528] Figure 18B shows an example of using the light-receiving element 130S as a touch sensor. As shown in Figure 18B, the light emitted by the light-emitting element in layer 357 is reflected by the finger 352 that is in contact with the display device 50E, and the light-receiving element in layer 353 detects the reflected light. This makes it possible to detect that the finger 352 has come into contact with the display device 50E.

[0529] Figure 18C shows an example of using the light-receiving element 130S as a non-contact sensor. As shown in Figure 18C, the light emitted by the light-emitting element in layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50E, and the light-receiving element in layer 353 detects the reflected light.

[0530] <Example of Display Device Configuration 6> The display device 50F shown in Figure 19A is an example of a display device to which an MML (metal maskless) structure is applied. In other words, the display device 50F has a light-emitting element manufactured without using a fine metal mask.

[0531] In a display device using an MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by depositing a light-emitting layer onto one surface and then processing it using lithography. Therefore, it is possible to realize high-definition display devices or display devices with high aperture ratios, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be made separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and displays high quality. For example, if the display device is composed of three types of light-emitting elements, such as a blue light-emitting element, a green light-emitting element, and a red light-emitting element, three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by lithography three times.

[0532] Because MML (Multilayer Molded) devices can be manufactured without using a metal mask, they can exceed the resolution limits imposed by the precision required for metal mask alignment. Furthermore, when manufacturing devices without a metal mask, the equipment and cleaning processes associated with metal mask manufacturing are eliminated. Additionally, since the lithography process can utilize equipment common to or similar to that used for transistor manufacturing, there is no need to introduce special equipment for manufacturing MML devices. Thus, MML structures allow for lower manufacturing costs, making them suitable for mass production of devices.

[0533] In a display device to which an MML structure is applied, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement. Therefore, a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) can be realized using a so-called stripe arrangement in which the R, G, and B subpixels are each arranged in one direction.

[0534] By providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element.

[0535] By employing a film deposition process using an area mask and a processing process using a resist mask, light-emitting elements can be fabricated using a relatively simple process.

[0536] Note that the laminated structure from substrate 151 to insulating layer 235, and the laminated structure from protective layer 131 to substrate 152 are the same as those of the display device 50A, so their explanation is omitted.

[0537] In Figure 19A, light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 235.

[0538] The light-emitting element 130R includes a conductive layer 124R on an insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 130R shown in Figure 19A emits red light (R). Layer 133R has a light-emitting layer that emits red light. In the light-emitting element 130R, layer 133R and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be called the pixel electrode.

[0539] The light-emitting element 130G includes a conductive layer 124G on an insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 130G shown in Figure 19A emits green light (G). Layer 133G has a light-emitting layer that emits green light. In the light-emitting element 130G, layer 133G and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be called the pixel electrode.

[0540] The light-emitting element 130B includes a conductive layer 124B on an insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 130B shown in Figure 19A emits blue light (B). Layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, layer 133B and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124B and the conductive layer 126B can be called the pixel electrode.

[0541] In this specification, among the EL layers of a light-emitting element, layers provided in an island-like manner for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by multiple light-emitting elements is referred to as the common layer 114. In this specification, the common layer 114 may be omitted, and layers 133R, 133G, and 133B may be referred to as island-like EL layers, island-shaped EL layers, etc. Furthermore, light-emitting elements manufactured without using a metal mask do not need to have a common layer, and all layers constituting the EL layer may be formed in an island-like manner.

[0542] Layers 133R, 133G, and 133B are separated from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0543] Note that in Figure 19A, layers 133R, 133G, and 133B are all shown to be the same thickness, but this is not the only option. The thicknesses of layers 133R, 133G, and 133B may be different.

[0544] The conductive layer 124R is in contact with the conductive layer 112b of transistor 205R at openings provided in the insulating layer 218 and the insulating layer 235, and is connected to the conductive layer 112b. Similarly, the conductive layer 124G is connected to the conductive layer 112b of transistor 205G, and the conductive layer 124B is connected to the conductive layer 112b of transistor 205B.

[0545] The conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235. Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.

[0546] Layer 128 has the function of flattening the recesses of the conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B are provided on conductive layers 124R, 124G, and 124B and on layer 128, and are connected to conductive layers 124R, 124G, and 124B. Therefore, the regions that overlap with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, and the aperture ratio of the pixels can be increased. It is preferable to use conductive layers that function as reflective electrodes for conductive layers 124R and 126R.

[0547] Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used for layer 128 as appropriate. In particular, it is preferable that layer 128 be formed using an insulating material, and especially preferable that it be formed using an organic insulating material. For example, an organic insulating material that can be used for the insulating layer 237 described above can be applied to layer 128.

[0548] Figure 19A shows an example where the upper surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited. The upper surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0549] The height of the top surface of layer 128 and the height of the top surface of conductive layer 124R may be the same, approximately the same, or different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.

[0550] The end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or it may cover the side surface of the end of the conductive layer 124R. Preferably, the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape. Specifically, it is preferable that the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By making the side surface of the pixel electrode tapered, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0551] Detailed explanations of conductive layers 124G, 126G, and conductive layers 124B, 126B are omitted because they are the same as conductive layers 124R, 126R.

[0552] The top and sides of the conductive layer 126R are covered by layer 133R. Similarly, the top and sides of the conductive layer 126G are covered by layer 133G, and the top and sides of the conductive layer 126B are covered by layer 133B. Therefore, the entire region where the conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting region of the light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixels.

[0553] The upper surfaces and sides of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127. A common layer 114 is provided on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.

[0554] In Figure 19A, the insulating layer 237 shown in Figure 15A, etc., is not provided between the conductive layer 126R and layer 133R. Similarly, the insulating layer 237 is not provided between the conductive layer 126G and layer 133G, and between the conductive layer 126B and layer 133B. In other words, the display device 50F does not have an insulating layer (also called a partition, bank, spacer, etc.) that is in contact with the pixel electrodes and covers the upper edges of the pixel electrodes. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made. In addition, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.

[0555] As described above, layers 133R, 133G, and 133B each have an emissive layer. Preferably, layers 133R, 133G, and 133B each have an emissive layer and a carrier transport layer (electron transport layer or hole transport layer). Alternatively, preferably, layers 133R, 133G, and 133B each have an emissive layer and a carrier block layer (hole block layer or electron block layer). Alternatively, preferably, layers 133R, 133G, and 133B each have an emissive layer, a carrier block layer, and a carrier transport layer on the carrier block layer. It is more preferable that the carrier transport layer is provided on the emissive layer. It is more preferable that the carrier block layer is provided on the emissive layer. If the surfaces of layers 133R, 133G, and 133B are exposed to the atmosphere during the manufacturing process of the display device, providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer prevents the light-emitting layer from being exposed to the atmosphere. This reduces damage to the light-emitting layer and improves the reliability of the light-emitting element.

[0556] The common layer 114 may have, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together. The common layer 114 is shared by the light-emitting elements 130R, 130G, and 130B.

[0557] Each side of layer 133R, layer 133G, and layer 133B is covered by the insulating layer 125. The insulating layer 127 covers each side of layer 133R, layer 133G, and layer 133B via the insulating layer 125.

[0558] The sides (and even a portion of the top surface) of layers 133R, 133G, and 133B are covered by at least one of the insulating layers 125 and 127. This prevents the common layer 114 (or common electrode 115) from coming into contact with the pixel electrode and the sides of layers 133R, 133G, and 133B, thereby suppressing short circuits in the light-emitting element. This improves the reliability of the light-emitting element.

[0559] Preferably, the insulating layer 125 has regions that are in contact with the respective sides of layers 133R, 133G, and 133B. By configuring the insulating layer 125 to be in contact with layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.

[0560] The insulating layer 127 is provided on the insulating layer 125 so as to fill any recesses in the insulating layer 125. Preferably, the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.

[0561] By providing insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, thereby reducing the large height differences and irregularities on the formed surface of layers (e.g., carrier injection layers and common electrodes) on the island-shaped layers, making it flatter. Consequently, the coverage of the carrier injection layers and common electrodes can be improved.

[0562] The common layer 114 and the common electrode 115 are provided on layers 133R, 133G, 133B, insulating layer 125, and insulating layer 127. Before the insulating layer 125 and insulating layer 127 are provided, a step difference occurs due to the region where the pixel electrode and island-shaped EL layer are provided and the region where the pixel electrode and island-shaped EL layer are not provided (the region between light-emitting elements). In one embodiment of the present invention, the presence of the insulating layer 125 and insulating layer 127 can flatten this step difference and improve the coverage of the common layer 114 and the common electrode 115. Therefore, connection failures due to step breaks can be suppressed. In addition, it is possible to suppress the local thinning of the common electrode 115 due to the step difference and the resulting increase in electrical resistance.

[0563] The upper surface of the insulating layer 127 is preferably flatter. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex surface, and a concave surface. For example, the upper surface of the insulating layer 127 is preferably a convex surface with a large radius of curvature.

[0564] The insulating layer 125 can be a single-layer structure or a laminated structure of two or more layers. Preferably, the insulating layer 125 has one or more inorganic insulating layers. The insulating layer 125 can be made from the materials listed for insulating layer 106 and insulating layer 105. In particular, aluminum oxide is preferred because it has a high selectivity ratio with the EL layer during etching and has the function of protecting the EL layer during the formation of the insulating layer 127. In particular, by applying an inorganic insulating layer such as an aluminum oxide film, hafnium oxide film, or silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 can be formed with fewer pinholes and excellent function in protecting the EL layer. The insulating layer 125 may also be a laminated structure of a film formed by the ALD method and a film formed by the sputtering method. For example, the insulating layer 125 may be a laminated structure of an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0565] Preferably, the insulating layer 125 functions as a barrier film against at least one of water and oxygen. Preferably, the insulating layer 125 has the function of suppressing the diffusion of at least one of water and oxygen. Furthermore, preferably, the insulating layer 125 has the function of capturing or fixing (getting) at least one of water and oxygen.

[0566] The insulating layer 125 functions as a barrier film, thereby suppressing the intrusion of impurities (typically at least one of water and oxygen) that could diffuse from the outside into each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and, furthermore, a highly reliable display device.

[0567] The insulating layer 127 provided on the insulating layer 125 has the function of flattening the large height differences and irregularities in the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface forming the common electrode 115.

[0568] As the insulating layer 127, an insulating layer having an organic material can be suitably used. Preferably, a photosensitive resin is used as the organic material; for example, a photosensitive resin composition containing an acrylic resin is preferred. In this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0569] As the insulating layer 127, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimidoamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins may be used. Alternatively, as the insulating layer 127, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin may be used. Furthermore, a photoresist may be used as the photosensitive resin. Either a positive-type or negative-type material may be used as the photosensitive resin.

[0570] The insulating layer 127 may be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting element, the insulating layer 127 can suppress light leakage (stray light) from the light-emitting element to adjacent light-emitting elements through the insulating layer 127. This improves the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0571] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used in color filters (color filter materials). In particular, it is preferable to use a resin material obtained by laminating or mixing two or more color filter materials, as this can enhance the visible light shielding effect. In particular, by mixing three or more color filter materials, it is possible to create a black or near-black resin layer.

[0572] <Example of Display Device Configuration 7> Figure 19B shows an example of a cross-section of the display unit 162 of the display device 50G. The display device 50G differs from the display device 50F in that a coloring layer (such as a color filter) is provided for each sub-pixel of each color. The configuration shown in Figure 19B can be combined with the configuration shown in Figure 19A, which includes the region containing the FPC 172, the circuit unit 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection unit 140, and the end.

[0573] The display device 50G shown in Figure 19B includes light-emitting elements 130R, 130G, 130B, colored layers 132R, 132G, and 132B, etc.

[0574] The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50G via the colored layer 132R. Similarly, the light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50G via the colored layer 132G. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50G via the colored layer 132B.

[0575] Each of the light-emitting elements 130R, 130G, and 130B has a layer 133. These three layers 133 are formed using the same material and the same process. Furthermore, these three layers 133 are spaced apart from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0576] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 19B emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of a desired color.

[0577] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 19B emit blue light. In this case, layer 133 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. Furthermore, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. Moreover, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. By extracting the light that has passed through the color conversion layer via the colored layer, the colored layer absorbs light of colors other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.

[0578] <Example of Display Device Configuration 8> The display device 50H shown in Figure 20 differs from the display device 50G mainly in that it is a bottom-emission type display device.

[0579] The light emitted by the light-emitting element is emitted towards the substrate 151. It is preferable to use a material with high transmittance to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 is not a requirement.

[0580] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistors. Figure 20 shows an example in which a light-shielding layer 117 is provided on the substrate 151, an insulating layer 153 is provided on the light-shielding layer 117, and transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153. In addition, a colored layer 132R, a colored layer 132G, and a colored layer 132B are provided on the insulating layer 218, and an insulating layer 235 is provided on the colored layer 132R, a colored layer 132G, and a colored layer 132B.

[0581] The light-emitting element 130R, which overlaps with the colored layer 132R, has a conductive layer 124R, a conductive layer 126R, a layer 133, a common layer 114, and a common electrode 115.

[0582] The light-emitting element 130G, which overlaps with the colored layer 132G, has a conductive layer 124G, a conductive layer 126G, a layer 133, a common layer 114, and a common electrode 115.

[0583] The light-emitting element 130B, which overlaps with the colored layer 132B, has a conductive layer 124B, a conductive layer 126B, a layer 133, a common layer 114, and a common electrode 115.

[0584] The conductive layers 124R, 124G, 124B, 126R, 126G, and 126B are made of materials with high transmittance to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission type display device, a metal or the like with low electrical resistivity can be used for the common electrode 115, thereby suppressing voltage drops caused by the electrical resistance of the common electrode 115 and achieving high display quality.

[0585] By using a transistor according to one aspect of the present invention in a pixel circuit, the occupied area can be reduced, thereby increasing the aperture ratio of pixels or reducing the size of pixels in a display device with a bottom emission structure.

[0586] <Example of Display Device Configuration 9> The display device 50I shown in Figure 21 is a liquid crystal display device in VA mode.

[0587] Substrates 151 and 152 are bonded together by an adhesive layer 144. Furthermore, the liquid crystal 262 is sealed within the region enclosed by substrates 151, 152, and the adhesive layer 144. A polarizing plate 260a is located on the outer surface of substrate 152, and a polarizing plate 260b is located on the outer surface of substrate 151. Although not shown, a backlight can be provided outside of polarizing plate 260a or outside of polarizing plate 260b.

[0588] The circuit board 151 is provided with transistors 205D, 205R, 205G, a connector 197, a spacer 224, and the like. Transistor 205D is a transistor provided in the circuit section 164, and transistors 205R and 205G are transistors provided in the display section 162.

[0589] An insulating layer 218 is provided on transistors 205R, 205G, and 205D, an insulating layer 235 is provided on the insulating layer 218, and a liquid crystal element 60 is provided on the insulating layer 235.

[0590] The substrate 152 is provided with colored layers 132R, 132G, a light-shielding layer 117, an insulating layer 225, a conductive layer 263, and the like. The conductive layer 263 functions as a common electrode for the liquid crystal element 60.

[0591] Each sub-pixel of the display unit 162 comprises a transistor, a liquid crystal element 60, and a colored layer. For example, a sub-pixel that emits red light comprises a transistor 205R, a liquid crystal element 60, and a colored layer 132R that transmits red light. Similarly, a sub-pixel that emits green light comprises a transistor 205G, a liquid crystal element 60, and a colored layer 132G that transmits green light. Although not shown, a sub-pixel that emits blue light similarly comprises a transistor, a liquid crystal element 60, and a colored layer that transmits blue light.

[0592] The liquid crystal element 60 has a pixel electrode 111, a conductive layer 263, and liquid crystal 262 sandwiched between them.

[0593] A conductive layer 264 is provided on the same plane as the conductive layer 103. The conductive layer 264 can be formed using the same process as the conductive layer 103. An electrode 266 is also provided on the same plane as the semiconductor layer 108. The electrode 266 is formed using the same process as regions 108P and 108Q of the semiconductor layer 108 (see Figure 2B), and has low electrical resistance, similar to the source and drain regions of a transistor. The conductive layer 264 has a region that overlaps with the electrode 266 via an insulating layer 105. Capacitance is formed by the conductive layer 264, the electrode 266, and the insulating layer 105 between them. The display device 50I can also be said to have a capacitive element 270A in the region where ...

Claims

It has a semiconductor layer, a conductive layer, a first insulating layer, and a second insulating layer. The semiconductor layer has a region that is in contact with the upper surface of the first insulating layer. The semiconductor layer has indium oxide, The semiconductor layer contains fluorine, The semiconductor layer has a first region that overlaps with the conductive layer via the second insulating layer, and a pair of second regions that sandwich the first region. The second region described above contains impurity elements, The aforementioned impurity elements are one or more of hydrogen, boron, phosphorus, and fluorine. A semiconductor device wherein the concentration of the impurity element in the second region is higher than the concentration of the impurity element in the first region. 　 In claim 1, The first insulating layer is a semiconductor device having fluorine. 　 It has a semiconductor layer, a conductive layer, a first insulating layer, and a second insulating layer. The semiconductor layer has a region that is in contact with the upper surface of the first insulating layer. The semiconductor layer comprises indium, element M, and oxygen. The element M is one or more of gallium, aluminum, and tin. The semiconductor layer contains fluorine, The semiconductor layer has a first region that overlaps with the conductive layer via the second insulating layer, and a pair of second regions that sandwich the first region. The second region described above contains impurity elements, The aforementioned impurity elements are one or more of hydrogen, boron, phosphorus, and fluorine. A semiconductor device wherein the concentration of the impurity element in the second region is higher than the concentration of the impurity element in the first region. 　 In claim 3, The first insulating layer is a semiconductor device having fluorine. 　 In claim 3, A semiconductor device wherein the indium content in the semiconductor layer is 60% or more and 99% or less. 　 In any one of claims 1 to 5, The semiconductor layer comprises a first metal oxide layer, a second metal oxide layer on the first metal oxide layer, and a third metal oxide layer on the second metal oxide layer. A semiconductor device wherein the second metal oxide layer has a region with a higher hydrogen concentration than the first metal oxide layer and the third metal oxide layer, respectively. 　 In claim 6, The second metal oxide layer has a hydrogen concentration of 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３ The region has the following characteristics: A semiconductor device wherein the first metal oxide layer and the third metal oxide layer each have a region in which the hydrogen concentration is 1 / 100 or more and 1 / 8 or less of the hydrogen concentration in the second metal oxide layer. 　 In claim 6, A semiconductor device wherein the second metal oxide layer has regions with lower film density than the first metal oxide layer and the third metal oxide layer, respectively. 　 In claim 6, A semiconductor device wherein the thickness of the second metal oxide layer is greater than the thickness of the first metal oxide layer and the thickness of the third metal oxide layer, respectively. 　 A first insulating layer is formed, The first insulating layer is subjected to plasma treatment using a gas containing fluorine. A metal oxide film is formed on the first insulating layer. The first insulating layer and the metal oxide film are subjected to heat treatment. The aforementioned metal oxide film is processed into an island shape to form a semiconductor layer. A second insulating layer is formed on the semiconductor layer. A conductive layer is formed on the second insulating layer described above. Using the conductive layer as a mask, an impurity element is supplied to a region of the semiconductor layer that does not overlap with the conductive layer. A method for manufacturing a semiconductor device, wherein the impurity element is one or more of hydrogen, boron, phosphorus, and fluorine. 　 In claim 10, A method for fabricating a semiconductor device, wherein nitrogen trifluoride gas is used as the aforementioned gas. 　 In claim 10 or claim 11, A method for manufacturing a semiconductor device, wherein a plasma CVD apparatus is used for the plasma treatment. 　 In claim 10 or claim 11, A plasma CVD apparatus is used to form the first insulating layer. A method for manufacturing a semiconductor device, comprising performing the plasma treatment continuously in a vacuum after forming the first insulating layer.

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