Transistorless computing architecture based on charge-packet coincidence

Abstract

A transistorless computing architecture is disclosed in which logic operations are performed by controlling the propagation and temporal coincidence of localized charge packets. Logical outputs are generated when cumulative charge at an interaction region exceeds a defined energy threshold within a temporal coincidence window. The architecture eliminates current-switching semiconductor transistors in the logic evaluation path and replaces voltage-threshold switching with energy-based coincidence detection. The system enables scalable, low-power computation using charge accumulation, timing relationships, and geometrically defined interaction regions.

Description

[0001] TRANSISTORLESS COMPUTING ARCHITECTURE BASED ON CHARGE-PACKET COINCIDENCE TECHNICAL FIELD

[0002] The present invention relates to electronic computation architectures and, more particularly, to transistorless logic systems in which digital computation is performed using charge-packet propagation, temporal coincidence, and energy-threshold mechanisms rather than current-switching semiconductor devices.

[0003] BACKGROUND

[0004] Modern digital computing systems rely on semiconductor transistors that perform logic operations by switching electrical current based on voltage thresholds. Continued scaling of such devices is limited by leakage currents, thermal dissipation, and variability at nanometer dimensions.

[0005] Alternative approaches, including charge- coupled devices (CCD), single-electron devices, and phase-based systems, have been explored. However, CCD-based systems rely on sequential charge transfer controlled by clocked potential wells, and therefore do not perform logic through direct coincidence of independent charge packets. Other approaches rely on electrostatic steering or threshold switching elements, retaining transistor-like behavior.

[0006] Accordingly, there remains a need for a computing architecture in which logic operations are performed without current-switching devices and without sequential charge transfer, while enabling deterministic logic behavior through physically defined interaction mechanisms.

[0007] SUMMARY OF THE INVENTION

[0008] The present invention discloses a transistorless computing architecture in which logic operations are performed through the temporal coincidence and cumulative energy of localized charge packets.

[0009] In contrast to conventional transistor-based logic, the disclosed system does not rely on voltage threshold switching or continuous current flow. Instead, localized charge packets are introduced into conductive paths and propagate toward an interaction region.

[0010] A logic output is generated only when the cumulative charge contributed by multiple charge packets exceeds a defined energy threshold within a temporal coincidence window.If charge packets arrive outside the coincidence window or individually do not provide sufficient cumulative energy, the output is suppressed.

[0011] The architecture is inherently self-timed and does not require a global clock signal. Logic determination is governed by the physical arrival timing and energy accumulation of charge packets rather than by externally imposed switching events.

[0012] The invention may be implemented in electrical, electrostatic, electromagnetic, optical, acoustic, or hybrid physical domains, provided that localized packets preserve temporal relationships and contribute to cumulative energy at an interaction region.

[0013] BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates an example embodiment of a transistor less logic structure comprising a plurality of conductive paths (101, 102) converging at an interaction region (103), and an output conductive path (104) configured to receive a logic output based on charge packet interaction.

[0014] FIG. 2 illustrates an example embodiment of introducing localized charge packets (204) into a conductive path (203) using a non-switching coupling element (202) coupled to a signal source (201).

[0015] FIG. 3 illustrates an example embodiment in which multiple charge packets (301, 302) arrive at an interaction region (303) within a predetermined temporal or phase relationship, resulting in cumulative charge exceeding a threshold and generation of an output charge packet (304).

[0016] FIG. 4 illustrates an example embodiment in which charge packets (401, 402) arrive at an interaction region (403) outside a predetermined temporal or phase relationship, resulting in cumulative charge remaining below the threshold and suppression of output generation (404).

[0017] FIG. 5 illustrates a nonlinear relationship between cumulative charge at an interaction region and output response, wherein output is generated only when cumulative charge exceeds a defined threshold.

[0018] DETAILED DESCRIPTION

[0019] Charge Packet Representation

[0020] In the disclosed architecture, a logical state is represented by the presence or absence of a localized charge packet within a defined conductive path or region. A logical “1” corresponds to the presence of a localized charge packet, while a logical “0” corresponds to the absence of such a packet.

[0021] The charge packets may comprise electrons, holes, or other localized charge distributions and propagate through conductive or field-defined paths under applied electrical or electrostatic conditions. The packets maintain sufficient spatial and temporal integrityduring propagation to enable interaction at an interaction region. The invention is not limited to a specific charge magnitude or carrier type, provided that the packet retains sufficient integrity to participate in coincidence-based logic evaluation. The interaction and logic determination occur without establishing a continuous current conduction path between input and output.

[0022] Logic Gate Operation

[0023] Logic gates are formed by arranging conductive paths such that two or more charge packets may converge at a defined interaction region. Logical evaluation is performed by packet interaction rather than by modulation of a conductive channel.

[0024] An output charge packet is configured to generate when multiple input charge packets arrive at the interaction region within a predetermined temporal window or phase relationship. If the input packets arrive independently, sequentially, or outside the defined temporal or phase relationship, generation of an output packet is suppressed.

[0025] The interaction region accumulates charge contributions from multiple inputs, and a logic output is generated only when cumulative charge exceeds a threshold. This threshold arises from physical characteristics of the interaction region, including capacitance, leakage resistance, and coupling impedance, which together define the minimum cumulative charge required for output generation.

[0026] By way of example, an AND logic operation is performed when two input charge packets arrive at the interaction region simultaneously or with a defined phase alignment. In the absence of such coincidence, no output packet is produced.

[0027] Phase-Based Decision Mechanism

[0028] Temporal or phase relationships between charge packets serve as the decision variable for logic operations. Phase alignment may be established or controlled through propagation delay, coupling regions, geometric path length differences, passive delay structures, or external timing references.

[0029] This phase-based decision mechanism replaces voltage threshold comparison and enables deterministic digital logic evaluation based on transient physical interactions rather than steady-state electrical conditions.

[0030] Absence of Transistor Switching

[0031] The disclosed system performs logic evaluation without reliance on devices that control current flow by switching between conductive and non-conductive states. Logic operations occur through charge packet propagation, interaction, reinforcement, or suppression at interaction regions.

[0032] Any external electronic, electromechanical, or signal-conditioning components used for packet generation, timing control, or output detection do not participate in the logicaldecision-making process and are not required to perform current-switching logic operations.

[0033] Scalability and Implementation Variants

[0034] The invention is not limited to a particular dimensional scale, material system, or fabrication technique. Conductive paths and interaction regions may be arranged in two-dimensional or three-dimensional geometries, including planar, stacked, or volumetric configurations.

[0035] Charge packets may propagate through electrical, electrostatic, electromagnetic, acoustic, phononic, mechanical, or hybrid physical mechanisms, provided that packet coincidence and phase relationships can be preserved sufficiently for logic evaluation.

[0036] Hybrid Embodiments

[0037] The invention is not limited to implementations employing a single physical carrier or propagation domain. In various hybrid embodiments, localized packets utilized for logic operations may propagate across multiple physical domains while preserving the logical principles of packet coincidence and phase-based decision making.

[0038] In one hybrid embodiment, charge packets are generated electrically and subsequently coupled into optical, plasmonic, or electromagnetic propagation structures. Logic evaluation is performed when corresponding packets arrive at an interaction region within a defined temporal or phase relationship, producing a logic output without reliance on voltage threshold detection.

[0039] In another hybrid embodiment, electrical or optical packets are converted into acoustic, phononic, or mechanical excitations that propagate through solid or fluid media. Logic operations are performed when such packets arrive at an interaction region within a predetermined temporal or phase relationship, while non-coincident arrivals suppress output generation.

[0040] In further hybrid embodiments, packet propagation and interaction may occur across mixed electrical, optical, acoustic, mechanical, magnetic, or electromagnetic domains, including sequential or parallel domain transitions. The logic determination remains governed by packet coincidence and relative phase, independent of the physical carrier or propagation medium.

[0041] Hybrid embodiments may further include intermediary coupling structures, transducers, converters, or interfaces configured to transfer packet information between different physical domains while preserving the temporal or phase relationships relevant to logic evaluation.

[0042] Accordingly, the scope of the invention encompasses hybrid systems in which logical computation is performed by controlling the coincidence and phase relationship of localized packets, regardless of whether said packets propagate within a single physicaldomain or across multiple coupled domains.

[0043] In preferred embodiments, the system is implemented using electrical conductive structures, while other domains represent equivalent implementations.

[0044] Timing-Controlled and Self-Timed Coincidence Embodiments

[0045] In various embodiments, coincidence-based logic evaluation may be performed using either clocked timing control or self-timed operation.

[0046] In clocked embodiments, the introduction, propagation, or interaction of localized charge packets is coordinated with a reference timing signal. The coincidence window is thereby defined relative to said timing signal, enabling synchronous operation across multiple logic regions.

[0047] In self-timed embodiments, logic evaluation occurs without reliance on a global clock. Charge packet propagation delays, geometric path lengths, local coupling regions, or intrinsic physical propagation characteristics define the effective coincidence window. Such embodiments enable asynchronous operation and local timing determinism without centralized synchronization.

[0048] In all timing-controlled embodiments, the reference timing signal does not perform logical decision-making and does not gate a conductive channel, and the logic determination remains governed by packet coincidence at the interaction region.

[0049] Probabilistic and Deterministic Coincidence Windows

[0050] In certain embodiments, coincidence detection is deterministic, such that an output charge packet is generated whenever input charge packets arrive within a defined temporal or phase tolerance.

[0051] In other embodiments, coincidence detection is probabilistic. In such embodiments, the likelihood of output generation increases as the temporal or phase alignment of input charge packets approaches an optimal relationship. Logic evaluation may therefore be governed by a probability distribution associated with packet overlap, interaction strength, or coherence duration.

[0052] Probabilistic embodiments enable noise-tolerant, statistical, or neuromorphic computation while preserving the underlying principle of packet coincidence-based logic evaluation.

[0053] Multi-Input Interaction Region Embodiments

[0054] While example embodiments illustrate interaction regions receiving two input charge packets, the invention is not limited thereto.

[0055] In various embodiments, an interaction region is coupled to three or more conductive paths, each configured to deliver a corresponding charge packet. Logic output isgenerated when a defined subset or combination of said charge packets arrives within a predetermined temporal or phase relationship.

[0056] Such multi-input interaction regions enable realization of higher-order logic functions, including majority logic, threshold logic, and complex coincidence-based operations, without reliance on transistor-based current switching.

[0057] Cascaded Interaction Region and Logic Depth Embodiments

[0058] In further embodiments, multiple interaction regions are arranged in a cascaded configuration, such that an output charge packet generated by a first interaction region serves as an input charge packet for a subsequent interaction region.

[0059] Cascaded embodiments enable construction of multi-stage logic circuits, sequential logic, and computational pipelines. Charge packet regeneration, reinforcement, or timing adjustment may occur between interaction regions to preserve signal integrity and coincidence fidelity across logic depth.

[0060] Accordingly, complex computational functions may be realized through networks of interaction regions without introducing current-switching transistors or voltage threshold logic.

[0061] Exclusive-OR (XOR) Operation

[0062] In an alternative embodiment, logic operations are performed based on temporal noncoincidence of charge packets.

[0063] In such embodiments, conductive paths are configured to introduce controlled propagation delays such that charge packets from multiple inputs arrive at an interaction region with a defined temporal offset.

[0064] When only a single input is present, or when multiple inputs arrive at the interaction region outside the defined coincidence window, cumulative charge conditions result in an output exceeding the threshold.

[0065] When multiple inputs arrive simultaneously within the coincidence window, charge interactions may result in suppression of the output due to redistribution, interference, or insufficient incremental energy beyond the threshold condition.

[0066] Accordingly, the system produces an output when inputs are present but temporally misaligned, thereby implementing an exclusive-OR (XOR) logic function.

[0067] The temporal offset may be controlled by path length, impedance, delay elements, or coupling characteristics within the conductive paths.

[0068] INDUSTRIAL APPLICABILITY

[0069] The disclosed invention is applicable to the manufacture and operation of digital processing systems, including logic controllers, signal processing units, sensor- interface circuits,and specialized computing hardware. The architecture may be implemented in integrated circuits, hybrid electronic systems, or multi-domain computing platforms where logic evaluation is performed using localized charge packet interactions. By performing logic operations without reliance on current-switching transistors, the disclosed system is suitable for applications requiring low-power operation, dense integration, or operation under thermal, leakage, or radiation constraints.

Claims

AMENDED CLAIMSreceived by the International Bureau on 3 September 2026 (3.09.2026) Amendments Under Article 19Replacement claimsThe following complete set replaces all claims originally filed under PCT Rule 46.5(a). Claims 1-3 are amended. Claims 4-19 are unchanged.

1. A method of performing a logic operation, comprising: introducing localized charge packets into a plurality of conductive paths by a non-switching injection mechanism and without establishing a continuous source-drain conduction path; propagating said localized charge packets toward an interaction region comprising a capacitive accumulation node; wherein individual charge packets do not independently exceed a predefined charge threshold and charge contributions from multiple input paths are accumulated at said interaction region; and generating a logic output only when the cumulative charge at said interaction region exceeds said predefined charge threshold within a temporal coincidence window, wherein the logic determination is performed without a current-switching semiconductor transistor in a logic evaluation path and without sequential charge transfer between discrete storage elements.

2. A computing system comprising: a plurality of conductive paths configured to guide propagation of localized charge packets; an interaction region coupled to said conductive paths and configured as a capacitive accumulation node having defined electrical characteristics for accumulating charge contributions from multiple inputs; and an output generation mechanism configured to produce a logic output only when cumulative charge at said interaction region exceeds a defined charge threshold within a temporal coincidence interval, wherein individual charge packets do not independently exceed said threshold and wherein the system operates without current-switching semiconductor transistors in a logic evaluation path and without sequential charge transfer between discrete storage elements.

3. A logic device comprising: an interaction region coupled to a plurality of conductive paths; a nonswitching injection mechanism configured to introduce localized charge packets into said conductive paths; and a threshold response mechanism associated with a capacitive accumulation region and configured to generate an output only when coincident arrival of multiple charge packets causes cumulative charge at the interaction region to exceed a defined charge threshold within a temporal coincidence window, wherein logic determination is based on temporal coincidence and cumulative charge accumulation rather than voltage threshold switching and without current-switching semiconductor transistors in the logic evaluation path.

4. The method of claim 1, wherein said temporal coincidence window is defined by propagation delays along said conductive paths.

5. The method of claim 1 , wherein absence of coincidence results in suppression of the logic output due to cumulative charge remaining below said threshold.

6. The system of claim 2, wherein said interaction region is configured such that individual charge packets do not independently exceed said threshold.

7. The system of claim 2, wherein said capacitive accumulation node stores charge contributed by multiple inputs.

8. The device of claim 3, wherein said threshold response mechanism is determined by electrical characteristics including capacitance, leakage resistance, or coupling impedance.

9. The device of claim 3, wherein said logic operation is self-timed and does not require a global clock signal.

10. The method of claim 1, wherein said localized charge packets are introduced via capacitive coupling without forming a continuous conductive channel.

11. The system of claim 2, wherein logic output depends on cumulative charge exceeding said threshold rather than continuous current flow.

12. The device of claim 3, wherein said conductive paths are arranged in two-dimensional or three-dimensional geometries.

13. The method of claim 1 , wherein said temporal coincidence window is adjustable through path length, impedance, or propagation delay.

14. The system of claim 2, wherein said architecture operates without sequential charge transfer between discrete storage elements.

15. The method of claim 1 , wherein coincident inputs produce a nonlinear increase in output relative to individual inputs.

16. The system of claim 2, wherein said interaction region produces distinct output states corresponding to sub-threshold and super-threshold charge accumulation.

17. The method of claim 1 , wherein a logic output is generated when charge packets arrive outside the temporal coincidence window.

18. The system of claim 2, wherein conductive paths include delay elements configured to produce temporal offsets between charge packets.

19. The device of claim 3, wherein logic output depends on whether charge packets arrive within or outside the temporal coincidence window.[0001]Statement under Article 19(1)[0002]The Applicant respectfully submits that the amended claims further define the physical charge-domain mechanism disclosed in the application and address the inventive-step reasoning in the Written Opinion. D1 concerns superconducting temporal logic in which coincidence is implemented using Josephson-junction / SFQ circuitry and a critical-current switching condition. D2 concerns charge-transfer structures. Neither document, alone, discloses the claimed combination in which localized charge packets propagate to a common capacitive accumulation node, individual packets are insufficient to cross the charge threshold, and coincident packets cause cumulative charge at that node to exceed the threshold within a defined temporal coincidence window, thereby generating the logic output without current-switching semiconductor transistors in the logic evaluation path and without sequential transfer between discrete storage elements.[0003]The amendments therefore clarify the physical relationship among charge-packet propagation, transient accumulation, temporal coincidence and threshold output generation. The Applicant submits that the cited documents do not provide a teaching or motivation that would lead the skilled person to the claimed charge-domain logic mechanism without hindsight.[0004]The amendments are supported by the application as filed, including the originally filed claims and the description concerning localized charge packets, capacitive accumulation, cumulative threshold behavior, temporal coincidence, non-switching injection and operation without sequential charge transfer.

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