Printed wiring board

Abstract

This printed wiring board comprises a base film and a circuit. The base film has a main surface. The circuit is provided on the main surface. Let the z direction be the direction that is perpendicular to the main surface. Let the x direction be the direction that, when viewed from the z direction, is perpendicular to the direction in which the circuit extends. The circuit includes an upper surface region, a lower surface region, and a narrow region. The lower surface region is in contact with the main surface. The upper surface region is located opposite the lower surface region in the z direction. The narrow region is disposed between the upper surface region and the lower surface region in the z direction. A first width of the upper surface region in the x direction is equal to or greater than a second width of the lower surface region. The second width is greater than a third width of the narrow region.

Description

Printed wiring board

[0001] The present disclosure relates to a printed wiring board.

[0002] Conventionally, a printed wiring board in which a circuit is provided on a base film is known (for example, refer to Japanese Patent Laid-Open No. 2013-229585).

[0003] Japanese Patent Laid-Open No. 2013-229585

[0004] A printed wiring board according to the present disclosure includes a base film and a circuit. The base film has a main surface. The circuit is provided on the main surface. A direction perpendicular to the main surface is defined as a z-direction. A direction perpendicular to the extending direction of the circuit when viewed from the z-direction is defined as an x-direction. The circuit includes an upper surface region, a lower surface region, and a narrowed region. The lower surface region is in contact with the main surface. The upper surface region is located opposite to the lower surface region in the z-direction. The narrowed region is disposed between the upper surface region and the lower surface region in the z-direction. In the x-direction, the first width of the upper surface region is equal to or greater than the second width of the lower surface region. The second width is larger than the third width of the narrowed region.

[0005] Figure 1 is a cross-sectional view of a printed circuit board according to Embodiment 1. Figure 2 is a partially enlarged cross-sectional view of region II in Figure 1. Figure 3 is a flowchart showing a method for manufacturing a printed circuit board according to Embodiment 1. Figure 4 is a cross-sectional view showing one step in the method for manufacturing a printed circuit board according to Embodiment 1. Figure 5 is a cross-sectional view showing one step in the method for manufacturing a printed circuit board according to Embodiment 1. Figure 6 is a cross-sectional view showing one step in the method for manufacturing a printed circuit board according to Embodiment 1. Figure 7 is a cross-sectional view showing one step in the method for manufacturing a printed circuit board according to Embodiment 1. Figure 8 is a cross-sectional view showing one step in the method for manufacturing a printed circuit board according to Embodiment 1. Figure 9 is a cross-sectional view showing one step in the method for manufacturing a printed circuit board according to Embodiment 1. Figure 10 is a cross-sectional view showing one step in the method for manufacturing a printed circuit board according to Embodiment 1. Figure 11 is a cross-sectional view of a printed circuit board according to Embodiment 2. Figure 12 is a partially enlarged cross-sectional view of region XII in Figure 11. Figure 13 is a flowchart showing a method for manufacturing a printed circuit board according to Embodiment 2. Figure 14 is a cross-sectional view showing one step in the method for manufacturing a printed circuit board according to Embodiment 2. Figure 15 is a cross-sectional view showing one step in the method for manufacturing a printed circuit board according to Embodiment 2. Figure 16 is a cross-sectional view showing one step in the manufacturing method of a printed circuit board according to Embodiment 2.

[0006] There is a growing demand for miniaturization of circuits on printed circuit boards. As circuits become smaller, if circuits of a constant width are formed, the protective layer covering those circuits may become more prone to peeling. In addition, if the spacing between adjacent circuits becomes narrower, migration may occur on the surface of the base film, potentially leading to short-circuit failures.

[0007] This disclosure aims to provide a printed circuit board in which the adhesion of the protective layer is maintained and short-circuit defects do not occur.

[0008] According to this disclosure, it is possible to provide a printed circuit board in which the adhesion of the protective layer is maintained and short-circuit defects do not occur.

[0009] First, embodiments of the present disclosure will be listed and described. (1) The printed circuit board according to the present disclosure comprises a base film and a circuit. The base film has a main surface. The circuit is provided on the main surface. The direction perpendicular to the main surface is defined as the z direction. The direction perpendicular to the direction in which the circuit extends, as viewed from the z direction, is defined as the x direction. The circuit includes an upper region, a lower region, and a narrow region. The lower region is in contact with the main surface. The upper region is located opposite the lower region in the z direction. The narrow region is located between the upper region and the lower region in the z direction. In the x direction, the first width of the upper region is greater than or equal to the second width of the lower region. The second width is greater than the third width of the narrow region. In this way, the adhesion of the protective layer on the printed circuit board is maintained, and short-circuit defects do not occur.

[0010] (2) According to the printed circuit board described in (1) above, the narrow region may be positioned in the lower half of the circuit in the z direction. In this way, a printed circuit board can be obtained in which the second width of the lower region is less than or equal to the first width of the upper region.

[0011] (3) In the case of the printed circuit board described in (1) or (2) above, the thickness of the base film in the z direction may be 100 μm or less. In this way, a printed circuit board can be obtained in which peeling of the protective layer is prevented while keeping the thickness of the base film thin. If the thickness of the base film in the z direction exceeds 100 μm, the base film becomes less likely to bend and the protective layer becomes less likely to peel off, but the total thickness of the product to which the base film is applied becomes thicker, making it impossible to apply to narrow spaces.

[0012] (4) In the case of a printed circuit board according to any of (1) to (3) above, the height of the circuit in the z direction may be 5 μm or more and 40 μm or less. In this way, the adhesion of the protective layer on the printed circuit board is maintained.

[0013] (5) In the case of a printed circuit board according to any of (1) to (4) above, the circuit may include a seed layer in contact with the main surface. In this way, a printed circuit board can be obtained using a semi-additive method in which the adhesion of the protective layer is maintained and short-circuit defects do not occur.

[0014] (6) In the printed circuit board according to any of (1) to (5) above, the circuit may include a first circuit section and a second circuit section. The second circuit section may be spaced apart from the first circuit section in the x direction. In this way, the circuit on the printed circuit board is composed of multiple circuit sections.

[0015] (7) In the printed circuit board described in (6) above, the first width may be 5 μm or more and 40 μm or less. The sum of the shortest distance from the first circuit section to the second circuit section on the main surface and the second width may be 50 μm or less. In this way, a printed circuit board with miniaturized circuits can be obtained.

[0016] (8) In the printed circuit board described in (6) or (7) above, the shortest distance from the first circuit section to the second circuit section on the main surface may be greater than the shortest distance from the upper half of the first circuit section to the upper half of the second circuit section. In this way, the spacing between adjacent circuits on the main surface is increased, and migration does not occur on the surface (main surface) of the base film. As a result, a printed circuit board that does not experience short-circuit defects can be obtained.

[0017] (9) In the printed circuit board described in (8) above, the shortest distance from the first circuit section to the second circuit section on the main surface may be 5 μm or more. In this case, the spacing between adjacent circuits on the main surface is sufficiently large, so migration does not occur on the surface (main surface) of the base film.

[0018] (10) In the case of a printed circuit board relating to any of (1) to (9) above, the difference between the second width and the third width may be 0.2 μm or more and 10 μm or less. In this way, the adhesion of the protective layer on the printed circuit board is maintained.

[0019] Next, the details of the embodiments of this disclosure will be described with reference to the drawings. In the following drawings, identical or corresponding parts will be given the same reference numerals, and their descriptions will not be repeated.

[0020] (Embodiment 1) <Configuration of Printed Wiring Board> The configuration of the printed wiring board 100 according to Embodiment 1 will be described below.

[0021] Figure 1 is a cross-sectional view of a printed circuit board 100 according to Embodiment 1. Figure 2 is a partially enlarged cross-sectional view of region II in Figure 1. As shown in Figure 1, the printed circuit board 100 has a base film 1, a circuit 3, and a protective layer 4.

[0022] The material constituting the base film 1 has electrical insulation properties and flexibility. The material constituting the base film 1 may be, for example, polyimide. However, the material constituting the base film 1 is not limited to this.

[0023] The base film 1 has main surfaces 11 and 12. The main surfaces 11 and 12 are the end faces in the thickness direction (z direction) of the base film 1. Main surface 12 is located opposite to main surface 11. Circuit 3 is provided on the main surfaces 11 and 12.

[0024] As shown in Figure 1, the direction perpendicular to the main surface 11 is defined as the z-direction. The direction in which the circuit 3 extends, as viewed from the z-direction, is defined as the y-direction. The direction perpendicular to the direction in which the circuit 3 extends (y-direction), as viewed from the z-direction, is defined as the x-direction. In other words, the x-direction and the y-direction are perpendicular to the z-direction. From a different perspective, the x-direction is the width direction of the circuit 3. The z-direction is the height direction of the circuit 3.

[0025] As shown in Figure 1, the thickness T of the base film 1 in the z direction may be 5 μm or more and 100 μm or less, or 10 μm or more and 90 μm or less. From the viewpoint of miniaturizing the printed circuit board 100 so that it can be applied to narrow spaces, the thickness T of the base film 1 in the z direction may be 25 μm or 50 μm.

[0026] A seed layer 21, which is made of copper foil, may be provided on both sides (main surfaces 11 and 12) of the base film 1. The seed layer 21 is a component that makes up the circuit 3. The material that makes up the seed layer 21 is copper or a copper alloy. The thickness of the seed layer 21 in each z direction may be 0.1 μm or more. The thickness of the seed layer 21 in each z direction may be 2.0 μm or less, 1.5 μm or less, or 0.8 μm or less. In this way, when the seed layer 21 is thin, the amount of the circuit 3 removed by etching when etching the underlying layer of the circuit 3 is suppressed.

[0027] As shown in Figure 1, the circuit 3 includes a seed layer 21, an electroplating layer 31, an etching acceleration section 32, and an electroless plating layer 33. In this embodiment 1, the circuit 3 is formed by stacking the seed layer 21, the electroless plating layer 33, the etching acceleration section 32, and the electroplating layer 31 in that order.

[0028] The underlayer of circuit 3 consists of a seed layer 21 and an electroless plating layer 33. The underlayer of circuit 3 does not necessarily include the electroless plating layer 33, and may consist only of the seed layer 21. The seed layer 21 is in contact with the main surface 11. The electroless plating layer 33 is placed on top of the seed layer 21. The material constituting the electroless plating layer 33 is copper or a copper alloy. The electroless plating layer 33 is formed by electroless plating.

[0029] The etching acceleration section 32 is a part in the manufacturing method of the printed circuit board 100, which will be described later, where etching is accelerated. The etching acceleration section 32 may be a layer having an observable thickness in the z direction, or it may be the interface between the electroless plating layer 33 and the electrolytic plating layer 31. When etching the underlayer of the circuit 3, the etching speed of the etching acceleration section 32 is relatively faster than the etching speed of the other layers constituting the circuit 3. In this way, a region where the width of the circuit 3 in the x direction is smallest (narrow region A3, which will be described later) is formed in the etching acceleration section 32.

[0030] The electroplating layer 31 is, for example, placed on the etching acceleration section 32. The material constituting the electroplating layer 31 is copper or a copper alloy. The electroplating layer 31 is formed by electroplating.

[0031] As shown in Figure 2, the height T1 of the circuit 3 in the z direction may be 5 μm or more and 40 μm or less, or 10 μm or more and 20 μm or less. In this way, the adhesion of the protective layer 4 on the printed circuit board 100 is maintained.

[0032] As shown in Figures 1 and 2, circuit 3 is composed of multiple circuit sections. Specifically, as shown in Figure 2, circuit 3 includes a first circuit section 3a and a second circuit section 3b. The second circuit section 3b is spaced apart from the first circuit section 3a in the x-direction.

[0033] The protective layer 4 protects the circuit 3. The protective layer 4 may also be insulating. The protective layer 4 may be, for example, a coverlay, a solder resist, or a bonding sheet. The material constituting the protective layer 4 is, for example, a resin.

[0034] Here, a feature of the printed circuit board 100 according to this embodiment 1 is that, as shown in Figure 2, the width of the circuit 3 in the x-direction is not constant in the z-direction. As shown in Figure 2, the circuit 3 includes an upper region A1, a lower region A2, and a narrow region A3. The lower region A2 is formed by the bottom surface (lower surface) of the seed layer 21. The upper region A1 is located opposite the lower region A2 in the z-direction. Specifically, it is a region where the distance from the lower region A2 is 90 percent of the height T1 of the circuit 3, resulting in a height T3. The narrow region A3 is located between the upper region A1 and the lower region A2 in the z-direction. As mentioned above, the narrow region A3 is formed in the etching promotion section 32.

[0035] As shown in Figure 2, the first width W1 in the x-direction of the upper surface region A1 is greater than or equal to the second width W2 in the x-direction of the lower surface region A2. From a different perspective, the shortest distance P2 from the first circuit section 3a to the second circuit section 3b on the main surface 11 is greater than the shortest distance P1 from the upper half of the first circuit section 3a to the upper half of the second circuit section 3b. Note that the "shortest distance P1 from the upper half of the first circuit section 3a to the upper half of the second circuit section 3b" can also be the shortest distance from the upper surface region A1 of the first circuit section 3a to the upper surface region A1 of the second circuit section 3b. In other words, the shortest distance P1 is the distance from the first circuit section 3a to the second circuit section 3b at a position where the distance from the lower surface region A2 is 90 percent of the height T1 of the circuit 3 (height T3).

[0036] In this way, even if the circuit 3 is miniaturized, the distance between adjacent circuits 3 (for example, the first circuit section 3a and the second circuit section 3b) on the main surface 11 (the shortest distance P2 in Figure 2) is sufficiently large, so migration does not occur on the surface (main surface 11) of the base film 1. As a result, a printed circuit board that does not experience short-circuit defects can be obtained.

[0037] The shortest distance P2 from the first circuit section 3a to the second circuit section 3b on the main surface 11 may be 5 μm or more, or 10 μm or more. In this case, the spacing between adjacent circuits 3 on the main surface 11 is sufficiently large, so migration does not occur on the surface (main surface 11) of the base film 1.

[0038] In the z-direction, the narrow region A3 may be positioned in the lower half of the circuit 3. From a different perspective, the chipping acceleration section 32 may be positioned in the lower half of the circuit 3. The height T2 from the main surface 11 to the narrow region A3 in the z-direction may be 2.0 μm or less, 1.0 μm or less, or 0.4 μm or less. In this case, the second width W2 of the lower surface region A2 will be less than or equal to the first width W1 of the upper surface region A1. The height T2 from the main surface 11 to the narrow region A3 in the z-direction may be 0.1 μm or more.

[0039] Further, the second width W2 in the x-direction of the lower surface region A2 is larger than the third width W3 in the x-direction of the narrow region A3. That is, the first width W1 in the x-direction of the upper surface region A1 is larger than the third width W3 in the x-direction of the narrow region A3. By doing so, a recess is provided on the side surface of the circuit 3. Since the protective layer 4 is filled into the recess, the adhesion between the circuit 3 and the protective layer 4 is improved.

[0040] The difference between the second width W2 and the third width W3 is defined as a difference L1. The adhesion between the circuit 3 and the protective layer 4 depends on the difference L1. The difference L1 may be 0.2 μm or more and 10 μm or less, or may be 1.0 μm or more and 10 μm or less. In this way, the adhesion of the protective layer 4 in the printed wiring board 100 is maintained. If the difference L1 exceeds 10 μm, the circuit 3 may be peeled off.

[0041] In this manner, by forming the circuit 3 in which the third width W3 is smaller than each of the first width W1 and the second width W2, and the second width W2 is equal to or less than the first width W1, it is possible to obtain the printed wiring board 100 in which the adhesion of the protective layer 4 is maintained and short-circuit defects do not occur.

[0042] As described above, the printed wiring board 100 may have a miniaturized circuit 3. Specifically, the first width W1 may be 5 μm or more and 40 μm or less. A value obtained by adding the shortest distance P2 from the first circuit portion 3a to the second circuit portion 3b on the main surface 11 and the second width W2 is defined as a circuit interval P. The circuit interval P may be 50 μm or less, 40 μm or less, or 30 μm or less.

[0043] The second width W2 may be 30 μm or less, or 20 μm or less. In this way, the interval between the adjacent circuits 3 on the main surface 11 becomes sufficiently large, so that migration does not occur on the surface (main surface 11) of the base film 1. The second width W2 may be 5 μm or more. In this way, the adhesion between the circuit 3 and the base film 1 is maintained, and peeling of the circuit 3 from the base film 1 is suppressed.

[0044] <Method for manufacturing printed wiring board> Next, a method for manufacturing the printed wiring board 100 according to the first embodiment will be described. The printed wiring board 100 according to the first embodiment is basically manufactured using a semi-additive process. FIG. 3 is a flowchart showing the method for manufacturing the printed wiring board 100 according to the first embodiment. FIG. 4 to FIG. 10 are cross-sectional views showing respective steps of the method for manufacturing the printed wiring board 100 according to the first embodiment.

[0045] First, a step (S1) of preparing a base film 1 is performed. In this step (S1), as shown in FIG. 4, a substrate 10 including the base film 1 is prepared. The substrate 10 is, for example, a substrate for MSAP (Modified Semi Additive Process). Specifically, the substrate 10 includes the base film 1 and a seed layer 21. The seed layer 21 is provided on main surfaces 11 and 12 of the base film 1.

[0046] A hole may be formed in the prepared base film 1. Specifically, a hole penetrating the base film 1 so as to reach from the main surface 11 to the main surface 12 is formed. The hole can be formed by irradiating the base film 1 with a laser beam. After forming the hole, desmear treatment is performed to remove smear.

[0047] Next, a step (S2) of forming an electroless plating layer 33 is performed. In this step (S2), as shown in FIG. 5, the electroless plating layer 33 is formed by electroless plating. Specifically, the electroless plating layer 33 is formed over the seed layer 21.

[0048] Next, a step (S3) is performed to form the resist pattern 5. In this step (S3), as shown in Figure 6, the resist pattern 5 is formed on the electroless plating layer 33. Specifically, first, a resist, for example, in the form of a film, is attached to the electroless plating layer 33. Secondly, exposure and development are performed on the resist placed on the electroless plating layer 33. As a result, the remaining resist that was not removed becomes the resist pattern 5. The removed resist portions become openings 5h. After forming the resist pattern 5, a plasma descam treatment may be performed to prevent wiring defects.

[0049] The opening 5h is a region where the resist pattern 5 is not formed. In the step of forming the electroless plating layer 33 (S2) described above, if palladium is applied to the electroless plating layer 33 as a catalyst, the electroless plating layer 33 is exposed through the opening 5h.

[0050] Next, a step (S4) is performed to form an etching-promoting section 32. In this step (S4), as shown in Figure 7, an etching-promoting section 32 is formed on the electroless plating layer 33 exposed from the opening 5h. Specifically, palladium (Pd), a noble metal, is applied to the surface of the electroless plating layer 33 as a catalyst. Alternatively, a plating layer of zinc (Zn) or tin (Sn), a base metal (specifically, a metal whose standard electrode potential is lower than that of copper), is formed on the surface of the electroless plating layer 33. In this way, the interface between the electroless plating layer 33 and the electroplating layer 31 formed on the electroless plating layer 33 is formed as an etching-promoting section 32. By forming the etching-promoting section 32 in this way, etching proceeds more quickly in the step (S7) of etching the underlying layer.

[0051] In addition, if, in the step of preparing the base film 1 (S1), holes are not formed in the base film 1 and the step of forming the electroless plating layer 33 (S2) is not performed, palladium (Pd) may be directly applied to the seed layer 21 as a catalyst, or a plating layer may be directly formed on the seed layer 21 as an etching acceleration section 32.

[0052] Furthermore, the step of forming the etching acceleration section 32 (S4) may be included in the step of forming the resist pattern 5 (S3). Specifically, when performing the descam treatment after developing the resist pattern 5, the plasma output time may be adjusted to leave the scum as organic matter on the electroless plating layer 33. Alternatively, the scum may be left as organic matter on the electroless plating layer 33 by not performing the descam treatment after developing the resist pattern 5. In this way, the interface between the electroless plating layer 33 and the electroplating layer 31 formed on the electroless plating layer 33 is formed as the etching acceleration section 32. Since voids are formed inside the etching acceleration section 32 formed in this way, etching proceeds faster in the step of etching the underlying layer (S7).

[0053] Next, a step (S5) is performed to form the electroplating layer 31. In this step (S5), as shown in Figure 8, the electroplating layer 31 is formed on the etching acceleration portion 32 exposed from the opening 5h. The electroplating layer 31 is formed by electroplating. Specifically, the electroplating layer 31 is formed by passing an electric current through a base layer consisting of a seed layer 21 and an electroless plating layer 33 in a plating solution containing copper.

[0054] This step (S5) may include a step (S4) for forming an etching-promoting section 32. Specifically, before energizing the seed layer 21 and the electroless plating layer 33 to perform electroplating, the substrate layer is immersed in a solution containing a component used as a plating inhibitor (for example, a PEG (polyethylene glycol) solution), thereby forming an etching-promoting section 32 at the interface between the electroless plating layer 33 and the electroplating layer 31 formed on the electroless plating layer 33. The PEG solution is, for example, sulfuric acid containing PEG. PEG may also be included in the plating solution as an additive component. By forming the etching-promoting section 32 in this way, voids are formed inside the etching-promoting section 32, so that etching proceeds faster in the step (S7) for etching the substrate layer.

[0055] Alternatively, electroplating may be performed to form an electroplated layer (the first electroplated layer 31a shown in Figure 12) to a desired height, and then the electroplated layer may be immersed in a PEG solution. After that, electroplating is performed again to form a second electroplated layer 31b on top of the first electroplated layer 31a. As a result, the interface between the first electroplated layer 31a and the second electroplated layer 31b is formed as an etching-promoting portion 32.

[0056] Next, a step (S6) is performed to remove the resist pattern 5. In this step (S6), as shown in Figure 9, the resist pattern 5 is removed from above the etching acceleration section 32. As a result, the electroless plating layer 33 is exposed between the two adjacent electroplating layers 31.

[0057] Next, a step (S7) is performed to etch the underlying layer. In this step (S7), as shown in Figure 10, the etching acceleration section 32, the electroless plating layer 33, and the seed layer 21 are removed by etching. Specifically, an etching solution in which etching proceeds isotropically by reaction rate control is used to remove the underlying layer exposed between two adjacent electroplating layers 31. For example, a sulfuric acid-hydrogen peroxide aqueous solution may be used as the etching solution.

[0058] In this way, etching proceeds relatively quickly in the lower half of the circuit 3 where the etching acceleration section 32 is formed. Specifically, in the z direction, a recess is formed on the side surface of the circuit 3 centered on the etching acceleration section 32. From a different perspective, a narrow region A3 with the smallest width in the x direction is formed in the etching acceleration section 32. Because the etching acceleration section 32 is located in the lower half of the circuit 3, the second width W2 of the lower surface region A2 is less than or equal to the first width W1 of the upper surface region A1. As a result, as shown in Figure 2, a circuit 3 is formed in which the third width W3 is smaller than both the first width W1 and the second width W2, and the second width W2 is less than or equal to the first width W1.

[0059] Next, a step (S8) is performed to form a protective layer 4. In this step (S8), a protective layer 4 is formed to protect the circuit 3. The protective layer 4 may be, for example, a coverlay, a solder resist, or a bonding sheet. In this way, the printed circuit board 100 shown in Figures 1 and 2 can be obtained.

[0060] <Effects and Effects> The printed circuit board 100 according to this disclosure comprises a base film 1 and a circuit 3. The base film 1 has a main surface 11. The circuit 3 is provided on the main surface 11. The direction perpendicular to the main surface 11 is defined as the z direction. The direction perpendicular to the direction in which the circuit 3 extends (y direction), as viewed from the z direction, is defined as the x direction. The circuit 3 includes an upper surface region A1, a lower surface region A2, and a narrow region A3. The lower surface region A2 is in contact with the main surface 11. The upper surface region A1 is located opposite the lower surface region A2 in the z direction. The narrow region A3 is located between the upper surface region A1 and the lower surface region A2 in the z direction. In the x direction, the first width W1 of the upper surface region A1 is greater than or equal to the second width W2 of the lower surface region A2. The second width W2 is greater than the third width W3 of the narrow region A3.

[0061] In this way, the adhesion of the protective layer 4 on the printed circuit board 100 is maintained, and short-circuit defects do not occur.

[0062] According to the printed circuit board 100 described above, in the z-direction, the narrow region A3 is positioned in the lower half of the circuit 3.

[0063] In this way, a printed circuit board 100 can be obtained in which the second width W2 of the lower region A2 is less than or equal to the first width W1 of the upper region A1.

[0064] According to the printed circuit board 100 described above, the thickness T of the base film 1 in the z direction is 100 μm or less.

[0065] In this way, a printed circuit board 100 can be obtained in which the protective layer 4 is prevented from peeling off while keeping the thickness of the base film 1 thin.

[0066] According to the printed circuit board 100 described above, the height T1 of the circuit 3 in the z direction is 5 μm or more and 40 μm or less.

[0067] In this way, the adhesion of the protective layer 4 on the printed circuit board 100 is maintained.

[0068] According to the printed circuit board 100 described above, the circuit 3 includes a seed layer 21 that is in contact with the main surface 11. In this way, a printed circuit board 100 can be obtained using a semi-additive manufacturing method, in which the adhesion of the protective layer 4 is maintained and short-circuit defects do not occur.

[0069] According to the printed circuit board 100 described above, the circuit 3 includes a first circuit section 3a and a second circuit section 3b. The second circuit section 3b is spaced apart from the first circuit section 3a in the x-direction.

[0070] In this way, the circuit 3 on the printed circuit board 100 is composed of multiple circuit sections.

[0071] According to the printed circuit board 100 described above, the first width W1 is 5 μm or more and 40 μm or less. The value obtained by adding the shortest distance P2 from the first circuit section 3a to the second circuit section 3b on the main surface 11 and the second width W2 (circuit spacing P) is 50 μm or less.

[0072] In this way, a printed circuit board 100 equipped with miniaturized circuits 3 can be obtained.

[0073] According to the printed circuit board 100 described above, the shortest distance P2 from the first circuit section 3a to the second circuit section 3b on the main surface 11 is greater than the shortest distance P1 from the upper half of the first circuit section 3a to the upper half of the second circuit section 3b.

[0074] In this way, the spacing between adjacent circuits 3 on the main surface 11 increases, preventing migration from occurring on the surface (main surface 11) of the base film 1. As a result, a printed circuit board 100 can be obtained that is free from short-circuit defects.

[0075] According to the printed circuit board 100 described above, the shortest distance P2 from the first circuit section 3a to the second circuit section 3b on the main surface 11 is 5 μm or more.

[0076] In this way, the spacing between adjacent circuits 3 on the main surface 11 is sufficiently large, so migration does not occur on the surface (main surface 11) of the base film 1.

[0077] According to the printed circuit board 100 described above, the difference L1 between the second width W2 and the third width W3 is 0.2 μm or more and 10 μm or less.

[0078] In this way, the adhesion of the protective layer 4 on the printed circuit board 100 is maintained.

[0079] (Embodiment 2) <Configuration of Printed Wiring Board> Figure 11 is a cross-sectional view of the printed wiring board 100 according to Embodiment 2. Figure 11 corresponds to Figure 1. Figure 12 is a partially enlarged cross-sectional view of region XII in Figure 11. Figure 12 corresponds to Figure 2. The printed wiring board 100 shown in Figures 11 and 12 basically has the same configuration as the printed wiring board 100 shown in Figures 1 and 2 and can obtain the same effects, but the height T2 from the main surface 11 to the narrow region A3 in the z direction is different.

[0080] Specifically, circuit 3 includes a seed layer 21, a first electroplating layer 31a, a second electroplating layer 31b, an etching acceleration section 32, and an electroless plating layer 33. In this embodiment 2, circuit 3 is formed by stacking the seed layer 21, the electroless plating layer 33, the first electroplating layer 31a, the etching acceleration section 32, and the second electroplating layer 31b in that order.

[0081] When forming the electroplated layer 31 by electroplating, by applying current to the underlayer for a certain period of time at a current density lower than that used when forming the first electroplated layer 31a and the second electroplated layer 31b, an etching-promoting portion 32 having a different structure from the first electroplated layer 31a and the second electroplated layer 31b is formed. By forming the etching-promoting portion 32 in this way, etching in the etching-promoting portion 32 proceeds more quickly in the etching step (S7) of the underlayer.

[0082] In this way, by adjusting the position of the carving-promoting portion 32 in the z-direction, the narrow region A3 can be set to a desired height T2. By forming the carving-promoting portion 32 with a low current density, the carving-promoting portion 32 may be formed as a layer having an observable thickness in the z-direction.

[0083] After forming the first electroplating layer 31a, the etching acceleration portion 32 may be formed as the interface between the first electroplating layer 31a and the second electroplating layer 31b by forming the second electroplating layer 31b after a certain period of time has elapsed without passing an electric current through the underlying layer (no current flow).

[0084] <Method for Manufacturing Printed Wiring Boards> Next, a method for manufacturing the printed wiring board 100 according to Embodiment 2 will be described. Figure 13 is a flowchart showing the method for manufacturing the printed wiring board 100 according to Embodiment 2. Figures 14 to 16 are cross-sectional views showing one step in the method for manufacturing the printed wiring board 100 according to Embodiment 2.

[0085] First, the same steps as those shown in Figures 4 to 6 in the manufacturing method of the printed circuit board 100 according to Embodiment 1 are carried out. That is, first, the step of preparing the base film 1 (S11) is carried out. In this step (S11), a substrate 10 including the base film 1 is prepared as shown in Figure 4.

[0086] Next, a step (S12) is performed to form an electroless plating layer 33. In this step (S12), as shown in Figure 5, an electroless plating layer 33 is formed by electroless plating. Specifically, the electroless plating layer 33 is formed on the seed layer 21.

[0087] Next, a step (S13) is performed to form the resist pattern 5. In this step (S13), as shown in Figure 6, the resist pattern 5 is formed on the electroless plating layer 33.

[0088] Next, a step (S14) is performed to form the first electroplating layer 31a. In this step (S14), as shown in Figure 14, the first electroplating layer 31a is formed on the electroless plating layer 33 exposed from the opening 5h. Specifically, the current density is 0.5 A / dm ２ 10.0A / dm or more ２ In the following steps, the first electrolytic plating layer 31a is formed by applying current to the seed layer 21 and the electroless plating layer 33 that constitute the base layer.

[0089] Next, the process of forming the etching acceleration section 32 (S15) is carried out. In this process (S15), as shown in Figure 15, the etching acceleration section 32 is formed on the first electroplating layer 31a. Specifically, the etching acceleration section 32 is formed by applying current to the seed layer 21 and the electroless plating layer 33 constituting the base layer at a current density lower than that used in the process of forming the first electroplating layer 31a (S14). For example, a current density of 0.01 A / dm ２ 0.1A / dm or more ２ In the following steps, the first electrolytic plating layer 31a is formed by passing an electric current through the seed layer 21 and the electroless plating layer 33 that constitute the base layer. In this way, as shown in Figure 15, the etching acceleration section 32 is formed as a layer having an observable thickness in the z direction.

[0090] The next step (S16) may be performed after a certain period of time has elapsed without applying current to the underlying layer (no power). In this way, the etching acceleration section 32 is formed as the interface between the first electroplating layer 31a and the second electroplating layer 31b.

[0091] Next, a step (S16) is performed to form the second electroplating layer 31b. In this step (S16), as shown in Figure 16, the second electroplating layer 31b is formed on the etching acceleration section 32. Specifically, the current density is 0.5 A / dm ２ 10.0A / dm or more ２ In the following steps, the second electrolytic plating layer 31b is formed by applying current to the seed layer 21 and the electroless plating layer 33 that constitute the base layer.

[0092] Next, the same steps as those shown in Figures 9 and 10 in the manufacturing method of the printed circuit board 100 according to Embodiment 1 are carried out. Specifically, the step of removing the resist pattern 5 (S17) is carried out. In this step (S17), the resist pattern 5 is removed from on top of the electroless plating layer 33. As a result, the electroless plating layer 33 is exposed between two adjacent electroplating layers 31.

[0093] Next, the process of etching the underlying layer (S18) is performed. In this process (S18), the electroless plating layer 33 and the seed layer 21 are removed by etching. In this second embodiment, the position of the etching acceleration unit 32 in the z direction is higher than the position of the etching acceleration unit 32 in the z direction in the first embodiment. By adjusting the position of the etching acceleration unit 32 in the z direction in this way, the narrow region A3 can be set to a desired height T2.

[0094] Next, a step (S19) is performed to form a protective layer 4. In this step (S19), a protective layer 4 is formed to protect the circuit 3. The protective layer 4 may be, for example, a coverlay, a solder resist, or a bonding sheet. In this way, the printed circuit board 100 shown in Figures 11 and 12 can be obtained.

[0095] To verify the effectiveness of the printed circuit board 100 as described above, the frequency of peeling and migration of the protective layer 4 of the printed circuit board 100 was evaluated.

[0096] (Sample Preparation) The test subjects are printed circuit boards 100 corresponding to Sample 1 to Sample 17. Printed circuit boards 100 corresponding to Sample 1 to Sample 4 are comparative examples. Printed circuit boards 100 corresponding to Sample 5 to Sample 17 are examples. The manufacturing conditions for the printed circuit boards 100 are shown in Tables 1 and 2. In Table 1, from left to right, the thickness T of the base film 1, the thickness of the seed layer 21, the thickness of the electroless plating layer 33, the thickness of the resist pattern 5, the presence or absence of descam treatment after developing the resist pattern 5, and the plasma output time are shown. In Table 2, from left to right, the presence or absence of degreasing treatment, the presence or absence of immersion in PEG solution and the immersion time before performing the step of forming the electroplating layer 31 (S5), the thickness of the electroplating layer 31, the etching solution used in the step of etching the underlayer (S7), and the circuit spacing P (the sum of the shortest distance P2 from the first circuit section 3a to the second circuit section 3b on the main surface 11 and the second width W2) are shown.

[0097]

[0098]

[0099] As shown in Table 1, the step of forming the electroless plating layer 33 (S2) was not performed on the printed circuit board 100 for Sample 1. For the printed circuit boards 100 from Sample 1 to Sample 17, a descam treatment was performed with a plasma output of 500W after developing the resist pattern 5.

[0100] In the printed circuit board 100 of sample 10, a first electroplating layer 31a was formed to a thickness of 9 μm. Then, by applying current to the seed layer 21 and the electroless plating layer 33 constituting the base layer at a current density lower than that used in the process of forming the first electroplating layer 31a (S14), an etching acceleration section 32 with a thickness of 1 μm was formed. After forming the etching acceleration section 32, a second electroplating layer 31b with a thickness of 3 μm was formed. In other words, the thickness of the electroplating layer 31 is 13 μm.

[0101] In the printed circuit boards 100 for Sample 1 and Sample 3, the etching acceleration section 32 was not formed in circuit 3. Specifically, the output time for the descam processing was set to 120 seconds.

[0102] On the other hand, in the printed circuit boards 100 relating to Sample 2 and Samples 4 through 17, an etching acceleration section 32 was formed in the circuit 3. Specifically, in the printed circuit boards 100 relating to Sample 2, Samples 4 through 9, and Samples 11 through 16, the output time for the descam process was set to 40 seconds. In the printed circuit board 100 relating to Sample 17, the output time for the descam process was set to 80 seconds. In the printed circuit board 100 relating to Sample 10, the output time for the descam process was set to 120 seconds. As described above, after forming the first electroplating layer 31a, an etching acceleration section 32 with a thickness of 1 μm is formed by applying current to the seed layer 21 and the electroless plating layer 33 constituting the base layer at a current density lower than the current density in the process of forming the first electroplating layer 31a (S14).

[0103] As shown in Table 2, in the printed circuit boards 100 of Sample 1, Sample 3, and Samples 5 through 17, the etching solution used in the etching step (S7) of the underlying layer was a sulfuric acid-hydrogen peroxide aqueous solution. On the other hand, in the printed circuit boards 100 of Sample 2 and Sample 4, the etching solution used in the etching step (S7) of the underlying layer was a ferric chloride aqueous solution.

[0104] (Evaluation Results) Table 3 shows the shape of circuit 3 of the printed circuit board 100 from sample 1 to sample 17 that were manufactured. Table 4 shows the evaluation results of the printed circuit board 100 from sample 1 to sample 17 (frequency of peeling of protective layer 4 and frequency of migration). In Table 3, from left to right, the first width W1, second width W2, third width W3, difference L1, shortest distance P2, height T1 of circuit 3, and position of narrow region A3 (height T2 from main surface 11 to narrow region A3 in the z direction). In Table 4, from left to right, the frequency of peeling of protective layer 4 and the frequency of migration are shown.

[0105]

[0106]

[0107] In Table 4, if the peeling rate of protective layer 4 is 1 percent or less, the peeling frequency of protective layer 4 is evaluated as A. If the peeling rate of protective layer 4 is greater than 1 percent but 5 percent or less, the peeling frequency of protective layer 4 is evaluated as B. If the peeling rate of protective layer 4 is greater than 5 percent but 10 percent or less, the peeling frequency of protective layer 4 is evaluated as C. If the peeling rate of protective layer 4 is greater than 10 percent, the peeling frequency of protective layer 4 is evaluated as D.

[0108] In Table 4, if the migration rate is 5 percent or less, the migration frequency is rated as A. If the migration rate is between 5 percent and 20 percent, the migration frequency is rated as B. If the migration rate is greater than 20 percent, the migration frequency is rated as C.

[0109] In Sample 1, since the chipping acceleration section 32 is not formed in the circuit 3, the third width W3 is the same as the first width W1 and the second width W2. Therefore, the frequency of peeling of the protective layer 4 was D.

[0110] In sample 2, the first width W1 is smaller than the second width W2. Therefore, the protective layer 4 is prone to peeling, and the frequency of peeling of the protective layer 4 was D. On the other hand, since the shortest distance P2 is 5 μm or more, the frequency of migration was B.

[0111] In sample 3, since the chipping acceleration section 32 is not formed in circuit 3, the third width W3 is the same as the first width W1 and the second width W2. Therefore, the frequency of peeling of the protective layer 4 was D.

[0112] In sample 4, the first width W1 is smaller than the second width W2. Therefore, the protective layer 4 is prone to peeling, and the frequency of peeling of the protective layer 4 was D. Also, since the shortest distance P2 is less than 5 μm, the frequency of migration was C.

[0113] In sample 5, the first width W1 is greater than the second width W2. Therefore, the protective layer 4 is less likely to peel off, and the frequency of peeling of the protective layer 4 was B. Also, since the shortest distance P2 is 5 μm or more, the frequency of migration was B.

[0114] The shortest distance P2 in sample 6 was greater than the shortest distance P2 in sample 5, and the migration frequency was A.

[0115] The difference L1 in sample 7 was greater than the difference L1 in sample 5, and the frequency of peeling of the protective layer 4 was A.

[0116] The shortest distance P2 in sample 8 is greater than the shortest distance P2 in sample 5, and the difference L1 in sample 8 is greater than the difference L1 in sample 5. Therefore, the frequency of peeling of the protective layer 4 was A, and the frequency of migration was also A.

[0117] The shortest distance P2 in sample 9 is greater than the shortest distance P2 in sample 5, and the difference L1 in sample 9 is greater than the difference L1 in sample 5. Therefore, the frequency of peeling of the protective layer 4 was A, and the frequency of migration was also A.

[0118] In sample 10, the position of the narrow region A3 (height T2 from the main surface 11 to the narrow region A3 in the z direction) is more than half of the circuit height T1. Therefore, when the printed circuit board 100 is bent, the distance between circuits 3 increases, and the force with which the protective layer 4 catches on the narrow region A3 weakens. As a result, the frequency of peeling of the protective layer 4 was B.

[0119] In sample 11, the thickness T in the z-direction of the base film 1 exceeds 100 μm. As a result, the base film 1 becomes less prone to bending, and the protective layer 4 becomes less likely to peel off. However, the total thickness of the product to which the base film 1 is applied becomes thick, making it difficult to apply the base film 1 to a narrow space.

[0120] In sample 12, the circuit height T1 exceeded 40 μm. As a result, the seed layer 21 was not adequately removed, and the migration frequency was B.

[0121] The circuit height T1 in sample 13 is less than 5 μm. Therefore, the small circuit height T1 may cause the circuit to tip over.

[0122] In sample 14, the shortest distance P2 from the first circuit section 3a to the second circuit section 3b on the main surface 11 is the same as the shortest distance P1 from the upper half of the first circuit section 3a to the upper half of the second circuit section 3b. Therefore, the adhesion of the protective layer 4 is reduced. Consequently, the frequency of peeling of the protective layer 4 was B.

[0123] In sample 15, the circuit spacing P (the sum of the shortest distance P2 from the first circuit section 3a to the second circuit section 3b on the main surface 11 and the second width W2) exceeds 50 μm. As a result, the contact area between the protective layer 4 and the circuit 3 becomes small, and the adhesion of the protective layer 4 is reduced. Consequently, the frequency of peeling of the protective layer 4 was B.

[0124] The circuit spacing P in sample 16 is greater than the circuit spacing P in sample 5. Therefore, the frequency of migration was A.

[0125] The difference L1 in sample 17 was less than 0.2 μm. As a result, the adhesion of the protective layer 4 was reduced, and the frequency of peeling of the protective layer 4 was C.

[0126] In other words, in comparative examples Samples 1 to 4, the frequency of peeling of protective layer 4 was D, or the frequency of migration was C.

[0127] On the other hand, in samples 5 to 17, an etching acceleration section 32 was formed on the circuit 3, and the etching solution used in the etching process (S7) for the underlying layer was a sulfuric acid-hydrogen peroxide aqueous solution. Therefore, the frequency of peeling of the protective layer 4 was one of A, B, or C, and the frequency of migration was either A or B.

[0128] It should be understood that at least one configuration or feature described in each embodiment and example can be combined with other embodiments and examples, or modified in various ways.

[0129] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The basic scope of this disclosure is indicated by the claims rather than the embodiments described above, and all modifications within the meaning and scope of the claims are intended to be included.

[0130] 1 Base film, 3 Circuit, 3a First circuit section, 3b Second circuit section, 4 Protective layer, 5 Resist pattern, 5h Opening, 10 Substrate, 11, 12 Main surface, 21 Seed layer, 31 Electroplating layer, 31a First electroplating layer, 31b Second electroplating layer, 32 Etching acceleration section, 33 Electroless plating layer, 100 Printed wiring board, A1 Top area, A2 Bottom area, A3 Narrow area, L1 Difference, P Circuit spacing, P1, P2 Shortest distance, W1 First width, W2 Second width, W3 Third width.

Claims

1. A printed circuit board comprising a base film having a main surface and a circuit provided on the main surface, wherein the direction perpendicular to the main surface is the z-direction, and the direction perpendicular to the direction in which the circuit extends when viewed from the z-direction is the x-direction, the circuit includes a lower surface region in contact with the main surface, an upper surface region located opposite the lower surface region in the z-direction, and a narrow region located between the upper surface region and the lower surface region in the z-direction, wherein the first width of the upper surface region in the x-direction is greater than or equal to the second width of the lower surface region, and the second width is greater than the third width of the narrow region.

2. The printed circuit board according to claim 1, wherein in the z-direction, the narrow region is located in the lower half of the circuit.

3. The printed circuit board according to claim 1 or claim 2, wherein the thickness of the base film in the z-direction is 100 μm or less.

4. The printed circuit board according to any one of claims 1 to 3, wherein the height of the circuit in the z-direction is 5 μm or more and 40 μm or less.

5. The printed circuit board according to any one of claims 1 to 4, wherein the circuit includes a seed layer in contact with the main surface.

6. The printed circuit board according to any one of claims 1 to 5, wherein the circuit includes a first circuit section and a second circuit section arranged spaced apart from the first circuit section in the x-direction.

7. The printed circuit board according to claim 6, wherein the first width is 5 μm or more and 40 μm or less, and the sum of the shortest distance from the first circuit portion to the second circuit portion on the main surface and the second width is 50 μm or less.

8. The printed circuit board according to claim 6 or claim 7, wherein the shortest distance from the first circuit section to the second circuit section on the main surface is greater than the shortest distance from the upper half of the first circuit section to the upper half of the second circuit section.

9. The printed circuit board according to claim 8, wherein the shortest distance from the first circuit portion to the second circuit portion on the main surface is 5 μm or more.

10. The printed circuit board according to any one of claims 1 to 9, wherein the difference between the second width and the third width is 0.2 μm or more and 10 μm or less.

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