Semiconductor device

Abstract

The purpose of the present invention is to provide a semiconductor device with reduced failures caused by neutron radiation. The semiconductor device includes a semiconductor chip and a covering material that covers the semiconductor chip. The covering material contains barium sulfate and / or boron carbide as a neutron attenuation material. The neutron attenuation material attenuates neutron radiation having an energy of 1.0 eV or more and 1.0×109 eV or less. The content by volume C of the neutron attenuation material in the covering material satisfies the following formula: C ≥ –4lnX / μπE×1 / t, where X is a predetermined shielding ratio, μ is an attenuation coefficient, E is the effective energy of neutron radiation, and t is the thickness of the covering material containing the neutron attenuation material.

Description

Semiconductor device

[0001] The present disclosure relates to a semiconductor device.

[0002] A power module, which is a semiconductor device for controlling electric power, is configured by, for example, a semiconductor chip, an insulating substrate, a base plate, wires, terminals, solder, and a sealing material covering these components.

[0003] Japanese Unexamined Patent Application Publication No. 2022-37739

[0004] In the semiconductor device disclosed in Patent Document 1, the sealing member that seals the semiconductor chip contains a thermosetting resin and a filler.

[0005] However, cosmic rays, particularly neutron rays, pass through such a sealing member and penetrate into the interior of the semiconductor device. The neutron rays that have penetrated into the interior of the semiconductor device destroy the semiconductor chip and cause failure of the semiconductor device.

[0006] The present disclosure aims to solve the above problem and provide a semiconductor device in which failures caused by neutron rays are reduced.

[0007] A semiconductor device according to the present disclosure includes a semiconductor chip and a sealing material covering the semiconductor chip. The sealing material contains at least one of barium sulfate and boron carbide as a neutron attenuating material. The neutron attenuating material has an energy of 1.0 eV or more and 1.0×10 ９ eV or less and attenuates neutron rays. Where X is a predetermined shielding rate, μ is an attenuation coefficient, E is the effective energy of neutron rays, and t is the thickness of the sealing material containing the neutron attenuating material, C, which is the volume ratio content of the neutron attenuating material in the sealing material, satisfies the following formula: C≧−4lnX / μπE×1 / t.

[0008] According to the present disclosure, a semiconductor device with reduced failures caused by neutron rays is provided.

[0009] The objects, features, aspects, and advantages of the present disclosure will become more apparent from the following detailed description and the accompanying drawings.

[0010] FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment. FIG. 2 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment.

[0011] <Embodiment 1> Figure 1 is a cross-sectional view showing the configuration of a semiconductor device in Embodiment 1. The semiconductor device in Embodiment 1 is a semiconductor device for power control applications, and is a so-called power module. The semiconductor device includes a base plate 1, an insulating substrate 2, a semiconductor chip 3, a case 4, terminals 5, metal wires 6, and a sealing material 7.

[0012] The base plate 1 is, for example, a plate made of a metal such as copper or aluminum, or a plate made of a ceramic having high thermal conductivity, such as an AlSiC composite material. The base plate 1 has the function of transferring heat generated by electronic components such as semiconductor chips 3 to the outside.

[0013] The insulating substrate 2 is provided on the base plate 1. Although not shown in the figures, the insulating substrate 2 includes an insulating layer, a surface conductive layer, and a back heat dissipation layer. The insulating layer is, for example, a plate made of ceramic. The surface conductive layer and the back heat dissipation layer are made of a conductive material such as metal. The surface conductive layer is provided on the upper surface of the insulating layer and forms a circuit pattern. The back heat dissipation layer is provided on the lower surface of the insulating layer and is bonded to the base plate 1 via a bonding material (not shown).

[0014] The semiconductor chip 3 is bonded to the surface conductive layer of the insulating substrate 2 via a bonding material (not shown). The bonding material is a conductive material such as solder. The semiconductor chip 3 is formed of a semiconductor material such as Si. Preferably, the semiconductor chip 3 is formed of a wide-bandgap semiconductor such as SiC or GaN. The semiconductor chip 3 is, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), or a Schottky barrier diode. Alternatively, the semiconductor chip 3 may be an RC-IGBT (Reverse-Conducting IGBT) in which the IGBT and freewheeling diode are formed on a single chip.

[0015] Case 4 is fixed to the base plate 1 with adhesive 8. Case 4 has a frame in plan view. Case 4 houses the insulating substrate 2 and semiconductor chip 3 inside its frame. Case 4 is made of a thermoplastic resin such as PPS (Polyphenylene Sulfide).

[0016] Terminal 5 is electrically connected to the semiconductor chip 3. Here, one end of terminal 5 is bonded to the surface conductive layer of the insulating substrate 2. The other end of terminal 5 is exposed from the case 4, and terminal 5 is configured to be connectable to an external circuit (not shown) provided outside the semiconductor device. Terminal 5 is, for example, a metal plate such as copper that has been processed into a predetermined shape.

[0017] The metal wire 6 is bonded to the semiconductor chip 3 and the surface conductive layer of the insulating substrate 2. Although not shown in the diagram, the metal wire 6 may also be bonded to the semiconductor chip 3 and the terminal 5, or to the surface conductive layer and the terminal 5. The terminal 5, the surface conductive layer of the insulating substrate 2, and the metal wire 6 constitute the internal wiring of the semiconductor device.

[0018] The sealing material 7 is filled into the space inside the case 4. The sealing material 7 seals the surface of the base plate 1, the surface of the insulating substrate 2, the semiconductor chip 3, part of the terminals 5, and the metal wires 6. The sealing material 7 is, for example, silicone gel, epoxy resin, etc.

[0019] Case 4 and encapsulant 7 constitute the outer covering material that encloses the semiconductor chip 3. The outer covering material may contain only one of barium sulfate and boron carbide as a neutron attenuator, or it may contain both. In other words, the outer covering material contains at least one of barium sulfate and boron carbide as a neutron attenuator. The neutron attenuator provides 1.0 eV or more and 1.0 × 10⁻¹⁶ ９ It has the function of attenuating neutron beams with energies below eV.

[0020] Both the case 4 and the sealing material 7 that constitute the outer covering may contain a neutron attenuator, or only one of the case 4 and the sealing material 7 that constitute the outer covering may contain a neutron attenuator. In other words, the outer covering that contains a neutron attenuator is at least one of the case 4 and the sealing material 7.

[0021] In order to have the above function, preferably, C, which is the volume ratio of the neutron attenuating material in the outer covering material, satisfies the following formula (1).

[0022] C ≥ -4lnX / μπE × 1 / t ... (1) In equation (1), X is a predetermined shielding coefficient, μ is the attenuation coefficient, E is the effective energy of the neutron beam, and t is the thickness of the sheath material including the neutron attenuator.

[0023] Neutron beams incident on the semiconductor device are attenuated by the neutron attenuator contained in the outer casing. Because the neutron energy reaching the semiconductor chip 3 is attenuated, the failure rate of the semiconductor device is reduced.

[0024] In summary, the semiconductor device in Embodiment 1 includes a semiconductor chip 3 and an outer covering material that covers the semiconductor chip 3. The outer covering material contains at least one of barium sulfate and boron carbide as a neutron attenuator. The neutron attenuator has a neutron attenuation of 1.0 eV or more and 1.0 × 10⁻¹⁴ ９ The device attenuates neutron beams with energies of eV or less. When the predetermined shielding ratio is X, the attenuation coefficient is μ, the effective energy of the neutron beam is E, and the thickness of the outer sheath containing the neutron attenuator is t, the volume ratio of the neutron attenuator in the outer sheath, C, satisfies the following equation, i.e., C ≥ -4lnX / μπE × 1 / t.

[0025] In such a semiconductor device, the encapsulating material 7 and / or case 4 covering the semiconductor chip 3 contains a neutron attenuator. This reduces the amount of neutron radiation reaching the semiconductor chip 3. As a result, the semiconductor device's resistance to neutron radiation is improved without being constrained by the internal configuration, i.e., the electrical characteristics, of the semiconductor chip 3.

[0026] As described above, the semiconductor device of Embodiment 1 has both a case 4 and a sealing material 7 as outer covering materials. However, even if the semiconductor device has only a molding resin, i.e., only the sealing material 7, as outer covering material, such as in a configuration in which the semiconductor chip 3 is sealed by the transfer molding method, the same effects as described above can be obtained by using the same configuration as described above.

[0027] <Embodiment 2> Figure 2 is a cross-sectional view showing the configuration of a semiconductor device in Embodiment 2. The outer covering material in Embodiment 2 includes a first encapsulating material 7A that covers the semiconductor chip 3, and a second encapsulating material 7B that further covers the first encapsulating material 7A. The first encapsulating material 7A is a potting resin.

[0028] The neutron attenuator, similar to that in Embodiment 1, is contained only in the first encapsulant 7A and has the same function as in Embodiment 1. The volume ratio of the neutron attenuator in the first encapsulant 7A preferably satisfies the above formula (1). In this case, t in formula (1) is the thickness of the first encapsulant 7A containing the neutron attenuator.

[0029] Since the neutron attenuator is contained only in the first encapsulating material 7A surrounding the semiconductor chip 3, the neutron beam is attenuated over a smaller area. Therefore, failures of semiconductor devices are reduced with a less expensive configuration.

[0030] Although this disclosure has been described in detail, the above description is illustrative and not limiting in all respects. It is understood that countless variations not illustrated are conceivable.

[0031] This disclosure allows for the free combination of each embodiment, and enables the modification or omission of each embodiment as appropriate.

[0032] 1. Base plate, 2. Insulating substrate, 3. Semiconductor chip, 4. Case, 5. Terminals, 6. Metal wire, 7. Encapsulation material, 7A. First enclosure material, 7B. Second enclosure material, 8. Adhesive.

Claims

1. The device comprises a semiconductor chip and an outer covering material covering the semiconductor chip, wherein the outer covering material contains at least one of barium sulfate and boron carbide as a neutron attenuator, and the neutron attenuator has an emission of 1.0 eV or more and 1.0 × 10⁻¹⁰ ９ A semiconductor device that attenuates neutron beams having an energy of eV or less, and, when a predetermined shielding ratio is X, the attenuation coefficient is μ, the effective energy of the neutron beams is E, and the thickness of the outer covering material containing the neutron attenuating material is t, the volume ratio of the neutron attenuating material C in the outer covering material satisfies the following formula: C ≥ -4lnX / μπE × 1 / t.

2. The device comprises a semiconductor chip and an outer covering material covering the semiconductor chip, wherein the outer covering material contains at least one of barium sulfate and boron carbide as a neutron attenuator, and the neutron attenuator has an emission of 1.0 eV or more and 1.0 × 10⁻¹⁰ ９ A semiconductor device that attenuates neutron beams with energies below eV.

3. The semiconductor device according to claim 1 or 2, wherein the outer covering material including the neutron attenuator is at least one of a case for housing the semiconductor chip and a sealing material for sealing the semiconductor chip.

4. The semiconductor device according to claim 1 or 2, wherein the outer covering material comprises a first encapsulant covering the semiconductor chip and a second encapsulant further covering the first encapsulant, and the neutron attenuator is contained only in the first encapsulant.

5. The semiconductor device according to claim 4, wherein the first sealing material includes a potting resin.

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