Semiconductor element and method for manufacturing semiconductor element

Abstract

This semiconductor element is equipped with a base semiconductor layer including a nitride semiconductor and a functional layer positioned on the base semiconductor layer. The functional layer includes an active layer and a first semiconductor layer located below or above the active layer. The first semiconductor layer includes a first portion and a second portion connected to the first portion. The first portion includes a plurality of nitride semiconductor layers stacked in a first direction and forming a first superlattice structure, and the second portion includes a plurality of nitride semiconductor layers stacked in a second direction different from the first direction and forming a second superlattice structure.

Description

Semiconductor element, method for manufacturing a semiconductor element

[0001] This disclosure relates to semiconductor devices, etc.

[0002] Patent Document 1 discloses a laser element having a superlattice structure.

[0003] Japanese Patent Publication No. 2022-29865

[0004] The semiconductor device according to this disclosure comprises a base semiconductor layer containing a nitride semiconductor and a functional layer located on the base semiconductor layer, wherein the functional layer includes an active layer and a first semiconductor layer located below or above the active layer, the first semiconductor layer includes a first portion and a second portion connected to the first portion, the first portion includes a plurality of nitride semiconductor layers stacked in a first direction to form a first superlattice structure, and the second portion includes a plurality of nitride semiconductor layers stacked in a second direction different from the first direction to form a second superlattice structure.

[0005] This is a cross-sectional view showing an example of the configuration of a semiconductor device according to this embodiment. This is a partially enlarged view of Figure 1. This is a top view showing an example of the configuration of this semiconductor device. This is a cross-sectional view showing an example of the configuration of this semiconductor device. This is a partially enlarged view of Figure 1. This is a partially enlarged view of Figure 1. This is a cross-sectional view showing an example of the configuration of this semiconductor device. This is a cross-sectional view showing an example of the configuration of this semiconductor device. This is a flowchart showing a method for manufacturing this semiconductor device. This is a cross-sectional view showing a method for manufacturing this semiconductor device. This is a perspective view showing a method for manufacturing this semiconductor device. This is a flowchart showing a method for manufacturing this semiconductor device. This is a cross-sectional view showing a method for manufacturing this semiconductor device. This is a block diagram showing a manufacturing apparatus for this semiconductor device. This is a block diagram showing a manufacturing apparatus for this semiconductor device. This is an image showing an example of the cross-sectional configuration of this semiconductor device.

[0006] Figure 1 is a cross-sectional view showing an example of the configuration of a semiconductor device according to this embodiment. Figure 2 is a partially enlarged view of Figure 1. Figure 3 is a top view showing an example of the configuration of this semiconductor device. Figure 4 is a cross-sectional view showing an example of the configuration of this semiconductor device. Figures 5 and 6 are partially enlarged views of Figure 1.

[0007] As shown in Figures 1 to 5, the semiconductor element 20 comprises a base semiconductor layer 8 containing a nitride semiconductor and a functional layer 9 located on the base semiconductor layer 8. The functional layer 9 includes an active layer 9K and a first semiconductor layer L1 located below or above the active layer 9K. The first semiconductor layer L1 includes a first portion V1 and a second portion V2 connected to the first portion V1.

[0008] As shown in Figure 2, the first portion V1 includes a plurality of nitride semiconductor layers 11 stacked in a first direction, forming a first superlattice structure T1. The first direction is, for example, the c-axis direction Dc of the nitride semiconductor. The second portion V2 includes a plurality of nitride semiconductor layers 12 stacked in a direction different from the first direction, forming a second superlattice structure T2. The second direction is, for example, a diagonal direction Df with respect to the c-axis direction Dc. The first superlattice structure T1 and the second superlattice structure T2 may be connected.

[0009] The first superlattice structure T1 and the second superlattice structure T2 only need to be connected in some parts. The first superlattice structure T1 and the second superlattice structure T2 may be connected in such a continuous manner as nitride semiconductor layers 11 and 12. The connection between the first superlattice structure T1 and the second superlattice structure T2 can be confirmed, for example, by an electron microscope image of the cross-section in the thickness direction, as shown in Figure 17. As shown in Figures 2 and 17, the first semiconductor layer L1 may include a bent portion KS located in the connection region of the nitride semiconductor layer 11 and the nitride semiconductor layer 12. By forming a bent portion KS in the connection region of the nitride semiconductor layers 11 and 12 in this way, stress is more easily relieved.

[0010] The width of the first superlattice structure T1 (size in the Da direction) may be set to be larger than the width of the second superlattice structure T2 in a cross-sectional view in the thickness direction. The widths of the top and bottom edges (size in the Da direction) of the first superlattice structure T1 and the second superlattice structure T2 may be the same or different in a cross-sectional view in the thickness direction. As shown in Figure 17, the semiconductor layer L1 containing the first superlattice structure T1 and the second superlattice structure T2 may be located above the active layer 9K. In a cross-sectional view in the thickness direction, the length of the top edge (size in the Da direction of the top layer pair) of the first superlattice structure T1 may be larger than the length of the bottom edge (size in the Da direction of the bottom layer pair) on the base semiconductor layer side. In a cross-sectional view in the thickness direction, the width of the top layer pair (size in the layer direction Ds) of the second superlattice structure T2 may be smaller than the width of the bottom layer pair (size in the layer direction Ds).

[0011] In the semiconductor device 20, since the first superlattice structure T1 and the second superlattice structure T2 are connected, the shear stress on the multiple nitride semiconductor layers 11 is easily relieved by the multiple nitride semiconductor layers 12. This makes it possible to reduce slip defects (for example, linear crystal defects) along the direction in which the multiple nitride semiconductor layers 11 are stacked. The angle between the c-axis direction Dc and the oblique direction Df may be 25° to 95°, 50° to 70°, or 53° to 63°.

[0012] The first superlattice structure T1 and the second superlattice structure T2 can have thicknesses set to, for example, 200 nm to 1000 nm. The thickness of the first superlattice structure T1 may be different from the thickness of the second superlattice structure T2. Specifically, the thickness of the first superlattice structure T1 may be set to be smaller than the thickness of the second superlattice structure T2. The second superlattice structure T2 may have a smaller thickness per period (the thickness of the pair of layers) compared to the first superlattice structure T1. In this case, the shear stress on the first superlattice structure T1 is more easily relieved by the second superlattice structure T2. The first semiconductor layer L1 may be located below the active layer 9k. The superlattice structure is obtained by forming multiple periods of semiconductor layer pairs with different compositions (for example, pairs of nitride semiconductor layers). The thickness of each layer in the superlattice structure is, for example, 1.0 to 100 nm or 2.0 to 40 nm.

[0013] The functional layer 9 may include a lower semiconductor layer 9S located below the active layer 9K and an upper semiconductor layer 9H located above the active layer 9K. The lower semiconductor layer 9S may include an n-type semiconductor layer, and the upper semiconductor layer 9H may include a p-type semiconductor layer. The lower semiconductor layer 9S may include a first semiconductor layer L1, and the upper semiconductor layer 9H may include a second semiconductor layer L2. The semiconductor element 20 may include an electrode EA located on the upper semiconductor layer 9H. The semiconductor element 20 may be a laser diode or an LED.

[0014] The base semiconductor layer 8 contains a nitride semiconductor as its main component. The base semiconductor layer 8 may be a nitride semiconductor crystal. Nitride semiconductors can be expressed as, for example, AlxGayInzN (0≦x≦1; 0≦y≦1; 0≦z≦1; x+y+z=1), and specific examples include GaN-based semiconductors, AlN (aluminum nitride), InAlN (indium aluminum nitride), and InN (indium nitride). GaN-based semiconductors are semiconductors containing gallium atoms (Ga) and nitrogen atoms (N), and typical examples include GaN, AlGaN, AlGaInN, and InGaN. The base semiconductor layer 8 may be doped (e.g., n-type including a donor) or undoped.

[0015] The base semiconductor layer 8 can be formed by the ELO (Epitaxial Lateral Overgrowth) method using a crystal growth substrate containing a seed pattern (described later). The base B located above the seed pattern becomes a dislocation inheritance region with many threading dislocations. The wing regions F located on both sides of the base B become low-defect regions with a smaller threading dislocation density compared to the dislocation inheritance region of the base B. The threading dislocation density of the wing regions F may be 1 / 5 or less, 1 / 10 or less, or 1 / 100 or less of the threading dislocation density of the base B.

[0016] The first semiconductor layer L1 may include a GaN layer and an AlxInyGa(1-x-y)N layer (0 < x + y ≤ 1). For example, as shown in Figure 2, in the first superlattice structure T1, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlN layers, and InN layers may be stacked over multiple periods. In the second superlattice structure T2, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlN layers, and InN layers may be stacked over multiple periods. Here, for the binary mixed crystal layer (AlGaN layer, InGaN layer, AlInN layer) and the ternary mixed crystal layer (AlInGaN layer), the composition ratio of the multiple group III metal elements contained is arbitrary.

[0017] As shown in Figures 2 to 4, the base semiconductor layer 8 may have a shape with the m-axis direction Dm as its longitudinal direction. In a cross section perpendicular to the m-axis direction Dm (a cross section parallel to the m-plane), the nitride semiconductor layer 11 of the first part V1 and the nitride semiconductor layer 12 of the second part V2 are connected.

[0018] The thickness (length in the Dc direction) of the functional layer 9 may be 0.1 to 10 μm or 0.3 to 3.0 μm. The width (length in the Da direction) of the functional layer 9 may be 10 to 10,000 μm or 30 to 300 μm.

[0019] In the first semiconductor layer L1, the width W1 of the a-axis direction Da of the first portion V1 is 2 × 10⁻¹⁰ of the width W2 of the a-axis direction Da of the second portion V2. １ ~2 x 10 ５ It is often twice the number, and more preferably 2 × 10 ３ ~2 x 10 ４ It may be double. The third part V3 in Figure 1 is formed on the opposite side of the second part V2 in the a-axis direction Da. When the width of the third part V3 (Figure 1) in the a-axis direction Da is W3 (not shown), the width W1 is 1 × 10 with respect to at least one of the widths W2 and W3. １ ~1 x 10 ５ It is often twice the number, and more preferably 1 × 10⁻⁶. ３ ~1 x 10 ４It may be double. By setting the size relationship between width W1 and at least one of widths W2 and W3 to this numerical range, the shear stress applied to the first part V1 in the first semiconductor layer L1 can be efficiently relieved by at least one of the superlattice structure of the second part V2 and the superlattice structure of the third part V3.

[0020] Each nitride semiconductor layer 11 of the first part V1 and each nitride semiconductor layer 12 of the second part V2 may contain at least one element of gallium (Ga), aluminum (Al), and indium (In), and a nitrogen element.

[0021] The upper surface of the second part V2 may be aligned with a predetermined crystal plane of the nitride semiconductor, for example, it may be parallel. The predetermined crystal plane may be the {11-22} plane. The nitride semiconductor layer 11 of the first part V1 (first superlattice structure) may be parallel to the c-plane of the base semiconductor layer 8, and the nitride semiconductor layer 12 of the second part V2 (second superlattice structure) may be parallel to the {11-22} plane of the base semiconductor layer 8. The nitride semiconductor layer 12 of the second part V2 (second superlattice structure) may be perpendicular to the r-axis of the base semiconductor layer 8.

[0022] As shown in Figures 1 and 5, the first semiconductor layer L1 may include a third portion V3 connected to a first portion V1, with the a-axis direction of the nitride semiconductor being the third direction Da, the m-axis direction of the nitride semiconductor being the fourth direction Dm, the c-axis direction of the nitride semiconductor being the first direction Dc, and the diagonal direction being the second direction Df. The third portion V3 may include a plurality of nitride semiconductor layers 13 stacked in a fifth direction Dk different from the first direction Dc and the second direction Df, forming a third superlattice structure. The acute angle formed by the first direction Dc and the second direction Df may be equal to the acute angle formed by the first direction Dc and the fifth direction Dk.

[0023] Figure 6 is a cross-sectional view showing an example of the configuration of this semiconductor device. As shown in Figures 1 and 6, the functional layer 9 may include a second semiconductor layer L2. An active layer 9K may be located between the first semiconductor layer L1 and the second semiconductor layer L2. The second semiconductor layer L2 may include a fourth portion V4 and a fifth portion V5 connected to the fourth portion V4. The fourth portion V4 may include a plurality of nitride semiconductor layers 14 stacked in the c-axis direction Dc of the nitride semiconductor, forming a fourth superlattice structure T4. The fifth portion V5 may include a plurality of nitride semiconductor layers 15 stacked in an oblique direction Df with respect to the c-axis direction Dc, forming a fifth superlattice structure T5. The fifth superlattice structure T5 may have a thickness that is smaller by one period compared to the fourth superlattice structure T4. The stacking directions of the second superlattice structure T2 and the fifth superlattice structure T5 may be the same.

[0024] In the third superlattice structure T3, the fourth superlattice structure T4, and the fifth superlattice structure T5, pair layers consisting of two layers selected from GaN, AlGaN, InGaN, AlInGaN, AlInN, AlN, and InN layers may be stacked over multiple periods.

[0025] Figures 7 and 8 are cross-sectional views showing an example of the configuration of this semiconductor device. As shown in Figures 7 and 8, the active layer 9K is a light-emitting layer, and the first semiconductor layer L1 may be a guide layer GS or a cladding layer CS. The semiconductor device 20 shown in Figures 7 and 8 is a laser diode, and on the base semiconductor layer 8, it comprises a lower cladding layer CS, a lower guide layer GS, an active layer 9K, an upper guide layer GH, and an upper cladding layer CH in this order. The lower cladding layer CS, lower guide layer GS, active layer 9K, upper guide layer GH, and upper cladding layer CH constitute an optical resonator 17. The optical resonator 17 has its resonator length direction in the m-axis direction Dm.

[0026] The lower guide layer GS (first semiconductor layer L1) may include a first portion V1 and a second portion V2 connected to the first portion V1. The first portion V1 may include a plurality of nitride semiconductor layers stacked in the c-axis direction Dc to form a first superlattice structure T1, and the second portion V2 may include a plurality of nitride semiconductor layers stacked in an oblique direction Df with respect to the c-axis direction Dc to form a second superlattice structure T2. The first and second superlattice structures T1 and T2 may be connected. The first superlattice T1 of the lower guide layer GS (L1) can be obtained, for example, by forming 25 periodic InGaN layer (3 nm) / GaN layer (3 nm) pairs (the In composition of the InGaN layer is, for example, 8%).

[0027] The upper guide layer GH (second semiconductor layer L2) may include a fourth region V4 and a fifth region V5 connected to the fourth region V4. The fourth region V4 may include a plurality of nitride semiconductor layers stacked in the c-axis direction Dc to form a fourth superlattice structure, and the fifth region V5 may include a plurality of nitride semiconductor layers stacked in an oblique direction Df with respect to the c-axis direction Dc to form a fifth superlattice structure T5. The fourth and fifth superlattice structures T4 and T5 may be connected. The fourth superlattice T4 of the upper guide layer GH (L2) can be obtained, for example, by forming 13 periodic InGaN layer (3 nm) / GaN layer (3 nm) pairs (the In composition of the InGaN layer is, for example, 8%).

[0028] The lower cladding layer CS (third semiconductor layer L3) may include a seventh region V7 and an eighth region V8 connected to the seventh region V7. The seventh region V7 may include a plurality of nitride semiconductor layers stacked in the c-axis direction Dc to form a seventh superlattice structure T7, and the eighth region V8 may include a plurality of nitride semiconductor layers stacked in an oblique direction Df with respect to the c-axis direction Dc to form an eighth superlattice structure T8. The seventh and eighth superlattice structures T7 and T8 may be connected. The seventh superlattice T7 of the lower cladding layer CS (L3) can be obtained, for example, by forming 90 periodic AlGaN layer (5 nm) / GaN layer (5 nm) pairs (the Al composition of the AlGaN layer is, for example, 18%).

[0029] The upper cladding layer CH (fourth semiconductor layer L4) may include a ninth region V9 and a tenth region V10 connected to the ninth region V9. The ninth region V9 may include a plurality of nitride semiconductor layers stacked in the c-axis direction Dc to form a ninth superlattice structure T9, and the tenth region V10 may include a plurality of nitride semiconductor layers stacked in an oblique direction Df with respect to the c-axis direction Dc to form a tenth superlattice structure T10. The ninth and tenth superlattice structures T9 and T10 may be connected. The ninth superlattice T9 of the upper cladding layer CS (L4) can be obtained, for example, by forming 75 periodic AlGaN layer (3 nm) / GaN layer (5 nm) pairs (the Al composition of the AlGaN layer is, for example, 18%).

[0030] A multiple quantum well (MQW) structure with an InGaN layer / GaN layer can be used for the active layer 9K.

[0031] Figure 9 is a flowchart showing the method for manufacturing the semiconductor device. Figure 10 is a cross-sectional view showing the method for manufacturing the semiconductor device. As shown in Figures 1 and 2 and Figures 9 and 10, the method for manufacturing the semiconductor device includes steps S5 and S7. In step S5, a semiconductor substrate 10 having a base semiconductor layer containing a nitride semiconductor is prepared. In step S7, a functional layer 9 is formed on the base semiconductor layer 5, including an active layer 9K and a first semiconductor layer L1 located below or above the active layer 9K. The first semiconductor layer L1 has a first superlattice structure T1 with the c-axis direction Dc as the stacking direction and a second superlattice structure T2 with the diagonal direction Df to the c-axis direction Dc as the stacking direction. The first superlattice structure T1 and the second superlattice structure T2 may be connected.

[0032] In this semiconductor device manufacturing method, the shear stress applied to the first superlattice structure T1, with the c-axis direction Dc as the stacking direction, is more easily absorbed by the second superlattice structure T2, with the diagonal direction Df as the stacking direction. This reduces slip defects (e.g., linear crystal defects) observed in the cross-section perpendicular to the c-axis. The second superlattice structure T2 can have a smaller thickness per period (the thickness of the pair of layers) compared to the first superlattice structure T1. In this case, the shear stress applied to the first superlattice structure T1 is absorbed more effectively by the second superlattice structure T2.

[0033] In this method for manufacturing a semiconductor device, the base semiconductor layer 8 may have a shape whose longitudinal direction is the m-axis direction Dm. In a cross section orthogonal to the m-axis direction Dm (a cross section parallel to the m-plane), the nitride semiconductor layer 11 of the first superlattice structure T1 and the nitride semiconductor layer 12 of the second superlattice structure T2 are connected. In the first semiconductor layer L1, the width W1 of the first portion V1 in the a-axis direction Da is, relative to the width W2 of the second portion V2 in the a-axis direction Da, 2×10 ２ to 2×10 ５ times, or 2×10 ３ to 2×10 ４ times. The nitride semiconductor layer 11 and the nitride semiconductor layer 12 may each contain at least one element selected from gallium (Ga), aluminum (Al) and indium (N), and nitrogen. The upper surface of the second portion V2 may be parallel to a predetermined crystal plane of the nitride semiconductor. The predetermined crystal plane may be a {11-22} plane.

[0034] In this method for manufacturing a semiconductor device, in each of the first superlattice structure T1 and the second superlattice structure T2, a pair layer composed of two layers selected from a GaN layer, an AlGaN layer, an InGaN layer, an AlInGaN layer, an AlInN layer, an AlN layer, and an InN layer may be laminated over a plurality of periods. The first superlattice structure T1 and the second superlattice structure T2 can be formed, for example, using an MOCVD (Metal Organic Chemical Vapor Deposition) apparatus under the following conditions.

[0035] For example, the conditions for forming the GaN layers of the first superlattice structure T1 and the second superlattice structure T2 can include a growth temperature of 1030 to 1100°C, a growth pressure of 100 kPa, and a V / III ratio of 2000 to 5000. The V / III ratio is the ratio of the number of moles of the group V element (nitrogen) to the number of moles of the group III element (Ga) in the supplied raw material. Under these conditions, the growth rate of the GaN layer in the second superlattice structure T2 becomes lower than the growth rate of the GaN layer in the first superlattice structure T1, and the thickness of one period of the second superlattice structure T2 can be made smaller than the thickness of one period of the first superlattice structure T1.

[0036] The ratio of the growth rate (lateral growth rate) of the GaN layer in the second superlattice structure T2 to the growth rate (c-plane growth rate) of the GaN layer in the first superlattice structure T1 is defined as the lateral growth ratio, and the following findings have been obtained regarding the lateral growth ratio of the GaN layer. The lateral plane is, for example, a (11-22) plane.

[0037] The lateral growth ratio of the GaN layer decreases by lowering the growth temperature. The lateral growth ratio of the GaN layer decreases by increasing the growth pressure. The lateral growth ratio of the GaN layer decreases by increasing the V / III ratio. The lateral growth ratio of the GaN layer decreases by increasing the partial pressure of the group V source material. The lateral growth ratio of the GaN layer decreases by increasing the total flow rate of the source materials. By setting these parameters (growth temperature, growth pressure, V / III ratio, group V partial pressure, total flow rate), a desired lateral growth ratio in the formation of the GaN layer is achieved, and slip defects in the first semiconductor layer L1 can be more effectively reduced.

[0038] As conditions for forming the AlGaN layers of the first and second superlattice structures T1 and T2, a growth temperature of 1030 to 1100°C, a growth pressure of 50 to 100 kPa (depending on the composition of Al), and a V / III ratio of 2000 to 8000 can be cited. Under these conditions, the growth rate of the AlGaN layer in the second superlattice structure T2 is lower than the growth rate of the AlGaN layer in the first superlattice structure T1, and the thickness of one period of the second superlattice structure T2 can be made smaller than the thickness of one period of the first superlattice structure T1. The following findings have also been obtained regarding the lateral growth ratio of the AlGaN layer. The lateral plane is, for example, a (11-22) plane.

[0039] The lateral growth ratio of the AlGaN layer decreases by lowering the growth temperature. The lateral growth ratio of the AlGaN layer decreases by increasing the growth pressure. The lateral growth ratio of the AlGaN layer decreases by increasing the V / III ratio. The lateral growth ratio of the AlGaN layer decreases by increasing the partial pressure of the group V source material. The lateral growth ratio of the AlGaN layer decreases by increasing the total flow rate of the source materials. By setting these parameters (growth temperature, growth pressure, V / III ratio, group V partial pressure, total flow rate), a desired lateral growth ratio in the formation of the AlGaN layer is achieved, and slip defects in the first semiconductor layer L1 can be more effectively reduced.

[0040] Further, as conditions for forming the InGaN layers of the first and second superlattice structures T1 and T2, a growth temperature of 700 to 900°C, a growth pressure of 100 kPa, and a V / III ratio of 10000 to 30000 can be mentioned. Under these conditions, the growth rate of the InGaN layer in the second superlattice structure T2 becomes lower than the growth rate of the InGaN layer in the first superlattice structure T1, and the thickness of one period of the second superlattice structure T2 can be made smaller than the thickness of one period of the first superlattice structure T1.

[0041] When comparing the case where the base semiconductor layer 8 is a GaN layer and an AlGaN layer is formed above the base semiconductor layer 8, with the case where an InGaN layer is formed, the case where the InGaN layer is formed tends to have more defects. Possible reasons for this include, for example, that in terms of lattice constant, InGaN deviates more from GaN than AlGaN, and that InGaN is under tensile strain while AlGaN is under compressive strain. That is, in the functional layer 9, the portion using InGaN is preferably a superlattice structure (GaN layer / InGaN layer), and the portion requiring AlGaN can be a non-superlattice structure (AlGaN single layer) or a superlattice structure with a relatively large thickness per period (GaN layer / AlGaN layer).

[0042] Further, when comparing the case where an InGaN layer is used in a layer lower than the active layer 9K with the case where an InGaN layer is used in a layer higher than the active layer 9K, the case where the InGaN layer is used in the layer lower than the active layer 9K has a greater influence on the active layer 9K.

[0043] Therefore, the priority for adopting a superlattice structure decreases in the order of the n-side (layer lower than the active layer 9K) InGaN layer, the n-side (layer lower than the active layer 9K) AlGaN layer, the p-side (layer higher than the active layer 9K) InGaN layer, and the p-side (layer higher than the active layer 9K) AlGaN layer. This is the same regardless of whether the functional layer 9 is a semiconductor laser or an LED. In the semiconductor laser of FIG. 8, at least the lower guide layer GS including the InGaN layer is defined as the superlattice structure T1.

[0044] Regarding Figure 8, a cladding layer (CS / CH) of a blue semiconductor laser preferably has an Al composition of 3-10%, and the layer thickness may be 500-2000 nm for the lower (n-side) cladding layer CS and 200-1000 nm for the upper (p-side) cladding layer CH. In this case, the defect generation results were similar for a superlattice structure (1 period of 10 nm) consisting of a pair of 5 nm AlGaN and 5 nm GaN layers, and for a superlattice structure (1 period of 60 nm) consisting of a pair of 30 nm AlGaN and 30 nm GaN layers. A superlattice structure does not need to be used for cladding layers with a low Al composition of about 3% (especially the upper cladding layer CH).

[0045] Regarding Figure 8, a guide layer (GS / GH) for the blue semiconductor laser is preferably composed of 1.0 to 10% In, and the layer thickness may be 50 to 500 nm on both the lower (n-side) and upper (p-side). In this case, a superlattice structure consisting of a pair of 3 nm InGaN and 3 nm GaN layers (6 nm period) showed better defect generation results than a superlattice structure consisting of a pair of 10 nm InGaN and 10 nm GaN layers (20 nm period).

[0046] In Figure 8, the thickness of one period of the first portion V1 (first superlattice structure) of the lower guide layer GS (first semiconductor layer L1) may be smaller than the thickness of one period of the fourth portion V4 (fourth superlattice structure) of the upper guide layer GH (second semiconductor layer L2). The thickness of one period of the first portion V1 (first superlattice structure) may be smaller than the thickness of one period of the seventh portion V7 (seventh superlattice structure) of the lower cladding layer CS (third semiconductor layer L3). The upper cladding layer CH (fourth semiconductor layer L4) may be a non-superlattice structure (a single layer of AlGaN).

[0047] Figure 11 is a cross-sectional view showing a method for manufacturing the semiconductor device. As shown in Figure 11, the semiconductor substrate 10 may include a main substrate 1 and a seed pattern 4 located above the main substrate 1 and including seed portions S1 and S2. The base semiconductor layer 8A (8) may include a base portion B1 extending upward from the seed portion S1 and a pair of wing portions F1 extending in the a-axis direction Da from the base portion B1. The base semiconductor layer 8B (8) adjacent to the base semiconductor layer 8A may include a base portion B2 extending upward from the seed portion S2 and a pair of wing portions F2 extending in the a-axis direction Da from the base portion B2. The wing portions F1 and F2 may be adjacent in the a-axis direction with a gap GP between them.

[0048] The main substrate 1 may be a different type of substrate (e.g., sapphire substrate, silicon substrate, silicon carbide substrate, AlN substrate) with a different lattice constant from the nitride semiconductor of the base semiconductor layer 8. A nitride semiconductor (e.g., AlN) can be used for the seed layer 4. The main substrate 1, seed layer 4, and mask pattern 6 may constitute a crystal growth substrate TK. The main substrate 1 and seed layer 4 may constitute a base substrate.

[0049] In a plan view, the seed portions S1 and S2 are located at the openings of the mask pattern 6. The mask portion 5 of the mask pattern 6 may function as a growth-inhibiting (selective growth) mask. Silicon nitride, silicon oxide, etc., can be used for the mask portion 5. In the crystal growth substrate TK, the seed portions S1 and S2 become the growth starting points for the base semiconductor layer 8, and the base semiconductor layer 8 can be formed by the ELO method as shown in Figure 11. A void JD may be located between the crystal growth substrate TK and the wing portion F1. Electrodes EA (anode) and EC (cathode) may be located on the functional layer 9. Electrode EA may be in contact with the upper semiconductor layer 9H, and electrode EC may be located on the lower semiconductor layer 9S (see Figure 7).

[0050] Figure 12 is a perspective view showing the manufacturing method of the semiconductor device. Figure 13 is a flowchart showing the manufacturing method of the semiconductor device. Figure 14 is a cross-sectional view showing the manufacturing method of the semiconductor device. The manufacturing method of the semiconductor device described in Figures 12 to 14 includes a step S10 of preparing an element substrate DK comprising a crystal growth substrate TK, a plurality of stripe-shaped base semiconductor layers 8 crystallized on the crystal growth substrate TK, and a plurality of functional layers 9 located on the plurality of base semiconductor layers 8; a step S20 of obtaining a group of individuals LA by dividing a plurality of structures JT on the crystal growth substrate TK, each of which includes a base semiconductor layer 8 and a functional layer 9, such that an end face CF parallel to the short side direction (a-axis direction Da) is formed on each structure JT; a step S30 of transferring a plurality of individuals (laser elements 20) included in the group of individuals LA to a transfer substrate SK; and a step S40 of dividing the transfer substrate SK to obtain a laser substrate 30 (laser chip, semiconductor device) containing one or more laser elements 20.

[0051] The division of the multiple striped structures JT may be performed by cleavage using the end faces CF as the cleavage plane, or by etching (dry or wet etching). The end faces CF formed by the division of the structures JT may include the end faces of the resonator of the solid (laser element 20).

[0052] In step S30, selective transfer can be performed such that the number of transferred individuals per unit area on the transfer substrate SK is smaller than the number of individuals per unit area in the individual population LA. For example, the spacing between multiple individuals (laser elements 20) in the m-axis direction (Dm) may be greater than or equal to the size (resonator length) of each individual in direction Dm. In step S40, the transfer substrate SK can be divided so as not to divide any of the individuals (laser elements 20). This reduces edge distortion of the individuals (laser elements 20) that occurs when the transfer substrate SK is divided.

[0053] The transfer substrate SK may also be a mounting substrate. In step S30, electrode EA may be connected to pad PA of the transfer substrate SK via a conductive layer, and electrode EC may be connected to pad PC of the transfer substrate SK via a conductive layer.

[0054] Figure 15 is a block diagram showing the semiconductor device manufacturing apparatus. The semiconductor device manufacturing apparatus 50 comprises an apparatus M5 that performs process S5 in Figure 10, an apparatus M7 that performs process S7 in Figure 10, and an apparatus MX that controls apparatus M5 and apparatus M7.

[0055] Figure 16 is a block diagram showing the semiconductor device manufacturing apparatus. The semiconductor device manufacturing apparatus 70 includes an apparatus M10 that performs the process S10 shown in Figure 13, an apparatus M20 that performs the process S20 shown in Figure 13, an apparatus M30 that performs the process S30 shown in Figure 13, an apparatus M40 that performs the process M40 shown in Figure 13, and an apparatus MY that controls apparatuses M10, M20, M30 and M40.

[0056] [Additional Notes] This disclosure is not limited to the embodiments and examples described above. Forms obtained by appropriately combining the technical means described separately in the embodiments and examples are also included in the scope of this disclosure. It will be easy for those skilled in the art to make various modifications or alterations based on this disclosure, and forms obtained by such modifications or alterations are also included in the scope of this disclosure.

[0057] Disclosure 1: A semiconductor device comprising a base semiconductor layer containing a nitride semiconductor and a functional layer located on the base semiconductor layer, wherein the functional layer includes an active layer and a first semiconductor layer located below or above the active layer, the first semiconductor layer includes a first portion and a second portion connected to the first portion, the first portion includes a plurality of nitride semiconductor layers stacked in a first direction to form a first superlattice structure, and the second portion includes a plurality of nitride semiconductor layers stacked in a second direction different from the first direction to form a second superlattice structure.

[0058] Disclosure 2: The semiconductor device according to Disclosure 1, wherein the first direction is the c-axis direction of the nitride semiconductor.

[0059] Disclosure Item 3: The semiconductor device according to Disclosure Item 1 or 2, wherein the first semiconductor layer includes a bent portion located in the connection region between a plurality of nitride semiconductor layers forming the first superlattice structure and a plurality of nitride semiconductor layers forming the second superlattice structure.

[0060] Disclosure Item 4: The semiconductor device according to any one of Disclosure Items 1 to 3, wherein the first semiconductor layer includes a GaN layer and an AlxInyGa(1-x-y)N layer (0 < x + y ≤ 1).

[0061] Disclosure 5: The semiconductor device according to any one of Disclosures 1 to 4, wherein in the first superlattice structure, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlInN layers, AlN layers, and InN layers are stacked over multiple periods, and in the second superlattice structure, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlN layers, and InN layers are stacked over multiple periods.

[0062] Disclosure Item 6: The base semiconductor layer has a shape with the m-axis direction as its longitudinal direction, and in a cross section perpendicular to the m-axis direction, the width of the first portion in the a-axis direction is 2 × 10 times the width of the second portion in the a-axis direction. ２ ~2 x 10 ５ A semiconductor device described in any one of disclosure items 1 to 5, which is double the original value.

[0063] Disclosure Item 7: The semiconductor device according to any one of Disclosure Items 1 to 6, wherein the second superlattice structure has a thickness of one period smaller than that of the first superlattice structure.

[0064] Disclosure 8: A semiconductor device according to any one of disclosures 1 to 5, wherein each nitride semiconductor layer of the first portion and each nitride semiconductor layer of the second portion comprises at least one element of gallium, aluminum, and indium, and a nitrogen element.

[0065] Disclosure 9: The semiconductor device according to any one of disclosures 1 to 8, wherein the second portion is parallel to a predetermined crystal plane of the nitride semiconductor.

[0066] Disclosure Item 10: The semiconductor device according to Disclosure Item 9, wherein the predetermined crystal plane is the {11-22} plane.

[0067] Disclosure Item 11: A semiconductor device according to any one of disclosure items 1 to 10, wherein the a-axis direction of the nitride semiconductor is the third direction, the m-axis direction of the nitride semiconductor is the fourth direction, the first semiconductor layer includes a third portion connected to the first portion, and the third portion includes a plurality of nitride semiconductor layers stacked in a fifth direction different from the first and second directions, forming a third superlattice structure.

[0068] Disclosure Item 12: The semiconductor device according to Disclosure Item 11, wherein the acute angle formed by the first direction and the second direction is equal to the acute angle formed by the first direction and the fifth direction.

[0069] Disclosure Item 13: The semiconductor device according to any one of Disclosure Items 1 to 12, wherein the first semiconductor layer is located below the active layer.

[0070] Disclosure Item 14: The semiconductor device according to any one of Disclosure Items 1 to 13, wherein the functional layer includes a second semiconductor layer, the active layer is located between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer includes a fourth portion and a fifth portion connected to the fourth portion, the fourth portion includes a plurality of nitride semiconductor layers stacked in the c-axis direction of the nitride semiconductor to form a fourth superlattice structure, and the fifth portion includes a plurality of nitride semiconductor layers stacked in a direction different from the c-axis direction to form a fifth superlattice structure.

[0071] Disclosure Item 15: The semiconductor device described in Disclosure Item 14, wherein the fifth superlattice structure has a thickness of one period smaller compared to the fourth superlattice structure.

[0072] Disclosure Item 16: The semiconductor device according to Disclosure Item 14, wherein the stacking directions of the second superlattice structure and the fifth superlattice structure are the same.

[0073] Disclosure Item 17: The semiconductor device according to any one of disclosure items 1 to 16, wherein the active layer is a light-emitting layer and the first semiconductor layer is a cladding layer or a guide layer.

[0074] Disclosure Item 18: A semiconductor device described in any one of Disclosure Items 1 to 17, which is a laser diode or an LED.

[0075] Disclosure Item 19: A method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate including a base semiconductor layer containing a nitride semiconductor; and forming a functional layer on the base semiconductor layer, the functional layer including an active layer and a first semiconductor layer located below or above the active layer, wherein the first semiconductor layer includes a first portion and a second portion connected to the first portion, the first portion includes a plurality of nitride semiconductor layers stacked in the c-axis direction of the nitride semiconductor to form a first superlattice structure, and the second portion includes a plurality of nitride semiconductor layers stacked in a direction different from the c-axis direction to form a second superlattice structure.

[0076] Disclosure Item 20: A method for manufacturing a semiconductor device according to Disclosure Item 19, wherein the first semiconductor layer comprises a GaN layer and an AlxInyGa(1-x-y)N layer (0 < x + y ≤ 1).

[0077] Disclosure 21: A method for manufacturing a semiconductor device according to Disclosure 19 or 20, wherein in the first superlattice structure, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlInN layers, AlN layers, and InN layers are stacked over multiple periods, and in the second superlattice structure, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlN layers, and InN layers are stacked over multiple periods.

[0078] Disclosure Item 22: The base semiconductor layer has a shape with the m-axis direction as its longitudinal direction, and in a cross section perpendicular to the m-axis direction, the width of the first portion in the a-axis direction is 2 × 10 times the width of the second portion in the a-axis direction. １ ~2 x 10 ５ A method for manufacturing a semiconductor device as described in any one of disclosure items 19 to 21, wherein the method is twice as effective.

[0079] Disclosure Item 23: A method for manufacturing a semiconductor device according to any one of Disclosure Items 19 to 22, wherein the second superlattice structure has a thickness of one period less than that of the first superlattice structure.

[0080] Disclosure Item 24: A method for manufacturing a semiconductor device according to any one of disclosure items 19 to 23, wherein the second portion is parallel to a predetermined crystal plane of the nitride semiconductor.

[0081] Disclosure Item 25: A method for manufacturing a semiconductor device according to Disclosure Item 24, wherein the predetermined crystal plane is the {11-22} plane.

[0082] Disclosure Item 26: A method for manufacturing a semiconductor device according to any one of Disclosure Items 19 to 25, wherein the semiconductor substrate includes a main substrate and a seed pattern located above the main substrate and including a seed portion, and the base semiconductor layer includes a base portion extending upward from the seed portion and a wing portion extending in a first direction from the base portion.

[0083] Disclosure Item 27: A method for manufacturing a semiconductor device according to Disclosure Item 26, wherein the main substrate is a different type of substrate with a different lattice constant from the nitride semiconductor.

[0084] 1 Main substrate 4 Seed layer 5 Mask area 6 Mask pattern 8 Base semiconductor layer 9 Functional layer 10 Semiconductor substrate 20 Semiconductor element (laser element) 30 Semiconductor element (laser substrate) L1 First semiconductor layer L1 Second semiconductor layer V1 First area V2 Second area DK Element substrate SK Transfer substrate JT Structure CF Edge TK Crystal growth substrate Dc First direction Df Second direction Da Third direction Dm Fourth direction

Claims

1. A semiconductor device comprising a base semiconductor layer containing a nitride semiconductor and a functional layer located on the base semiconductor layer, wherein the functional layer includes an active layer and a first semiconductor layer located below or above the active layer, the first semiconductor layer includes a first portion and a second portion connected to the first portion, the first portion includes a plurality of nitride semiconductor layers stacked in a first direction to form a first superlattice structure, and the second portion includes a plurality of nitride semiconductor layers stacked in a second direction different from the first direction to form a second superlattice structure.

2. The semiconductor element according to claim 1, wherein the first direction is the c-axis direction of the nitride semiconductor.

3. The semiconductor element according to claim 1 or 2, wherein the first semiconductor layer includes a bent portion located in the connection region between the plurality of nitride semiconductor layers forming the first superlattice structure and the plurality of nitride semiconductor layers forming the second superlattice structure.

4. The semiconductor device according to any one of claims 1 to 3, wherein the first semiconductor layer includes a GaN layer and an AlxInyGa(1-x-y)N layer (0 < x + y ≤ 1).

5. The semiconductor device according to any one of claims 1 to 4, wherein in the first superlattice structure, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlInN layers, AlN layers, and InN layers are stacked over multiple periods, and in the second superlattice structure, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlInN layers, AlN layers, and InN layers are stacked over multiple periods.

6. The base semiconductor layer has a shape with the m-axis direction as its longitudinal direction, and in a cross section perpendicular to the m-axis direction, the width of the first portion in the a-axis direction is 2 × 10⁻¹⁰ of the width of the second portion in the a-axis direction. ２ ~2 x 10 ５ A semiconductor element according to any one of claims 1 to 5, which is double the original amount.

7. The semiconductor device according to any one of claims 1 to 6, wherein the second superlattice structure has a thickness of one period smaller than that of the first superlattice structure.

8. The semiconductor device according to any one of claims 1 to 5, wherein each nitride semiconductor layer of the first portion and each nitride semiconductor layer of the second portion comprises at least one element of gallium, aluminum, and indium, and a nitrogen element.

9. The semiconductor element according to any one of claims 1 to 8, wherein the second portion is parallel to a predetermined crystal plane of the nitride semiconductor.

10. The semiconductor device according to claim 9, wherein the predetermined crystal plane is a {11-22} plane.

11. The semiconductor device according to any one of claims 1 to 10, wherein the a-axis direction of the nitride semiconductor is the third direction, the m-axis direction of the nitride semiconductor is the fourth direction, the first semiconductor layer includes a third portion connected to the first portion, and the third portion includes a plurality of nitride semiconductor layers stacked in a fifth direction different from the first and second directions, forming a third superlattice structure.

12. The semiconductor element according to claim 11, wherein the acute angle formed by the first direction and the second direction is equal to the acute angle formed by the first direction and the fifth direction.

13. The semiconductor device according to any one of claims 1 to 12, wherein the first semiconductor layer is located below the active layer.

14. The semiconductor element according to any one of claims 1 to 13, wherein the functional layer includes a second semiconductor layer, the active layer is located between the first semiconductor layer and the second semiconductor layer, the second semiconductor layer includes a fourth portion and a fifth portion connected to the fourth portion, the fourth portion includes a plurality of nitride semiconductor layers stacked in the c-axis direction of the nitride semiconductor to form a fourth superlattice structure, and the fifth portion includes a plurality of nitride semiconductor layers stacked in a direction different from the c-axis direction to form a fifth superlattice structure.

15. The semiconductor device according to claim 14, wherein the fifth superlattice structure has a thickness of one period smaller than that of the fourth superlattice structure.

16. The semiconductor device according to claim 14, wherein the stacking directions of the second superlattice structure and the fifth superlattice structure are the same.

17. The semiconductor device according to any one of claims 1 to 16, wherein the active layer is a light-emitting layer, and the first semiconductor layer is a cladding layer or a guide layer.

18. A semiconductor element according to any one of claims 1 to 17, which is a laser diode or an LED.

19. A method for manufacturing a semiconductor device, comprising the steps of: preparing a semiconductor substrate including a base semiconductor layer containing a nitride semiconductor; and forming a functional layer on the base semiconductor layer, the functional layer including an active layer and a first semiconductor layer located below or above the active layer, wherein the first semiconductor layer includes a first portion and a second portion connected to the first portion; the first portion includes a plurality of nitride semiconductor layers stacked in the c-axis direction of the nitride semiconductor to form a first superlattice structure; and the second portion includes a plurality of nitride semiconductor layers stacked in a direction different from the c-axis direction to form a second superlattice structure.

20. The method for manufacturing a semiconductor device according to claim 19, wherein the first semiconductor layer includes a GaN layer and an AlxInyGa(1-x-y)N layer (0 < x + y ≤ 1).

21. The method for manufacturing a semiconductor device according to claim 19 or 20, wherein in the first superlattice structure, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlInN layers, AlN layers, and InN layers are stacked over multiple periods, and in the second superlattice structure, pair layers consisting of two layers selected from GaN layers, AlGaN layers, InGaN layers, AlInGaN layers, AlInN layers, AlN layers, and InN layers are stacked over multiple periods.

22. The base semiconductor layer has a shape with the m-axis direction as its longitudinal direction, and in a cross section perpendicular to the m-axis direction, the width of the first portion in the a-axis direction is 2 × 10 times the width of the second portion in the a-axis direction. １ ~2 x 10 ５ A method for manufacturing a semiconductor device according to any one of claims 19 to 21, wherein the method is twice as effective.

23. The method for manufacturing a semiconductor device according to any one of claims 19 to 22, wherein the second superlattice structure has a thickness of one period less than that of the first superlattice structure.

24. The method for manufacturing a semiconductor device according to any one of claims 19 to 23, wherein the second portion is parallel to a predetermined crystal plane of the nitride semiconductor.

25. The method for manufacturing a semiconductor device according to claim 24, wherein the predetermined crystal plane is the {11-22} plane.

26. A method for manufacturing a semiconductor element according to any one of claims 19 to 25, wherein the semiconductor substrate includes a main substrate and a seed pattern located above the main substrate and including a seed portion, and the base semiconductor layer includes a base portion extending upward from the seed portion and a wing portion extending in a first direction from the base portion.

27. The method for manufacturing a semiconductor device according to claim 26, wherein the main substrate is a different type of substrate with a different lattice constant from the nitride semiconductor.

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