Semiconductor memory device

Abstract

A semiconductor memory device according to the present invention comprises a DRAM cell (1), a word line (2), a bit line (3), a row decoder circuit (5), and a column decoder circuit (6). The DRAM cell (1) is configured from a transistor (10) and a storage capacitor (11). The row decoder circuit (5) turns on the transistor (10) via the word line (2) only for a moment during reading operation.

Description

Semiconductor memory devices

[0001] This invention relates to the read / write operation of a cell structure using storage capacitors in a semiconductor memory device, particularly a DRAM.

[0002] Generally, a DRAM (Dynamic Random Access Memory) cell comprises a storage capacitor and a word line transistor (hereinafter referred to as a WL transistor) that controls access to the storage capacitor. In a read operation from a DRAM cell, the WL transistor is turned on with the bit line voltage set to zero, transferring charge from the storage capacitor to the bit line. The slight potential difference caused by the charge transfer is amplified by a sense amplifier to determine the logical value stored in the storage capacitor.

[0003] However, conventional methods almost completely discharge the charge of the storage capacitor, so the q stored in the capacitor ２ Energy equivalent to / 2C (where q is the charge of the capacitor and C is the capacity of the storage capacitor) is consumed as heat. Furthermore, even in the writing operation to the DRAM cell, if speed is prioritized, a large current flows due to the sharp voltage change, resulting in energy loss and heat generation (Non-Patent Literature 1). In DRAMs, which are becoming increasingly integrated and high-capacity, the energy loss per access accumulates and has become a major problem.

[0004] As described above, conventional DRAM cells have the following problems: (I) they consume a large amount of energy by completely discharging the storage capacitor during reading, and (II) they exhibit significant energy loss and heat generation due to the steep voltage application required for high-speed operation during writing. To solve these problems, a method is needed that minimizes the amount of storage capacitor discharged during reading and avoids sudden current changes by gradually changing the voltage during writing.

[0005] "Essential DRAM Basics Part 1: Principles of Reading and Writing and Internal Structure," Macnica, Inc., 2022, <https: / / emb.macnica.co.jp / articles / 17841 / >

[0006] The present invention was made to solve the above problems, and aims to provide a semiconductor memory device that can significantly reduce energy consumption per access in situations where power saving is the top priority over high-speed operation.

[0007] The semiconductor memory device of the present invention comprises a DRAM cell, a word line, a bit line, a row decoder circuit, and a column decoder circuit. The DRAM cell consists of a transistor whose gate is connected to the word line and whose drain is connected to the bit line, and a storage capacitor whose one end is connected to the source of the transistor and whose other end is connected to ground. The row decoder circuit momentarily turns on the transistor via the word line during a read operation. Furthermore, the semiconductor memory device of the present invention comprises a DRAM cell, a word line, a bit line, a row decoder circuit, and a column decoder circuit. The DRAM cell is composed of a transistor whose gate is connected to the word line and whose drain is connected to the bit line, and a storage capacitor whose one end is connected to the source of the transistor and whose other end is connected to ground. The column decoder circuit, during a write operation, sequentially performs a preparation step of quasi-statically changing the voltage of the bit line to a predetermined voltage according to the logic value read from the storage capacitor in the preceding read operation, and a discharge step performed after the preparation step, followed by a step of gradually changing the voltage of the bit line according to the logic value to be written to the storage capacitor. The row decoder circuit turns on the transistor via the word line when the preparation step is completed during the write operation.

[0008] According to the present invention, the row decoder circuit can significantly reduce energy loss by momentarily turning on a transistor via the word line during a read operation, thereby achieving a greater energy saving effect compared to conventional methods.

[0009] Furthermore, in this invention, the column decoder circuit gradually changes the voltage of the bit lines during the preparation step immediately before discharge and the step after discharge in the writing operation, thereby avoiding the large current and heat generation associated with the rapid voltage application in conventional methods.

[0010] Figure 1 is a block diagram showing the configuration of a semiconductor memory device according to an embodiment of the present invention. Figures 2A and 2B illustrate the read operation in an embodiment of the present invention. Figures 3A and 3C illustrate the write operation in an embodiment of the present invention.

[0011] The embodiments of the present invention will be described below with reference to the drawings. In DRAM, operations are typically performed in the order of read → write. The read operation will be described first, followed by the write operation.

[0012] Figure 1 is a block diagram showing the configuration of a semiconductor memory device (DRAM device) according to this embodiment. The semiconductor memory device comprises a DRAM cell 1, a word line 2, a bit line 3, a sense amplifier circuit 4, a row decoder circuit 5, a column decoder circuit 6, an I / O buffer circuit 7, and a memory 8. The DRAM cell 1 consists of a WL transistor 10 whose gate is connected to the word line 2 and whose drain is connected to the bit line 3, and a storage capacitor 11 whose one end is connected to the source of the WL transistor 10 and whose other end is connected to ground.

[0013] In Figure 1, for the sake of simplicity, only one DRAM cell 1, one word line 2, and one bit line 3 are shown. As is well known, in actual semiconductor memory devices, multiple DRAM cells 1 are arranged in a matrix, and it goes without saying that multiple word lines 2 and bit lines 3 are also provided.

[0014] In conventional reading operations, if the WL transistor 10 is left fully turned on, discharge from the storage capacitor 11 to the bit line 3 occurs continuously, eventually leading to almost complete discharge.

[0015] [Reading Operation] The reading operation of this embodiment will be explained using Figures 2A and 2B. Figure 2A shows the initial state. In the initial state, the column decoder circuit 6 sets the voltage V of the bit line 3. ＢＬ The voltage is set to 0V. The row decoder circuit 5 turns off the WL transistor 10. Next, the row decoder circuit 5 sets the voltage of bit line 3 V ＢＬ With the voltage at 0V, the WL transistor 10 is briefly turned on and then immediately turned off via the word line 2 (Figure 2B).

[0016] When the WL transistor 10 is turned on, the charge in the storage capacitor 11 is transferred to the bit line 3. The sense amplifier circuit 4 amplifies the slight potential change in the bit line 3 due to the charge transfer. By reading the amplified potential of the bit line 3 through the I / O buffer circuit 7, the logical value of "0" or "1" stored in the storage capacitor 11 can be obtained. The memory 8 temporarily stores the logical value of "0" or "1" that was stored in the storage capacitor 11.

[0017] As in the conventional method, turning on the WL transistor 10 causes a current I to flow as shown by the arrow in Figure 2B. However, in this embodiment, the WL transistor 10 is turned on for only a moment and then immediately turned off. Therefore, the amount of charge transferred from the storage capacitor 11 to the bit line 3 can be minimized, and q ２ Energy loss equivalent to / 2C (where q is the charge amount of the storage capacitor 11 and C is the capacitance of the storage capacitor 11) can be significantly reduced. In this embodiment, the above-mentioned "instantaneous" refers to a time that is longer than the time it takes for charge to move from the storage capacitor 11 to the bit line 3, and shorter than the RC time constant (R is the on-resistance between the drain and source of the WL transistor 10). The resistor R can be adjusted by the voltage of the WL transistor 10. Therefore, by setting the resistor R higher and making the time constant RC longer, the time during which the WL transistor 10 is turned on can be extended.

[0018] [Write Operation] Next, the write operation will be described with reference to FIGS. 3A to 3C. FIG. 3A shows a preparatory step (quasi-static application step) immediately before discharging. In the conventional write operation, after the storage capacitor 11 is completely discharged while the bit line 3 is at 0 V, a desired bit line voltage is applied to perform writing.

[0019] On the other hand, in the present embodiment, before discharging the storage capacitor 11, the column decoder circuit 6 sets the voltage V of the bit line 3 in accordance with the logic value of the storage capacitor 11 read in the immediately preceding read operation ＢＬ quasi-statically from 0 V to a predetermined voltage (±ΔV ＢＬ ) (FIG. 3A). Here, ±ΔV ＢＬ is the bit line voltage applied when writing logic values "0" and "1" to the storage capacitor 11. When the logic value of the storage capacitor 11 read in the immediately preceding read operation is "0", the column decoder circuit 6 sets the voltage V of the bit line 3 as shown in FIG. 3A ＢＬ to ΔV ＢＬ . When the logic value of the storage capacitor 11 is "1", the column decoder circuit 6 sets the voltage V of the bit line 3 ＢＬ to -ΔV ＢＬ .

[0020] The quasi-static change of the voltage V ＢＬ means that the voltage V ＢＬ is changed over a time longer than the time constant of the bit line 3. The time constant of the bit line 3 is determined by the resistance R of the bit line 3 Ｂ and the parasitic capacitance C of the bit line 3 Ｂ , that is R Ｂ C Ｂ . By gently changing the voltage V ＢＬ , heat generation of the WL transistor 10 can be suppressed. Previous studies have shown that in an ideal situation where an almost infinite amount of time can be spent, the heat generation in the preparatory step can be made substantially zero (Reference: Alexei O. Orlov, et al., "Experimental Test of Landauer's Principle at the Sub-k BT Level”, Japanese Journal of Applied Physics, 51, 2012, 06FE10”).

[0021] The preparation process is complete, and the voltage V of bit line 3 is ＢＬ When the voltage of the bit line 3 approaches the potential of the storage capacitor 11, the row decoder circuit 5 completely turns on the WL transistor 10 via the word line 2 (Figure 3B). ＢＬ Since the potential is close to that of the storage capacitor 11, the storage capacitor 11 does not discharge during the process shown in Figure 3B, and no heat is generated.

[0022] Next, the column decoder circuit 6 adjusts the voltage V of the bit line 3 according to the logic value to be written to the storage capacitor 11. ＢＬ ±ΔV ＢＬ The voltage is gradually changed up to (Figure 3C). When writing the logical value "1", the column decoder circuit 6 changes the voltage of the bit line 3 as shown in Figure 3C. ＢＬ to -ΔV ＢＬ Also, if you want to write a logical value of "0", the column decoder circuit 6 will set the voltage of bit line 3 to V ＢＬ ΔV ＢＬ I'll do that.

[0023] A gradual change is a change in voltage V ＢＬ This means that the voltage V is changed over a time period longer than the respective time constants of the storage capacitor 11 and the bit line 3. ＢＬ During this change, if a potential difference occurs between the bit line 3 and the storage capacitor 11, the WL transistor 10 will heat up. ＢＬ By gradually changing the voltage and keeping the potential difference as small as possible while writing, the heat generated by the WL transistor 10 can be suppressed.

[0024] In the preparation step shown in Figure 3A, the result read in the previous reading operation is used, so it is necessary to store the logical value of the storage capacitor 11 somewhere. If a DRAM cell is used for storage, q ２ / 2C, a finite amount of heat generation equivalent to this will occur. Therefore, in the present embodiment, the logic value of "0" or "1" stored in the storage capacitor 11 is saved to a memory 8 such as an MRAM (Magnetoresistive Random Access Memory) that can reach the Landauer limit. The column decoder circuit 6, according to the value stored in the memory 8, sets the voltage V of the bit line 3 ＢＬ to ΔV ＢＬ or −ΔV ＢＬ . Although there is a method of replacing the entire DRAM with MRAM, in the present embodiment, it is sufficient to provide one MRAM ahead of the sense amplifier circuit 4, so there is no need to replace the entire DRAM with MRAM.

[0025] As described above, in the present embodiment, by turning on the WL transistor 10 only for a moment and immediately turning it off during the read operation, the energy loss can be greatly reduced, and a greater energy saving effect can be obtained compared with the prior art.

[0026] Furthermore, in the present embodiment, in the preparation step immediately before discharge during the write operation and the write step after discharge, the voltage V of the bit line 3 ＢＬ is gradually changed, whereby large current and large heat generation associated with conventional rapid voltage application can be avoided.

[0027] Furthermore, in the present embodiment, the read result obtained by the sense amplifier circuit 4 is saved to the ultra-low power consumption memory 8 such as an MRAM, whereby the rewrite energy loss can be suppressed. In the present embodiment, it is not necessary to integrate MRAM on a large scale, and it can be realized only by arranging the memory 8 for a limited number of bits in the vicinity of the sense amplifier circuit 4. As described above, in the present embodiment, in cases where power saving needs are prioritized over high-speed operation, significant energy reduction that was difficult to achieve with the prior art is enabled.

[0028] A part or all of the above embodiments can also be described as in the following appendices, but is not limited to the following.

[0029] (Supplementary Note 1) A semiconductor memory device of the present invention includes a DRAM cell, a word line, a bit line, a row decoder circuit, and a column decoder circuit. The DRAM cell is composed of a transistor having a gate connected to the word line and a drain connected to the bit line, and a storage capacitor having one end connected to the source of the transistor and the other end connected to ground. The row decoder circuit turns on the transistor only for a moment via the word line during a read operation.

[0030] (Supplementary Note 2) In the semiconductor memory device according to Supplementary Note 1, the row decoder circuit turns on the transistor for a time shorter than the RC time constant, where R is the on-resistance of the transistor and C is the capacitance of the storage capacitor.

[0031] (Supplementary Note 3) A semiconductor memory device of the present invention includes a DRAM cell, a word line, a bit line, a row decoder circuit, and a column decoder circuit. The DRAM cell is composed of a transistor having a gate connected to the word line and a drain connected to the bit line, and a storage capacitor having one end connected to the source of the transistor and the other end connected to ground. The column decoder circuit sequentially performs, during a write operation, a preparation step of quasi-statically changing the voltage of the bit line to a predetermined voltage according to a logic value read from the storage capacitor in the immediately preceding read operation, and a step of gradually changing the voltage of the bit line according to a logic value to be written to the storage capacitor after a discharge step performed after the preparation step. The row decoder circuit performs the discharge step of turning on the transistor via the word line at the point in time when the preparation step is completed during the write operation.

[0032] (Supplementary Note 4) In the semiconductor memory device according to Supplementary Note 3, the column decoder circuit changes the voltage of the bit line over a time longer than the time constant of the bit line in the preparation step.

[0033] (Note 5) In the semiconductor memory device described in Note 3, the column decoder circuit, after the discharge step, changes the voltage of the bit line for a longer period of time than the time constants of the storage capacitor and the bit line, according to the logic value to be written to the storage capacitor.

[0034] (Note 6) The semiconductor memory device described in Note 3 further comprises a memory configured to store a logical value read from the storage capacitor in a read operation immediately preceding a write operation, and the column decoder circuit changes the voltage of the bit line in accordance with the logical value stored in the memory during the preparation step.

[0035] (Note 7) In the semiconductor memory device described in Note 6, the memory is MRAM.

[0036] 1...DRAM cell, 2...Word line, 3...Bit line, 4...Sense amplifier circuit, 5...Row decoder circuit, 6...Column decoder circuit, 7...I / O buffer circuit, 8...Memory, 10...WL transistor, 11...Storage capacitor.

Claims

1. A semiconductor memory device comprising a DRAM cell, a word line, a bit line, a row decoder circuit, and a column decoder circuit, wherein the DRAM cell is composed of a transistor whose gate is connected to the word line and whose drain is connected to the bit line, and a storage capacitor whose one end is connected to the source of the transistor and whose other end is connected to ground, and the row decoder circuit is characterized in that it momentarily turns on the transistor via the word line during a read operation.

2. A semiconductor memory device according to claim 1, wherein the row decoder circuit turns on the transistor for a time shorter than the RC time constant, when the on-resistance of the transistor is R and the capacitance of the storage capacitor is C.

3. A semiconductor memory device comprising a DRAM cell, a word line, a bit line, a row decoder circuit, and a column decoder circuit, wherein the DRAM cell is composed of a transistor whose gate is connected to the word line and whose drain is connected to the bit line, and a storage capacitor whose one end is connected to the source of the transistor and whose other end is connected to ground, the column decoder circuit, during a write operation, sequentially performs a preparation step of quasi-statically changing the voltage of the bit line to a predetermined voltage according to the logic value read from the storage capacitor in the preceding read operation, and a discharge step performed after the preparation step, followed by a step of gradually changing the voltage of the bit line according to the logic value to be written to the storage capacitor, and the row decoder circuit, during a write operation, performs the discharge step of turning on the transistor via the word line when the preparation step is completed.

4. A semiconductor memory device according to claim 3, wherein the column decoder circuit changes the voltage of the bit line for a longer time than the time constant of the bit line in the preparation step.

5. A semiconductor memory device according to claim 3, wherein the column decoder circuit, after the discharge step, changes the voltage of the bit line for a longer time than the time constants of the storage capacitor and the bit line, according to the logic value to be written to the storage capacitor.

6. A semiconductor memory device according to claim 3, further comprising a memory configured to store a logical value read from the storage capacitor in a read operation immediately preceding a write operation, wherein the column decoder circuit changes the voltage of the bit line in accordance with the logical value stored in the memory during the preparation step.

7. A semiconductor memory device according to claim 6, wherein the memory is MRAM.

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