Sample and hold circuit
Patent Information
- Application Number
- PCT/JP2025/015097
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2025-04-17
- Publication Date
- 2026-10-22
Smart Images
Figure JP2025015097_22102026_PF_FP_ABST
Abstract
Description
Sampling-Hold Circuit
[0001] This invention relates to a sampling-and-hold circuit capable of handling high-frequency signals.
[0002] Conventional sampling-and-hold circuits require dedicated capacitors and switch circuits to temporarily hold analog signals. However, typical sampling-and-hold circuits require complex circuitry to handle signals with frequencies above GHz. Furthermore, additional circuitry is needed if a homodyne detection function for frequency downconversion is required.
[0003] In recent years, methods have been proposed to detect high-frequency signals using nanoscale DRAM (Dynamic Random Access Memory). The transistors and capacitors that make up the DRAM cell have a transistor cutoff frequency f ｃｕｔｏｆｆ Higher frequencies f ｃａｒｒｉｅｒ By applying an AC (Alternating Current) signal, it is possible to accumulate charge according to the strength of the AC signal. In other words, by applying an AC signal at a low frequency f ｍｏｄ When the modulation is applied, f ｍｏｄ ga f ｃｕｔｏｆｆ If it is lower than f, then the charge stored in the capacitor will also be f ｍｏｄ The modulation component is reflected. This makes homodyne detection using DRAM possible (Non-Patent Literature 1).
[0004] Analog modulation methods include amplitude modulation (AM) and frequency modulation (FM), which use carrier signals with frequencies of several hundred GHz or 1Hz. Digital modulation methods include amplitude shift keying (ASK) and frequency shift keying (FSK).
[0005] However, while the technology disclosed in Non-Patent Document 1 uses DRAM to realize homodyne detection functionality, it has not been able to realize sampling and holding functionality for high-frequency signals.
[0006] Chloe Salhani, et al., "Sensing an alternating-current signal beyond the cutoff frequency using a single-electron dynamic random-access memory", PHYSICAL REVIEW APPLIED, 23, L021001, 2025
[0007] The present invention has been made to solve the above problems, and an object thereof is to provide a sampling hold circuit capable of handling high-frequency signals.
[0008] The sampling hold circuit of the present invention includes a DRAM cell composed of a first transistor and a capacitor, and a second transistor connected to the DRAM cell. The first transistor has a drain connected to the input terminal of the sampling hold circuit, and is turned on in a sampling mode and turned off in a hold mode according to a voltage input to its gate. The capacitor has one end connected to the source of the first transistor and the other end connected to ground. The second transistor has a gate connected to the source of the first transistor, and a drain connected to the output terminal of the sampling hold circuit.
[0009] According to the present invention, by providing the DRAM cell and the second transistor, sampling and holding of high-frequency signals can be performed. With the present invention, a sampling hold circuit capable of handling high-frequency signals can be realized with a simple configuration, and a homodyne detection function that cannot be obtained with a general sampling hold circuit can be realized.
[0010] Figure 1 is a circuit diagram showing the configuration of a sampling-hold circuit according to the first embodiment of the present invention. Figure 2 is a diagram showing the relationship between the cutoff frequency, carrier frequency, modulation frequency, and capacitor voltage in the first embodiment of the present invention. Figure 3 is a diagram showing the timing of the operation of the sampling-hold circuit according to the first embodiment of the present invention. Figure 4 is a circuit diagram showing the configuration of a sampling-hold circuit according to the second embodiment of the present invention. Figure 5 is a diagram showing the timing of the operation of the sampling-hold circuit according to the second embodiment of the present invention.
[0011] [First Embodiment] Figure 1 is a circuit diagram showing the configuration of a sampling-hold circuit according to the first embodiment of the present invention. The sampling-hold circuit includes a transistor Q1 whose drain is connected to the input terminal IN of the sampling-hold circuit, a capacitor C1 whose one end is connected to the source of transistor Q1 and whose other end is connected to ground, a transistor Q2 whose gate is connected to the source of transistor Q1 and whose drain is connected to the output terminal OUT of the sampling-hold circuit, a control circuit 11 that controls the on / off state of transistor Q1, and a readout circuit 12 that reads a signal from transistor Q2. In this embodiment, MOSFETs are used as transistors Q1 and Q2. Transistor Q1 and capacitor C1 constitute a DRAM cell 20.
[0012] Figure 1 shows a schematic configuration of a sampling-hold circuit; in an actual configuration, peripheral circuits such as resistors and bias circuits would be necessary. These peripheral circuits are well-known and can be easily designed by those skilled in the art.
[0013] By applying a signal to the input terminal IN and switching transistor Q1 on / off, the input signal is stored in capacitor C1. The signal stored in capacitor C1 is amplified by transistor Q2. This allows the signal to be read out while retaining the signal stored in capacitor C1.
[0014] Here, the cutoff frequency of the DRAM cell 20, which consists of a capacitor C1 and a transistor Q1, is f. ｃｕｔｏｆｆas follows. The channel resistance of transistor Q1 can be adjusted by the voltage applied from control circuit 11 to the gate of transistor Q1. If the channel resistance is low, the cutoff frequency f ｃｕｔｏｆｆ increases, and if the channel resistance is high, the cutoff frequency f ｃｕｔｏｆｆ decreases.
[0015] When a carrier signal with a frequency f higher than the cutoff frequency f ｃｕｔｏｆｆ ｃａｒｒｉｅｒ is applied to the input terminal IN, charges corresponding to the voltage amplitude S of the carrier signal are accumulated in capacitor C1, and as shown in FIG. 2, the voltage across capacitor C1 becomes S ｍｏｄ ｍｏｄ . On the other hand, the voltage amplitude of the carrier signal is modulated as S ｍｏｄ sin(2πf ｍｏｄ t). When the frequency f ｍｏｄ is lower than the cutoff frequency f ｃｕｔｏｆｆ , the voltage across capacitor C1 becomes S ｍｏｄ sin(2πf ｍｏｄ t).
[0016] In this embodiment, in the hold mode, the control circuit 11 completely turns off transistor Q1 (increases the FET channel resistance), and sets the cutoff frequency f ｃｕｔｏｆｆ to a frequency f lower than the sampling frequency f of the sample-and-hold circuit ｓａｍｐｌｉｎｇ ｃｕｔｏｆｆ _ ｈｏｌｄ . In the sampling mode, the control circuit 11 turns on transistor Q1. With transistor Q1 in the on state, when a signal to be sampled is input to the input terminal IN, the voltage across capacitor C1 changes according to the input signal in a state where the cutoff frequency is f ｃｕｔｏｆｆ . At this time, as described above, by setting the frequency f of the signal to be sampled ｃａｒｒｉｅｒ to be equal to or higher than the sampling frequency f ｓａｍｐｌｉｎｇ , the voltage across capacitor C1 becomes S ｍｏｄ .
[0017] In the next hold mode, the control circuit 11 turns off transistor Q1 by the voltage applied to the gate, and changes the cutoff frequency from f ｃｕｔｏｆｆ to f ｃｕｔｏｆｆ _ｈｏｌｄ This is changed. As a result, the channel resistance of transistor Q1 increases, and the voltage of capacitor C1 is fixed. The readout circuit 12 reads the voltage of capacitor C1 from the drain of transistor Q2.
[0018] The timing of the above operations is shown in Figure 3. Figure 3(a) shows the time variation of the cutoff frequency of the DRAM cell 20, and Figure 3(b) shows the timing of the read operation from transistor Q2. In Figure 3(a), the hold mode period is indicated by "H" and the sampling mode period by "S". In Figure 3(b), the period during which the read circuit 12 reads the signal via transistor Q2 is indicated by "on", and the period during which no read operation is performed is indicated by "off".
[0019] In sampling mode, the cutoff frequency of the DRAM cell 20 is f ｃｕｔｏｆｆ In this case, the S of the input signal ｍｏｄ For the voltage across capacitor C1 to match, 1 / f ｃｕｔｏｆｆ We must wait for the above time. In this case, 1 / f ｍｏｄ >> 1 / f ｃｕｔｏｆ This allows the sampling mode time to be significantly shorter than the time it takes for the modulated signal to change. In other words, even with a sampling delay, the modulated input signal can be accurately sampled.
[0020] Furthermore, in hold mode, it is necessary to maintain the signal held in capacitor C1 in sampling mode. Since an input signal is applied even in hold mode, it is necessary to read the voltage of capacitor C1 via transistor Q2 before the voltage of capacitor C1 changes due to the input signal. For this reason, the cutoff frequency is f ｃｕｔｏｆｆ _ ｈｏｌｄ The time dt from then until the voltage of capacitor C1 is read via transistor Q2 is then... ｄｅｌａｙ The length of time dt during which the readout circuit 12 reads the signal via transistor Q2 is... ｍｅａｓ is 1 / f ｃｕｔｏｆｆ _ ｈｏｌｄ It must be shorter. However, in reality, 1 / f ｃｕｔｏｆｆ _ ｈｏｌｄIt can be easily made longer. Therefore, dt ｄｅｌａｙ , dt ｍｅａｓ Considering that the above conditions can be easily met, f ｃｕｔｏｆｆ _ ｈｏｌｄ <<f ｓａｍｐｌｉｎｇ <f ｃｕｔｏｆｆ It is sufficient to satisfy the following conditions. Through the above operations, in this embodiment, the signal S superimposed on the carrier signal is obtained. ｍｏｄ sin(2πf) ｍｏｄ t) can be sampled and held until the next sampling mode arrives.
[0021] [Second Embodiment] In the first embodiment, f ｓａｍｐｌｉｎｇ The input signal is sampled and held at a frequency of f. However, when reading the signal through transistor Q2, the appropriate reading frequency f is determined according to the magnitude of the current and noise. ｒｅａｄｏｕｔ This f is determined. ｒｅａｄｏｕｔ ga f ｓａｍｐｌｉｎｇ When it is lower than 1 / f ｓａｍｐｌｉｎｇ It is not possible to read the input signal at a specific frequency. This embodiment solves the problem of the first embodiment.
[0022] Figure 4 is a circuit diagram showing the configuration of a sampling-hold circuit according to a second embodiment of the present invention. The sampling-hold circuit of this embodiment comprises a plurality of blocks 10-1 to 10-n (where n is an integer of 2 or more), a control circuit 11a, and a readout circuit 12a.
[0023] The configuration of transistors Q1-1 to Q1-n, Q2-1 to Q2-n and capacitors C1-1 to C1-n within each block 10-1 to 10-n is the same as the configuration of transistors Q1 and Q2 and capacitor C1 in the first embodiment. The transistors Q1-1 to Q1-n and capacitors C1-1 to C1-n constitute DRAM cells 20-1 to 20-n.
[0024] In this embodiment, the circuits consisting of transistors Q1 and Q2 and capacitor C1 from the first embodiment are arranged in parallel as a single block, and the input terminals of each block 10-1 to 10-n are shared as the terminal Multi_IN. Signals are read from each block 10-1 to 10-n at the timings described in the first embodiment. However, in this embodiment, as shown in Figure 5, the sampling mode timing, hold mode timing, and readout timing of each block are set to 1 / f for each block. ｓａｍｐｌｉｎｇ２ They are shifting one by one in order (f ｓａｍｐｌｉｎｇ２ > f ｓａｍｐｌｉｎｇ ).
[0025] Figure 5(a) shows the time variation of the cutoff frequency of the DRAM cell 20-1 in block 10-1, and Figure 5(b) shows the timing of the read operation from transistor Q2-1 in block 10-1. Similar to Figure 3, in Figure 5(a), the hold mode period is indicated by "H" and the sampling mode period by "S". In Figure 5(b), the period during which the read circuit 12a reads the signal via transistor Q2-1 is "on", and the period during which no read is performed is "off".
[0026] Figure 5(c) shows the time variation of the cutoff frequency of the DRAM cell 20-2 in block 10-2, and Figure 5(d) shows the timing of the read operation from transistor Q2-2 in block 10-2. Compared to block 10-1, the sampling mode timing, hold mode timing, and the timing at which the read circuit 12a reads the signal via transistor Q2-2 are all 1 / f ｓａｍｐｌｉｎｇ２ It's behind schedule.
[0027] Figure 5(e) shows the time variation of the cutoff frequency of the DRAM cell 20-n in block 10-n, and Figure 5(f) shows the timing of the read operation from transistor Q2-n in block 10-n. For block 10-1, the sampling mode timing, hold mode timing, and the timing at which the read circuit 12a reads the signal via transistor Q2-n are each (n-1) / f ｓａｍｐｌｉｎｇ２It's behind schedule.
[0028] Thus, in this embodiment, 1 / f ｓａｍｐｌｉｎｇ Shorter than 1 / f ｓａｍｐｌｉｎｇ２ Since the input signal can be read out at a specific frequency, high-speed signal sampling and holding becomes possible.
[0029] In the first and second embodiments, the control circuits 11, 11a and the read circuits 12, 12a are either hardware that performs the listed functions or hardware programmed to perform the listed functions. The hardware can be any hardware that is programmed or configured to perform the listed functions.
[0030] Some or all of the above examples may also be described as follows, but are not limited to the following:
[0031] (Note 1) The sampling-hold circuit of the present invention comprises a DRAM cell consisting of a first transistor and a capacitor, and a second transistor connected to the DRAM cell, wherein the drain of the first transistor is connected to the input terminal of the sampling-hold circuit, and it turns on in sampling mode and off in hold mode depending on the voltage input to the gate, the capacitor has one end connected to the source of the first transistor and the other end connected to ground, and the gate of the second transistor is connected to the source of the first transistor and the drain is connected to the output terminal of the sampling-hold circuit.
[0032] (Note 2) The sampling-hold circuit described in Note 1 uses a sampling frequency of f ｓａｍｐｌｉｎｇ , the cutoff frequency of the DRAM cell in sampling mode is f ｃｕｔｏｆｆ , the cutoff frequency of the DRAM cell in hold mode is f ｃｕｔｏｆｆ _ ｈｏｌｄ When this is the case, f ｃｕｔｏｆｆ _ ｈｏｌｄ <<f ｓａｍｐｌｉｎｇ <f ｃｕｔｏｆｆ It satisfies the condition.
[0033] (Note 3) The sampling-hold circuit described in Note 1 or 2 further comprises a control circuit configured to turn on the first transistor in sampling mode and turn it off in hold mode, and a readout circuit configured to read the voltage of the capacitor via the second transistor in hold mode.
[0034] (Note 4) In the sampling-hold circuit described in Note 1 or 2, the circuit consisting of the DRAM cell and the second transistor is treated as one block, multiple blocks are arranged in parallel, the input terminals of each block are shared terminals, and the sampling frequency f of each block ｓａｍｐｌｉｎｇ In contrast, the timing of the sampling mode for each block, the timing of the hold mode for each block, and the timing of reading the signal through the second transistor for each block are set to 1 / f for each block. ｓａｍｐｌｉｎｇ２ (f ｓａｍｐｌｉｎｇ２ > f ｓａｍｐｌｉｎｇ Shift them one by one.
[0035] (Note 5) The sampling-hold circuit described in Note 4 further comprises a control circuit configured to turn on the first transistor in sampling mode and off in hold mode, and a read circuit configured to read the voltage of the capacitor via the second transistor in hold mode, wherein the control circuit sets the timing of the sampling mode and the timing of the hold mode for each block to 1 / f for each block. ｓａｍｐｌｉｎｇ２ The timing of reading the signal through the second transistor of each block is shifted sequentially, and the reading circuit adjusts the timing of reading the signal through the second transistor of each block to 1 / f for each block. ｓａｍｐｌｉｎｇ２ Shift them one by one.
[0036] Q1, Q1-1 to Q1-n, Q2, Q2-1 to Q2-n...transistors, C1, C1-1 to C1-n...capacitors, 10-1 to 10-n...blocks, 11, 11a...control circuits, 12, 12a...read circuits, 20, 20-1 to 20-n...DRAM cells.
Claims
1. A sampling-hold circuit comprising a DRAM cell consisting of a first transistor and a capacitor, and a second transistor connected to the DRAM cell, wherein the drain of the first transistor is connected to the input terminal of a sampling-hold circuit, and turns on in sampling mode and off in hold mode depending on the voltage input to the gate, the capacitor has one end connected to the source of the first transistor and the other end connected to ground, and the gate of the second transistor is connected to the source of the first transistor and the drain is connected to the output terminal of the sampling-hold circuit.
2. In the sampling-hold circuit according to claim 1, the sampling frequency is f ｓａｍｐｌｉｎｇ , the cutoff frequency of the DRAM cell in sampling mode is f ｃｕｔｏｆｆ , the cutoff frequency of the DRAM cell in hold mode is f ｃｕｔｏｆｆ _ ｈｏｌｄ When this is the case, f ｃｕｔｏｆｆ _ ｈｏｌｄ <<f ｓａｍｐｌｉｎｇ <f ｃｕｔｏｆｆ A sampling-and-hold circuit characterized by satisfying the following conditions.
3. A sampling-hold circuit according to claim 1 or 2, further comprising: a control circuit configured to turn on the first transistor in sampling mode and turn it off in hold mode; and a readout circuit configured to read the voltage of the capacitor via the second transistor in hold mode.
4. The sampling hold circuit according to claim 1 or 2, wherein a circuit consisting of the DRAM cell and the second transistor is defined as one block, a plurality of the blocks are arranged in parallel, an input terminal of each block is a shared terminal, and a sampling frequency f of each block ｓａｍｐｌｉｎｇ , wherein each of a timing of a sampling mode of each block, a timing of a hold mode of each block, and a timing of reading a signal through the second transistor of each block is sequentially shifted by 1 / f for each block ｓａｍｐｌｉｎｇ２ (f ｓａｍｐｌｉｎｇ２ >f ｓａｍｐｌｉｎｇ ).
5. The sampling-hold circuit according to claim 4, further comprising: a control circuit configured to turn on the first transistor in sampling mode and off in hold mode; and a readout circuit configured to read the voltage of the capacitor via the second transistor in hold mode, wherein the control circuit sets the timing of the sampling mode and the timing of the hold mode for each block to 1 / f for each block. ｓａｍｐｌｉｎｇ２ The timing of reading the signal through the second transistor of each block is shifted sequentially, and the reading circuit adjusts the timing of reading the signal through the second transistor of each block to 1 / f for each block. ｓａｍｐｌｉｎｇ２ A sampling-and-hold circuit characterized by sequentially shifting the values.