Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention pertains to a semiconductor device comprising: a semiconductor substrate; a full-circumference gate transistor that is provided on a front surface side of the semiconductor substrate, one of a source / drain extending toward the rear surface side of the semiconductor substrate; an isolation insulating film that is filled in an opening penetrating the semiconductor substrate, and embeds a portion, of the one of the source / drain, extending toward the rear surface side of the semiconductor substrate; and a rear surface side contact that is provided penetrating the semiconductor substrate and is connected to the other of the source / drain. The other of the source / drain has a shorter extension height toward the rear surface side of the semiconductor substrate than the one of the source / drain, and the diameter of the rear surface side contact gradually narrows from the rear surface side and toward the front surface side of the semiconductor substrate, and matches the diameter of the other of the source / drain at a connection portion with the other of the source / drain.

Description

Semiconductor Device and Method for Manufacturing Semiconductor Device

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] Patent Document 1 listed below discloses a semiconductor device having a configuration in which the source / drain of an all-around gate transistor formed on the front surface side of a semiconductor substrate is connected to a back surface side contact of the semiconductor substrate. This Patent Document 1 shows a state in which a sacrificial layer containing a dielectric material extends from one source / drain toward the back surface side of the semiconductor substrate, and a back surface side contact penetrating the semiconductor substrate is connected to the other source / drain.

[0003] U.S. Patent Publication No. 2023 / 0093101

[0004] However, in the configuration disclosed in Patent Document 1, the effect of preventing leakage from the source / drain via the semiconductor substrate is not sufficient.

[0005] Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can improve the prevention of leakage from the source / drain via the semiconductor substrate in a configuration where the source / drain of an all-around gate transistor formed on the front surface side of a semiconductor substrate is connected to a back surface side contact of the semiconductor substrate.

[0006] To solve the above problems, the present invention provides a semiconductor device comprising: a semiconductor substrate; a full-circumference gate transistor provided on the surface side of the semiconductor substrate, with one of the source / drain extending toward the back side of the semiconductor substrate; an isolation insulating film filled in an opening penetrating the semiconductor substrate, which fills the portion of the one source / drain extending toward the back side of the semiconductor substrate; and a back-side contact provided penetrating the semiconductor substrate and connected to the other source / drain, wherein the other source / drain has a smaller extension height toward the back side of the semiconductor substrate than the one source / drain, and the diameter of the back-side contact gradually narrows from the back side to the surface side of the semiconductor substrate, and matches the diameter of the other source / drain at the connection portion with the other source / drain; and a method for manufacturing the semiconductor device.

[0007] The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can improve the prevention of leakage from the source / drain through the semiconductor substrate in a configuration in which the source / drain of a full-circumference gate transistor formed on the surface side of a semiconductor substrate is connected to contacts on the back side of the semiconductor substrate.

[0008] This is a diagram showing the configuration of the semiconductor device of the first embodiment. This is the manufacturing process diagram (1) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (2) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (3) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (4) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (5) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (6) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (7) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (8) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (9) of the semiconductor device of the first embodiment. This is the manufacturing process diagram (10) of the semiconductor device of the first embodiment. This is a diagram showing the configuration of the semiconductor device of the second embodiment. This is the manufacturing process diagram (1) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (2) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (3) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (4) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (5) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (6) of the semiconductor device of the second embodiment. This is the manufacturing process diagram (part 7) for the semiconductor device of the second embodiment.

[0009] Hereinafter, embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the embodiments described below, the same reference numerals are used for the same components, and some redundant descriptions will be omitted.

[0010] <First Embodiment> <Configuration of Semiconductor Device of the First Embodiment> Figure 1 is a diagram showing the configuration of a semiconductor device 1 of the first embodiment, and is a cross-sectional view in the gate length direction of a full-circumference gate transistor 1a having this semiconductor device 1. The full-circumference gate transistor 1a shown in Figure 1 is provided on the surface S1 side, which is one of the main surfaces of the semiconductor substrate 10. In Figure 1, the upper side of the semiconductor substrate 10 is shown as the back surface S2, and the lower side is shown as the front surface S1. Each full-circumference gate transistor 1a comprises a nanosheet laminate 13, a source / drain 18sd, a gate insulating film 19, and a gate electrode 20g.

[0011] The nanosheet laminate 13 is constructed by stacking multiple nanosheet layers 12, and is made of, for example, silicon. Each nanosheet layer 12 constitutes a semiconductor channel and is stacked with spacing between them. Each of these nanosheet layers 12 forms a GAA (Gate All Around) structure, surrounded all around by a gate electrode 20g via a gate insulating film 19. The gate electrode 20g may have a multilayer structure of two or more layers.

[0012] The source / drain 18sd are located on both sides of the gate length direction of the nanosheet laminate 13. These source / drain 18sd are formed by epitaxial growth from the semiconductor substrate 10 and the nanosheet layer 12.

[0013] One of these source / drain 18sd, source / drain 18sd1, is connected to a surface-side contact of the semiconductor substrate 10 (not shown in the illustration), and is connected to a surface-side wiring via this surface-side contact. This one source / drain 18sd1 extends toward the back surface S2 side of the semiconductor substrate 10. An insulating layer 17 is laminated on the back surface S2 side of the semiconductor substrate 10 at the one source / drain 18sd1. This insulating layer 17 is used as a mask when pattern etching the semiconductor substrate 10 in the manufacturing process of the semiconductor device 1, which will be described later.

[0014] In contrast, the other source / drain 18sd2 of the source / drain 18sd has a shorter extension height toward the back surface S2 side of the semiconductor substrate 10 than the other source / drain 18sd1. The extension height of the other source / drain 18sd2 toward the back surface side of the semiconductor substrate 10 may be as far as the surface S1 of the semiconductor substrate 10.

[0015] The semiconductor device 1 also has a separation insulating film 21 that embeds one of the source / drain 18sd, the source / drain 18sd1, and a back-side contact 22 connected to the other source / drain 18sd2.

[0016] The isolation insulating film 21 is filled into an opening 10b in the semiconductor substrate 10. The opening 10b is provided through the semiconductor substrate 10 and encloses the portion of one source / drain 18sd1 that extends toward the back surface S2 side of the semiconductor substrate 10, and the insulating layer 17. As a result, the isolation insulating film 21 filled into the opening 10b fills the portion of one source / drain 18sd1 that extends toward the back surface S2 side of the semiconductor substrate 10, and the insulating layer 17. Such an isolation insulating film 21 is exemplified by one containing a silicon oxide material, but is not limited thereto, and Low-k materials such as SiOxHy and SiCxOyHz can also be preferably used. The composition ratio (x, y, z) of these materials is not limited.

[0017] Furthermore, the back-side contact 22 is provided through the semiconductor substrate 10 and is connected to the other source / drain 18sd2 of the source / drain 18sd. The diameter of this back-side contact 22 gradually narrows from the back side S2 to the front side S1 of the semiconductor substrate 10 due to the semiconductor device manufacturing procedure described below. At the connection point with the other source / drain 18sd2, the diameter of the back-side contact 22 matches the diameter of the other source / drain 18sd2, and the other source / drain 18sd2 and the back-side contact 22 are in a continuous shape. Although not shown in the illustration here, the back-side contact 22 is further connected to back-side wiring. This back-side wiring constitutes, for example, a Backside Power Delivery Network (BSPDN).

[0018] <Method of Manufacturing a Semiconductor Device of the First Embodiment> Figures 2 to 11 are process diagrams (1) to (10) showing the manufacturing method of the semiconductor device 1 of the first embodiment described above. Hereinafter, the manufacturing method of the semiconductor device 1 of the first embodiment and the detailed configuration of each part will be explained in accordance with the manufacturing process sequence of the semiconductor device shown in Figures 2 to 11. Figures 2 to 11 are diagrams showing the cross-sectional portions corresponding to Figure 1.

[0019] First, as shown in Figure 2, a pattern of line-shaped nanosheet laminates 13 extending in the left-right direction in the drawing is formed on the upper surface S1 side of a semiconductor substrate 10, for example, made of silicon. In Figures 2 and onward, the upper side of the semiconductor substrate 10 is shown as the back surface S2, and the lower side as the front surface S1.

[0020] The nanosheet laminate 13 has a structure in which a sacrificial sheet layer 11 and a nanosheet layer 12 made of a semiconductor material are alternately stacked in this order. The sacrificial sheet layer 11 is made of a material that can be selectively etched with respect to the nanosheet layer 12 made of a semiconductor material. For example, when silicon is used as the semiconductor material constituting the nanosheet layer 12, silicon germanium is used as the sacrificial sheet layer 11.

[0021] Subsequently, a dummy gate 14 is formed in a linear shape extending in the depth direction on the drawing, and an insulating sidewall 15 is formed on the side wall of the dummy gate 14. Such dummy gates 14 and sidewalls 15 form lines that cross the nanosheet laminate 13. The dummy gate 14 is formed using, for example, polysilicon, and the sidewalls 15 are formed using, for example, SiBCN (boronated silicon carbide nitride).

[0022] Subsequently, the dummy gate 14 and sidewall 15 are used as masks to etch the line-shaped nanosheet laminate 13, and then the surface S1 layer of the semiconductor substrate 10 is etched. As a result, the nanosheet laminate 13 is patterned in an island-like manner as shown in the figure, and groove patterns 10a are formed on the surface S1 side of the semiconductor substrate 10.

[0023] Next, as shown in Figure 3, both ends of the sacrificial sheet layer 11 exposed on the side wall of the nanosheet laminate 13 are replaced with insulating inner spacers 16. In this process, first, both ends of the sacrificial sheet layer 11 are selectively thinned by isotropic etching. Then, an insulating film is deposited by isotropic deposition, and the insulating film is etched back by anisotropic etching. This leaves the insulating film sandwiched only between each nanosheet layer 12 and between the bottom nanosheet layer 12 and the semiconductor substrate 10, and the remaining insulating film is formed as the inner spacer 16.

[0024] Next, as shown in Figure 4, an insulating layer 17 is formed at the bottom of the groove pattern 10a formed on the surface S1 side of the semiconductor substrate 10, and a source / drain 18sd is formed above it. The insulating layer 17 is formed, for example, by depositing a silicon nitride film and then etching back the silicon nitride film by anisotropic etching. In this case, by adjusting the irradiation angle of the etchant, the silicon nitride film is left only at the bottom of the groove pattern 10a, and the remaining silicon nitride film becomes the insulating layer 17. The material used for the insulating layer 17 is not limited to silicon nitride, but may also be silicon oxide, aluminum oxide, silicon oxide carbide nitride, silicon oxide nitride, silicon oxide carbide, or a combination thereof. The composition ratio of each of these materials is not limited. The insulating layer 17 may also be formed from the same material as the inner spacer 16 described using Figure 3, in which case the formation of the insulating layer 17 may be carried out in the same process as the formation of the inner spacer 16.

[0025] Furthermore, the source / drain 18sd is formed by epitaxial growth from the sidewall of the semiconductor substrate 10 and the exposed surface of the nanosheet layer 12. In this case, epitaxial growth may be carried out in steps, for example, as follows: First, in the first step, a bottom-up epitaxial layer is formed in the groove pattern 10a of the semiconductor substrate 10; in the second step, a buffer epitaxial layer is formed on the exposed surface of the nanosheet layer 12; and in the third step, a main epitaxial layer is formed between the nanosheet stacks 13.

[0026] Next, as shown in Figure 5, a gate electrode 20g is formed via a gate insulating film 19 so as to cover the entire circumference of the nanosheet layer 12. In this process, first, the dummy gate 14 (see Figure 4) is removed by selective etching, and then the sacrificial sheet layer 11 (see Figure 4) between the nanosheet layers 12 is selectively etched away by etching from the exposed surface of the nanosheet laminate 13. This exposes the central part of the silicon nanosheet layer 12 around its entire circumference.

[0027] Next, a gate insulating film 19 is formed on the exposed surface of the nanosheet layer 12, and then a gate electrode 20g is formed via the gate insulating film 19. The gate electrode 20g then fills the spaces between the nanosheet layers 12, the space between the bottom nanosheet layer 12 and the semiconductor substrate 10, and the spaces between the sidewalls 15. At this time, the gate insulating film 19 is formed using a high dielectric constant film, and the gate electrode 20g is formed to contain tungsten (W). As a result, a full-circumference gate transistor 1a is obtained in which the entire circumference of the nanosheet layer 12 is surrounded by the gate electrode 20g via the gate insulating film 19.

[0028] Following the above steps, although not shown in the diagram here, an interlayer insulating film is formed to cover the entire circumference of the gate transistor 1a, and a surface-side contact is formed that is connected to one of the source / drain 18sd1 of the source / drain 18sd. Furthermore, surface-side wiring connected to the surface-side contact and gate electrode 20g, and an interlayer insulating film are formed as needed to complete the processing of the surface S1 side of the semiconductor substrate 10.

[0029] Next, as shown in Figure 6, the carrier substrate 100 is bonded to the surface S1 side of the semiconductor substrate 10 where the gate transistor 1a is formed all around, and thereafter, processing is carried out on the back surface S2 side of the semiconductor substrate 10. Note that the drawings from Figure 6 onwards are inverted vertically compared to the drawings in Figures 2 to 5. After bonding the carrier substrate 100, the semiconductor substrate 10 is thinned as needed, and then the processing on the back surface S2 side of the semiconductor substrate 10, which will be described below, is carried out.

[0030] First, as shown in Figure 7, a pattern is formed on the semiconductor substrate 10 to expose the portion of one of the source / drain 18sd1 that extends to the back surface S2 side of the semiconductor substrate 10, and the insulating layer 17. This opening 10b penetrates the semiconductor substrate 10, exposing the gate insulating film 19 and the inner spacer 16 at its bottom. This opening 10b also has an opening shape that encloses the portion of one of the source / drain 18sd1 that extends to the back surface S2 side of the semiconductor substrate 10, and the insulating layer 17.

[0031] In forming the pattern of such an opening 10b, the semiconductor substrate 10 is etched using a resist pattern (not shown here) and an insulating layer 17 as a mask. The etching is performed by anisotropic etching, such as RIE (Reactive Ion Etching). The etching is performed with the insulating layer 17 acting as a mask, preventing film loss on one of the source / drain 18sd1 while forming an opening 10b with the gate insulating film 19 and inner spacer 16 exposed at the bottom. Thus, the insulating layer 17, which functions as a mask for one of the source / drain 18sd1, is embedded in the groove pattern 10a (see Figure 2), just like the other source / drain 18sd1. Therefore, the mask made of this insulating layer 17 is formed by self-alignment.

[0032] Next, as shown in Figure 8, a separation insulating film 21 is filled into the opening 10b, and the portion of one source / drain 18sd1 that extends toward the back surface S2 side of the semiconductor substrate 10, and the insulating layer 17 are filled with the separation insulating film 21. This separation insulating film 21 is provided in contact with the gate insulating film 19 and the inner spacer 16. To form such a separation insulating film 21, first, an insulating film is deposited on the back surface S2 of the semiconductor substrate 10 so as to fill the opening 10b. Then, the insulating film is etched back until the back surface S2 of the semiconductor substrate 10 is exposed. This leaves the insulating film only inside the opening 10b, and the insulating film remaining inside the opening 10b becomes the separation insulating film 21. Such a separation insulating film 21 is made of, for example, silicon oxide.

[0033] When filling the opening 10b with the separation insulating film 21, for example, a liner film made of silicon nitride may be formed, and the insulating film made of silicon oxide may be filled into the opening 10b via the liner film. In such a case, the separation insulating film 21 in the opening 10b will include an insulating liner film made of silicon nitride material and an insulating film made of silicon oxide material whose side walls are covered by the liner film.

[0034] Next, as shown in Figure 9, a recess 10c is patterned on the back surface S2 side of the semiconductor substrate 10 to expose the insulating layer 17 laminated on the other source / drain 18sd2 of the source / drain 18sd of the all-around gate transistor 1a. This recess 10c is deeper than or equal to the depth at which the insulating layer 17 is exposed, and the semiconductor substrate 10 remains at the bottom, and the side wall of the other source / drain 18sd2 may be exposed. This recess 10c may also have a shape that includes the entire circumference of the insulating layer 17 and the other source / drain 18sd2.

[0035] In forming such a recess 10c pattern, the semiconductor substrate 10 is etched using a resist pattern (not shown in the illustration) as a mask. At this time, a recess 10c is formed with the semiconductor substrate 10 remaining at the bottom.

[0036] Next, as shown in Figure 10, the insulating layer 17 (see Figure 9) exposed within the recess 10c is selectively etched and removed.

[0037] Next, as shown in Figure 11, the other source / drain 18sd2 exposed within the recess 10c is selectively etched and removed. In this process, the portion of the other source / drain 18sd2 extending toward the back surface S2 of the semiconductor substrate 10 is removed, and the other source / drain 18sd2 is reduced in thickness to approximately the same height as the surface S1 of the semiconductor substrate 10. As a result, the recess 10c takes on a shape in which the opening diameter is gradually narrowed from the back surface S2 of the semiconductor substrate 10 toward the surface S1.

[0038] After the above steps, as shown in Figure 1, a conductive material such as a metal material is embedded in the recess 10c formed in the semiconductor substrate 10 to form a back-side contact 22 that reaches the other source / drain 18sd2. To form the back-side contact 22, first, a conductive material is deposited on the back surface S2 of the semiconductor substrate 10 so as to fill the recess 10c. Next, the conductive material is CMP polished until the back surface S2 of the semiconductor substrate 10 is exposed, leaving the conductive material only in the recess 10c, and the conductive material remaining in the recess 10c is formed as the back-side contact 22. The back-side contact 22 formed in this way has a diameter that gradually narrows from the back surface S2 side to the front surface S1 side of the semiconductor substrate 10. Furthermore, at the connection portion with the other source / drain 18sd2, the back-side contact 22 matches the diameter of the other source / drain 18sd2 and has a shape that is continuous with the other source / drain 18sd2.

[0039] After the above steps, although not shown in the diagram here, backside wiring connected to the backside contacts 22 is formed on the backside S2 side of the semiconductor substrate 10. The backside wiring constitutes, for example, a backside power delivery network (BSPDN). Subsequently, a cap insulating film is formed to cover the backside wiring to complete the semiconductor device 1.

[0040] Before filling the recess 10c with a conductive material, a procedure may be performed to form an insulating liner film on the side circumferential wall of the recess 10c. In this case, a back-side contact 22 is formed in the recess 10c, with its side walls covered by an insulating liner film. This liner film may contain, for example, a silicon nitride material such as silicon nitride.

[0041] <Effects of the First Embodiment> According to the first embodiment described above, by covering the portion of one source / drain 18sd1 of the all-around gate transistor 1a that extends to the back side of the semiconductor substrate 10 with an insulating film 21 that penetrates the semiconductor substrate 10, one source / drain 18sd1 can be completely insulated from the semiconductor substrate 10. As a result, even with a configuration that reduces the connection resistance with the back side contact 22 by connecting the other source / drain 18sd2 to the back side contact 22 in the vicinity of the nanosheet layer 12 constituting the semiconductor channel, it is possible to improve the effect of preventing source / drain leakage through the semiconductor substrate 10. Furthermore, the insulating layer 17 functions as a stressor for one source / drain 18sd1, thereby applying strain to one source / drain 18sd1 and the nanosheet layer 12 connected to one source / drain 18sd1.

[0042] <Second Embodiment> <Configuration of the Semiconductor Device of the Second Embodiment> Figure 12 is a diagram showing the configuration of the semiconductor device 2 of the second embodiment, and is a cross-sectional view in the gate length direction of the all-around gate transistor 1a of this semiconductor device 2. The difference between the semiconductor device 2 shown in Figure 12 and the semiconductor device 1 of the first embodiment (see Figure 1) is that an insulating layer 17 (see Figure 1) is not laminated on one of the source / drain 18sd1 of the source / drain 18sd of each all-around gate transistor 1a. The other configurations are the same as those of the semiconductor device 1 of the first embodiment, so their explanation is omitted here.

[0043] <Method of Manufacturing a Semiconductor Device of the Second Embodiment> Figures 13 to 19 are process diagrams (1) to (7) showing the method of manufacturing the semiconductor device 2 of the second embodiment described above. Hereinafter, the method of manufacturing the semiconductor device 2 of the second embodiment and the detailed configuration of each part will be explained in accordance with the manufacturing process sequence of the semiconductor device shown in Figures 13 to 19. Figures 13 to 19 are diagrams showing the cross-sectional portions corresponding to Figure 12 above.

[0044] First, the procedure described with reference to FIGS. 2 to 3 in the first embodiment is performed. Thereby, by etching using the line-shaped dummy gate 14 and the sidewall 15 as a mask, the nanosheet laminate 13 is patterned into an island shape, and a groove pattern 10a is formed on the surface S1 side of the semiconductor substrate 10. In addition, both ends of the sacrificial sheet layer 11 exposed on the side wall of the nanosheet laminate 13 are replaced with insulating inner spacers 16.

[0045] Next, as shown in FIG. 13, source / drains 18sd are formed in the groove pattern 10a formed on the surface S1 side of the semiconductor substrate 10. The source / drains 18sd are formed by epitaxial growth from the side wall of the semiconductor substrate 10 and the exposed surface of the nanosheet layer 12, which is the same as in the first embodiment. However, since the semiconductor substrate 10 is exposed at the bottom surface of the groove pattern 10a, epitaxial growth also occurs from the bottom surface of the groove pattern 10a, which is different from the first embodiment.

[0046] Thereafter, the steps shown in FIGS. 14 to 15 are performed in the same manner as the procedure described with reference to FIGS. 5 to 6 in the first embodiment. First, as shown in FIG. 14, a gate electrode 20g is formed via a gate insulating film 19 so as to cover the entire circumference of the nanosheet layer 12, thereby forming an all-around gate transistor 1a. Thereafter, as shown in FIG. 15, a carrier substrate 100 is bonded to the surface S1 side of the semiconductor substrate 10 where the all-around gate transistor 1a is formed. Note that the drawings after FIG. 15 are drawings that are upside down with respect to the drawing of FIG. 14.

[0047] Next, as shown in FIG. 16, an opening 10b that exposes a portion of one source / drain 18sd1 among the source / drains 18sd that extends toward the back surface S2 side of the semiconductor substrate 10 is patterned in the semiconductor substrate 10. This opening 10b penetrates through the semiconductor substrate 10, and has a configuration in which the gate insulating film 19 and the inner spacer 16 are exposed at the bottom. In addition, this opening 10b has an opening shape that encloses the portion of the one source / drain 18sd1 that extends toward the back surface S2 side of the semiconductor substrate 10.

[0048] In such pattern formation of the opening 10b, the semiconductor substrate 10 is etched using a resist pattern (not shown here) as a mask. The etching is performed by anisotropic etching such as RIE (Reactive Ion Etching).

[0049] Next, as shown in FIG. 17, the isolation insulating film 21 is filled into the opening 10b, and the portion of one source / drain 18sd1 extending toward the back surface S2 side of the semiconductor substrate 10 is embedded with the isolation insulating film 21. The formation of such an isolation insulating film 21 may be performed in the same manner as the procedure described with reference to FIG. 8 in the first embodiment.

[0050] Next, as shown in FIG. 18, a recess 10c that exposes the other source / drain 18sd2 of the source / drains 18sd of the gate-all-around transistor 1a is patterned on the back surface S2 side of the semiconductor substrate 10. This recess 10c has a depth equal to or greater than the depth at which the other source / drain 18sd2 is exposed, and a depth at which the semiconductor substrate 10 remains at the bottom, and the side wall of the other source / drain 18sd2 may be exposed. Further, the recess 10c may have a shape including the entire periphery of the other source / drain 18sd2.

[0051] In such pattern formation of the recess 10c, the semiconductor substrate 10 is etched using a resist pattern (not shown here) as a mask. At this time, the recess 10c with the semiconductor substrate 10 left at the bottom is formed.

[0052] Next, as shown in FIG. 19, the other source / drain 18sd2 exposed in the recess 10c is selectively etched and removed. At this time, the portion of the other source / drain 18sd2 extending toward the back surface S2 side of the semiconductor substrate 10 is removed, and the other source / drain 18sd2 is thinned to a height approximately equal to the front surface S1 of the semiconductor substrate 10.

[0053] After the above, as shown in Figure 12, a conductive material such as a metal material is embedded in the recess 10c formed in the semiconductor substrate 10 to form a back-side contact 22 that reaches the other source / drain 18sd2. The formation of the back-side contact 22 can be carried out in the same manner as the procedure described in the first embodiment, thereby forming a back-side contact 22 connected to the other source / drain 18sd2. The back-side contact 22 formed in this manner has a diameter that gradually narrows from the back side S2 of the semiconductor substrate 10 toward the front side S1. Furthermore, at the connection portion with the other source / drain 18sd2, the back-side contact 22 matches the diameter of the other source / drain 18sd2 and has a shape that is continuous with respect to the other source / drain 18sd2.

[0054] Although not shown in the diagrams here, the process is the same as in the first embodiment. Backside wiring connected to backside contacts is formed on the backside S2 side of the semiconductor substrate 10, and a cap insulating film is formed to cover the backside wiring to complete the semiconductor device 2.

[0055] <Effects of the Second Embodiment> Even in the second embodiment described above, by covering the portion of one source / drain 18sd1 of the all-around gate transistor 1a that extends to the back side of the semiconductor substrate 10 with an isolation insulating film 21 that penetrates the semiconductor substrate 10, one source / drain 18sd1 can be completely insulated from the semiconductor substrate 10. As a result, similar to the first embodiment, even if the connection resistance with the back side contact 22 is reduced by connecting the other source / drain 18sd2 to the back side contact 22 in the vicinity of the nanosheet layer 12 constituting the semiconductor channel, it is possible to improve the effect of preventing source / drain leakage through the semiconductor substrate 10.

[0056] 1, 2... Semiconductor device 1a... Full-circumference gate transistor 10... Semiconductor substrate 10a... Groove pattern 10b... Aperture 10c... Recess 11... Sacrificial sheet layer 12... Nanosheet layer 13... Nanosheet laminate 14... Dummy gate 15... Sidewall 16... Inner spacer 17... Insulating layer 18sd... Source / drain 18sd1... One source / drain 18sd2... The other source / drain 19... Gate insulating film 20g... Gate electrode 21... Isolation insulating film 22... Backside contact 100... Carrier substrate S1... Front surface S2... Back surface

Claims

1. A semiconductor device comprising: a semiconductor substrate; a full-circumference gate transistor provided on the surface side of the semiconductor substrate, with one of the source / drain extending toward the back side of the semiconductor substrate; an isolation insulating film filled in an opening penetrating the semiconductor substrate, which fills the portion of the one source / drain extending toward the back side of the semiconductor substrate; and a back-side contact provided penetrating the semiconductor substrate and connected to the other source / drain, wherein the other source / drain has a smaller extension height toward the back side of the semiconductor substrate than the one source / drain, and the diameter of the back-side contact gradually narrows from the back side to the surface side of the semiconductor substrate, and matches the diameter of the other source / drain at the connection portion with the other source / drain.

2. The semiconductor device according to claim 1, further comprising an insulating layer laminated on the back side of the semiconductor substrate at one of the source / drains, wherein the insulating layer is embedded in the isolation insulating film and is made of a different material from the isolation insulating film.

3. The semiconductor device according to claim 2, wherein the insulating layer has the same diameter as one of the source / drains.

4. The semiconductor device according to claim 2, wherein the all-around gate transistor comprises a nanosheet laminate formed by stacking a plurality of nanosheet layers made of a semiconductor material, and an insulating inner spacer sandwiched between the nanosheet layers, wherein the insulating layer is made of the same material as the inner spacer.

5. The semiconductor device according to claim 2, wherein the separating insulating film comprises a silicon oxide material, and the insulating layer comprises a silicon nitride material.

6. The semiconductor device according to claim 1, wherein the separating insulating film comprises an insulating liner film made of a silicon nitride material and a silicon oxide material whose side walls are covered by the liner film.

7. The semiconductor device according to claim 1, wherein the side peripheral wall of the back contact is covered with an insulating liner film.

8. A method for manufacturing a semiconductor device having a full-circumference gate transistor, comprising the steps of: patterning a linear nanosheet laminate in an island shape on the surface of a semiconductor substrate by etching from a line-shaped dummy gate and a sidewall covering the sidewall of the dummy gate, thereby stacking a plurality of nanosheet layers made of semiconductor material, and further forming a groove pattern on the surface side of the semiconductor substrate; forming sources / drains extending toward the back side of the semiconductor substrate on both sides of the nanosheet laminate by epitaxial growth from the inner wall of the groove pattern and the nanosheet layers on the semiconductor substrate; forming an opening that penetrates the semiconductor substrate while exposing the portion of one of the sources / drains that extends toward the back side of the semiconductor substrate; filling the opening with an insulating film and embedding the portion of one of the sources / drains that extends toward the back side of the semiconductor substrate with the insulating film; and forming a recess on the back side of the semiconductor substrate that exposes the other source / drain. A method for manufacturing a semiconductor device, comprising the steps of: selectively etching away the other source / drain exposed in the recess to deepen the bottom of the recess; and forming a back-side contact connected to the other source / drain in the recess.

9. The method for manufacturing a semiconductor device according to claim 8, wherein, after forming the groove pattern and before forming the source / drain, an insulating layer is formed at the bottom of the groove pattern, and in the step of forming an opening that penetrates the semiconductor substrate, the semiconductor substrate is pattern-etched using the resist pattern and the insulating layer as a mask.

10. The method for manufacturing a semiconductor device according to claim 9, wherein in the step of forming the recess on the back side of the semiconductor substrate, the semiconductor substrate is pattern-etched until at least the insulating layer is exposed, and in the step of excavating the bottom of the recess, after removing the insulating layer, the other source / drain is selectively removed to a height equivalent to that of the surface of the semiconductor substrate.

11. The method for manufacturing a semiconductor device according to claim 9, wherein the separating insulating film comprises a silicon oxide material and the insulating layer comprises a silicon nitride material.

12. The method for manufacturing a semiconductor device according to claim 8, wherein when forming an insulating layer at the bottom of the groove pattern, an insulating inner spacer is simultaneously sandwiched between the nanosheet layers of the nanosheet laminate.

13. The method for manufacturing a semiconductor device according to claim 8, wherein an insulating liner film is formed to cover the inner wall of the opening before filling the opening with a separating insulating film.

14. The method for manufacturing a semiconductor device according to claim 8, wherein the slender peripheral wall of the recess is covered with an insulating liner film before forming the back-side contact connected to the other source / drain in the recess.

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