Semiconductor device and method for manufacturing semiconductor device

Abstract

The present invention is a semiconductor device comprising: a semiconductor substrate; a gate-all-around transistor provided on a top surface side of the semiconductor substrate; a back surface-side contact provided through the semiconductor substrate and connected to a first source / drain among the sources / drains of the gate-all-around transistor; and an isolation insulating film extending from a second source / drain of the sources / drains to the back surface side of the semiconductor substrate. The back surface-side contact has a diameter that becomes gradually smaller from the back surface side of the semiconductor substrate toward the front surface side and that is equal to the diameter of the first source / drain at a junction with the first source / drain. The isolation insulating film has, at a junction with the second source / drain, a diameter large enough to encompass the second source / drain and is joined to the rear surface-side contact at least at a position closer to the back surface side of the semiconductor substrate than the junction with the second source / drain.

Description

Semiconductor device and method for manufacturing semiconductor device

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] Patent Document 1 below discloses a semiconductor device having a configuration in which the source / drain of an all-around gate transistor formed on the front surface side of a semiconductor substrate is connected to a back surface side contact of the semiconductor substrate. This Patent Document 1 shows a state in which a sacrificial layer containing a dielectric material extends from the second source / drain toward the back surface side of the semiconductor substrate, and the back surface side contact penetrating the semiconductor substrate is connected to the first source / drain.

[0003] U.S. Patent Publication No. 2023 / 0093101

[0004] However, in the configuration disclosed in Patent Document 1, the effect of preventing leakage from the source / drain through the semiconductor substrate was not sufficient.

[0005] Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can improve the prevention of leakage from the source / drain through the semiconductor substrate in a configuration where the source / drain of an all-around gate transistor formed on the front surface side of a semiconductor substrate is connected to a back surface side contact of the semiconductor substrate.

[0006] To solve the above problems, the present invention provides a semiconductor device comprising: a semiconductor substrate; a full-circumference gate transistor provided on the surface side of the semiconductor substrate; a back-side contact provided through the semiconductor substrate and connected to a first source / drain of the source / drain of the full-circumference gate transistor; and an isolation insulating film extending from a second source / drain of the source / drain to the back side of the semiconductor substrate, wherein the diameter of the back-side contact gradually narrows from the back side to the surface side of the semiconductor substrate, and at the connection portion with the first source / drain it matches the diameter of the first source / drain; the isolation insulating film has a diameter that encloses the second source / drain at the junction with the second source / drain, and is bonded to the back-side contact at least on the back side of the semiconductor substrate beyond the junction with the second source / drain; and a method for manufacturing a semiconductor device.

[0007] The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can improve the prevention of leakage from the source / drain through the semiconductor substrate in a configuration in which the source / drain of a full-circumference gate transistor formed on the surface side of a semiconductor substrate is connected to contacts on the back side of the semiconductor substrate.

[0008] This is a diagram showing the configuration of the semiconductor device of the embodiment. This is the manufacturing process diagram (1) of the semiconductor device of the embodiment. This is the manufacturing process diagram (2) of the semiconductor device of the embodiment. This is the manufacturing process diagram (3) of the semiconductor device of the embodiment. This is the manufacturing process diagram (4) of the semiconductor device of the embodiment. This is the manufacturing process diagram (5) of the semiconductor device of the embodiment. This is the manufacturing process diagram (6) of the semiconductor device of the embodiment. This is the manufacturing process diagram (7) of the semiconductor device of the embodiment. This is the manufacturing process diagram (8) of the semiconductor device of the embodiment. This is the manufacturing process diagram (9) of the semiconductor device of the embodiment. This is the manufacturing process diagram (10) of the semiconductor device of the embodiment. This is the manufacturing process diagram (11) of the semiconductor device of the embodiment. This is the manufacturing process diagram (12) of the semiconductor device of the embodiment. This is the manufacturing process diagram (13) of the semiconductor device of the embodiment. This is the manufacturing process diagram (14) of the semiconductor device of the embodiment. This is the manufacturing process diagram (15) of the semiconductor device of the embodiment.

[0009] Hereinafter, embodiments to which the present invention is applied will be described in detail, based on the drawings, in the order of the configuration of the semiconductor device and the method for manufacturing the semiconductor device. In the following description, the same reference numerals will be used to denote the same components.

[0010] <<Configuration of Semiconductor Device>> Figure 1 is a diagram showing the configuration of a semiconductor device 1 according to an embodiment, and is a cross-sectional view in the gate length direction of a full-circumference gate transistor 1a having this semiconductor device 1. The full-circumference gate transistor 1a shown in Figure 1 is provided on the surface S1 side, which is one of the main surfaces of a semiconductor substrate 10 made of silicon. In Figure 1, the upper side of the semiconductor substrate 10 is shown as the back surface S2, and the lower side is shown as the front surface S1. Each full-circumference gate transistor 1a comprises a nanosheet laminate 13, a source / drain 19sd, a gate insulating film 20, and a gate electrode 21g.

[0011] The nanosheet laminate 13 has a structure in which multiple nanosheet layers 12 are stacked, and is made of, for example, silicon. Each nanosheet layer 12 constitutes a semiconductor channel and is stacked with spacing between them. These nanosheet layers 12 form a GAA (Gate All Around) structure in which the entire circumference is surrounded by a gate electrode 21g via a gate insulating film 20. The gate electrode 21g may have a multilayer structure of two or more layers.

[0012] The source / drain 19sd are positioned on both sides of the gate length direction of the nanosheet laminate 13. These source / drain 19sd are formed by epitaxial growth from the nanosheet layer 12. The source / drain 19sd also contain p-type or n-type impurities corresponding to the conductivity type of each full-circumference gate transistor 1a. Such source / drains are, as an example, made of silicon germanium containing p-type or n-type impurities.

[0013] The semiconductor device 1 having the all-around gate transistor 1a described above also has a back-side contact 24 and an isolation insulating film 26.

[0014] The isolation insulating film 26 extends from the second source / drain 19sd2 of the source / drain 19sd to the back surface S2 side of the semiconductor substrate 10. The second source / drain 19sd2 is connected to a surface-side contact (not shown) formed on the front surface S1 side of the semiconductor substrate 10. Such an isolation insulating film 26 fills the second opening 10c provided in the semiconductor substrate 10.

[0015] The isolation insulating film 26 has a diameter that encloses the second source / drain 19sd2 and is bonded to the back-side contact 24 at least on the back-side S2 side of the semiconductor substrate 10, beyond the junction with the second source / drain 19sd2. Such an isolation insulating film 26 is composed of a silicon oxide material.

[0016] The back-side contact 24 is connected to the first source / drain 19sd1 of the source / drain 19sd, and is connected to the back-side wiring, which is not shown in the illustration. The back-side wiring constitutes, for example, a Backside Power Delivery Network (BSPDN). Such a back-side contact 24 is provided penetrating the semiconductor substrate 10. The back-side contact 24 is made of a conductive material such as metal that fills the first opening 10b provided in the semiconductor substrate 10 with the first source / drain 19sd1 as its bottom.

[0017] The diameter of the back-side contact 24 gradually narrows from the back side S2 to the front side S1 of the semiconductor substrate 10, due to the semiconductor manufacturing procedure described below. Furthermore, at the connection between the back-side contact 24 and the first source / drain 19sd1, the back-side contact 24 and the first source / drain 19sd1 are connected without any misalignment, and their diameters either match or the diameter of the back-side contact 24 may be larger.

[0018] ≪Method of Manufacturing a Semiconductor Device≫ Figures 2 to 16 are process diagrams (1) to (15) showing the method of manufacturing the semiconductor device 1 of the embodiment described above. Hereinafter, the method of manufacturing the semiconductor device 1 of the embodiment and the detailed configuration of each part will be explained in accordance with the manufacturing process sequence of the semiconductor device shown in Figures 2 to 16. Figures 2 to 16 are diagrams showing the cross-sectional portions corresponding to Figure 1.

[0019] First, as shown in Figure 2, a pattern of line-shaped nanosheet laminates 13 extending in the left-right direction in the drawing is formed on the upper surface S1 side of a semiconductor substrate 10, for example, made of silicon. In Figures 2 to 6, the upper side of the semiconductor substrate 10 is shown as the surface S1, and the lower side as the back surface S2.

[0020] The nanosheet laminate 13 has a structure in which sacrificial sheet layers 11 and nanosheet layers 12 made of semiconductor material are alternately stacked in this order. The sacrificial sheet layer 11 is made of a material that can be selectively etched with respect to the nanosheet layers 12 made of semiconductor material. For example, when silicon is used as the semiconductor material constituting the nanosheet layer 12, silicon germanium is used as the sacrificial sheet layer 11.

[0021] Next, a dummy gate 14 is formed in a linear shape extending in the depth direction on the drawing, and an insulating sidewall 15 is formed on the side wall of the dummy gate 14. Such dummy gates 14 and sidewalls 15 form lines that cross the nanosheet laminate 13. The dummy gate 14 is formed using, for example, polysilicon, and the sidewalls 15 are formed using, for example, SiBCN (boronated silicon carbide nitride).

[0022] Subsequently, the dummy gate 14 and sidewall 15 are used as masks to etch the line-shaped nanosheet laminate 13, and then the semiconductor substrate 10 is etched from the surface S1 side. As a result, the nanosheet laminate 13 is patterned in an island-like manner as shown in the figure, and groove patterns 10a are formed on the surface S1 side of the semiconductor substrate 10.

[0023] Next, as shown in Figure 3, a bottom-up layer 16 is formed to fill the groove pattern 10a of the semiconductor substrate 10, and then a cap layer 17 is formed to cover the surface of the bottom-up layer 16. The bottom-up layer 16 is made of a material that can be selectively etched from the semiconductor substrate 10, and is made of, for example, silicon germanium with a germanium content exceeding 10 at%. Such a bottom-up layer 16 is formed by epitaxial growth from the inner wall of the groove pattern 10a.

[0024] The cap layer 17 is a layer used as a stopper when etching the bottom-up layer 16 from the back surface S2 side of the semiconductor substrate 10 in subsequent processes, and contains silicon. Such a cap layer 17 is made of, for example, silicon or silicon germanium. The silicon may be free of impurities, or contain n-type or p-type impurities. The silicon germanium is made of a material with a lower germanium concentration than the source / drain 19sd and the bottom-up layer 16, and a higher etching selectivity than the source / drain 1sd and the bottom-up layer 16. Such a cap layer 17 is formed with a film thickness of, for example, about 4 nm, and is formed with a surface height of the same size as or less than the surface S1 of the semiconductor substrate 10. Such a cap layer 17 is formed by epitaxial growth from the side walls of the bottom-up layer 16 and the groove pattern 10a.

[0025] Next, as shown in Figure 4, both ends of the sacrificial sheet layer 11 exposed on the side wall of the nanosheet laminate 13 are replaced with insulating inner spacers 18. In this process, first, both ends of the sacrificial sheet layer 11 are selectively thinned by isotropic etching. Then, an insulating film is formed by isotropic deposition, and the insulating film is etched back by anisotropic etching. This leaves the insulating film sandwiched only between the nanosheet layers 12 and between the bottom nanosheet layer 12 and the semiconductor substrate 10, and the remaining insulating film is formed as the inner spacer 18. Note that the formation of the inner spacer 18 may be performed before the formation of the bottom-up layer 16 or before the formation of the cap layer 17, provided that it is performed after the formation of the groove pattern 10a as described in Figure 2.

[0026] Next, as shown in Figure 5, source / drain 19sd are formed on both sides of the exposed surface of the nanosheet laminate 13. At this time, each source / drain 19sd containing p-type or n-type impurities is formed by epitaxial growth from the exposed surface of the nanosheet layer 12 and the surface of the cap layer 17. The formation of each conductivity type of source / drain 19sd is carried out with other areas covered by a resist pattern. The source / drain 19sd formed here is made of a material having an etching selectivity ratio with the cap layer 17, for example, silicon germanium.

[0027] Next, as shown in Figure 6, a gate electrode 21g is formed via a gate insulating film 20 so as to cover the entire circumference of the nanosheet layer 12. In this process, first, the dummy gate 14 (see Figure 5) is removed by selective etching, and then the sacrificial sheet layer 11 (see Figure 5) between the nanosheet layers 12 is selectively etched away by etching from the exposed surface of the nanosheet laminate 13. This exposes the central part of the silicon nanosheet layer 12 around its entire circumference.

[0028] Subsequently, a gate insulating film 20 is formed on the exposed surface of the nanosheet layer 12, and then a gate electrode 21g is formed via the gate insulating film 20. The gate electrode 21g then fills the spaces between the nanosheet layers 12, the space between the bottom nanosheet layer 12 and the semiconductor substrate 10, and the spaces between the sidewalls 15. In this process, the gate insulating film 20 is formed using a high dielectric constant film, and the gate electrode 21g is formed using, for example, tungsten (W). This results in a full-circumference gate transistor 1a in which the entire circumference of the nanosheet layer 12 is surrounded by the gate electrode 21g via the gate insulating film 20.

[0029] Following the above steps, although not shown in the diagram here, an interlayer insulating film is formed to cover the entire gate transistor 1a, and a surface-side contact is formed that is connected to the second source / drain 19sd2 of the source / drain 19sd. Furthermore, surface-side wiring connected to the surface-side contact and gate electrode 21g, and an interlayer insulating film are formed as needed to complete the processing of the surface S1 side of the semiconductor substrate 10.

[0030] Next, as shown in Figure 7, the carrier substrate 100 is bonded to the surface S1 side of the semiconductor substrate 10 where the gate transistor 1a is formed all around, and thereafter, processing is carried out on the back surface S2 side of the semiconductor substrate 10. Note that the drawings from Figure 7 onwards are inverted vertically compared to the drawings in Figures 2 to 6. After bonding the carrier substrate 100, the semiconductor substrate 10 is thinned as needed, and then the processing on the back surface S2 side of the semiconductor substrate 10, which will be described below, is carried out.

[0031] First, as shown in Figure 8, an insulating film 22 is formed on the back surface S2 of the semiconductor substrate 10, and then a hard mask film 23 is formed on top of it. The insulating film 22 is made of, for example, silicon oxide, and the hard mask film 23 is made of silicon nitride.

[0032] Next, as shown in Figure 9, a first opening 10b is formed in the hard mask film 23, the insulating film 22, and the semiconductor substrate 10 to expose the bottom-up layer 16 laminated on the first source / drain 19sd1 of the source / drain 19sd. Here, the first source / drain 19sd1 is the source / drain 19sd that is not connected to the surface-side contact. The first opening 10b formed here penetrates the hard mask film 23 and the insulating film 22, exposing the bottom-up layer 16 and the semiconductor substrate 10 at its bottom. The first opening 10b is also formed with a diameter large enough to enclose the bottom-up layer 16 laminated on the first source / drain 19sd1 at its bottom surface and to take into account the contact resistance of the back-side contact to be formed later.

[0033] Such first openings 10b are formed by anisotropic etching, such as reactive ion etching (RIE), using a resist pattern (not shown in the illustration) as a mask. During this process, etching is carried out so that the bottom-up layer 16 remains as an etch stopper.

[0034] Next, as shown in Figure 10, the bottom-up layer 16 (see Figure 9) exposed within the first opening 10b is selectively removed from the semiconductor substrate 10, thereby excavating the bottom of the first opening 10b. At this time, the cap layer 17 is used as an etching stopper to etch the bottom-up layer 16, thereby exposing the cap layer 17 at the bottom of the first opening 10b. As a result, the first opening 10b takes on a shape in which the opening diameter is gradually narrowed from the back surface S2 to the front surface S1 side of the semiconductor substrate 10.

[0035] Next, as shown in Figure 11, the cap layer 17 (see Figure 10) exposed at the bottom of the first opening 10b is selectively removed. This exposes the first source / drain 19sd1 at the bottom of the first opening 10b. At this time, the cap layer 17 is selectively removed. This suppresses the widening of the bottom of the first opening 10b, makes the opening diameter of the first opening 10b match the diameter of the first source / drain 19sd1, and maintains the distance between the first opening 10b and the gate insulating film 20 and gate electrode 21g. Note that the opening diameter of the first opening 10b may be wider than the diameter of the first source / drain 19sd1.

[0036] Although a configuration in which a cap layer 17 is laminated on the source / drain 19sd has been described here, a configuration without a cap layer 17 is also possible. In such a configuration, the first source / drain 19sd1 can be exposed by removing the bottom-up layer 16 at the bottom of the first opening 10b.

[0037] Next, as shown in Figure 12, the first opening 10b, formed with the first source / drain 19sd1 as its bottom surface, is filled with a conductive material such as a metal material to form a back-side contact 24 that reaches the first source / drain 19sd1. To form the back-side contact 24, first, a conductive material is deposited on the hard mask film 23 so as to fill the first opening 10b. Then, the conductive material is CMP polished until the hard mask film 23 is exposed, leaving the conductive material only inside the first opening 10b, and the conductive material remaining inside the first opening 10b is formed as the back-side contact 24.

[0038] Before filling the first opening 10b with a conductive material, a procedure may be performed to form an insulating liner film on the side circumferential wall of the first opening 10b. In this case, a back-side contact 24 is formed inside the first opening 10b, with its side walls covered by an insulating liner film. This liner film contains, for example, a silicon nitride material such as silicon nitride. However, when forming the separation insulating film described later, if an insulating liner film is formed in a preceding step, it is not necessary to form a liner film covering the side walls of the first opening 10b.

[0039] The back-side contact 24 formed as described above has a diameter that gradually narrows from the back side S2 of the semiconductor substrate 10 toward the front side S1. Furthermore, this back-side contact 24 has a diameter that matches or is slightly wider than the source / drain 19sd2, ensuring a sufficient distance from the gate insulating film 20 and the gate electrode 21g. This improves the prevention of short circuits between the first source / drain 19sd1 and the gate electrode 21g via the back-side contact 24. Moreover, the back-side contact 24 formed by embedding the first opening 10b has a diameter of sufficient size considering the contact resistance. Note that the opening diameter of the first opening 10b may be wider than the diameter of the first source / drain 19sd1.

[0040] Next, as shown in Figure 13, a protective insulating film 25 is formed to cover the back-side contact 24 and the hard mask film 23. For example, silicon oxide is used for the protective insulating film 25.

[0041] Next, as shown in Figure 14, a second opening 10c is formed in the protective insulating film 25, hard mask film 23, insulating film 22, and semiconductor substrate 10 to expose the bottom-up layer 16 laminated on the second source / drain 19sd2 of the source / drain 19sd. The second source / drain 19sd2 is connected to the surface-side contact. The second opening 10c formed here has a configuration in which the bottom-up layer 16 and semiconductor substrate 10 are exposed at the bottom. The second opening 10c also has an opening shape that encloses the bottom-up layer 16 laminated on the second source / drain 19sd2 at its bottom surface, and has an opening diameter that is slightly larger than the diameter of the bottom-up layer 16. The formation of such a second opening 10c is carried out in the same procedure as the formation of the first opening 10b described with reference to Figure 9.

[0042] Next, as shown in Figure 15, the bottom-up layer 16 (see Figure 14) exposed within the second opening 10c is selectively removed from the semiconductor substrate 10, thereby excavating the bottom of the second opening 10c. At this time, the cap layer 17 is used as an etching stopper to etch the bottom-up layer 16, exposing the cap layer 17 at the bottom of the second opening 10c. As a result, the second opening 10c takes on a shape in which the opening diameter is gradually narrowed from the back surface S2 to the front surface S1 of the semiconductor substrate 10. It is preferable that the etching of the bottom-up layer 16 here be carried out by a method that causes little damage to the etching surface, such as wet or dry chemical etching.

[0043] Next, as shown in Figure 16, the cap layer 17 (see Figure 15) exposed at the bottom of the second opening 10c is selectively removed by isotropic etching. At the same time, the semiconductor substrate 10 exposed on the inner wall of the second opening 10c is etched back by isotropic etching to widen the opening diameter at the bottom of the second opening 10c. In this case, the bottom of the second opening 10c may be widened until it reaches the already formed back-side contact 24.

[0044] Such selective etching of the cap layer 17 and the semiconductor substrate 10 may be wet etching using TMAH (tetramethylammonium hydroxide) as an etchant, or isotropic dry etching.

[0045] Note that the selective etching of the semiconductor substrate 10 is not limited to stopping in a state where the second opening 10c reaches the large-diameter portion of the back-side contact 24 as illustrated, and the etching may be further continued. In this case, the opening shape of the second opening 10c also becomes a shape that widens from the back surface side toward the front surface side of the semiconductor substrate 10.

[0046] Further, in a configuration where the cap layer 17 is not formed, the second source / drain 19sd2 is exposed by removing the bottom-up layer 16 at the bottom of the second opening 10c, and then selective etching of the semiconductor substrate 10 is performed to widen the opening diameter of the second opening 10c.

[0047] After the above steps, as shown in FIG. 1, the inside of the second opening 10c with the second source / drain 19sd2 exposed on the bottom surface is filled with the isolation insulating film 26. Such an isolation insulating film 26 extends from the second source / drain 19sd2 toward the back surface S2 side of the semiconductor substrate 10. In addition, the isolation insulating film 26 has a diameter slightly larger than that of the source / drain 19sd1 at the junction with the source / drain 19sd1. However, in the step of widening the second opening 10c described with reference to FIG. 16, if the selective etching of the semiconductor substrate 10 is continued even after the second opening 10c reaches the large-diameter portion of the back-side contact 24, the isolation insulating film 26 has a diameter that widens from the back surface S2 side toward the front surface S1 side of the semiconductor substrate 10.

[0048] In forming the isolation insulating film 26 that fills the second opening 10c, first, an insulating film is deposited over the protective insulating film 25 (see FIG. 16) so as to fill the second opening 10c. At this time, isotropic deposition is performed so that the entire interior of the second opening 10c, whose intermediate portion is widened, is filled with the insulating film. Thereafter, the insulating film and the protective insulating film 25 are polished by CMP until the hard mask film 23 and the backside contact 24 are exposed. As a result, the insulating film is left only inside the second opening 10c, and the insulating film remaining inside the second opening 10c is defined as the isolation insulating film 26.

[0049] Such an isolation insulating film 26 includes a silicon oxide material such as silicon oxide. More specifically, the isolation insulating film 26 is preferably formed such that the dielectric constant decreases toward the outer periphery. In this case, when the insulating film is deposited over the protective insulating film 25 (see FIG. 16) so as to fill the second opening 10c, the composition ratio of carbon, oxygen, hydrogen, etc. in the silicon oxide material is changed so that the dielectric constant of the insulating film increases from the initial stage to the late stage of deposition. By reducing the dielectric constant on the outer peripheral side of the isolation insulating film 26 in this manner, the effect of suppressing leakage from the backside contact 24 can be enhanced.

[0050] When filling the interior of the second opening 10c with the insulating film, a liner film made of, for example, silicon nitride may be deposited, and the interior of the second opening 10c may be filled with the insulating film via the liner film. In such a case, the isolation insulating film 26 inside the second opening 10c includes an insulating liner film using a silicon nitride material, and an insulating film made of a silicon oxide material whose periphery is covered by the liner film.

[0051] After the above steps, although illustration is omitted here, backside wiring connected to the backside contact 24 is formed on the back surface S2 side of the semiconductor substrate 10. The backside wiring constitutes, for example, a Backside Power Delivery Network (BSPDN). Thereafter, a cap insulating film is formed so as to cover the backside wiring, whereby the semiconductor device 1 is completed.

[0052] ≪Effects of the Embodiment≫ According to the embodiment described above, the isolation insulating film 26 extending from the second source / drain 19sd2 of the all-around gate transistor 1a toward the semiconductor substrate 10 encloses the second source / drain 19sd at the junction with the second source / drain 19sd2, and is joined to the back-side contact 24 on the back surface S2 side of the semiconductor substrate 10 from the junction with the second source / drain 19sd2. As a result, by connecting the first source / drain 19sd1 to the back-side contact 24 in the vicinity of the nanosheet layer 12 constituting the semiconductor channel, it is possible to improve the prevention of source / drain leakage through the semiconductor substrate 10, even in a configuration that reduces the connection resistance with the back-side contact 24.

[0053] Furthermore, in the manufacturing procedure for the semiconductor device 1, by forming the back-side contact 24 and then forming the separating insulating film 26, it is possible to form a back-side contact 24 having a sufficiently large diameter regardless of the expansion of the widened portion A1 of the separating insulating film 26.

[0054] 1... Semiconductor device 1a... Full-circumference gate transistor 10... Semiconductor substrate 10a... Groove pattern 10b... First opening 10c... Second opening 11... Sacrificial sheet layer 12... Nanosheet layer 13... Nanosheet laminate 14... Dummy gate 15... Sidewall 16... Bottom-up layer 17... Cap layer 18... Inner spacer 19sd... Source / drain 19sd1... First source / drain 19sd2... Second source / drain 20... Gate insulating film 21g... Gate electrode 22... Insulating film 23... Hard mask film 24... Backside contact 25... Protective insulating film 26... Separating insulating film 100... Carrier substrate A1... Widened section S1... Front surface S2... Back surface

Claims

1. A semiconductor device comprising: a semiconductor substrate; a full-circumference gate transistor provided on the surface side of the semiconductor substrate; a back-side contact provided through the semiconductor substrate and connected to a first source / drain of the source / drain of the full-circumference gate transistor; and an isolation insulating film extending from a second source / drain of the source / drain to the back side of the semiconductor substrate, wherein the diameter of the back-side contact gradually narrows from the back side to the front side of the semiconductor substrate, and at the connection portion with the first source / drain it matches the diameter of the first source / drain; and the isolation insulating film has a diameter that encloses the second source / drain at the junction with the second source / drain, and is bonded to the back-side contact at least on the back side of the semiconductor substrate beyond the junction with the second source / drain.

2. The semiconductor device according to claim 1, wherein the isolation insulating film has a widened portion with a larger diameter on the back side of the semiconductor substrate than on the front side of the semiconductor substrate, and is bonded to the back side contact at the widened portion.

3. The semiconductor device according to claim 1, wherein the isolation insulating film has a diameter that widens from the back side to the front side of the semiconductor substrate.

4. The semiconductor device according to claim 1, wherein the isolation insulating film has a configuration in which the dielectric constant decreases toward the outer periphery.

5. The semiconductor device according to claim 1, wherein the separating insulating film comprises an insulating liner film made of a silicon nitride material and a silicon oxide material whose side walls are covered by the liner film.

6. The semiconductor device according to claim 1, wherein the side peripheral wall of the back contact is covered with an insulating liner film, and the separating insulating film is bonded to the back contact via the insulating liner film.

7. A process of patterning a linear nanosheet laminate in an island shape on the surface of a semiconductor substrate by etching from a linear dummy gate and a sidewall covering the sidewall of the dummy gate, thereby stacking multiple nanosheet layers made of semiconductor material, and further forming a groove pattern on the surface side of the semiconductor substrate; forming a bottom-up layer within the groove pattern by epitaxial growth from the semiconductor substrate; forming an insulating inner spacer between the nanosheet layers; forming sources / drains on both sides of the nanosheet laminate on the bottom-up layer by epitaxial growth from the nanosheet layers; covering the entire circumference of the nanosheet layer with a gate electrode via a gate insulating film after forming the sources / drains; patterning a first opening on the semiconductor substrate to expose the bottom-up layer stacked on the first source / drain, and selectively removing the bottom-up layer within the first opening to expose the first source / drain at the bottom of the first opening. A method for manufacturing a semiconductor device, comprising the steps of: filling the first opening with a conductive material to form a back-side contact connected to the first source / drain; patterning a second opening on the semiconductor substrate to expose a bottom-up layer laminated on the second source / drain among the sources / drains, selectively etching and removing the bottom-up layer within the second opening to expose the second source / drain at the bottom of the second opening; widening the second opening to reach the back-side contact by selective etching of the semiconductor substrate exposed on the side wall of the second opening; and filling the second opening with an insulating film to form an isolation insulating film extending from the second source / drain toward the back side of the semiconductor substrate.

8. The method for manufacturing a semiconductor device according to claim 7, wherein the diameter of the second opening is widened by expanding the second opening, thereby widening the diameter of the second opening from the back side to the front side of the semiconductor substrate.

9. The method for manufacturing a semiconductor device according to claim 7, wherein an insulating liner film is formed to cover the inner wall of the second opening before filling the inside of the second opening with an insulating film to form the separating insulating film.

10. The method for manufacturing a semiconductor device according to claim 7, wherein the side walls of the first opening are covered with an insulating liner film before the first opening is filled with a conductive material.

11. A method for manufacturing a semiconductor device according to claim 7, comprising the steps of forming a cap layer in the groove pattern by epitaxial growth from the semiconductor substrate and the bottom-up layer after forming the bottom-up layer and before forming the source / drain, in the step of exposing the first source / drain, the bottom-up layer and the cap layer in the first opening are sequentially and selectively etched off to expose the first source / drain at the bottom of the first opening, and in the step of exposing the second source / drain, the bottom-up layer in the second opening is selectively etched off to expose the cap layer at the bottom of the second opening, the exposed cap layer is etched to expose the second source / drain, and the semiconductor substrate exposed on the side wall of the second opening is etched to widen the second opening.

12. The method for manufacturing a semiconductor device according to claim 11, wherein the diameter of the first opening is maintained when etching off the cap layer exposed at the bottom of the first opening.

13. The method for manufacturing a semiconductor device according to claim 11, wherein the bottom-up layer comprises silicon germanium, the source / drain comprises silicon germanium, and the cap layer comprises silicon, wherein the cap layer is made of a material having a lower germanium concentration than the source / drain and the bottom-up layer, and a higher etching selectivity than the source / drain and the bottom-up layer.

14. The method for manufacturing a semiconductor device according to claim 7, wherein the isolation insulating film comprises a silicon oxide material.

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