Semiconductor device and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device comprising: a substrate having a trench-type element isolation on one main surface side; a gate-all-around transistor that is arranged on the one main surface side of the substrate and isolated by the trench-type element isolation; a rear-surface-side wiring that is arranged on the other main surface side of the substrate; a dielectric isolation film that is arranged between the substrate and a nanosheet laminate constituting the gate-all-around transistor; a rear-surface-side contact that is arranged in a connection hole penetrating the substrate, and that connects the rear-surface-side wiring with one of a source and a drain of the gate-all-around transistor; and a sacrificial film that is arranged between the substrate and the other of the source and the drain of the gate-all-around transistor. In the connection hole in which the rear-surface-side contact is arranged, a part of an inner wall is constituted by the trench-type element isolation and the dielectric isolation film.

Description

Semiconductor device and method for manufacturing semiconductor device

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] As a technique related to a method for forming a back-side contact in a semiconductor device using a nanosheet laminate, there is a technique described in Patent Document 1 below. This Patent Document 1 describes a procedure of exposing the back surface of an epitaxial placeholder, removing the epitaxial placeholder to form a trench, and forming a back-side contact in the trench, in the patterning step of the back-side contact. The back-side contact formed in this manner is connected to the epitaxial source / drain formed above the epitaxial placeholder.

[0003] U.S. Patent Publication No. 2024 / 0429103

[0004] Here, the epitaxial placeholder to be replaced with the back-side placeholder is epitaxially grown in a deep groove formed in the semiconductor layer between the nanosheet laminates before the formation of the epitaxial source / drain, so its composition is unstable. As a result, in the etching for removing the epitaxial placeholder from the back surface, it is difficult to secure etching selectivity of the epitaxial placeholder with respect to the epitaxial source / drain. In addition, since the groove in which the epitaxial placeholder is formed has a small opening width, the back-side contact formed by replacing the epitaxial placeholder has a high resistance value.

[0005] Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the resistance of a back contact connected to the source / drain of an all-around gate transistor using a nanosheet laminate.

[0006] To achieve this objective, the present invention provides a semiconductor device comprising: a substrate having groove-type element isolation on one main surface side; a full-circumference gate transistor disposed on one main surface side of the substrate separated by the groove-type element isolation; back-side wiring disposed on the other main surface side of the substrate; a dielectric isolation film disposed between the nanosheet laminate constituting the full-circumference gate transistor and the substrate; a back-side contact disposed in a connection hole penetrating the substrate and connecting one of the source / drain of the full-circumference gate transistor to the back-side wiring; and a sacrificial film disposed between the other of the source / drain of the full-circumference gate transistor and the substrate, wherein the connection hole in which the back-side contact is disposed has an inner wall partly formed by the groove-type element isolation and the dielectric isolation film. The present invention also provides a method for manufacturing such a semiconductor device.

[0007] The present invention provides a semiconductor device and a method for manufacturing a semiconductor device that can reduce the resistance of the back surface contacts connected to the source / drain of a full-circumference gate transistor using a nanosheet laminate.

[0008] This is a cross-sectional view of the main part of the semiconductor device according to the embodiment. This is a process diagram (1) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (2) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (3) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (4) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (5) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (6) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (7) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (8) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (9) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (10) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (11) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (12) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (13) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (14) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (15) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (16) showing the manufacturing method of the semiconductor device according to the embodiment. This is a process diagram (17) showing the manufacturing method of the semiconductor device according to the embodiment.

[0009] ≪Semiconductor Device≫ Figure 1 is a cross-sectional view showing the configuration of a semiconductor device 1 according to an embodiment, and shows the cross-section of the source / drain 20sd portion in the gate width direction [Wg] and the cross-section in the gate length direction [Lg] of the all-around gate transistor 1a of the semiconductor device 1. The semiconductor device 1 has a plurality of all-around gate transistors 1a on one main surface side (front side) of the insulating layer 104, and back side wiring 106 on the other main surface side (back side) of the insulating layer 104.

[0010] Here, the insulating layer 104 is provided in place of the first substrate used as a carrier substrate in the manufacture of the semiconductor device 1, and functions as a substrate on which the all-around gate transistor 1a is arranged. Such an insulating layer 104 has a groove-type element separator 14 on one main surface side on which the all-around gate transistor 1a is provided. The groove-type element separator 14 is composed of a liner layer 14a that covers the inner wall of the groove and an insulating material 14b that fills the inside of the groove via the liner layer 14a.

[0011] Each all-around gate transistor 1a is positioned on one main surface side of the insulating layer 104 separated by a groove-type element separator 14. Such all-around gate transistors 1a are constructed using a nanosheet laminate 13, which is made of stacked nanosheet layers 12 made of silicon, for example. A bottom dielectric isolation film (BDI) 10 is placed at the bottom surface of the nanosheet laminate 13, between the nanosheet laminate 13 and the insulating layer 104 which serves as the substrate. Each nanosheet layer 12 is stacked with spacing on the dielectric isolation film 10 provided on the insulating layer 104, and its entire circumference is surrounded by a gate electrode 23g via a gate insulating film 22, forming a GAA (Gate All Around) structure. The gate electrode 23g may have a multilayer structure of two or more layers.

[0012] Furthermore, each full-circumference gate transistor 1a has source / drain 20sd epitaxially grown from the nanosheet layer 12 on both sides of the gate length direction [Lg] of the nanosheet layer 12. These source / drain 20sd are either a first source / drain 20sd1 connected to the surface wiring 26, or a second source / drain 20sd2 connected to the back wiring 106.

[0013] Of these, the first source / drain 20sd1 is placed on top of a sacrificial film 19 located in a position surrounded by the dielectric isolation film 10 and the groove-type element isolation 14. In other words, the sacrificial film 19 is placed between the first source / drain 20sd1 and the insulating layer 104. This first source / drain 20sd1 is connected to the surface wiring 26 via a surface contact 25 on the side opposite to the sacrificial film 19.

[0014] On the other hand, the second source / drain 20sd2 is positioned on top of the back-side contact 105, which is located in a position surrounded by the dielectric isolation film 10 and the groove-type element isolation 14 described above. These second source / drain 20sd2 are connected to the back-side wiring 106 via the back-side contact 105 on the opposite side from the front-side wiring 26.

[0015] Here, the back-side contact 105 connects the second source / drain 20sd2 and the back-side wiring 106. This back-side contact 105 is embedded in a connection hole 104a that penetrates the insulating layer 104, which is the substrate. This connection hole 104a is formed in the insulating layer 104 by pattern etching from the other main surface side of the insulating layer 104, with the dielectric isolation film 10 and the groove-type element separator 14 acting as etching stoppers. Part of the inner wall of this connection hole 104a is composed of the groove-type element separator 14 and the dielectric isolation film 10. Furthermore, the back-side contact 105, which is positioned in this connection hole 104a, is connected to the second source / drain 20sd2 through the openings in the dielectric isolation film 10 and the openings in the groove-type element separator 14. As a result, the back-side contact 105 is self-aligned with respect to the second source / drain 20sd2.

[0016] Furthermore, the diameter of the back-side contact 105 on the back-side wiring 106 side is larger than the diameter of the connection point with the second source / drain 20sd2, i.e., the diameter of the second source / drain 20sd2. The diameter of the connection point between the back-side contact 105 and the second source / drain 20sd2 is the opening diameter of the dielectric isolation film 10 and the groove-type element isolation 14, respectively. Also, the back-side contact 105 encloses the second source / drain 20sd2 in a plan view.

[0017] ≪Method of Manufacturing a Semiconductor Device≫ Figures 2 to 18 are process diagrams (1) to (17) showing the method of manufacturing the semiconductor device 1 of the embodiment described above. The method of manufacturing the semiconductor device 1 and the detailed configuration of each part will be explained below in accordance with the order of the semiconductor device manufacturing process shown in Figures 2 to 18. Figures 2 to 18 show at least one of the following: a plan view, a cross-section of each part in the X direction in the plan view, and a Y-Y cross-section in each manufacturing process. The X direction is the gate width direction [Wg] of the full-circumference gate transistor formed here. The Y direction is the gate length direction [Lg] of the full-circumference gate transistor formed here.

[0018] First, as shown in Figure 2, a first substrate 100 is prepared. This first substrate 100 is used as a carrier substrate and has a configuration in which a semiconductor layer 103 made of silicon is provided on a semiconductor substrate 101 made of silicon, with a sacrificial film 102 in between. The sacrificial film 102 is made of, for example, silicon germanium.

[0019] A sacrificial layer 10' is formed on one main surface of the first substrate 100 on the semiconductor layer 103 side, and then a nanosheet laminate 13 is formed by stacking a plurality of nanosheet layers 12 made of semiconductor material via a sacrificial sheet layer 11.

[0020] The sacrificial sheet layer 11 is constructed using a material that allows for selective etching of the nanosheet layer 12, which is made of a semiconductor material. For example, when silicon is used as the semiconductor material constituting the nanosheet layer 12, silicon germanium is used as the sacrificial sheet layer 11. The sacrificial layer 10' is made of silicon germanium containing a higher concentration of germanium than the sacrificial sheet layer 11.

[0021] Next, as shown in Figure 3, the nanosheet laminate 13 and the sacrificial layer 10' are patterned in a line extending in one direction (in this case, the Y direction). At this time, the nanosheet laminate 13 and the sacrificial layer 10' are patterned by etching using a resist pattern (not shown in this figure) as a mask.

[0022] Subsequently, using the resist pattern as a mask, the surface side of the semiconductor layer 103 on the first substrate 100 is etched back to form a groove 103a, and a groove-type element separator 14 is formed consisting of a liner layer 14a that covers the inner wall of the groove 103a and an insulating material 14b that fills the inside of the groove 103a via the liner layer 14a.

[0023] First, a liner layer 14a, for example, made of silicon nitride, is deposited to cover the linearly patterned nanosheet laminate 13, the sacrificial layer 10', and the inner wall of the groove 103a. Next, a film made of an insulating material such as silicon oxide is deposited to fill the groove 103a covered by the liner layer 14a. Then, the insulating material is etched back to a position lower than the nanosheet laminate 13, leaving the insulating material 14b in the groove 103a. After that, the liner layer 14a is etched isotropically to expose the linearly patterned nanosheet laminate 13. During the etching of the liner layer 14a, the etching of the insulating material 14b also progresses, causing the insulating material 14b to recede further. As a result, the liner layer 14a covers from inside the groove 103a to the side wall of the sacrificial layer 10', and the groove-type element separator 14 fills the inside of the groove 103a at a lower position.

[0024] Next, as shown in Figure 4, a dummy gate 16 is formed extending substantially perpendicular to the nanosheet laminate 13 so as to cross the linearly patterned nanosheet laminate 13. Then, the sacrificial layer 10' (see Figure 3) is selectively etched to form a cavity in the lower part of the nanosheet laminate 13 using the linear dummy gate 16 as supports, and a dielectric separation film 10 is deposited to fill this cavity. The dielectric separation film 10 is a layer that acts as an etching stopper in the subsequent etching process from the back side of the first substrate 100. Such a dielectric separation film 10 is made of, for example, silicon oxide (SiO), silicon nitride (SiN), silicon oxycarbidine nitride (SiOCN), silicon oxycarbidine (SiOC), boron-containing silicon carbonitride (SiBCN), aluminum oxide (AlO), or hafnium oxide (HfO).

[0025] After the above steps, an insulating sidewall 17 is formed on the side wall of the dummy gate 16. The dummy gate 16 is made of, for example, polycrystalline silicon or amorphous silicon. The insulating sidewall 17 is made of, for example, boron-containing silicon carbonitride (SiBCN). Subsequently, the nanosheet laminate 13 is patterned in an island-like manner on the dielectric separation film 10 by etching using the dummy gate 16 and the insulating sidewall 17 as a mask. At this time, by etching the nanosheet laminate 13 using the dielectric separation film 10 as an etching stopper, it is possible to prevent over-etching of the semiconductor layer 103 and to make the depth between the nanosheet laminates 13 uniform.

[0026] Next, as shown in Figure 5, the dielectric isolation film 10 is patterned in an island-like manner by etching using the dummy gate 16 and insulating sidewall 17 as masks, exposing the semiconductor layer 103. At this time, over-etching of the semiconductor layer 103 is prevented by selectively etching a thin dielectric isolation film 10 relative to the semiconductor layer 103.

[0027] Next, as shown in Figure 6, the sacrificial sheet layer 11 exposed on the side wall of the nanosheet laminate 13 is selectively reduced by isotropic etching.

[0028] Next, as shown in Figure 7, insulating inner spacers 18 are formed on the exposed side walls of the sacrificial sheet layer 11 so as to fill the spaces between the silicon nanosheet layers 12. First, a silicon nitride film is deposited by isotropic deposition to fill the spaces between the nanosheet layers 12. Then, the silicon nitride film is etched back by anisotropic etching. This leaves the silicon nitride film only between the nanosheet layers 12, and the silicon nitride film remaining between the nanosheet layers 12 is formed as the inner spacer 18.

[0029] Next, as shown in Figure 8, a sacrificial film 19 is formed on the exposed surface of the semiconductor layer 103 by selective deposition. This sacrificial film 19 is formed using a material that can be selectively etched away from the dielectric separation film 10 and the liner layer 14a. For example, if the dielectric separation film 10 and the liner layer 14a are made of silicon nitride, the sacrificial film 19 may be formed of silicon oxide, or vice versa, or other combinations may be used. Alternatively, for example, the sacrificial film 19 may be a silicon germanium layer epitaxially grown on the semiconductor layer 103.

[0030] Next, as shown in Figure 9, source / drain 20sd are formed on both sides of the exposed surface of the nanosheet laminate 13, that is, on both sides in one direction (here, the Y direction) of the nanosheet laminate 13. At this time, source / drain 20sd containing p-type or n-type impurities are formed by epitaxial growth from the exposed surface of the nanosheet layer 12. The formation of each conductivity type of source / drain 20sd is carried out with other areas covered by a resist pattern.

[0031] Next, as shown in Figure 10, the source / drain 20sd between the dummy gates 16 is embedded with the embedded insulating film 21. In this case, the embedded insulating film 21 is embedded over the source / drain 20sd between the dummy gates 16 via the insulating sidewall 17, and the embedded insulating film 21 is formed to cover the dummy gates 16 and the insulating sidewall 17. After that, the embedded insulating film 21 is CMP polished until the dummy gates 16 and the insulating sidewall 17 are exposed, leaving the embedded insulating film 21 only between the dummy gates 16 via the insulating sidewall 17.

[0032] Next, as shown in Figure 11, the dummy gate 16 (see Figure 10) is removed by selective etching, and then the sacrificial sheet layer 11 (see Figure 10) between the nanosheet layers 12 is selectively etched away by etching from the exposed surface of the nanosheet laminate 13. This exposes the central part of the silicon nanosheet layer 12 around its entire circumference.

[0033] Next, as shown in Figure 12, a gate electrode 23g is formed on the exposed surface of the nanosheet layer 12 via a gate insulating film 22. The gate electrode 23g then fills the spaces between the nanosheet layers 12, between the bottom nanosheet layer 12 and the dielectric separation film 10, and between the insulating sidewalls 17. In this case, the gate insulating film 22 is formed using a high dielectric constant film, and the gate electrode 23g is formed using tungsten (W) or titanium nitride (TiN). This results in a full-circumference gate transistor 1a in which the entire circumference of the nanosheet layer 12 is surrounded by the gate electrode 23g via the gate insulating film 22. This full-circumference gate transistor 1a has a nanosheet laminate 13 provided via a dielectric separation film 10 on one main surface of the first substrate 100 on which the groove-type element isolation 14 is formed, and a source / drain 20sd provided via a sacrificial film 19.

[0034] Next, as shown in Figure 13, the all-around gate transistor 1a is embedded in the interlayer insulating film 24. Then, a surface-side contact 25 is formed that penetrates the interlayer insulating film 24 and the embedded insulating film 21 and reaches the target source / drain 20sd. The target source / drain 20sd here is the first source / drain 20sd1 that is connected to the surface-side wiring 26 via the surface-side contact 25. Next, a surface-side wiring 26 connected to the surface-side contact 25 is formed on the interlayer insulating film 24, and a planar insulating film 27 is formed to embed it. Then, the second substrate 28, which serves as a carrier substrate, is bonded to the planar insulating film 27. This completes the surface-side processing of the first substrate 100, and the back-side processing described below is carried out.

[0035] First, as shown in Figure 14, the semiconductor substrate 101, sacrificial film 102, and semiconductor layer 103 are sequentially removed from the back side opposite to the front side to which the second substrate 28 is bonded. This exposes the dielectric isolation film 10, liner layer 14a, and sacrificial film 19.

[0036] Next, as shown in Figure 15, an insulating layer 104 is formed on top of the dielectric isolation film 10, the groove-type element isolation 14, and the sacrificial film 19 so as to fill in the irregularities caused by the groove-type element isolation 14, and the surface of the insulating layer 104 is planarized as needed. This replaces the first substrate (see Figure 13) with a substrate made of the insulating layer 104.

[0037] Next, as shown in Figure 16, a connection hole 104a is formed in the insulating layer 104 at a position that exposes the target source / drain 20sd. Here, the target source / drain 20sd is the second source / drain 20sd2 that will be connected to the back-side wiring to be formed later. At this time, a resist pattern (not shown here) is used as a mask, and the dielectric isolation film 10 and the liner layer 14a of the groove-type element isolation 14 are used as stoppers to etch the insulating layer 104 from the back side. The sacrificial film 19, which is placed on top of the target source / drain 20sd, is exposed at the bottom of the etching, and the etching is stopped. At this point, the bottom surface of the connection hole 104a is the etching bottom surface with the sacrificial film 19 exposed.

[0038] In this case, a connection hole 104a is formed that has an opening shape that encloses the second source / drain 20sd2 in a plan view. The opening shape of the connection hole 104a is made large enough to reduce the resistance of the back-side contact formed inside the connection hole 104a.

[0039] Next, as shown in Figure 17, the sacrificial film 19 exposed at the bottom of the connection hole 104a is removed by etching, exposing the second source / drain 20sd2 at the bottom of the connection hole 104a.

[0040] Next, as shown in Figure 18, a back-side contact 105 is formed by filling the connection hole 104a and connecting it to the second source / drain 20sd2. At this time, a conductive material film, such as tungsten (W) or copper (Cu), is deposited to fill the connection hole 104a, and the deposited conductive material film is etched back. This leaves the conductive material film only inside the connection hole 104a, forming the back-side contact 105 connected to the second source / drain 20sd2.

[0041] Thereafter, as shown in FIG. 1, the back-side wiring 106 connected to the back-side contact 105 is formed over the insulating layer 104. The back-side wiring 106 may be configured by, for example, a multilayer wiring using copper, and constitutes, for example, a back-side power supply network. Thus, the semiconductor device 1 is completed.

[0042] <Effects of Embodiment> According to the embodiment described above, the connection hole 104a reaching the second source / drain 20sd2 is formed by etching the insulating layer 104 using the trench-type element isolation 14 and the dielectric isolation film 10 under the nanosheet stacked body 13 as stoppers (see FIG. 16). Accordingly, even when the opening shape of the connection hole 104a is made wider than the diameter of the source / drain 20sd, the dielectric isolation film 10 serves as a protective film, so that the gate insulating film 22 and the gate electrode 23g are not damaged. As a result, the resistance of the back-side contact 105 formed in the connection hole 104a can be reduced.

[0043] In addition, in forming the connection hole 104a, after the insulating layer 104 is pattern-etched until the sacrificial film 19 is exposed, the thin sacrificial film 19 only needs to be removed by etching, so that the film thickness loss of the second source / drain 20sd2 can be prevented. Therefore, the characteristics of the gate-all-around transistor 1a can be ensured.

[0044] Further, the formation of the connection hole 104a as described above does not require an advanced technique such as forming an epitaxial placeholder at a deep position below the source / drain 20sd between the nanosheet stacked bodies 13, so that the epitaxial process can be simplified.

[0045] 1... Semiconductor device 1a... Full-circumference gate transistor 10... Dielectric isolation film 11... Sacrificial sheet layer 12... Nanosheet layer 13... Nanosheet laminate 14... Groove-type element isolation 14a... Liner layer 14b... Insulating material 16... Dummy gate 17... Insulating sidewall 18... Inner spacer 19... Sacrificial film 20sd... Source / drain 20sd1... First source / drain 20sd2... Second source / drain 21... Embedded insulating film 22... Gate insulating film 23g... Gate electrode 24... Interlayer insulating film 25... Surface contact 26... Surface wiring 27... Planarizing insulating film 28... Second substrate 100... First substrate 101... Semiconductor substrate 102... Sacrificial film 103... Semiconductor layer 103a... Groove 104... Insulating layer (substrate) 104a... Connection hole 105... Backside contact 106... Rear side wiring

Claims

1. A semiconductor device comprising: a substrate having groove-type element isolation on one main surface side; a full-circumference gate transistor disposed on one main surface side of the substrate separated by the groove-type element isolation; back-side wiring disposed on the other main surface side of the substrate; a dielectric isolation film disposed between the nanosheet laminate constituting the full-circumference gate transistor and the substrate; a back-side contact disposed in a connection hole penetrating the substrate and connecting one of the source / drain of the full-circumference gate transistor to the back-side wiring; and a sacrificial film disposed between the other of the source / drain of the full-circumference gate transistor and the substrate, wherein the connection hole in which the back-side contact is disposed has an inner wall partly formed by the groove-type element isolation and the dielectric isolation film.

2. The semiconductor device according to claim 1, wherein the diameter of the back-side contact on the other main surface side of the substrate is greater than the diameter of the source / drain.

3. The semiconductor device according to claim 1, wherein the back-side contact encloses one of the source / drain in a plan view.

4. The semiconductor device according to claim 1, wherein the substrate is an insulating layer.

5. The semiconductor device according to claim 1, wherein the groove-type element isolation comprises a liner layer covering the inner wall of a groove formed on one main surface side of the substrate, and an insulating material filling the groove through the liner layer, and the connection hole is formed in part by the liner layer and the dielectric isolation film in the groove-type element isolation.

6. A method for manufacturing a semiconductor device, comprising the steps of: forming a full-circumference gate transistor having a nanosheet laminate provided via a dielectric isolation film and a source / drain provided via a sacrificial film on one main surface of a substrate on which groove-type element isolation is formed; forming a connection hole reaching one of the source / drain in the substrate by pattern etching from the other main surface of the substrate with the groove-type element isolation and the dielectric isolation film as stoppers and removing the sacrificial film; forming a back-side contact connected to one of the source / drain in the connection hole; and forming a back-side wiring on the other main surface of the substrate connected to one of the source / drain via the back-side contact.

7. The method for manufacturing a semiconductor device according to claim 6, wherein in the step of forming the connection hole, the connection hole is formed in an opening shape that encloses one of the source / drain in a plan view.

8. The method for manufacturing a semiconductor device according to claim 6, wherein, after forming the all-around gate transistor and before forming the connection holes in the substrate, the substrate is replaced with a substrate made of an insulating layer.

9. The method for manufacturing a semiconductor device according to claim 6, wherein the groove-type element isolation comprises a liner layer covering the inner wall of a groove formed on one main surface side of the substrate, and an insulating material filling the groove through the liner layer, and in the step of forming the connection hole, pattern etching is performed using the liner layer and the dielectric isolation film as stoppers.

10. The method for manufacturing a semiconductor device according to claim 6, wherein in the step of forming the connection hole, the substrate is pattern-etched from the other main surface side until the sacrificial film is exposed, and then the sacrificial film exposed on the etching bottom surface is removed.

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