Semiconductor device and method for producing semiconductor device

Abstract

The present invention provides a semiconductor device comprising: a plurality of gate-all-around transistors which are disposed in a matrix shape; a trench isolation which is disposed between the plurality of gate-all-around transistors; an insulating layer which is provided on one side of a surface on which the gate-all-around transistors and the trench isolation are disposed; a through via which is provided so as to pass through the insulating layer and the trench isolation; and a backside contact which is connected, on the side opposite to the insulating layer, to a target source / drain among sources / drains of the plurality of gate-all-around transistors, wherein the trench isolation, the through via, and the backside contact form substantially the same plane on the side opposite to the insulating layer.

Description

Semiconductor device and method for manufacturing semiconductor device

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device.

[0002] As a technique related to a method for forming a back-side contact in a semiconductor device using a nanosheet laminate, there is a technique described in Patent Document 1 below. This Patent Document 1 describes a procedure of exposing the back surface of an epitaxial placeholder, removing the epitaxial placeholder to form a trench, and forming a back-side contact in the trench in the patterning step of the back-side contact. The back-side contact formed in this manner is connected to the epitaxial source / drain formed over the epitaxial placeholder.

[0003] U.S. Patent Publication No. 2024 / 0429103

[0004] Meanwhile, some of the back-side contacts are connected to through vias for leading front-side wirings such as signal lines to the back side without passing through transistors, in addition to those connected to the source / drain. Since the back-side contact connected to such a through via has a different depth from the back-side contact connected to the source / drain, it needs to be formed in a separate step, which causes an increase in the number of manufacturing steps.

[0005] Accordingly, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which can reduce the number of manufacturing steps.

[0006] To achieve this objective, the present invention provides a semiconductor device comprising: a plurality of all-around gate transistors arranged in a matrix; groove-shaped element separators arranged between the plurality of all-around gate transistors; an insulating layer provided on one side of the arrangement plane between the all-around gate transistors and the groove-shaped element separators; through vias provided through the insulating layer and the groove-shaped element separators; and a back-side contact connected to a target source / drain of the source / drain of the plurality of all-around gate transistors on the side opposite to the insulating layer, wherein the groove-shaped element separators, the through vias and the back-side contacts constitute substantially the same plane on the side opposite to the insulating layer. The present invention also provides a method for manufacturing such a semiconductor device.

[0007] The present invention provides a semiconductor device and a method for manufacturing the same that can reduce the number of manufacturing steps.

[0008] This is a cross-sectional view showing the configuration of a semiconductor device according to an embodiment. This is a plan view showing step 1 of the method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view showing step 1 of the method for manufacturing a semiconductor device according to an embodiment, and is a cross-sectional view taken along the line X-X in Figure 2A. This is a cross-sectional view showing step 1 of the method for manufacturing a semiconductor device according to an embodiment, and is a cross-sectional view taken along the line Y-Y in Figure 2A. This is a cross-sectional view showing step 2 of the method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view showing step 3 of the method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view showing step 4 of the method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view showing step 5 of the method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view showing step 6 of the method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view showing step 7 of the method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view showing step 8 of the method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view showing step 9 of the method for manufacturing a semiconductor device according to an embodiment. This is a cross-sectional view showing step 10 of the method for manufacturing a semiconductor device according to an embodiment. This is a plan view showing step 10 of the method for manufacturing a semiconductor device according to an embodiment.

[0009] ≪Semiconductor Device≫ Figure 1 is a cross-sectional view showing the configuration of a semiconductor device 1 according to an embodiment, and shows the cross-section of the source / drain 15sd portion in the gate width direction [Wg] and the cross-section in the gate length direction [Lg] of the all-around gate transistor 1a of this semiconductor device 1.

[0010] The semiconductor device 1 shown in Figure 1 has a plurality of full-circumference gate transistors 1a arranged in a matrix. The semiconductor device 1 also has groove-type element separators 10 arranged between the full-circumference gate transistors 1a. The semiconductor device 1 also has an embedded insulating layer 18 and an insulating layer 20 provided on one side (the lower side in the drawing of Figure 1) of the arrangement surface between the full-circumference gate transistors 1a and the groove-type element separators 10.

[0011] Each full-circumference gate transistor 1a has a nanosheet laminate 13 formed by stacking multiple nanosheet layers 12, a gate electrode 14g that covers the entire circumference of each nanosheet layer 12, and a source / drain 15sd. The source / drain 15sd sandwiches the nanosheet laminate 13 in the gate length direction [Lg].

[0012] The groove-type element separator 10 extends in the gate length direction [Lg] and separates the full-circumference gate transistors 1a that are arranged adjacent to each other in the gate width direction [Wg]. Such a groove-type element separator 10 comprises a liner layer 10a extending in the gate length direction [Lg] and an insulating material 10b sandwiched between the liner layers 10a.

[0013] Furthermore, the semiconductor device 1 includes through vias 19 that penetrate the embedded insulating layer 18 and the groove-type element separator 10. In addition, the semiconductor device 1 includes a back-side contact 31 connected to the source / drain 15sd on the side opposite to the embedded insulating layer 18.

[0014] The through via 19 is provided embedded within a connection hole 18a formed through the embedded insulating layer 18 and the groove-type element separator 10, and has a tapered side wall shape in which the diameter decreases from the embedded insulating layer 18 side to the groove-type element separator 10 side.

[0015] The back-side contacts 31 are connected to the target source / drain 15s of the multiple full-circumference gate transistors 1a, and are arranged in overlap with these source / drain 15s. Such back-side contacts 31 are sandwiched between the liner layers 10a of the groove-type element separator 10. These back-side contacts 31, together with the groove-type element separator 10 and the through-vias 19, constitute substantially the same plane 30a on the side opposite to the embedded insulating layer 18. Here, substantially the same plane 30a refers to surfaces arranged at substantially the same height position, where the difference in height position within the plane 30a may be, for example, less than 1 nm, less than 2 nm, or less than 5 nm in terms of surface roughness (Ra). Furthermore, substantially the same plane 30a allows for irregularities to occur on the polished surface during polishing when forming this plane 30a. Such irregularities on the polished surface are caused by differences in the material of the components constituting the polished surface.

[0016] Furthermore, the semiconductor device 1 has surface-side wiring 22 provided above the embedded insulating layer 18 (downward side in the drawing of Figure 1) and back-side wiring 33 provided on the opposite side (upward side in the drawing of Figure 1).

[0017] The surface-side wiring 22 is positioned above the embedded insulating layer 18, for example, via an insulating layer 20, and is connected to the through-via 19 via a surface-side contact 21 provided within the insulating layer 20. Another surface-side wiring, not shown here, is connected to the gate electrode 14g and source / drain 15sd of the full-circumference gate transistor 1a via another surface-side contact.

[0018] The back-side wiring 33 is arranged on substantially the same plane 30a as the back-side contact 31, the groove-type element separator 10, and the through-via 19. This back-side wiring 33 is connected to the back-side contact 31 and the through-via 19, respectively. As a result, the back-side wiring 33 is connected to the source / drain 15sd of the full-circumference gate transistor 1a via the back-side contact 31 and to the front-side wiring 22 via the through-via 19.

[0019] In the configuration described above, the grooved element separator 10, the through via 19, and the back-side contact 31 are arranged on substantially the same plane 30a. The back-side wiring 33 is also arranged on this plane 30a.

[0020] Next, the detailed configuration of the semiconductor device 1 described above will be explained in accordance with the manufacturing process of the semiconductor device 1.

[0021] ≪Method of Manufacturing a Semiconductor Device≫ Figures 2 to 12 are diagrams showing steps 1 to 10 of the method of manufacturing the semiconductor device 1 according to the embodiment described above. Hereinafter, the method of manufacturing the semiconductor device 1 and the detailed configuration of each part will be explained in accordance with the steps shown in Figures 2 to 12. Figure 2 is a plan view (Figure 2A) showing step 1 of the method of manufacturing the semiconductor device, an X-X cross-sectional view in the plan view (Figure 2B), and a Y-Y cross-sectional view in the plan view (Figure 2C). Figures 3 to 11 are drawings corresponding to the X-X cross-section in the plan view (Figure 2A), and Figure 12 is a plan view corresponding to Figure 11. In the following explanation, the gate width direction [Wg] of the full-circumference gate transistor formed here will be defined as the X direction, and the gate length direction [Lg] will be defined as the Y direction.

[0022] First, as shown in Figures 2A, 2B, and 2C, a groove-type element separator 10 (shown only in Figure 2B) and a full-circumference gate transistor 1a are formed on one main surface (hereinafter referred to as surface 100a) of the substrate 100. Then, an embedded insulating layer 18 is formed on the source / drain 15sd and on top of the groove-type element separator 10 so as to fill the space between the gate electrodes 14g of the full-circumference gate transistor 1a. The substrate 100 is, for example, a semiconductor substrate.

[0023] The groove-type element separator 10 extends in the Y direction and consists of a liner layer 10a that covers the inner wall of a groove 101 formed on the surface 100a side of the substrate 100, and an insulating material 10b that fills the inside of the groove 101 via the liner layer 10a. The liner layer 10a is made of a material that is resistant to etching of the insulating material 10b. Such a liner layer 10a is, for example, a silicon nitride film, and the insulating material 10b is silicon oxide.

[0024] Furthermore, the all-around gate transistors 1a are arranged on the surface 100a side of the substrate 100 separated by the groove-type element separator 10, along the extension direction (Y direction) of the groove-type element separator 10. Each of these all-around gate transistors 1a comprises a nanosheet laminate 13 formed by stacking multiple nanosheet layers 12, a gate electrode 14g arranged around the entire circumference of each nanosheet layer 12, and source / drain 15sd arranged on both sides of the nanosheet laminate 13 in the Y direction.

[0025] Of these, the nanosheet laminate 13 is arranged in a matrix on the surface 100a of the substrate 100 separated by the groove-type element separator 10. The multiple nanosheet layers 12 constituting each nanosheet laminate 13 are stacked with spacing between them by sandwiching inner spacers 16 between the nanosheet layers 12 on both sides in the Y direction and between the bottom nanosheet layer 12 and the substrate 100. Each nanosheet layer 12 has a GAA (Gate All Around) structure in which its entire circumference is surrounded by a gate electrode 14g via a gate insulating film (not shown).

[0026] The gate electrode 14g extends in the X direction, which is substantially perpendicular to the extension direction (Y direction) of the groove-type element separator 10, and may be shared by multiple nanosheet stacks 13 in the X direction. Such a gate electrode 14g may have a multilayer structure of two or more layers. Furthermore, the gate electrode 14g and the source / drain 15sd, which will be described next, are insulated by the inner spacer 16 described above and the gate spacer 17 provided next to the gate electrode 14g on the nanosheet stack 13.

[0027] Furthermore, the source / drain 15sd is an epitaxial source / drain grown epitaxially from the nanosheet layer 12 and the substrate 100. Such a source / drain 15sd is covered with an embedded insulating layer 18 embedded between the gate electrodes 14g on the nanosheet laminate 13.

[0028] Next, as shown in Figure 3, through vias 19 are formed that penetrate the embedded insulating layer 18 and the insulating material 10b of the groove-type element separator 10, reaching the liner layer 10a of the groove-type element separator 10. To form such through vias 19, first, a connection hole 18a with the liner layer 10a as the bottom surface is formed by pattern etching of the embedded insulating layer 18 and the insulating material 10b, using the liner layer 10a as an etching stopper. Then, a conductive material is deposited to fill the connection hole 18a, and the conductive material is chemically mechanically polished (CMP) until the embedded insulating layer 18 is exposed, leaving the conductive material only inside the connection hole 18a. Finally, the conductive material remaining inside the connection hole 18a is formed as a through via 19.

[0029] Furthermore, since the through via 19 has a certain height, its diameter will also be above a certain size, and it may be formed in contact with an adjacent source / drain 15sd. In this case, the source / drain 15sd that the through via 19 contacts cannot function as a source / drain 15sd and will simply become an epitaxial pattern 15.

[0030] After forming the through vias 19 as described above, an insulating layer 20 is deposited on the through vias 19 and the embedded insulating layer 18. Then, surface-side contacts 21 connected to the through vias 19 are formed within the insulating layer 20. At the same time, surface-side contacts connected to the necessary locations of the source / drain 15sd may also be formed.

[0031] Subsequently, surface-side wiring 22 is formed on the insulating layer 20. The surface-side wiring 22 is, for example, a signal line connected to the through-via 19 via a surface-side contact 21, and other wiring connected to the source / drain 15sd via another surface-side contact (not shown here).

[0032] After the above steps, a planarizing insulating film 23 is formed to embed the surface wiring 22, and the carrier substrate 200 is bonded to the surface 100a side of the substrate 100 via the planarizing insulating film 23.

[0033] Next, Figure 4 (and subsequent drawings up to Figure 11) is a diagram in which the top and bottom of Figure 3 are reversed, with the carrier substrate 200 at the bottom of the drawing. As shown in Figure 4, in the next step, the liner layer 10a of the grooved element separator 10 is used as a stopper, and the substrate 100 is polished (CMP) from the other main surface (hereinafter referred to as the back surface 100b) side to expose the bottom of the liner layer 10a. As a result, the substrate 100 is left only between the grooved element separators 10, and the grooved element separators 10 are arranged between the substrates 100.

[0034] Next, as shown in Figure 5, the substrate 100 (see Figure 4) remaining between the liner layers 10a of the groove-type element separator 10 is selectively removed by etching. This exposes the source / drain 15sd of the full-circumference gate transistor 1a between the groove-type element separators 10. This also exposes the bottom of the nanosheet laminate 13 (see Figure 2C) of the full-circumference gate transistor 1a between the groove-type element separators 10.

[0035] Next, as shown in Figure 6, an insulating film 30 is formed on the source / drain 15sd of the full-circumference gate transistor 1a, filling the gaps between the liner layers 10a of the groove-type element separator 10. Then, using the liner layers 10a of the groove-type element separator 10 as stoppers, CMP (Chemical Multiplication) is performed on the insulating film 30, leaving the insulating film 30 only between the groove-type element separators 10. This forms a plane 30a composed of the insulating film 30 and the groove-type element separators 10.

[0036] Next, as shown in Figure 7, a resist pattern 102 is formed on the plane 30a formed by CMP of the insulating film 30, opening up the portion of the source / drain 15sd corresponding to the target source / drain 15sd. Here, the target source / drain 15sd is the one that will be connected to the back-side contact to be formed later. After that, the insulating film 30 is etched away using the resist pattern 102 and the liner layer 10a as a mask. This exposes the target source / drain 15sd between the groove-type element separators 10 at the bottom of the opening in the resist pattern 102. After the target source / drain 15sd is exposed, the resist pattern 102 is ashingly removed.

[0037] Next, as shown in Figure 8, a conductive material film 31a is formed on the plane 30a in a manner that fills the gaps between the groove-shaped element separators 10. The conductive material film 31a is, for example, a metallic material.

[0038] Next, as shown in Figure 9, the liner layer 10a of the grooved element separator 10 is used as a stopper to perform CMP of the conductive material film 31a, leaving the conductive material film 31a only on the source / drain 15sd exposed between the grooved element separators 10. Then, the conductive material film 31a left between the grooved element separators 10 is formed by self-alignment as a back-side contact 31 that connects to the target source / drain 15sd.

[0039] Next, as shown in Figure 10, the CMP between the bottom of the liner layer 10a and the back-side contact 31 is advanced to the extent that the liner layer 10a on the insulating material 10b in the groove-type element separator 10 is removed. This exposes the insulating material 10b in the groove-type element separator 10 and the bottom of the through-via 19. This also reduces the film thickness of the back-side contact 31, making the exposed surfaces of the back-side contact 31, the through-via 19, and the groove-type element separator 10 approximately the same height, and arranging the back-side contact 31, the through-via 19, and the groove-type element separator 10 on approximately the same plane 30a. Note that the plane 30a of approximately the same height formed by this CMP includes an uneven shape due to the difference in material of the members constituting the polished surface.

[0040] Next, as shown in Figure 11, back-side wiring 33 is formed on the plane 30a formed by the CMP, connected to the through via 19 and the back-side contact 31, respectively. Here, Figure 12 is a plan view of Figure 11 as seen from the direction of the back-side wiring 33. As shown in Figure 12, the back-side wiring 33 is formed by extending in a direction perpendicular to the extension direction of the gate electrode 14g, for example. Such back-side wiring 33 may, together with wiring formed in the upper layer, constitute, for example, a back-side power network.

[0041] Subsequently, as shown in Figure 1, if the wiring 33 on the back side and the wiring in the upper layer are formed, an insulating layer 34 is formed to cover these wirings, thereby completing the semiconductor device 1.

[0042] <<Effects of the Embodiment>> According to the embodiment described above, by arranging the back-side contact 31, the through-via 19, and the exposed surface of the groove-type element separator 10 on substantially the same plane, the back-side wiring 33 and the through-via 19 provided on this plane can be directly connected without the need for contacts. Therefore, the step of forming contacts for connecting the through-via 19 to the back-side wiring 33 can be omitted, and the number of manufacturing steps for the semiconductor device 1 can be reduced.

[0043] Furthermore, as explained with reference to Figure 9, the conductive material film 31a remaining between the groove-shaped element separators 10 is formed as a back-side contact 31 by self-alignment through CMP of the conductive material film 31a. Therefore, insulation between adjacent back-side contacts 31 is reliably ensured by the groove-shaped element separators 10. This makes it possible to omit the formation of insulating structures for insulating between densely arranged back-side contacts 31, thereby also reducing the number of manufacturing steps for the semiconductor device 1.

[0044] 1... Semiconductor device 1a... Full-circumference gate transistor 10... Groove-type element isolation 10a... Liner layer 10b... Insulating material 12... Nanosheet layer 13... Nanosheet laminate 14g... Gate electrode 15... Epitaxial pattern 15sd... Source / drain 16... Inner spacer 17... Gate spacer 18a... Connection hole 18... Embedded insulating layer 19... Through via 20... Insulating layer 21... Front contact 22... Front wiring 23... Planar insulating film 30... Insulating film 30a... Planar 31... Back contact 31a... Conductive material film 33... Back wiring 34... Insulating layer 100... Substrate 100a... Front 100b... Back 101... Groove 102... Resist pattern 200... Carrier substrate

Claims

1. A semiconductor device comprising: a plurality of full-circumference gate transistors arranged in a matrix; groove-shaped element separators arranged between the plurality of full-circumference gate transistors; an insulating layer provided on one side of the arrangement surface between the full-circumference gate transistors and the groove-shaped element separators; through vias provided through the insulating layer and the groove-shaped element separators; and a back-side contact connected to a target source / drain of the source / drain of the plurality of full-circumference gate transistors on the side opposite to the insulating layer, wherein the groove-shaped element separators, the through vias and the back-side contacts form substantially the same plane on the side opposite to the insulating layer.

2. The semiconductor device according to claim 1, wherein the groove-shaped element isolation comprises a liner layer and an insulating material sandwiched between the liner layers.

3. The semiconductor device according to claim 1, wherein a back-side wiring connected to the back-side contact and the through-via is provided on the plane on which the groove-type element separator, the through-via and the back-side contact are arranged.

4. The semiconductor device according to claim 1, wherein surface-side wiring connected to the through-via is provided on the insulating layer.

5. The semiconductor device according to claim 1, wherein the back-side contact is sandwiched between the groove-type element separators.

6. A step of forming groove-type element isolations, in which grooves covered with a liner layer are filled with an insulating material, and a plurality of full-circumference gate transistors separated by the groove-type element isolations, on one main surface side of a substrate; a step of forming an insulating layer on one main surface of the substrate that covers the sources / drains of the groove-type element isolations and the plurality of full-circumference gate transistors; a step of forming a connection hole with the liner layer as the bottom surface by pattern etching the insulating layer and the insulating material with the bottom of the liner layer as a stopper, and forming a through via by filling the connection hole with a conductive material; a step of exposing the bottom of the liner layer by polishing the substrate from the other main surface side, and then exposing the plurality of full-circumference gate transistors between the groove-type element isolations by etching away the substrate remaining between the liner layers; a step of forming an insulating film on the plurality of full-circumference gate transistors so as to fill the gaps between the liner layers; a step of exposing a target source / drain among the sources / drains constituting the plurality of full-circumference gate transistors by pattern etching of the insulating film; A method for manufacturing a semiconductor device, comprising the steps of: forming a back-side contact connected to the exposed source / drain between the liner layers; and, after forming the back-side contact, removing the bottom of the liner layer to expose the through-via.

7. The method for manufacturing a semiconductor device according to claim 6, wherein in the step of exposing the through via, the bottom of the liner layer and the back side contact are polished so that the exposed surface of the through via and the exposed surface of the back side contact are placed on substantially the same plane.

8. The method for manufacturing a semiconductor device according to claim 7, wherein a back-side wiring connected to the through via and the back-side contact is formed on the plane.

9. The method for manufacturing a semiconductor device according to claim 6, wherein, after the step of forming the through vias, and before exposing the bottom of the liner layer, surface wiring connected to the through vias is formed.

10. The method for manufacturing a semiconductor device according to claim 6, wherein in the step of exposing the target source / drain, a resist pattern is formed on a surface composed of the liner layer and the insulating film, and the insulating film is etched off using the resist pattern and the liner layer as a mask.

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