Semiconductor device

Abstract

Provided is a semiconductor device comprising: a semiconductor element having main electrodes on both surfaces; a substrate having an insulating base material, a front surface metal body, and a rear surface metal body; a joint part connected to the front surface metal body; a conductive spacer (70) connected to the main electrodes and the front surface metal body; a sealing body (30); and a protective film (31) provided between the conductive spacer (70) and the sealing body (30). Furthermore, a plating film (70m) is provided on the surface of the conductive spacer (70). At least a part of the plating film (70m) facing the protective film (31) is provided with an uneven part (71) and a metal oxide film (70o), and the metal oxide film (70o) is in contact with the protective film (31).

Description

Semiconductor device Cross-reference to related applications

[0001] This application is based on Japanese Patent Application No. 2025-68375 filed on April 17, 2025, the entire contents of which are incorporated herein by reference.

[0002] The disclosure in this specification relates to a semiconductor device.

[0003] Patent Document 1 discloses a semiconductor device in which a semiconductor chip is mounted on a lead frame and sealed with a sealing resin.

[0004] Japanese Unexamined Patent Publication No. 2009-302209

[0005] Incidentally, a semiconductor device may be configured to include a semiconductor element, a resin sealing body, and a substrate having a front surface metal body, an insulating base material, and a back surface metal body. In such a semiconductor device, stress may be generated in the insulating base material due to contact between the front surface metal body, the insulating base material, and the resin sealing body. Accordingly, it is conceivable that the stress generated in the insulating base material of the semiconductor device is relieved by a protective film. However, in the semiconductor device, the protective film may peel off depending on the state of the object in contact with the protective film. From the above viewpoints, or from other viewpoints not mentioned, further improvements are required for semiconductor devices.

[0006] One disclosed object is to provide a semiconductor device capable of suppressing peeling of a protective film.

[0007] The semiconductor device disclosed herein comprises: a semiconductor element having main electrodes on both sides in the thickness direction; a substrate having an insulating substrate, a surface metal body disposed on a part of the surface of the insulating substrate and electrically connected to the main electrodes, and a back metal body disposed on the back surface of the insulating substrate; a first metal member connected to the surface metal body; a second metal member connected to the main electrodes and the surface metal body; a metal film provided on the surfaces of the surface metal body, the first metal member and the second metal member; a resin encapsulant that integrally seals the semiconductor element, the substrate, the first metal member and the second metal member while in contact with a part of the insulating substrate; and a protective film provided between the semiconductor element, the insulating substrate, the surface metal body, the first metal member and the second metal member and the resin encapsulant to protect the insulating substrate, wherein at least a portion of the metal film facing the protective film has an uneven surface and an oxidized surface that is in contact with the protective film.

[0008] Thus, the semiconductor device has an uneven surface where the oxidized surface is in contact with the protective film. Therefore, the semiconductor device can suppress the peeling of the protective film.

[0009] The various embodiments disclosed in this specification employ different technical means to achieve their respective objectives. The claims and the reference numerals in parentheses in this section are illustrative in their correspondence with the embodiments described later and are not intended to limit the technical scope. The objectives, features, and effects disclosed in this specification will become clearer by referring to the subsequent detailed description and the accompanying drawings.

[0010] This figure shows the circuit configuration of a power conversion device to which a semiconductor device is applied. This is a perspective view showing a semiconductor device. This is a perspective view showing a semiconductor device. This is a plan view showing a semiconductor device. This is a cross-sectional view along the line V-V in Figure 4. This is a cross-sectional view along the line VI-VI in Figure 4. This is a cross-sectional view along the line VII-VII in Figure 4. This is a cross-sectional view along the line VIII-VIII in Figure 4. This is a plan view showing the state in which a semiconductor element is mounted on the substrate on the drain electrode side. This is an enlarged cross-sectional view of region X in Figure 5. This is an enlarged cross-sectional view of region XI in Figure 10. This is a cross-sectional view showing the hole in a modified example. This is a plan view showing the hole in a modified example. This is a cross-sectional view showing the hole in a modified example. This is a plan view showing the state in which a semiconductor element is mounted on the substrate on the drain electrode side of a modified example. This is a plan view showing the state in which a semiconductor element is mounted on the substrate on the drain electrode side of a modified example. This is a plan view showing the state in which a semiconductor element is mounted on the substrate on the drain electrode side of a modified example.

[0011] The embodiments will be described below with reference to the drawings. The semiconductor device of this embodiment is applied, for example, to a power conversion device for a mobile body that uses a rotating electric machine as a drive source. The mobile body is, for example, an electric vehicle (EV), a hybrid vehicle (HV), a plug-in hybrid vehicle (PHV), an aircraft such as a drone, a ship, construction machinery, or agricultural machinery. An example of application to a vehicle will be described below.

[0012] <Vehicle Drive System> First, the general configuration of the vehicle drive system 1 will be explained based on Figure 1. As shown in Figure 1, the vehicle drive system 1 is equipped with a DC power supply 2, a motor generator 3, and a power converter 4.

[0013] The DC power supply 2 is a DC voltage source composed of rechargeable secondary batteries. The secondary batteries are, for example, lithium-ion batteries or nickel-metal hydride batteries. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as the vehicle's driving source, i.e., an electric motor. The motor generator 3 also functions as a generator during regeneration. The power converter 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0014] <Power Conversion Device> Next, the circuit configuration of the power conversion device 4 will be described based on Figure 1. The power conversion device 4 is equipped with a power conversion circuit. The power conversion device 4 in this embodiment is equipped with a smoothing capacitor 5 and an inverter 6 which is a power conversion circuit.

[0015] The smoothing capacitor 5 primarily smooths the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to the P line 7, which is the high-potential power line, and the N line 8, which is the low-potential power line. The P line 7 is connected to the positive terminal of the DC power supply 2, and the N line 8 is connected to the negative terminal of the DC power supply 2. The positive terminal of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative terminal of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2.

[0016] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage to a three-phase AC voltage according to switching control by a control circuit (not shown) and outputs it to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 in response to the rotational force from the wheels to a DC voltage according to switching control by the control circuit and outputs it to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power supply 2 and the motor generator 3.

[0017] The inverter 6 is configured with three phase upper and lower arm circuits 9. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. The connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via the output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a portion of each of the P line 7, N line 8, and output line 10 is made of conductive material such as a busbar.

[0018] In this embodiment, an n-channel type MOSFET 11 is used as the switching element constituting each arm. The number of switching elements constituting each arm is not particularly limited; there may be one or multiple. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0019] As an example, in this embodiment, each arm has two MOSFETs 11. The two MOSFETs 11 constituting one arm are connected in parallel. In the upper arm 9H, the drains of the two parallel-connected MOSFETs 11 are connected to the P line 7. In the lower arm 9L, the sources of the two parallel-connected MOSFETs 11 are connected to the N line 8. The sources of the two parallel-connected MOSFETs 11 in the upper arm 9H and the drains of the two parallel-connected MOSFETs 11 in the lower arm 9L are interconnected. The two parallel-connected MOSFETs 11 are turned on and off at the same timing by a common gate drive signal (drive voltage).

[0020] Each MOSFET 11 is connected in antiparallel to a freewheeling diode 12. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or it may be a separate diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain. The upper and lower arm circuit 9 for one phase is provided by a single semiconductor device 20. Details of the semiconductor device 20 will be described later.

[0021] The power converter 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage to a DC voltage of a different value. The converter is provided between the DC power supply 2 and the smoothing capacitor 5. The converter is configured, for example, with a reactor and the above-described up-and-down arm circuit 9. With this configuration, step-up and step-down voltage conversion is possible. The power converter 4 may also include a filter capacitor to remove power supply noise from the DC power supply 2. The filter capacitor is provided between the DC power supply 2 and the converter.

[0022] The power converter 4 may include a drive circuit for the switching elements that make up the inverter 6, etc. The drive circuit supplies a drive voltage to the gate of the corresponding arm's MOSFET 11 based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on or off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0023] The power converter 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0024] Various types of sensors include, for example, current sensors, rotation angle sensors, and voltage sensors. The current sensor detects the phase current flowing through the windings 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit outputs, for example, a PWM signal as a drive command. The control circuit is configured to include, for example, a processor and memory. PWM is an abbreviation for Pulse Width Modulation.

[0025] <Semiconductor Devices> Next, semiconductor devices will be described based on Figures 2 to 11. Figure 2 is a perspective view of the semiconductor device 20. Figure 3 is a perspective view of the semiconductor device 20, similar to Figure 2. Figure 3 is a transparent view showing the internal structure. Figure 4 is a plan view of the semiconductor device 20. Figure 4 is a transparent view showing the internal structure. Figure 5 is a cross-sectional view along the line V-V in Figure 4. Figure 6 is a cross-sectional view along the line VI-VI in Figure 4. Figure 7 is a cross-sectional view along the line VII-VII in Figure 4. Figure 7 clearly illustrates the bonding wire 110. Figure 8 is a cross-sectional view along the line VIII-VIII in Figure 4.

[0026] In the following, the thickness direction of the semiconductor element (semiconductor substrate) is defined as the Z direction. The direction perpendicular to the Z direction, in which the semiconductor elements constituting the upper arm 9H and the semiconductor elements constituting the lower arm 9L are aligned, is defined as the Y direction. The direction perpendicular to both the Z and Y directions is defined as the X direction. Unless otherwise specified, the shape viewed from the Z direction, in other words, the shape along the XY plane defined by the X and Y directions, is defined as the planar shape. The view from the Z direction is sometimes simply referred to as the planar view. Furthermore, the term "arrangement" is not limited to the mounting surface, but may also refer to any overlapping positional relationship in a planar view.

[0027] As shown in Figures 2 to 8, the semiconductor device 20 constitutes one of the upper and lower arm circuits 9 described above, that is, one phase of the upper and lower arm circuit 9. The semiconductor device 20 includes a encapsulant 30, a protective film 31, a semiconductor element 40, substrates 50 and 60, a conductive spacer 70, an arm connection portion 80, and an external connection terminal 90.

[0028] The encapsulant 30 encapsulates a portion of the other elements constituting the semiconductor device 20. The remaining portions of the other elements are exposed outside the encapsulant 30. The encapsulant 30 integrally encapsulates the semiconductor element 40, the substrates 50 and 60, the conductive spacer 70, and the arm connection portion 80, while, for example, contacting a portion of the insulating substrates 51 and 61. The encapsulant 30 corresponds to a resin encapsulant.

[0029] The sealant 30 is made of, for example, a resin. An example of a resin is an epoxy resin. The sealant 30 is molded from resin by, for example, a transfer molding method. Such a sealant 30 may be called a resin sealant, molded resin, or resin molded body. The sealant 30 may also be formed using, for example, a gel. The gel is filled (placed) in, for example, the opposing regions of a pair of substrates 50 and 60.

[0030] As shown in Figures 2 to 8, the sealing body 30 has a substantially rectangular shape in plan. The sealing body 30 has one surface 30a and a back surface 30b which is opposite to the one surface 30a in the Z direction. The one surface 30a and the back surface 30b are, for example, flat surfaces. It also has a side surface which connects the one surface 30a and the back surface 30b. The side surface includes two side surfaces 30c and 30d from which the external connection terminal 90 protrudes. The side surface 30d is opposite to the side surface 30c in the X direction.

[0031] The semiconductor element 40 is formed by creating a switching element on a semiconductor substrate made of materials such as silicon (Si) or a semiconductor with a wider bandgap than silicon (wide-bandgap semiconductor). Examples of wide-bandgap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 40 is sometimes referred to as a power element or semiconductor chip.

[0032] The semiconductor element 40 of this embodiment is formed by creating the n-channel type MOSFET 11 described above on a semiconductor substrate made of SiC. The MOSFET 11 has a vertical structure such that the main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), i.e., in the Z direction. The semiconductor element 40 has main electrodes for the switching element on both sides in its thickness direction, i.e., in the Z direction. Specifically, as main electrodes, it has a drain electrode 40D on one side and a source electrode 40S on the back side, which is the opposite side in the Z direction from the other side.

[0033] If diode 12 is a parasitic diode, the source electrode 40S also serves as the anode electrode, and the drain electrode 40D also serves as the cathode electrode. Diode 12 may be configured on a separate chip from MOSFET 11. The drain electrode 40D is the main electrode on the high-potential side (first main electrode), and the source electrode 40S is the main electrode on the low-potential side (second main electrode). Hereafter, the drain electrode 40D and source electrode 40S may be referred to as main electrodes 40D and 40S.

[0034] The semiconductor element 40 has a substantially rectangular shape in plan. As shown in Figure 4, the semiconductor element 40 has a pad 40P formed on its back surface at a different position from the source electrode 40S. The source electrode 40S and the pad 40P are exposed from a protective film (not shown) formed on the back surface of the semiconductor substrate. The drain electrode 40D is formed over almost the entire surface of one side. The source electrode 40S is formed on a portion of the back surface of the semiconductor element 40. In a plan view, the drain electrode 40D has a larger area than the source electrode 40S.

[0035] Pad 40P is a signal electrode. Pad 40P is electrically isolated from the source electrode 40S. Pad 40P is formed at the end opposite to the source electrode 40S formation region in the Y direction. Pad 40P includes a gate electrode pad.

[0036] The example shown illustrates a semiconductor element 40 having a MOSFET 11 as a switching element, but it is not limited to this. For example, an IGBT or an RC-IGBT, which integrates an IGBT and a diode (FWD) into a single chip, can also be used. IGBT is an abbreviation for Insulated Gate Bipolar Transistor. RC is an abbreviation for Reverse Conducting. FWD is an abbreviation for Free Wheel Diode.

[0037] The semiconductor device 20 comprises a plurality of semiconductor elements 40 having the above configuration. The configuration of each semiconductor element 40 is common to all others. The plurality of semiconductor elements 40 include semiconductor elements 40H that constitute the upper arm 9H and semiconductor elements 40L that constitute the lower arm 9L. Semiconductor element 40H is sometimes referred to as the upper arm element, and semiconductor element 40L is sometimes referred to as the lower arm element. Each of the semiconductor elements 40H and 40L is an arm element that constitutes one arm. Semiconductor element 40H corresponds to the first semiconductor element. Semiconductor element 40L corresponds to the second semiconductor element.

[0038] As shown in Figure 4, the semiconductor device 20 of this embodiment comprises two semiconductor elements 40H and two semiconductor elements 40L. The two semiconductor elements 40H are arranged in the X direction (one direction) in a plan view. Similarly, the two semiconductor elements 40L are arranged in the X direction in a plan view. The semiconductor elements 40H and 40L are aligned in the Y direction in a plan view. The Y direction is a first direction perpendicular to the Z direction, which is the thickness direction of the semiconductor element 40. The X direction is a second direction perpendicular to the Z direction and the first direction (Y direction). The semiconductor device 20 has two rows of semiconductor elements 40H and 40L along the Y direction. The X direction is a one direction, corresponding to the arrangement direction.

[0039] Each semiconductor element 40 is positioned at approximately the same location in the Z direction. As shown in Figure 5 and other figures, the drain electrode 40D of each semiconductor element 40 faces the substrate 50. The source electrode 40S of each semiconductor element 40 faces the substrate 60.

[0040] Substrates 50 and 60 are arranged so as to sandwich the plurality of semiconductor elements 40 in the Z direction. The substrates 50 and 60 are arranged such that at least portions thereof face each other in the Z direction. The substrates 50 and 60 enclose all of the plurality of semiconductor elements 40 (40H, 40L) in plan view.

[0041] The substrate 50 is disposed on the drain electrode 40D side with respect to the semiconductor element 40. The substrate 60 is disposed on the source electrode 40S side with respect to the semiconductor element 40. As will be described later, the substrate 50 is electrically connected to the drain electrode 40D to provide a wiring function. Similarly, the substrate 60 is electrically connected to the source electrode 40S to provide a wiring function. For this reason, the substrates 50 and 60 may be referred to as wiring substrates. The substrate 50 may be referred to as a drain substrate, and the substrate 60 may be referred to as a source substrate.

[0042] The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. For this reason, the substrates 50 and 60 may be referred to as heat dissipation members. Of the pair of substrates 50 and 60 that sandwich the semiconductor element 40 in the Z direction, the substrate 50 is a first substrate, and the substrate 60 is a second substrate.

[0043] The substrate 50 has a facing surface 50a that faces the semiconductor element 40, and a back surface 50b that is the surface opposite to the facing surface 50a. The substrate 50 includes an insulating base material 51, a front surface metal body 52, and a back surface metal body 53. The substrate 50 is a substrate in which the insulating base material 51 and the metal bodies 52, 53 are laminated.

[0044] The front surface metal body 52 is in contact with the surface of the insulating base material 51. The front surface metal body 52 is disposed on the surface of the insulating base material 51 in the Z direction. The front surface metal body 52 is disposed on a portion of the insulating base material 51 and is electrically connected to the drain electrode 40D.

[0045] The insulating base material 51 has the front surface metal body 52 disposed on a part of itself. In other words, the front surface metal body 52 is partially provided with respect to the insulating base material 51. The surface of the insulating base material 51 is a surface facing the semiconductor element 40 in the Z direction.

[0046] The back metal body 53 is in contact with the back surface of the insulating substrate 51. The back metal body 53 is positioned on the back surface of the insulating substrate 51. The back surface of the insulating substrate 51 is the opposite surface of the front surface of the insulating substrate 51.

[0047] The substrate 60 has a facing surface 60a that faces the semiconductor element 40, and a back surface 60b that is opposite to the facing surface 60a. The substrate 60 comprises an insulating substrate 61, a surface metal body 62, and a back metal body 63. The substrate 60 is a substrate in which the insulating substrate 61 and the metal bodies 62 and 63 are laminated.

[0048] The surface metal body 62 is in contact with the surface of the insulating substrate 61. The surface metal body 62 is positioned on the surface of the insulating substrate 61 in the Z direction. The surface metal body 62 is positioned on a part of the insulating substrate 61 and is electrically connected to the source electrode 40S. The surface metal body 62 is electrically connected to the source electrode 40S via the conductive spacer 70.

[0049] The insulating substrate 61 has a surface metal body 62 arranged on a part of it. In other words, the surface metal body 62 is partially provided on the insulating substrate 61. The surface of the insulating substrate 61 is the surface facing the semiconductor element 40 in the Z direction.

[0050] The back metal body 63 is in contact with the back surface of the insulating substrate 61. The back metal body 63 is positioned on the back surface of the insulating substrate 61. The back surface of the insulating substrate 61 is the opposite surface of the front surface of the insulating substrate 61.

[0051] In the first substrate, substrate 50, the insulating substrate 51 is the first insulating substrate, the surface metal body 52 is the first surface metal body, and the back metal body 53 is the first back metal body. In the second substrate, substrate 60, the insulating substrate 61 is the second insulating substrate, the surface metal body 62 is the second surface metal body, and the back metal body 63 is the second back metal body. Hereafter, the surface metal bodies 52, 62 and the back metal bodies 53, 63 may be simply referred to as metal bodies 52, 53, 62, and 63.

[0052] The insulating substrate 51 electrically separates the surface metal body 52 and the back metal body 53. Similarly, the insulating substrate 61 electrically separates the surface metal body 62 and the back metal body 63. The insulating substrates 51 and 61 are sometimes referred to as insulating layers. The material of the insulating substrates 51 and 61 is a resin or an inorganic ceramic material. As a resin, for example, epoxy resins and polyimide resins can be used. As a ceramic, for example, Al ２ O ３ (alumina), Si ３ N ４ Silicon nitride (Silicon Nibble) can be used.

[0053] When the insulating substrates 51 and 61 are made of resin, the substrates 50 and 60 are sometimes referred to as metal-resin substrates. When the insulating substrates 51 and 61 are made of ceramic, the substrates 50 and 60 are sometimes referred to as metal-ceramic substrates.

[0054] In the case of insulating substrates 51 and 61 made of resin material, inorganic fillers (inorganic fillers) may be included in the resin to improve heat dissipation, insulation, etc. The coefficient of linear expansion may be adjusted by adding fillers. For example, Al ２ O ３ SiO ２ Silicon dioxide (Silicon dioxide), aluminum nitride (AlN), boron nitride (BN), etc., can be used as fillers. The insulating substrates 51 and 61 may contain only one type of filler or may contain multiple types.

[0055] Considering heat dissipation and insulation properties, in the case of resin-based materials, the thickness of each insulating substrate 51 and 61, i.e., the length in the Z direction, is preferably about 50 μm to 300 μm. In the case of ceramic-based materials, the thickness of the insulating substrates 51 and 61 is preferably about 200 μm to 500 μm. In the Z direction, the surface of the insulating substrates 51 and 61 is the inner surface, i.e., the surface facing the semiconductor element 40, and the back surface, which is the surface opposite to the surface in the Z direction, is the outer surface.

[0056] The insulating substrates 51 and 61 may have the same material composition or they may be different. In this embodiment, resin-based insulating substrates 51 and 61 are used, and their material composition is the same. The coefficient of linear expansion of the insulating substrates 51 and 61 is adjusted to be approximately the same as that of the sealant 30 by adding a filler to the resin. By adding a filler to the resin, the coefficients of linear expansion of the insulating substrates 51 and 61 and the sealant 30 are close to the values ​​of the metal (Cu) that constitutes the metal bodies 52, 53, 62, and 63.

[0057] The metal bodies 52, 53, 62, and 63 are provided, for example, as metal plates or metal foils. The metal bodies 52, 53, 62, and 63 are formed from metals with good electrical and thermal conductivity, such as Cu or Al. The thickness of each of the metal bodies 52, 53, 62, and 63 is, for example, about 0.1 mm to 3 mm.

[0058] As shown in Figures 5 to 8, in this embodiment, the surface metal body 52 is thicker than the back metal body 53. The surface metal body 62 is thicker than the back metal body 63. The surface metal body 52 on the drain electrode 40D side is thicker than the surface metal body 62 on the source electrode 40S side. Alternatively, the back metal bodies 53, 63 may be made thicker than the corresponding surface metal bodies 52, 62. The thickness of the surface metal body 52 and the back metal body 53 may be approximately equal, or the thickness of the surface metal body 62 and the back metal body 63 may be approximately equal.

[0059] The surface metal bodies 52 and 62 are patterned. The surface metal bodies 52 and 62 provide wiring, or circuits. For this reason, the surface metal bodies 52 and 62 are sometimes referred to as circuit patterns, wiring layers, or circuit conductors. The surface metal bodies 52 and 62 may have a plating film of Ni-based or Au on their metal surfaces. Hereafter, the patterns of the surface metal bodies 52 and 62 may be referred to as circuit patterns.

[0060] The surface metal body 52 and the area on the surface of the insulating substrate 51 where the surface metal body 52 is not positioned form the opposing surface 50a of the substrate 50. Similarly, the surface metal body 62 and the area on the surface of the insulating substrate 61 where the surface metal body 62 is not positioned form the opposing surface 60a of the substrate 60.

[0061] Furthermore, as shown in Figure 10, the portion of the opposing surface 50a where the joining materials 100 and 103 are not provided is designated as the exposed surface S22. Similarly, the portion of the opposing surface 60a where the joining materials 102 and 103 are not provided is designated as the exposed surfaces S21 and S31. The exposed surface S21 is the surface of the N wiring 64, which will be explained later. The exposed surface S31 is the surface of the relay wiring 65, which will be explained later.

[0062] For example, surface metal bodies 52 and 62, patterned into a predetermined shape by press working or etching, may be prepared and then attached to a two-layer laminate consisting of insulating substrates 51 and 61 and back metal bodies 53 and 63 to form substrates 50 and 60. Alternatively, after forming a three-layer laminate consisting of surface metal bodies 52 and 62, insulating substrates 51 and 61, and back metal bodies 53 and 63, the surface metal bodies 52 and 62 may be patterned by cutting or etching.

[0063] As shown in Figures 4 and 7, the surface metal body 52 has P wiring 54 and intermediate wiring 55. The P wiring 54 and intermediate wiring 55 are electrically isolated by a predetermined gap. This gap is filled with a sealant 30. Therefore, the P wiring 54 and intermediate wiring 55 on the insulating substrate 51 face the sealant 30 without the surface metal body 52 in between.

[0064] As shown in Figure 5, the P wiring 54 is connected to the P terminal 91P (described later) and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 electrically connects the P terminal 91P and the drain electrode 40D of the semiconductor element 40H. The P wiring 54 is sometimes referred to as positive electrode wiring or high-potential power supply wiring.

[0065] As shown in Figure 5, the relay wiring 55 is connected to the drain electrode 40D of the semiconductor element 40L, the arm connection portion 80, and the output terminal 92. The relay wiring 55 electrically connects the arm connection portion 80 and the drain electrode 40D of the semiconductor element 40L. The relay wiring 55 electrically connects the source electrode 40S of the semiconductor element 40H and the drain electrode 40D of the semiconductor element 40L to the output terminal 92. In the surface metal body 52 (first surface metal body), the P wiring 54 is the first power supply wiring, and the relay wiring 55 is the first relay wiring.

[0066] The P wiring 54 and the relay wiring 55 are arranged side by side in the Y direction. In the Y direction, the P wiring 54 is located on the side of the power terminal 91, and the relay wiring 55 is located on the side of the output terminal 92. In other words, the P wiring 54 is located close to the side surface 30c of the encapsulant 30, and the relay wiring 55 is located close to the side surface 30d.

[0067] On the other hand, the surface metal body 62 has N wiring 64 and relay wiring 65, as shown in Figures 5 and 7. The N wiring 64 and relay wiring 65 are electrically isolated by a predetermined gap. This gap is filled with a sealant 30. Therefore, the space between the N wiring 64 and relay wiring 65 in the insulating substrate 61 faces the sealant 30 without the surface metal body 62 being in between.

[0068] As shown in Figure 6, the N wiring 64 is connected to the N terminal 91N (described later) and the source electrode 40S of the semiconductor element 40L. The N wiring 64 electrically connects the N terminal 91N and the source electrode 40S of the semiconductor element 40L. The N wiring 64 is sometimes referred to as the N wiring.

[0069] The relay wiring 65 is connected to the source electrode 40S and the arm connection portion 80 of the semiconductor element 40H. The relay wiring 65 electrically connects the source electrode 40S and the arm connection portion 80 of the semiconductor element 40H. In the surface metal body 62 (second surface metal body), the N wiring 64 is the second power supply wiring, and the relay wiring 65 is the second relay wiring.

[0070] The relay wiring 65 overlaps the semiconductor element 40H in a plan view. In other words, the semiconductor element 40H is positioned on the relay wiring 65. The source electrode 40S of the semiconductor element 40H is connected to the relay wiring 65.

[0071] The back metal bodies 53 and 63 are electrically isolated from the circuit including the semiconductor element 40 by insulating substrates 51 and 61. The back metal bodies 53 and 63 are sometimes referred to as metal base substrates. The heat generated by the semiconductor element 40 is transferred to the back metal bodies 53 and 63 via the front metal bodies 52 and 62 and insulating substrates 51 and 61. The back metal bodies 53 and 63 provide a heat dissipation function.

[0072] The back metal bodies 53 and 63 of this embodiment have a substantially rectangular shape in plan, and their outer contours substantially coincide with the outer contours of the front metal bodies 52 and 62. The back metal bodies 53 and 63 are so-called solid conductors arranged over almost the entire back surface of the insulating substrates 51 and 61.

[0073] As described above, the coefficient of thermal expansion of the insulating substrates 51 and 61 is adjusted by adding fillers, so warping can be suppressed even if the patterns are different on the front and back sides. Of course, the back metal bodies 53 and 63 may also be patterned so that they match the front metal bodies 52 and 62 in a plan view.

[0074] In this embodiment, the back metal bodies 53 and 63 are arranged over almost the entire back surface of the corresponding insulating substrates 51 and 61. To further enhance the heat dissipation effect, at least one of the back metal bodies 53 and 63 may be exposed from the sealant 30. In this embodiment, the back metal body 53 is exposed from one surface 30a of the sealant 30, and the back metal body 63 is exposed from the back surface 30b. The exposed surface of the back metal body 53 is substantially flush with the surface 30a. The exposed surface of the back metal body 63 is substantially flush with the back surface 30b. The back metal bodies 53 and 63 constitute the back surfaces 50b and 60b of the substrates 50 and 60.

[0075] The conductive spacer 70 provides a spacer function to ensure a predetermined distance between the semiconductor element 40 and the substrate 60. For example, the conductive spacer 70 ensures a height for electrically connecting the corresponding signal terminal 93 to the pad 40P of the semiconductor element 40. In other words, the conductive spacer 70 is provided to electrically connect the pad 40P and the signal terminal 93 by bonding wire 110. The conductive spacer 70 corresponds to a second metal member.

[0076] As shown in Figure 10, the conductive spacer 70 has one surface S1 facing the substrate 60, a surface S2 opposite to surface S1, and an annular side surface S3 that extends from surface S1 to the opposite surface S2. The opposite surface S2 is the surface facing the semiconductor element 40.

[0077] The conductive spacer 70 is located in the middle of the electrical and thermal conduction path between the source electrode 40S of the semiconductor element 40 and the substrate 60, and provides wiring and heat dissipation functions. The conductive spacer 70 contains a metallic material with good electrical and thermal conductivity, such as Cu. The conductive spacer 70 may have a plating film on its surface. The conductive spacer 70 is a columnar body with a planar shape that is approximately the same size as the source electrode 40S in a plan view.

[0078] The conductive spacer 70 is sometimes referred to as a terminal, terminal block, or metal block. The semiconductor device 20 has the same number of conductive spacers 70 as the semiconductor elements 40. Specifically, it has four conductive spacers 70. The conductive spacers 70 are individually connected to the semiconductor elements 40 (Figure 9).

[0079] The arm connection portion 80 electrically connects the relay wirings 55 and 65. In other words, the arm connection portion 80 electrically connects the upper arm 9H and the lower arm 9L. The arm connection portion 80 is provided between the semiconductor element 40H and the semiconductor element 40L in the Y direction. In a plan view, the arm connection portion 80 is provided in the overlapping region of the relay wiring 55 and the relay wiring 65. As shown in Figures 5 and 7, the arm connection portion 80 of this embodiment is configured to include a joint portion 81 and a joining material 103.

[0080] The joint portion 81 is a metal columnar body provided separately from the surface metal bodies 52 and 62. The joint portion 81 is connected to the surface metal body 52 and the surface metal body 62. Such a joint portion 81 is sometimes called a joint terminal. In the Z direction, a connecting material 103 is interposed between one end of the joint portion 81 and the relay wiring 55, and a connecting material 103 is interposed between the other end and the relay wiring 65. The joint portion 81 corresponds to the first metal member.

[0081] As shown in Figure 10, the joint portion 81 has one surface S11 facing the substrate 60, the opposite surface S12 of the surface S11, and an annular side surface S13 that is connected to the surface S11 and the opposite surface S12. The opposite surface S12 is the surface facing the substrate 50.

[0082] Alternatively, the joint portion 81 may be integrally connected to at least one of the surface metal bodies 52, 62. In other words, the joint portion 81 may be integrally provided with the surface metal bodies 52, 62 as part of the substrates 50, 60. The arm connection portion 80 may be configured without the joint portion 81. In other words, the arm connection portion 80 may be configured to consist only of the joining material 103.

[0083] As shown in Figure 10, the protective film 31 is provided on the surfaces of the semiconductor element 40, the insulating substrates 51, 61, the surface metal bodies 52, 62, the conductive spacer 70, and the joint portion 81. The protective film 31 is provided on the parts of the semiconductor element 40, the surface metal bodies 52, 62, the conductive spacer 70, and the joint portion 81 that are not joined by the joining materials 100-103. The protective film 31 is provided, for example, opposite the exposed surfaces S21, S22, and S31. The protective film 31 is also provided opposite the side surfaces S3 and S13. More specifically, the protective film 31 is in contact with the plating film 70m or the metal oxide film 70o, which will be described later.

[0084] Furthermore, the protective film 31 is provided in areas of the insulating substrates 51 and 61 where surface metal bodies 52 and 62 are not present. In other words, the protective film 31 is in contact with the insulating substrate 61, for example, as shown in the divided region EPA1.

[0085] Thus, the protective film 31 is provided between the semiconductor element 40 and the sealant 30. The protective film 31 is provided between the insulating substrates 51, 61 and the sealant 30. The protective film 31 is provided between the surface metal bodies 52, 62 and the sealant 30. The protective film 31 is provided between the conductive spacer 70 and the sealant 30. The protective film 31 is provided between the joint portion 81 and the sealant 30.

[0086] The protective film 31 is provided to protect the insulating substrates 51 and 61. The protective film 31 is made of a material that is more stretchable than the sealant 30. In other words, the protective film 31 is made of a material that is more responsive to deformation than the sealant 30. The protective film 31 is made of, for example, polyamide-imide. However, the protective film 31 may be made of a material other than polyamide-imide. The protective film 31 is also called a primer.

[0087] The coefficients of linear expansion of the insulating substrates 51 and 61 are adjusted to be approximately the same as those of the sealant 30. However, the coefficients of linear expansion of the insulating substrates 51 and 61 differ from those of the surface metal bodies 52 and 62. Therefore, the insulating substrates 51 and 61 are susceptible to stress due to the expansion and contraction of the sealant 30 and the expansion and contraction of the surface metal bodies 52 and 62 (external forces). In particular, stress is likely to occur in the insulating substrates 51 and 61 at the points where they are in contact with the sealant 30 and the surface metal bodies 52 and 62. Therefore, the insulating substrates 51 and 61 are prone to cracking starting from the points where they are in contact with the sealant 30 and the surface metal bodies 52 and 62.

[0088] In particular, in structures where the protective film 31 is not provided, stress generation becomes significant in the insulating substrates 51 and 61. In other words, the sealant 30 comes into contact with the insulating substrates 51 and 61. Therefore, the sealant 30 adheres well in the areas where it is in contact with the insulating substrates 51 and 61. On the other hand, the sealant 30 also comes into contact with the surface metal bodies 52 and 62, which are made of different materials. Therefore, the sealant 30 is prone to peeling in the areas where it is in contact with the surface metal bodies 52 and 62. Furthermore, in the semiconductor device 20, areas that adhere well and areas that are prone to peeling are adjacent to each other.

[0089] Therefore, in a semiconductor device 20 without a protective film 31, stress tends to concentrate at the boundary between the region where the sealant 30 and the insulating substrates 51 and 61 are in contact, and the region where the sealant 30 and the surface metal bodies 52 and 62 are in contact. Consequently, the insulating substrates 51 and 61 are prone to cracking. Furthermore, the insulating substrates 51 and 61 are subjected to external forces due to the delamination of the sealant 30 and the surface metal bodies 52 and 62. These external forces cause the insulating substrates 51 and 61 to crack.

[0090] The protective film 31 deforms when an external force is applied. Through this deformation, the protective film 31 reduces the external force applied to the insulating substrates 51 and 61. Therefore, the protective film 31 can suppress the stress generated in the insulating substrates 51 and 61 by the external force. In other words, the protective film 31 is provided to protect the insulating substrates 51 and 61 from external forces. The protective film 31 can also be described as a component that alleviates the stress generated in the insulating substrates 51 and 61.

[0091] Furthermore, the protective film 31 can improve the adhesion between the sealant 30 and the surface metal bodies 52 and 62. As a result, the protective film 31 can prevent the formation of a boundary between areas that adhere well and areas that are prone to peeling.

[0092] The external connection terminal 90 is a terminal for electrically connecting the semiconductor device 20 to an external device. The external connection terminal 90 is formed using a metal material with good conductivity, such as copper. The external connection terminal 90 is, for example, a plate. The external connection terminal 90 is sometimes referred to as a lead.

[0093] As shown in Figures 2, 3, and 4, the external connection terminal 90 includes a power terminal 91, an output terminal 92, and a signal terminal 93. The power terminal 91 includes a P terminal 91P and an N terminal 91N. The P terminal 91P, the N terminal 91N, and the output terminal 92 are main terminals that are electrically connected to the main electrodes of the semiconductor element 40. The signal terminal 93 includes a signal terminal 93H on the upper arm 9H side and a signal terminal 93L on the lower arm 9L side.

[0094] The power terminal 91 is an external connection terminal 90 that is electrically connected to the power lines 7 and 8 described above. The P terminal 91P is electrically connected to the positive terminal of the smoothing capacitor 5. The P terminal 91P is sometimes referred to as the positive terminal or high-potential power terminal. The P terminal 91P is connected to the P wiring 54 of the surface metal body 52. ​​In other words, the P terminal 91P is connected to the drain electrode 40D of the semiconductor element 40H that constitutes the upper arm 9H.

[0095] As shown in Figure 5, the P terminal 91P is connected to the vicinity of one end of the P wiring 54 in the Y direction. The P terminal 91P extends in the Y direction from the connection (joint) with the P wiring 54 and protrudes out of the sealant 30 from near the center in the Z direction on the side surface 30c. The semiconductor device 20 of this embodiment is equipped with two P terminals 91P.

[0096] As shown in Figures 4 and 9, terminal P 91P is positioned adjacent to terminal N 91N in a plan view, that is, closer to the center. The two terminals P 91P are positioned side by side in the X direction. The two terminals P 91P are positioned at approximately the same location in the Z direction.

[0097] The N terminal 91N is electrically connected to the negative terminal of the smoothing capacitor 5. The N terminal 91N is sometimes referred to as the negative terminal or low-potential power supply terminal. As shown in Figure 6, the N terminal 91N is connected to the N wiring 64 of the surface metal body 62. In other words, the N terminal 91N is connected to the source electrode 40S of the semiconductor element 40L that constitutes the lower arm 9L.

[0098] The N terminal 91N is connected to the vicinity of one end of the N wiring 64 in the Y direction. The N terminal 91N extends in the Y direction from the junction with the N wiring 64 and protrudes out of the encapsulant 30 from near the center in the Z direction on the side surface 30c. The semiconductor device 20 has two N terminals 91N. The two N terminals 91N are arranged side by side in the Y direction. The two N terminals 91N are arranged in approximately the same position in the Z direction.

[0099] As shown in Figure 4, the two N terminals 91N are positioned outside the two P terminals 91P in the X direction. In a plan view, one N terminal 91N is positioned near one P terminal 91P, and the other N terminal 91N is positioned near the other P terminal 91P. In the X direction, adjacent N terminals 91N and P terminals 91P have their sides facing each other in a portion including the portion that protrudes from the sealing body 30.

[0100] The output terminal 92 is electrically connected to the corresponding phase winding 3a (stator coil) of the motor generator 3. The output terminal 92 is sometimes referred to as the O terminal or AC terminal. As shown in Figures 3 and 5, the output terminal 92 is connected to the relay wiring 55 of the surface metal body 52 on the substrate 50. In other words, the output terminal 92 is connected to the connection point between the upper arm 9H and the lower arm 9L.

[0101] The output terminal 92 is connected to the vicinity of one end of the relay wiring 55 in the Y direction. The output terminal 92 extends in the Y direction from the junction with the relay wiring 55 and protrudes out of the sealant 30 from near the center in the Z direction on the side surface 30d. The semiconductor device 20 has two output terminals 92. One output terminal 92 is connected to one of the pair of extensions 552, and the other is connected to the other of the pair of extensions 552. The two output terminals 92 are arranged side by side in the X direction. The two output terminals 92 are located at approximately the same position in the Z direction.

[0102] Signal terminal 93 is electrically connected to a drive circuit (driver) (not shown). Signal terminal 93H is electrically connected to the pad 40P of the semiconductor element 40H via a connecting member such as a bonding wire 110. The number of signal terminals 93H is not particularly limited. Signal terminals 93H only need to include at least one terminal for applying a drive voltage to the gate electrode of the semiconductor element 40H. The bonding wire 110 corresponds to a wire.

[0103] The semiconductor device 20 of this embodiment is equipped with two signal terminals 93H. One of the signal terminals 93H is a gate electrode terminal. The gate electrode pads 40P of two semiconductor elements 40H are electrically connected to the gate electrode signal terminal 93H.

[0104] The signal terminal 93H extends in the Y direction from the joint with the bonding wire 110 and protrudes out of the sealant 30 from near the center in the Z direction on the side surface 30c. At least a portion of the protruding part of the signal terminal 93H extends in the same direction as the power terminal 91. The signal terminal 93H is positioned between the two P terminals 91P in the X direction. In other words, the external connection terminals 90 protruding from the side surface 30c are arranged in the X direction in the order of N terminal 91N, P terminal 91P, two signal terminals 93H, P terminal 91P, and N terminal 91N.

[0105] The signal terminals 93L are electrically connected to the pads 40P of the semiconductor element 40L via connecting members such as bonding wires 110. The number of signal terminals 93L is not particularly limited. The signal terminals 93L should include at least one terminal for applying a drive voltage to the gate electrode of the semiconductor element 40L. The signal terminals 93L may also include a terminal that is electrically connected to the Kelvin source electrode of the semiconductor element 40.

[0106] The semiconductor device 20 of this embodiment is equipped with four signal terminals 93L. One of the signal terminals 93L is a gate electrode terminal. The gate electrode pads 40P of two semiconductor elements 40L are electrically connected to the gate electrode signal terminal 93L.

[0107] The signal terminal 93L extends in the Y direction from the joint with the bonding wire 110 and protrudes out of the sealant 30 from near the center in the Z direction on the side surface 30d. At least a portion of the protruding part of the signal terminal 93L extends in the same direction as the output terminal 92. The signal terminal 93L is positioned between the two output terminals 92 in the X direction. In other words, the external connection terminal 90 protruding from the side surface 30d is arranged in the X direction in the order of output terminal 92, four signal terminals 93L, and output terminal 92.

[0108] As shown in Figures 4 and 7, one end of the bonding wire 110 is connected to the pad 40P. The other end of the bonding wire 110 is connected to the signal terminal 93. As shown in Figures 4 and 9, the multiple signal terminals 93H are arranged in a line in the X direction.

[0109] As shown in Figures 5 and 6, the drain electrode 40D of the semiconductor element 40 is joined to the surface metal body 52 via a bonding material 100. The source electrode 40S of the semiconductor element 40 is joined to the conductive spacer 70 via a bonding material 101. The conductive spacer 70 is joined to the surface metal body 62 via a bonding material 102. The joint portion 81 is joined to the metal bodies 52, 62 via a bonding material 103. Of the external connection terminals 90, the main terminals P terminal 91P, N terminal 91N, and output terminal 92 are joined to the corresponding surface metal bodies 52, 62 via a bonding material 104.

[0110] The bonding materials 100 to 104 are conductive bonding materials. For example, solder can be used as the bonding materials 100 to 104. An example of solder is a multi-component lead-free solder containing Cu, Ni, etc., in addition to Sn. Instead of solder, a sintered bonding material such as sintered silver may be used.

[0111] The P terminal 91P, N terminal 91N, and output terminal 92 may be directly joined to the corresponding surface metal bodies 52 and 62 without the use of the bonding material 104. The P terminal 91P, N terminal 91N, and output terminal 92 may also be directly joined to the surface metal bodies 52 and 62 by methods such as ultrasonic bonding, friction stir bonding, or laser welding. If the joint portion 81 is provided separately from the substrates 50 and 60, the joint portion 81 may be directly joined to the surface metal bodies 52 and 62.

[0112] As described above, in the semiconductor device 20, multiple semiconductor elements 40 constituting one phase of the upper and lower arm circuit 9 are sealed by a sealing body 30. The sealing body 30 integrally seals multiple semiconductor elements 40, a part of the substrate 50, a part of the substrate 60, multiple conductive spacers 70, an arm connection part 80, and a part of the external connection terminal 90. The sealing body 30 seals the insulating substrates 51, 61 and the surface metal bodies 52, 62 on the substrates 50 and 60.

[0113] The semiconductor element 40 is positioned between substrates 50 and 60 in the Z direction. The semiconductor element 40 is sandwiched between the opposing substrates 50 and 60. This allows heat from the semiconductor element 40 to be dissipated to both sides in the Z direction. The semiconductor device 20 has a double-sided heat dissipation structure. The back surface 50b of substrate 50 is substantially flush with one surface 30a of the encapsulant 30. The back surface 60b of substrate 60 is substantially flush with the back surface 30b of the encapsulant 30. Since the back surfaces 50b and 60b are exposed surfaces, heat dissipation can be enhanced.

[0114] Here, the surface metal bodies 52, 62, conductive spacer 70, and joint portion 81 will be explained in detail using Figures 9, 10, and 11. The surfaces of the surface metal bodies 52, 62, conductive spacer 70, and joint portion 81 are provided with a plating film 70m. In other words, the surface metal bodies 52, 62, conductive spacer 70, and joint portion 81 have a plating film 70m, which is a thin metal film, formed on them by a plating process. As shown in Figure 11, for example, the conductive spacer 70 has a plating film 70m provided on its side surface S3.

[0115] In the following, the plating film 70m provided on the surfaces of the surface metal bodies 52, 62, the conductive spacer 70, and the joint portion 81 will also be referred to as the plating film 70m of the surface metal bodies 52, 62, the conductive spacer 70, and the joint portion 81. For example, the plating film 70m provided on the surface of the conductive spacer 70 will be referred to as the plating film 70m of the conductive spacer 70.

[0116] The plating film 70m is provided, for example, with nickel (Ni) as the main component. The surface metal bodies 52, 62, conductive spacer 70, and joint portion 81 are the objects to which the plating film 70m is applied, and are also referred to as the target metal bodies. The plating film 70m corresponds to a metal film. The entire target metal body is covered with the plating film 70m.

[0117] Furthermore, the plating film 70m may be provided only on the portion of the target metal body that faces the sealant 30 or the protective film 31. In other words, the plating film 70m may be provided only between the target metal body and the sealant 30. Also, the plating film 70m may be provided on at least one of the surface metal bodies 52, 62, the conductive spacer 70, and the joint portion 81.

[0118] As shown in Figure 11, the plating film 70m has uneven surfaces 71. More specifically, the uneven surfaces 71 are formed in the plating film 70m by laser irradiation. The uneven surfaces 71 have, for example, sharp angles at their apex and base. In other words, the uneven surfaces 71 are also referred to as laser-roughened areas, roughened areas, or laser-roughened parts.

[0119] The surface of the uneven portion 71 of the plating film 70m is oxidized. In other words, the metal oxide film 70o is formed on the surface of the plating film 70m when the uneven portion 71 is formed. The surface of the uneven portion 71 is a metal oxide film 70o.

[0120] The uneven portion 71 is provided on at least a portion of the plating film 70m that faces the protective film 31. Therefore, it can be said that a metal oxide film 70o is provided between the uneven portion 71 and the protective film 31. The metal oxide film 70o is in contact with the protective film 31. It can also be said that the plated film 70m has an oxidized surface with the uneven portion 71 in contact with the protective film 31. The metal oxide film is, for example, a nickel oxide film.

[0121] As shown in Figures 10 and 11, the uneven portion 71 is preferably provided on the plating film 70m of the conductive spacer 70, for example. The uneven portion 71 is formed on the plating film 70m provided on the side surface S3. More specifically, the uneven portion 71 is provided within a predetermined range in the Z direction from the source electrode 40S on the plating film 70m of the conductive spacer 70, as shown in the first formation region UEA1. The uneven portion 71 is also provided in an annular shape on the plating film 70m of the conductive spacer 70. In other words, the uneven portion 71 is provided so as to surround the central axis of the conductive spacer 70. The central axis is a virtual straight line along the Z direction.

[0122] This allows the semiconductor device 20 to suppress the bonding material 101 from connecting with the conductive spacer 70. In other words, the semiconductor device 20 can suppress the bonding material 101 from crawling up the conductive spacer 70.

[0123] Furthermore, as shown in Figures 9 and 10, it is preferable that the uneven portion 71 is provided, for example, on the plating film 70m of the surface metal body 52. ​​The uneven portion 71 is formed on the plating film 70m provided on the exposed surface S22. More specifically, as shown in the second formation region UEA2, the uneven portion 71 is provided around the source electrode 40S in the plating film 70m of the surface metal body 52. ​​Furthermore, it is preferable that the uneven portion 71 is provided in an annular shape so as to surround the source electrode 40S in the plating film 70m of the surface metal body 52. ​​This allows the semiconductor device 20 to suppress the bonding material 100 from wetting and spreading along the surface metal body 52.

[0124] Furthermore, the uneven portion 71 may be formed on the plating film 70m provided on the side surface forming the gap between the surface metal bodies 52 and 62. In other words, the uneven portion 71 may be formed on the plating film 70m provided on the side surface of the P wiring 54 and on the plating film 70m provided on the relay wiring 55. Also, the uneven portion 71 may be formed on the plating film 70m provided on the side surface of the N wiring 64 and on the plating film 70m provided on the side surface of the relay wiring 65. Moreover, the uneven portion 71 may be provided over the entire area of ​​the plating film 70m.

[0125] <Effects> As described above, the semiconductor device 20 has an oxidized surface with an uneven portion 71, i.e., the metal oxide film 70o is in contact with the protective film 31. Therefore, the semiconductor device 20 can suppress the peeling of the protective film 31. More specifically, the polyamide-imide material of the protective film 31 is susceptible to moisture absorption. Due to moisture absorption by the protective film 31, the plating film 70m of the semiconductor device 20 may corrode. However, because the metal oxide film 70o is in contact with the protective film 31, the corrosion of the plating film 70m can be suppressed in the semiconductor device 20. Therefore, the semiconductor device 20 can suppress the peeling of the protective film 31 due to corrosion of the plating film 70m.

[0126] Furthermore, since peeling of the protective film 31 is suppressed in the semiconductor device 20, the insulating substrates 51 and 61 can be protected by the protective film 31. In other words, the semiconductor device 20 can maintain the function of the protective film 31. The function of the protective film 31 is to protect the insulating substrates 51 and 61.

[0127] (Modification) Here, a modification of the semiconductor device 20 will be described using Figures 12 to 17. In the modification, one semiconductor element 40H is mounted on the P wiring 54 and one semiconductor element 40L is mounted on the relay wiring 55. However, the semiconductor device 20 of the modification may also be provided with semiconductor elements 40H and 40L, similar to the embodiment described above.

[0128] The semiconductor device 20 may have holes 72a in at least a portion of the surface metal bodies 52, 62, conductive spacers 70, and joint portions 81. The holes 72a are provided in at least a portion of the surface metal bodies 52, 62, conductive spacers 70, and joint portions 81 that are facing the sealing body 30. In this embodiment, as an example, a case is adopted in which holes 72a are provided in the relay wiring 55, which is part of the surface metal body 52. ​​Note that Figures 12 to 17 omit the illustration of the plating film 70m and the metal oxide film 70o. The holes 72a are also called pinholes.

[0129] As shown in Figure 12, the hole 72a is a bottomed hole. The hole 72a is a recessed area relative to the exposed surface S22. The hole 72a is formed on the surface metal body 52 by etching or the like. The hole 72a can be formed in the same process as the patterning of the surface metal bodies 52 and 62. The surface metal body 52 has multiple holes 72a. It can be said that the surface metal body 52 has a group of holes including multiple holes 72a.

[0130] As shown in Figure 13, the opening area of ​​the opening end 722 of the hole 72a is smaller than the opening area of ​​the interior 721. The interior 721 is the widest opening area in the hole 72a. In this embodiment, as an example, a circular hole 72a is used in plan view. However, the shape of the hole 72a is not limited to a circle. The surface metal body 52 is provided with the hole 72a in an undercut shape.

[0131] After the hole 72a is formed on the surface metal body 52, a plating film 70m is applied. Then, a protective film 31 is applied to the surface metal body 52. ​​The protective film 31 is applied not only to the exposed surface S22 but also to the inner surface of the hole 72a. Therefore, the protective film 31 has both flat and concave portions. Furthermore, a part of the sealant 30 is positioned in the hole 72a. In other words, a part of the sealant 30 is also provided inside the hole 72a.

[0132] The semiconductor device 20 can increase the contact area between the sealant 30 and the protective film 31 compared to a configuration without the hole 72a. Therefore, the semiconductor device 20 can suppress delamination between the sealant 30 and the protective film 31. Furthermore, since a portion of the sealant 30 is located within the hole 72a, which has a narrow opening area at the open end 722, delamination can be suppressed even further in the semiconductor device 20.

[0133] As shown in Figure 14, the surface metal body 52 may have a hole 72b instead of a hole 72a. The hole 72b gradually widens from the bottom 723 towards the opening end 722. The semiconductor device 20 can increase the contact area between the sealant 30 and the protective film 31 compared to a configuration without the hole 72b. Therefore, the semiconductor device 20 can suppress the peeling of the sealant 30 and the protective film 31.

[0134] Furthermore, as shown in Figure 15, the multiple holes 72a are arranged in a line in one direction. In a plan view, the multiple holes 72a are located between the semiconductor element 40L and the joint portion 81. In a plan view, it can also be said that the multiple holes 72a are located along the drain electrode 40D. In a plan view, the uneven portion 71 is provided between the multiple holes 72a and the semiconductor element 40L. Note that the holes 72b are located in the same position as the holes 72a.

[0135] As shown in Figure 16, the multiple holes 72a may be arranged in an annular pattern. In a plan view, the multiple holes 72a are arranged in an annular pattern surrounding the semiconductor element 40L. It can also be said that the multiple holes 72a are arranged in an annular pattern around the drain electrode 40D. In a plan view, the uneven surface 71 is provided between the multiple holes 72a and the semiconductor element 40L.

[0136] As shown in Figure 17, the hole 72a may be a straight line extending in one direction. In other words, the hole 72a is provided in the shape of a groove. The hole 72a is provided between the semiconductor element 40L and the joint 81. It can also be said that the hole 72a is provided along the drain electrode 40D. In plan view, the hole 72a may be an annular groove surrounding the semiconductor element 40L. In plan view, a recessed portion 71 is provided between the hole 72a and the semiconductor element 40L.

[0137] Furthermore, it is preferable that the hole 72a be provided so as to avoid the opposing region of the divided region EPA1 shown in Figure 10. Therefore, it can be said that the hole 72a is provided between its opposing region and the semiconductor element 40L. Also, it can be said that the hole 72a is provided between its opposing region and the second formation region UEA2.

[0138] Since the semiconductor device 20 is provided with a protective film 31, even if the plating film 70m has irregularities 71, it is difficult to obtain an adhesion effect of the sealant 30. Furthermore, the coefficient of linear expansion of the sealant 30 is different from that of the surface metal bodies 52 and 62. Therefore, the protective film 31 is susceptible to stress due to the force (external force) applied to it by the expansion and contraction of the sealant 30 and the expansion and contraction of the surface metal bodies 52 and 62. The protective film 31 is stretched when an external force is applied.

[0139] If the shrinkage or thermal expansion of the sealant 30 of the semiconductor device 20 becomes excessive, the protective film 31 may be stretched and lose its elasticity. In this case, the stress generated in the bonding materials 100-104, main electrodes 40D, 40S, and pads 40P protected by the sealant 30 of the semiconductor device 20 may increase. As a result, malfunctions may occur in the bonding materials 100-104, main electrodes 40D, 40S, and pads 40P of the semiconductor device 20.

[0140] However, the modified semiconductor device 20 can suppress the peeling of the sealant 30 and the protective film 31, as described above. Therefore, the modified semiconductor device 20 can suppress the stretching of the protective film 31. Consequently, the modified semiconductor device 20 can reduce defects occurring in the bonding materials 100-104, the main electrodes 40D, 40S, and the pad 40P.

[0141] Preferred embodiments of the present disclosure have been described above. The present disclosure is not limited to such embodiments or structures. The present disclosure encompasses a variety of modifications and variations within the scope of equivalents. In addition, while various combinations and forms are shown in the present disclosure, other combinations and forms that include only one, more, or fewer of these elements also fall within the scope and idea of ​​the present disclosure.

[0142] (Disclosure of Technical Ideas) This specification discloses several technical ideas as described in the following paragraphs. Some paragraphs may be written in a polydependent form, where subsequent paragraphs alternately refer to preceding paragraphs. Furthermore, some paragraphs may be written in a polydependent form, where they refer to other polydependent paragraphs. These paragraphs written in a polydependent form define several technical ideas.

[0143] (Technical Concept 1) A semiconductor element (40) having main electrodes (40D, 40S) on both sides in the thickness direction; a substrate (50, 60) having an insulating substrate (51, 61), surface metal bodies (52, 62) disposed on a part of the surface of the insulating substrate and electrically connected to the main electrodes, and back metal bodies (53, 63) disposed on the back surface of the insulating substrate; a first metal member (81) connected to the surface metal body; a second metal member (70) connected to the main electrodes and the surface metal body; a metal film (70m) provided on the surfaces of the surface metal body, the first metal member and the second metal member; a resin encapsulant (30) that is in contact with a part of the insulating substrate and integrally encapsulates the semiconductor element, the substrate, the first metal member and the second metal member; and a protective film (31) provided between the semiconductor element, the insulating substrate, the surface metal body, the first metal member and the second metal member and the resin encapsulant to protect the insulating substrate. A semiconductor device in which at least a portion of the metal film facing the protective film is provided with an uneven surface (71) and the oxidized surface is in contact with the protective film.

[0144] (Technical Concept 2) The semiconductor device according to Technical Concept 1, comprising a bonding material (101) for electrically joining the main electrode and the second metal member, wherein the uneven portion is provided on the metal film provided on the second metal member.

[0145] (Technical idea 3) The semiconductor device according to technical idea 2, wherein the uneven portion is provided in an annular shape within a predetermined range from the main electrode in the metal film provided on the second metal member.

[0146] (Technical Idea 4) The semiconductor device according to any one of Technical Ideas 1 to 3, wherein the main electrode comprises a first main electrode provided on one surface of the semiconductor element and a second main electrode provided on the back surface of the semiconductor element, the surface metal body comprises a first surface metal body electrically connected to the first main electrode and a second surface metal body electrically connected to the second main electrode via the second metal member, and the uneven portion is provided on the metal film provided on the first surface metal body.

[0147] (Technical idea 5) The semiconductor device according to technical idea 4, wherein the uneven portion is provided around the main electrode of the metal film provided on the first surface metal body.

[0148] (Technical Idea 6) At least a portion of the surface metal body, the first metal member, and the second metal member facing the resin encapsulant is provided with a bottomed hole (72a, 72b), and a portion of the resin encapsulant is arranged in the hole, the semiconductor device according to any one of Technical Ideas 1 to 5.

[0149] (Technical Idea 7) The semiconductor device according to Technical Idea 6, wherein the opening area of ​​the opening end (722) of the hole is smaller than the opening area of ​​the interior (721).

Claims

1. A semiconductor element (40) having main electrodes (40D, 40S) on both sides in the thickness direction; a substrate (50, 60) having an insulating substrate (51, 61), surface metal bodies (52, 62) disposed on a part of the surface of the insulating substrate and electrically connected to the main electrodes, and back metal bodies (53, 63) disposed on the back surface of the insulating substrate; a first metal member (81) connected to the surface metal body; a second metal member (70) connected to the main electrodes and the surface metal body; a metal film (70m) provided on the surfaces of the surface metal body, the first metal member and the second metal member; a resin encapsulant (30) that is in contact with a part of the insulating substrate and integrally encapsulates the semiconductor element, the substrate, the first metal member and the second metal member; and a protective film (31) provided between the semiconductor element, the insulating substrate, the surface metal body, the first metal member and the second metal member and the resin encapsulant to protect the insulating substrate. A semiconductor device in which at least a portion of the metal film facing the protective film is provided with an uneven surface (71) and the oxidized surface is in contact with the protective film.

2. The semiconductor device according to claim 1, comprising a bonding material (101) for electrically joining the main electrode and the second metal member, wherein the uneven portion is provided on the metal film provided on the second metal member.

3. The semiconductor device according to claim 2, wherein the uneven portion is provided in an annular shape within a predetermined range from the main electrode in the metal film provided on the second metal member.

4. The semiconductor device according to any one of claims 1 to 3, wherein the main electrode comprises a first main electrode provided on one surface of the semiconductor element and a second main electrode provided on the back surface of the semiconductor element, the surface metal body comprises a first surface metal body electrically connected to the first main electrode and a second surface metal body electrically connected to the second main electrode via the second metal member, and the uneven portion is provided on the metal film provided on the first surface metal body.

5. The semiconductor device according to claim 4, wherein the uneven portion is provided around the main electrode of the metal film provided on the first surface metal body.

6. The semiconductor device according to any one of claims 1 to 3, wherein at least a portion of the surface metal body, the first metal member, and the second metal member facing the resin encapsulant is provided with a bottomed hole (72a, 72b), and a portion of the resin encapsulant is disposed in the hole.

7. The semiconductor device according to claim 6, wherein the opening area of ​​the opening end (722) of the hole is smaller than the opening area of ​​the interior (721).

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