Substrate processing method and substrate processing apparatus

Abstract

A substrate processing method according to an embodiment of the present disclosure comprises a first step, a second step, and a third step. In the first step, a first chemical solution is supplied to the surface of a substrate to attach a modifying group to exposed silicon oxide. In the second step, a second chemical solution is supplied to the surface of the substrate to attach a silyl group to the modifying group. In the third step, the substrate to which the silyl group is attached is dried.

Description

Substrate Processing Method and Substrate Processing Apparatus

[0001] Embodiments of the present disclosure relate to a substrate processing method and a substrate processing apparatus.

[0002] Conventionally, a technique has been developed in which the surface of a substrate is subjected to a liquid treatment to impart water repellency, and then the substrate is dried, in order to dry the substrate while preventing collapse of patterns formed on a semiconductor substrate (see Patent Document 1).

[0003] Japanese Unexamined Patent Application Publication No. 2010-114414

[0004] The present disclosure provides a technique capable of improving the water repellency performance of a substrate.

[0005] A substrate processing method according to an aspect of the present disclosure includes a first step, a second step, and a third step. In the first step, a first chemical solution is supplied to the surface of a substrate to attach modifying groups to exposed silicon oxide. In the second step, a second chemical solution is supplied to the surface of the substrate to attach silyl groups to the modifying groups. In the third step, the substrate to which the silyl groups are attached is dried.

[0006] According to the present disclosure, the water repellency performance of a substrate can be improved. Note that the effects described herein are not necessarily limited, and may be any of the effects described in the present disclosure.

[0007] Figure 1 is a block diagram illustrating the schematic configuration of a substrate processing system according to the embodiment. Figure 2 is a schematic plan view of the input area, batch area, and IF area of ​​the substrate processing system according to the embodiment. Figure 3 is a schematic plan view of the IF area, single-wafer area, and output area of ​​the substrate processing system according to the embodiment. Figure 4 is a block diagram illustrating the configuration of an etching tank according to the embodiment. Figure 5 is a schematic diagram showing an example of a specific configuration of a single-wafer processing unit according to the embodiment. Figure 6 is a flowchart illustrating the substrate processing procedure performed by the substrate processing system according to the embodiment. Figure 7 is a diagram illustrating an example of the procedure for water-repellent treatment according to the embodiment. Figure 8 is a diagram illustrating an example of the procedure for water-repellent treatment according to the embodiment. Figure 9 is a diagram illustrating an example of the procedure for water-repellent treatment according to the embodiment. Figure 10 is a diagram illustrating an example of the procedure for water-repellent treatment according to the embodiment. Figure 11 is a diagram illustrating an example of the procedure for water-repellent treatment according to the embodiment. Figure 12 is a diagram illustrating an example of the procedure for water-repellent treatment according to the embodiment. Figure 13 is a diagram illustrating an example of the procedure for water-repellent treatment according to the embodiment. Figure 14 is a diagram illustrating an example of the procedure for drying treatment according to the embodiment. Figure 15 is a diagram illustrating the state of the silicon oxide surface during the water-repellent treatment in a reference example. Figure 16 is a diagram illustrating the state of the silicon oxide surface during the water-repellent treatment according to the embodiment. Figure 17 is a diagram showing the contact angle of the wafer after the water-repellent treatment in the embodiment and reference example. Figure 18 is a diagram showing the relationship between the processing time of the modification group adhesion treatment according to the embodiment and the contact angle of the wafer.

[0008] The embodiments of the substrate processing method and substrate processing apparatus disclosed herein will be described in detail below with reference to the attached drawings. However, the embodiments described below do not limit this disclosure. Furthermore, it should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from reality. Moreover, there may be differences in dimensional relationships or ratios between different parts of the drawings.

[0009] Furthermore, in the embodiments described below, expressions such as "constant," "orthogonal," or "perpendicular" may be used, but these expressions do not require strict "constant," "orthogonal," or "perpendicular" conditions. In other words, each of the above expressions allows for deviations such as manufacturing accuracy or installation accuracy.

[0010] Furthermore, in the drawings referenced below, for the sake of clarity, mutually orthogonal X, Y, and Z axis directions are sometimes defined, and a Cartesian coordinate system is shown with the positive Z axis pointing vertically upward.

[0011] Conventionally, in order to prevent the collapse of patterns formed on a semiconductor substrate while drying the substrate, a technique has been developed in which the surface of the substrate is treated with a liquid to make it water-repellent, and then the substrate is dried.

[0012] In the conventional technology described above, if the substrate is not properly treated to be water-repellent, there is a risk of pattern collapse during the subsequent drying process. However, there was room for further improvement in enhancing the water-repellent performance of the substrate in the conventional technology described above.

[0013] Therefore, there is a need for a technology that can overcome the aforementioned problems and improve the water-repellent properties of the substrate.

[0014] <Configuration of the Substrate Processing System> First, the configuration of the substrate processing system 1 according to the embodiment will be described with reference to Figure 1. Figure 1 is a block diagram showing the schematic configuration of the substrate processing system 1 according to the embodiment.

[0015] As shown in Figure 1, the substrate processing system 1 according to this embodiment includes a loading area A1, a batch area A2, an IF (interface) area A3, a single-wafer area A4, and an unloading area A5. The loading area A1, batch area A2, IF area A3, single-wafer area A4, and unloading area A5 are arranged in this order, for example.

[0016] In the substrate processing system 1 according to this embodiment, first, semiconductor wafers W (see Figure 2) (hereinafter simply referred to as "wafers W") are brought into the loading area A1. The loading area A1 is provided with a first loading section 20 (see Figure 2) on which a carrier containing multiple wafers W is placed.

[0017] In the loading area A1, processes such as taking multiple wafers W from the carrier C (see Figure 2) placed on the first mounting section 20 to form lots, and transferring the formed lots to the batch area A2 are carried out.

[0018] Batch area A2 is provided with a batch processing unit that processes wafers W in batches. In this embodiment, etching and other processes are performed on wafers W in batches using the batch processing unit in batch area A2. Batch area A2 is also provided with a lot transport mechanism 50 (see Figure 2) for transporting lots. The lot transport mechanism 50 transports lots formed in the input area A1 to batch area A2.

[0019] In IF area A3, wafers W are transferred from batch area A2 to single-wafer area A4. IF area A3 is provided with an interface unit 55 (see Figure 2) for transporting wafers W one by one. In IF area A3, wafers W are transported one by one from batch area A2 to single-wafer area A4 using this interface unit 55.

[0020] The single-wafer area A4 is provided with a single-wafer processing unit 6 (see Figure 3) for liquid treatment and drying of each wafer W individually.

[0021] In other words, in the substrate processing system 1 according to this embodiment, etching of wafers W is performed in batch area A2 in lot units, and then liquid treatment and drying of wafers W are performed one wafer at a time in single-wafer area A4.

[0022] The unloading area A5 is provided with a second loading section 83 (see Figure 3) on which empty carriers C are placed. In the unloading area A5, wafers W that have finished drying in the single-wafer area A4 are placed on carriers C (see Figure 3) on the second loading section 83.

[0023] Next, the specific configuration of the substrate processing system 1 according to the embodiment will be described with reference to Figures 2 and 3. First, the configurations of the loading area A1, batch area A2, and IF area A3 will be described with reference to Figure 2. Figure 2 is a schematic plan view of the loading area A1, batch area A2, and IF area A3 of the substrate processing system 1 according to the embodiment.

[0024] (Regarding the loading area) As shown in Figure 2, the loading area A1 contains the carrier loading section 2 and the lot forming section 3. The carrier loading section 2 and the lot forming section 3 are arranged, for example, along the direction of arrangement of areas A1 to A5 (X-axis direction). The lot forming section 3 is adjacent to the batch area A2.

[0025] The carrier loading section 2 comprises a first loading section 20, a first transport mechanism 21, carrier stocks 22 and 23, and a carrier loading platform 24.

[0026] Multiple carriers C transported from the outside are placed on the first mounting section 20. A carrier C is a container that holds multiple (for example, 25) wafers W arranged vertically in a horizontal position. The first transport mechanism 21 transports the carriers C between the first mounting section 20, carrier stocks 22 and 23, and carrier mounting table 24.

[0027] The lot formation unit 3 comprises a second transport mechanism 30 and a plurality (for example, two) of lot holding units 31, and forms lots composed of a plurality of wafers W. In one embodiment, one lot is formed by combining a total of 50 wafers W housed in, for example, two carriers C.

[0028] Multiple wafers W forming a single lot are arranged, for example, with their surfaces facing each other and at a certain interval between them. The number of wafers W constituting a single lot is not limited to 50. For example, a lot may consist of 100 wafers W.

[0029] The second transport mechanism 30 transports multiple wafers W between the carrier C placed on the carrier mounting table 24 and the lot holding unit 31. The second transport mechanism 30 is composed of, for example, an articulated robot and transports multiple (for example, 25) wafers W at once. The second transport mechanism 30 can also change the orientation of the multiple wafers W from a horizontal orientation to a vertical orientation during transport.

[0030] The lot holding unit 31 holds multiple wafers W in a vertical position for one lot. The second transport mechanism 30 takes multiple wafers W from the carrier C placed on the carrier mounting table 24 and places them in a vertical position on the lot holding unit 31. For example, one lot is formed by repeating this operation twice.

[0031] (Regarding the batch area) Batch area A2 contains a pre-processing unit 4A, multiple (in this case, two) etching processing units 4B, and a post-processing unit 4C. The pre-processing unit 4A, the multiple etching processing units 4B, and the post-processing unit 4C are examples of batch processing units.

[0032] The pre-processing unit 4A, the multiple etching processing units 4B, and the post-processing unit 4C are arranged in this order along the direction of arrangement of areas A1 to A5 (X-axis direction). The pre-processing unit 4A is adjacent to, for example, the input area A1, and the post-processing unit 4C is adjacent to, for example, the IF area A3.

[0033] The pre-treatment section 4A includes a pre-treatment tank 40, a rinsing tank 41, and a rod immersion mechanism 42.

[0034] The processing tanks 40 and 41 are capable of accommodating one lot of wafers W arranged in a vertical position. Processing tank 40 stores a processing solution for pretreatment. For example, processing tank 40 stores DHF (dilute hydrofluoric acid) as a processing solution for pretreatment, in this case for removing the native oxide film. Processing tank 41 stores a processing solution for rinsing (for example, DIW (Deionized Water)).

[0035] The lot immersion mechanism 42 holds multiple wafers W that form a lot in a vertical position. The lot immersion mechanism 42 has a lifting mechanism for raising and lowering the held lot, which lowers the lot from above the processing tanks 40 and 41 to immerse it in the processing tanks 40 and 41, or raises the lot that has been immersed in the processing tanks 40 and 41 to remove it from the processing tanks 40 and 41.

[0036] Furthermore, the rod immersion mechanism 42 has a horizontal movement mechanism, which allows the rod to be moved horizontally between the upper position of the treatment tank 40 and the upper position of the treatment tank 41. Here, an example is shown where the pre-treatment tank 40 is located on the positive X-axis side of the rinsing treatment tank 41, but the pre-treatment tank 40 may also be located on the negative X-axis side of the rinsing treatment tank 41.

[0037] The etching processing unit 4B includes an etching tank 43, a rinsing tank 44, and rod immersion mechanisms 45 and 46.

[0038] Processing tanks 43 and 44 are capable of accommodating one lot of wafers W arranged in a vertical position. Processing tank 43 stores an etching solution (hereinafter also referred to as "etching solution"). Details of processing tank 43 will be described later. Processing tank 44 stores a rinsing solution (for example, DIW).

[0039] The lot immersion mechanisms 45 and 46 hold multiple wafers W that form a lot in a vertical position with a certain interval between them. The lot immersion mechanism 45 has a lifting mechanism for raising and lowering the held lot, and can lower the lot from above the processing tank 43 to immerse it in the processing tank 43, or raise the lot that has been immersed in the processing tank 43 to remove it from the processing tank 43.

[0040] Similarly, the rod immersion mechanism 46 also has a lifting mechanism for raising and lowering the held rod, which can be used to lower the rod from above the processing tank 44 to immerse it in the processing tank 44, or to raise the rod that has been immersed in the processing tank 44 to remove it from the processing tank 44.

[0041] Note that although an example in which the processing tank 43 for etching processing is located on the X-axis positive direction side of the processing tank 44 for rinsing is shown here, the processing tank 43 for etching processing may be located on the X-axis negative direction side of the processing tank 44 for rinsing.

[0042] The post-processing unit 4C includes a processing tank 47 for post-processing, a processing tank 48 for rinsing, and a lot immersion mechanism 49. The processing tank 47 and the processing tank 48 can accommodate one lot of wafers W arranged in a vertical posture.

[0043] A processing liquid for post-processing is stored in the processing tank 47. For example, SC1 (a mixed solution of ammonia, hydrogen peroxide and water) is stored in the processing tank 40 as a processing liquid for post-processing, here for cleaning. Further, a processing liquid for rinsing (such as DIW) is stored in the processing tank 48. Such a processing tank 48 for rinsing is adjacent to the IF area A3.

[0044] The lot immersion mechanism 49 holds the plurality of wafers W forming a lot in a vertical posture. The lot immersion mechanism 49 has an elevating mechanism that raises and lowers the held lot, and lowers the lot from above the processing tanks 47 and 48 to immerse the lot in the processing tanks 47 and 48, or raises the lot immersed in the processing tanks 47 and 48 to take it out from the processing tanks 47 and 48.

[0045] Further, the lot immersion mechanism 49 has a horizontal movement mechanism, and can horizontally move the lot between a position above the processing tank 47 and a position above the processing tank 48.

[0046] Here, an example in which four batch processing units (the pre-processing unit 4A, the plurality of etching processing units 4B, and the post-processing unit 4C) are arranged in the batch area A2 is shown, but the number of batch processing units is not limited to this example, and may be, for example, one.

[0047] The substrate processing system 1 includes a lot transport mechanism 50. The lot transport mechanism 50 is positioned to span the carry-in area A1 and the batch area A2, and transports a lot from the carry-in area A1 to the batch area A2.

[0048] The lot transport mechanism 50 comprises a holder 51, a rail 52, and a moving body 53. The holder 51 holds a lot in which multiple wafers W are in a vertical position. The rail 52 extends along the X-axis from the lot holding section 31 in the loading area A1 to the processing tank 48 in the batch area A2. The moving body 53 is mounted on the rail 52 and moves the holder 51 along the rail 52.

[0049] The lot transport mechanism 50 holds the lot held in the lot holding section 31 using the holder 51 and transports the held lot to the batch area A2. The lot transport mechanism 50 then transports the lot in the order of pre-processing section 4A, etching section 4B, and post-processing section 4C.

[0050] Here, the etching tank 43 will be described with reference to Figure 4. Figure 4 is a block diagram showing the configuration of the etching tank 43 according to this embodiment.

[0051] In the processing tank 43, for example, a given etching solution is used to remove the silicon nitride film (SiN) and silicon oxide film (SiO2) formed on the wafer W. ２ An etching process is performed to selectively etch the silicon nitride film among the ) . In such an etching process, for example, phosphoric acid (H ３ PO ４ A solution prepared by adding a silicon (Si)-containing compound to an aqueous solution to adjust the silicon concentration is used as an etching solution.

[0052] Methods for adjusting the silicon concentration in the etching solution include immersing a dummy substrate in an aqueous phosphoric acid solution to dissolve silicon (seasoning), or dissolving a silicon-containing compound such as colloidal silica in an aqueous phosphoric acid solution. Alternatively, the silicon concentration may be adjusted by adding an aqueous solution of a silicon-containing compound to the aqueous phosphoric acid solution.

[0053] As shown in Figure 4, the etching tank 43 comprises an inner tank 101 and an outer tank 102. The inner tank 101 is a box-shaped tank with an open top, and stores etching solution inside. A lot formed from multiple wafers W is immersed in the inner tank 101. The outer tank 102 is open at the top and is located around the upper part of the inner tank 101. Etching solution that overflows from the inner tank 101 flows into the outer tank 102.

[0054] Furthermore, the processing tank 43 includes a phosphoric acid aqueous solution supply unit 103, a silicon supply unit 104, and a DIW supply unit 105.

[0055] The phosphoric acid aqueous solution supply unit 103 includes a phosphoric acid aqueous solution supply source 131, a phosphoric acid aqueous solution supply line 132, and a flow rate regulator 133.

[0056] The phosphoric acid aqueous solution supply source 131 generates or stores a phosphoric acid aqueous solution concentrated to a desired phosphoric acid concentration. The phosphoric acid aqueous solution supply line 132 connects the phosphoric acid aqueous solution supply source 131 to the outer tank 102 and supplies the phosphoric acid aqueous solution from the phosphoric acid aqueous solution supply source 131 to the outer tank 102.

[0057] The flow regulator 133 is installed in the phosphoric acid aqueous solution supply line 132 and adjusts the amount of phosphoric acid aqueous solution supplied to the outer tank 102. The flow regulator 133 consists of an on / off valve, a flow control valve, and a flow meter, etc.

[0058] The silicon supply unit 104 includes a silicon supply source 141, a silicon supply line 142, and a flow rate regulator 143.

[0059] The silicon supply source 141 is, for example, a tank for storing an aqueous solution of a silicon-containing compound. The silicon supply line 142 connects the silicon supply source 141 to the outer tank 102 and supplies the aqueous solution of the silicon-containing compound from the silicon supply source 141 to the outer tank 102.

[0060] The flow regulator 143 is installed in the silicon supply line 142 and adjusts the amount of silicon-containing compound aqueous solution supplied to the outer tank 102. The flow regulator 143 consists of an on-off valve, a flow control valve, and a flow meter. By adjusting the amount of silicon-containing compound aqueous solution supplied by the flow regulator 143, the silicon concentration of the etching solution is adjusted.

[0061] The DIW supply unit 105 includes a DIW supply source 151, a DIW supply line 152, and a flow rate regulator 153.

[0062] The DIW supply source 151 is, for example, a tank for storing DIW. The DIW supply line 152 connects the DIW supply source 151 to the outer tank 102 and supplies DIW at a given temperature from the DIW supply source 151 to the outer tank 102.

[0063] The flow regulator 153 is installed in the DIW supply line 152 and adjusts the amount of DIW supplied to the outer tank 102. The flow regulator 153 consists of an on-off valve, a flow control valve, and a flow meter. By adjusting the amount of DIW supplied by the flow regulator 153, the temperature, phosphoric acid concentration, and silicon concentration of the etching solution are adjusted.

[0064] Furthermore, the processing tank 43 is equipped with a circulation unit 106. The circulation unit 106 circulates the etching solution between the inner tank 101 and the outer tank 102. The circulation unit 106 includes a circulation line 161, a plurality of nozzles 162, a filter 163, a heater 164, and a pump 165.

[0065] The circulation line 161 connects the outer tank 102 and the inner tank 101. One end of the circulation line 161 is connected to the bottom of the outer tank 102. The other end of the circulation line 161 is connected to a plurality of nozzles 162 located on the lower side inside the inner tank 101.

[0066] The filter 163, heater 164, and pump 165 are installed in the circulation line 161. The filter 163 removes impurities from the etching solution flowing through the circulation line 161. The heater 164 heats the etching solution flowing through the circulation line 161 to a temperature suitable for the etching process.

[0067] Pump 165 sends the etching solution from the outer tank 102 to the circulation line 161. The filter 163, heater 164, and pump 165 are installed in this order from the upstream side.

[0068] The circulation unit 106 sends the etching solution from the outer tank 102 into the inner tank 101 via the circulation line 161 and multiple nozzles 162. The etching solution sent into the inner tank 101 overflows from the inner tank 101 and flows back into the outer tank 102. In this way, the etching solution circulates between the inner tank 101 and the outer tank 102.

[0069] The circulation unit 106 may also be heated by the heater 164 to bring the etching solution to a boiling state.

[0070] (Regarding the IF area) Returning to the explanation of Figure 2, the interface unit 55 is located in IF area A3. The interface unit 55 is composed of, for example, a multi-joint robot and transports the wafers W one by one. The interface unit 55 can also change the orientation of multiple wafers W from a vertical to a horizontal orientation during transport.

[0071] The interface unit 55 takes one wafer W from the lot immersed in the rinsing tank 48 provided by the post-processing unit 4C, changes the orientation of the taken wafer W from vertical to horizontal, and then transports it to the single-wafer processing unit 6 in the single-wafer area A4, which will be described later.

[0072] (Regarding the single-wafer area and the unloading area) Next, the configuration of the single-wafer area A4 and the unloading area A5 will be described with reference to Figure 3. Figure 3 is a schematic plan view of the IF area A3, the single-wafer area A4, and the unloading area A5 of the substrate processing system 1 according to this embodiment.

[0073] The single-wafer area A4 contains multiple (two in the diagram) single-wafer processing units 6 and a single-wafer transport mechanism 7. The single-wafer processing unit 6 is an example of a substrate processing device.

[0074] The sheet-fed processing unit 6, the sheet-fed transport mechanism 7, and the sheet-fed processing unit 6 are arranged in this order, for example, along a direction perpendicular to the arrangement direction of areas A1 to A5 (the Y-axis direction). Specifically, the sheet-fed transport mechanism 7 is located in the center of the sheet-fed area A4 in the Y-axis direction, and the sheet-fed processing units 6 are located on both sides of the sheet-fed transport mechanism 7 in the Y-axis direction.

[0075] The single-wafer processing unit 6 performs liquid treatment on a single wafer W transported by the interface unit 55. Specifically, the single-wafer processing unit 6 applies a water-repellent treatment to the surface of the wafer W, and then dries the water-repellent treated wafer W. The wafer W that has been dried by the single-wafer processing unit 6 is removed from the single-wafer processing unit 6 by the single-wafer transport mechanism 7 and transported to the discharge area A5.

[0076] The single-wafer processing unit 6 is equipped with a wafer W loading entrance 61 and a wafer W loading entrance 62. The loading entrance 61 is located, for example, opposite the IF area A3, and the wafer W is loaded into it by the interface unit 55.

[0077] The discharge port 62 is provided, for example, in a position opposite the single-wafer transport mechanism 7, and the wafer W is discharged by the single-wafer transport mechanism 7. By providing the inlet 61 and the discharge port 62 in separate positions in this way, the loading and unloading of wafers W to and from the single-wafer processing unit 6 can be performed efficiently.

[0078] The single-wafer transport mechanism 7 is equipped with a holder for holding the wafer W. The single-wafer transport mechanism 7 is also capable of moving horizontally and vertically, as well as rotating about the vertical axis, and transports the wafer W using the holder. Specifically, the single-wafer transport mechanism 7 transports the wafer W from the single-wafer processing unit 6 to the wafer W mounting table 81 in the discharge area A5.

[0079] Here, the configuration of the single-wafer processing unit 6 will be described with reference to Figure 5. Figure 5 is a schematic diagram showing an example of a specific configuration of the single-wafer processing unit 6 according to the embodiment. As shown in Figure 5, the single-wafer processing unit 6 comprises a chamber 220, a substrate processing unit 230, a chemical solution supply unit 240, and a recovery cup 280.

[0080] Chamber 220 houses the substrate processing unit 230, the chemical supply unit 240, and the recovery cup 280. An FFU (Fan Filter Unit) 221 is provided on the ceiling of the chamber 220. The FFU 221 creates a downflow inside the chamber 220.

[0081] The substrate processing unit 230 comprises a substrate holding unit 231, a support column 232, and a rotational drive unit 233, and performs liquid treatment on the placed wafer W. The substrate holding unit 231 holds the wafer W horizontally. The support column 232 is a member that extends in the vertical direction, with its base end rotatably supported by the rotational drive unit 233, and its tip supporting the substrate holding unit 231 horizontally. The rotational drive unit 233 rotates the support column 232 around a vertical axis.

[0082] The substrate processing unit 230 rotates the support column 232 using the rotary drive unit 233, thereby rotating the substrate holding unit 231 supported by the support column 232, and thereby rotating the wafer W held in the substrate holding unit 231. The wafer W is held in the substrate holding unit 231 with the main surface to be treated with liquid facing upwards.

[0083] The chemical supply unit 240 supplies various chemicals to the wafer W held by the substrate holding unit 231. The chemical supply unit 240 includes nozzles 241, 242, and 243, an arm 251 that horizontally supports these nozzles 241, 242, and 243, and a swivel and lifting mechanism 253 that swivels and raises the arm 251.

[0084] Furthermore, the chemical supply unit 240 includes nozzles 244 and 245, an arm 252 that horizontally supports these nozzles 244 and 245, and a swivel and lifting mechanism 254 that rotates and raises the arm 252.

[0085] The nozzle 241 is connected to the DHF supply unit 262 via a flow regulator 261. DHF supplied from the DHF supply unit 262 is discharged from the nozzle 241. The discharge flow rate of this DHF can be controlled by the flow regulator 261.

[0086] The nozzle 242 is connected to the SC1 supply unit 264 via a flow regulator 263. SC1 supplied from the SC1 supply unit 264 is discharged from the nozzle 242. The discharge flow rate of this SC1 can be controlled by the flow regulator 263.

[0087] The nozzle 243 is connected to the IPA supply unit 266 via a flow regulator 265. IPA (isopropyl alcohol) supplied from the IPA supply unit 266 is discharged from the nozzle 243. The discharge flow rate of this IPA can be controlled by the flow regulator 265.

[0088] The nozzle 244 is connected to the DIW supply unit 268 via a flow regulator 267. DIW supplied from the DIW supply unit 268 is discharged from the nozzle 244. The discharge flow rate of this DIW can be controlled by the flow regulator 267.

[0089] The nozzle 245 is connected to the SMD supply unit 270 via a flow regulator 269. The SMD (Surface Molecular Dry) solution supplied from the SMD supply unit 270 is discharged from the nozzle 245. The discharge flow rate of this SMD solution can be controlled by the flow regulator 269.

[0090] The SMD solution is an example of a second chemical solution. The SMD solution is, for example, obtained by diluting a water-repellent agent used to make the surface of a wafer W water-repellent with thinner to a given concentration. As the water-repellent agent for this raw material, for example, a silylation agent (or silane coupling agent) can be used. Specifically, for example, HMDS (hexamethylzine lazane) can be used as the water-repellent agent for the raw material.

[0091] Furthermore, ether solvents or organic solvents belonging to the ketone group can be used as thinners. Specifically, for example, PGMEA (propylene glycol monomethyl ether acetate), cyclohexanone, and HFE (hydrofluoroether) can be used as thinners.

[0092] The collection cup 280 is positioned to surround the substrate holding section 231 and collects various chemical solutions scattered from the wafer W as the substrate holding section 231 rotates. A drain port 281 is formed at the bottom of the collection cup 280, and the chemical solutions collected by the collection cup 280 are discharged to the outside of the single-wafer processing section 6 through this drain port 281. An exhaust port 282 is also formed at the bottom of the collection cup 280 to discharge the gas supplied from the FFU 221 to the outside of the single-wafer processing section 6.

[0093] (Regarding the control device) Returning to the explanation of Figure 3, the substrate processing system 1 includes a control device 11. The control device 11 is, for example, a computer and comprises a control unit 12 and a storage unit 13. The storage unit 13 stores programs that control various processes performed in the substrate processing system 1.

[0094] The control unit 12 controls the operation of the substrate processing system 1 by reading and executing a program stored in the memory unit 13. The control unit 12 may be one or more circuits, or it may be provided as a single unit or in separate parts.

[0095] The program read by the control unit 12 may be one that was recorded on a computer-readable storage medium and installed from that storage medium into the storage unit 13 of the control device 11.

[0096] Computer-readable storage media include, for example, hard disks (HDs), flexible disks (FDs), compact discs (CDs), magnetic optical discs (MOs), and memory cards.

[0097] <Substrate Processing Procedure> Next, the substrate processing procedure performed by the substrate processing system 1 will be explained with reference to Figure 6. Figure 6 is a flowchart showing the substrate processing procedure performed by the substrate processing system 1 according to the embodiment. Each process shown in Figure 6 is performed according to the control of the control unit 12.

[0098] As shown in Figure 6, the control unit 12 first uses the second transport mechanism 30 to take out multiple wafers W from each of the two carriers C, and forms a lot with the multiple (for example, 25) wafers W housed in each carrier C (step S101).

[0099] The process of step S101 will be explained with reference to Figure 2. First, the first transport mechanism 21 takes the carrier C from the first mounting section 20 and places it on the carrier mounting table 24.

[0100] Then, the second transport mechanism 30 takes out multiple wafers W from the carrier C placed on the carrier mounting table 24, changes the orientation of the multiple wafers W from horizontal to vertical, and places the multiple wafers W on the lot holding unit 31. For example, by repeating this operation twice, a lot is formed.

[0101] Returning to the explanation of Figure 6, following the process in step S101, the control unit 12 performs pre-processing on the formed lot (step S102).

[0102] The process in step S102 will be explained with reference to Figure 2. First, the lot transport mechanism 50 receives the lot from the lot holding unit 31 and passes it to the lot immersion mechanism 42 of the pre-processing unit 4A. Then, the lot immersion mechanism 42 immerses the received lot in the DHF stored in the processing tank 40.

[0103] Subsequently, the lot immersion mechanism 42 removes the lot from the processing tank 40 and immerses it in the DIW stored in the processing tank 41. This washes away the DHF adhering to the wafer W with the DIW stored in the processing tank 41.

[0104] Returning to the explanation of Figure 6, following the process in step S102, the substrate processing system 1 performs an etching process on the lot processed by the preprocessing unit 4A (step S103).

[0105] The process in step S103 will be explained with reference to Figure 2. First, the lot transport mechanism 50 receives the lot from the lot immersion mechanism 42 of the pre-processing unit 4A and passes it to the lot immersion mechanism 45 of the etching processing unit 4B.

[0106] The lot immersion mechanism 45 then immerses the received lot in the etching solution stored in the processing tank 43. After that, the lot immersion mechanism 45 removes the lot from the processing tank 43 and passes it to the lot transport mechanism 50.

[0107] Next, the lot transport mechanism 50 passes the lot received from the lot immersion mechanism 45 to the lot immersion mechanism 46. The lot immersion mechanism 46 then immerses the received lot in the DIW stored in the processing tank 44. This washes away the etching solution adhering to the wafer W with the DIW stored in the processing tank 44.

[0108] Returning to the explanation of Figure 6, following the process in step S103, the control unit 12 performs a cleaning process on the lot processed by the etching processing unit 4B (step S104).

[0109] The process in step S104 will be explained with reference to Figure 2. The lot transport mechanism 50 receives the lot from the lot immersion mechanism 46 and passes it to the lot immersion mechanism 49 of the post-processing unit 4C. The lot immersion mechanism 49 then immerses the received lot in SC1 stored in the processing tank 47.

[0110] Subsequently, the lot immersion mechanism 49 removes the lot from the processing tank 47 and immerses it in the DIW stored in the processing tank 48. This washes away the SC1 adhering to the wafer W with the DIW stored in the processing tank 48.

[0111] Returning to the explanation of Figure 6, following the process in step S104, the control unit 12 performs a water-repellent treatment on the wafer W processed by the post-processing unit 4C (step S105). This water-repellent treatment is performed on a per-wafer W basis, not on a lot basis.

[0112] Specifically, the interface unit 55 (see Figure 3) takes out one wafer W (see Figure 2) from a lot held in the lot immersion mechanism 49 (see Figure 2) inside the processing tank 48 (see Figure 2).

[0113] The interface unit 55 then changes the wafer W from a vertical to a horizontal orientation and passes the wafer W to the substrate holding unit 231 (see Figure 5) in the single-wafer processing unit 6 (see Figure 3) via the loading port 61 (see Figure 3). A water-repellent treatment is then performed in the single-wafer processing unit 6. Details of this water-repellent treatment will be described later.

[0114] Next, the control unit 12 performs a drying process on the water-repellent treated wafer W (step S106). Details of this drying process will be described later.

[0115] Next, the substrate processing system 1 performs an unloading process in which the dried wafer W is placed in the carrier C (step S107).

[0116] The process of step S107 will be explained with reference to Figure 3. First, the single-wafer transport mechanism 7 removes the wafer W from the single-wafer processing unit 6 via the discharge port 62 and places the removed wafer W on the wafer mounting table 81. Then, the transport mechanism 82 removes the wafer W from the wafer mounting table 81 and places it on the carrier C placed on the second mounting unit 83.

[0117] <Water-repellent treatment> Next, the details of the water-repellent treatment (step S105) according to the embodiment will be explained with reference to Figures 7 to 18. Figures 7 to 14 are diagrams illustrating an example of the procedure for the water-repellent treatment according to the embodiment.

[0118] In the water-repellent treatment according to this embodiment, as shown in Figure 7, first, the control unit 12 (see Figure 3) controls the substrate processing unit 230 (see Figure 5) and the chemical supply unit 240 (see Figure 5), etc., to rotate the wafer W at a given speed while supplying DIW from the nozzle 244 to the upper surface of the wafer W. As a result, a liquid film of DIW is formed on the upper surface of the wafer W.

[0119] Next, as shown in Figure 8, the control unit 12 (see Figure 3) rotates the wafer W at a given speed while supplying SC1 from the nozzle 242 to the upper surface of the wafer W. The process in Figure 8 is an example of the fifth step, and the SC1 supplied from the nozzle 242 is an example of a cleaning solution. As a result, the upper surface of the wafer W is cleaned.

[0120] Next, as shown in Figure 9, the control unit 12 (see Figure 3) rotates the wafer W at a given speed and supplies DIW from the nozzle 244 to the upper surface of the wafer W. This washes away SC1 and other substances adhering to the wafer W with the DIW.

[0121] Next, as shown in Figure 10, the control unit 12 (see Figure 3) rotates the wafer W at a given speed while supplying DHF from the nozzle 241 to the upper surface of the wafer W. The process in Figure 10 is an example of the first step, and the DHF supplied from the nozzle 241 is an example of the first chemical solution and the HF aqueous solution. As a result, a liquid film of DHF is formed on the upper surface of the wafer W.

[0122] Next, as shown in Figure 11, the control unit 12 (see Figure 3) rotates the wafer W at a given speed while supplying IPA from the nozzle 243 to the upper surface of the wafer W. This forms a liquid film of IPA on the upper surface of the wafer W.

[0123] Next, as shown in Figure 12, the control unit 12 (see Figure 3) rotates the wafer W at a given speed while supplying SMD solution (simply labeled "SMD" in the drawing) from the nozzle 245 to the upper surface of the wafer W. The process in Figure 12 is an example of the second step. As a result, a liquid film of SMD solution is formed on the upper surface of the wafer W, and the wafer W is subjected to a water-repellent treatment.

[0124] Next, as shown in Figure 13, the control unit 12 (see Figure 3) rotates the wafer W at a given speed while supplying IPA from the nozzle 243 to the upper surface of the wafer W. The process in Figure 13 is an example of the fourth step. As a result, a liquid film of IPA is formed on the upper surface of the wafer W.

[0125] Figure 14 is a diagram illustrating an example of the drying process according to the embodiment. Following the process in Figure 13, the control unit 12 (see Figure 3) stops supplying each chemical solution to the wafer W and rotates the wafer W at high speed, as shown in Figure 14. This causes the IPA on the wafer W to be completely removed, and the wafer W is dried. The process in Figure 14 is an example of the third step.

[0126] As explained above, in the water-repellent treatment according to this embodiment, DHF is supplied to the wafer W before supplying the SMD solution, which is a water-repellent agent, to the wafer W. This improves the water-repellent performance of the wafer W. The reason for this is explained below.

[0127] Figure 15 is a diagram illustrating the state of the silicon oxide surface during the water-repellent treatment in the reference example. As shown in Figure 15(a), in the reference example, the silicon oxide (SiO in the figure) is treated by etching with an etching solution containing phosphoric acid. ｘ Phosphate ions P adhere to the surface of (as described).

[0128] Therefore, in the reference example, the wafer W is cleaned using a cleaning solution (for example, SC1). As a result, phosphate ions P are removed from the surface of the silicon oxide, as shown in Figure 15(b).

[0129] In the reference example, after this cleaning process, the wafer W is subjected to a water-repellent treatment with an SMD solution. As a result, as shown in Figure 15(c), silyl groups S adhere to the surface of the silicon oxide, and the surface of the silicon oxide is treated to be water-repellent.

[0130] Figure 16 is a diagram illustrating the state of the silicon oxide surface during the water-repellent treatment according to the embodiment. As shown in Figure 16(a), in this embodiment, similar to the reference example described above, phosphorus ions P are deposited on the surface of the silicon oxide by etching with an etching solution containing phosphoric acid.

[0131] Therefore, in this embodiment, the wafer W is cleaned using a cleaning solution (for example, SC1). As a result, phosphate ions P are removed from the surface of the silicon oxide, as shown in Figure 16(b).

[0132] In this embodiment, after this cleaning process, the wafer W is liquid-treated with DHF. As a result, modifying groups M adhere to the surface of the silicon oxide, as shown in Figure 16(c). These modifying groups M are, for example, fluoride ions.

[0133] In the state shown in Figure 16(c), SiF is formed on the surface of the silicon oxide. Furthermore, the silicon atoms located on the surface of the silicon oxide are attracted to electrons not only from oxygen ions but also from fluoride ions, resulting in a more positive charge compared to the case without fluoride ions.

[0134] Thus, in the state shown in Figure 16(c), the polarity of the SiF, i.e., the modifying group M, formed on the surface of the silicon oxide is increased.

[0135] In this embodiment, after the attachment treatment of the modifying group M, the wafer W is subjected to a water-repellent treatment with an SMD solution. As a result, as shown in Figure 16(d), silyl groups S are attached to the surface of the silicon oxide, and the surface of the silicon oxide is treated to be water-repellent.

[0136] Furthermore, in this embodiment, since the polarity of the modifying group M is increased, many silyl groups S adhere to the modifying group M, as shown in Figure 16(d). Thus, in this embodiment, more silyl groups S adhere to the surface of the silicon oxide due to the modifying group M, which can improve the water-repellent performance of the wafer W.

[0137] Figure 17 shows the contact angles of the wafer W after water-repellent treatment in the embodiment and reference example. Note that this reference example is the result when the water-repellent treatment is performed under all the same conditions as in the embodiment, except that the liquid treatment with DHF is not performed.

[0138] Figure 17 also shows the results when etching is performed with phosphoric acid before water-repellent treatment, when etching is performed with special phosphoric acid, and when etching with phosphoric acid is not performed before water-repellent treatment (no phosphoric acid).

[0139] As shown in Figure 17, in this embodiment, the contact angle after the water-repellent treatment is larger under all etching conditions compared to the reference example, indicating that the water-repellent performance of the wafer W has been improved.

[0140] Figure 18 shows the relationship between the processing time of the modification group M attachment process according to the embodiment and the contact angle of the wafer W. As shown in Figure 18, it can be seen that the modification group M attachment process according to the embodiment can produce a significant effect even when performed for a short time (5 seconds in this case). Furthermore, it can be seen that the effect of the modification group M attachment process according to the embodiment saturates even when processed for a longer period of time.

[0141] In the above embodiment, the process of attaching the modifying group M was shown using an aqueous HF solution (DHF), but this disclosure is not limited to such examples. For example, in this disclosure, the process of attaching the modifying group M may be carried out using an aqueous HCl (hydrochloric acid) solution. In this case, the modifying group M becomes a chloride ion.

[0142] This also improves the water-repellent properties of the wafer W, as the modifying group M causes more silyl groups S to adhere to the surface of the silicon oxide during the water-repellent treatment.

[0143] Furthermore, the attachment treatment of the modifying group M according to the embodiment is not limited to the use of an aqueous HF solution or an aqueous HCl solution, but other aqueous hydrogen halide solutions may also be used.

[0144] Furthermore, in the embodiment, when an aqueous HF solution is used for the attachment treatment of the modifying group M, the concentration of this aqueous HF solution may be 0.1 wt% to 1.0 wt%.

[0145] By setting the concentration of the HF aqueous solution to 0.1 wt% or higher, the attachment process of the modifying group M can be carried out efficiently. Furthermore, by setting the concentration of the HF aqueous solution to 1.0 wt% or lower, excessive etching of the wafer W by the HF aqueous solution can be suppressed.

[0146] Furthermore, in the embodiment, the amount of etching of the silicon oxide with the HF aqueous solution during the attachment treatment of the modifying group M may be 0.4 nm to 10 nm.

[0147] By setting the etching amount of silicon oxide by the HF aqueous solution to 0.4 nm or more, the modifying group M can be more easily attached to the outermost layer of the silicon oxide, thereby improving the water-repellent performance of the wafer W. Furthermore, by setting the etching amount of silicon oxide by the HF aqueous solution to 10 nm or less, excessive etching of the wafer W by the HF aqueous solution can be suppressed.

[0148] Furthermore, in the embodiment, when an aqueous HCl solution is used for the attachment treatment of the modifying group M, the concentration of this aqueous HCl solution may be 0.1 wt% to 1.0 wt%.

[0149] By setting the concentration of the HCl aqueous solution to 0.1 wt% or higher, the attachment treatment of the modifying group M can be carried out efficiently. Furthermore, by setting the concentration of the HCl aqueous solution to 1.0 wt% or lower, problems caused by excessive attachment of the modifying group M can be reduced.

[0150] Furthermore, in this embodiment, the SMD solution may also contain HMDS and PGMEA. This allows for efficient water-repellent treatment, thereby improving the water-repellent performance of the wafer W.

[0151] Furthermore, in the embodiment, as shown in Figure 13, a process of supplying IPA to the wafer W between the water-repellent treatment with the SMD solution and the drying treatment may be performed. This can further improve the water-repellent performance of the wafer W.

[0152] Furthermore, in the embodiment, as shown in Figure 8, the wafer W may be cleaned with a cleaning solution (for example, SC1) before the water-repellent treatment with the SMD solution. This allows substances that inhibit the water-repellent treatment, such as phosphorus ions P, to be removed from the wafer W in advance, thereby further improving the water-repellent performance of the wafer W.

[0153] The substrate processing method according to this embodiment includes a first step, a second step, and a third step. The first step involves supplying a first chemical solution (DHF) to the surface of the substrate (wafer W) to attach a modifying group M to the exposed silicon oxide. The second step involves supplying a second chemical solution (SMD solution) to the surface of the substrate (wafer W) to attach a silyl group S to the modifying group M. The third step involves drying the substrate (wafer W) to which the silyl group S has been attached. This improves the water-repellent performance of the wafer W.

[0154] Furthermore, in the substrate processing method according to this embodiment, the first chemical solution is an aqueous HF solution (DHF) or an aqueous HCl solution. This makes it possible to improve the water-repellent performance of the wafer W.

[0155] Furthermore, in the substrate processing method according to the embodiment, the concentration of the HF aqueous solution (DHF) is 0.1 wt% to 1.0 wt%. This allows for efficient adhesion of the modifying group M and suppresses excessive etching of the wafer W by the HF aqueous solution.

[0156] Furthermore, in the substrate processing method according to the embodiment, the etching amount of silicon oxide by the HF aqueous solution in the first step is 0.4 nm to 10 nm. This improves the water-repellent performance of the wafer W and suppresses excessive etching of the wafer W by the HF aqueous solution.

[0157] Furthermore, in the substrate processing method according to the embodiment, the concentration of the HCl aqueous solution is 0.1 wt% to 1.0 wt%. This allows for efficient adhesion of the modifying group M and reduces problems caused by excessive adhesion of the modifying group M.

[0158] Furthermore, in the substrate processing method according to the embodiment, the second chemical solution (SMD solution) contains HMDS (hexamethyldisilazane) and PGMEA (propylene glycol monomethyl ether acetate). This makes it possible to improve the water-repellent performance of the wafer W.

[0159] Furthermore, the substrate processing method according to the embodiment further includes a fourth step, performed between the second and third steps, in which IPA (isopropyl alcohol) is supplied to the substrate (wafer W) to which silyl groups S are attached. This makes it possible to improve the water-repellent performance of the wafer W.

[0160] Furthermore, the substrate processing method according to this embodiment further includes a fifth step, which is performed before the first step, in which a cleaning solution (SC1) is supplied to the surface of the substrate (wafer W). This further improves the water-repellent performance of the wafer W.

[0161] The substrate processing apparatus (single-wafer processing unit 6) according to the embodiment comprises a substrate holding unit 231, a rotation drive unit 233, a chemical solution supply unit 240, and a control unit 12. The substrate holding unit 231 holds the substrate (wafer W). The rotation drive unit 233 rotates the substrate holding unit 231. The chemical solution supply unit 240 has a plurality of nozzles 241, 245 that supply a first chemical solution (DHF) and a second chemical solution (SMD solution) to the upper surface of the substrate (wafer W). The control unit 12 controls each unit. The control unit 12 executes a first process, a second process, and a third process. The first process involves supplying the first chemical solution (DHF) to the surface of the substrate (wafer W) to attach modifying groups M to the exposed silicon oxide. The second process involves supplying the second chemical solution (SMD solution) to the surface of the substrate (wafer W) to attach silyl groups S to the modifying groups M. The third step involves drying the substrate (wafer W) to which the silyl groups S are attached. This improves the water-repellent properties of the wafer W.

[0162] While embodiments of this disclosure have been described above, this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from its spirit.

[0163] For example, the above embodiment shows an example in which the modifying group M is attached to each wafer W one by one in a single-wafer processing method, but the present disclosure is not limited to such an example. For example, the modifying group M may be attached to multiple wafers W at once in a batch processing method. This also improves the water-repellent performance of the wafers W.

[0164] Furthermore, although the above embodiment shows an example in which a water-repellent treatment is performed after etching the wafer W with an etching solution and before drying the wafer W, this disclosure is not limited to such an example. The technology of this disclosure may be applied to a wide variety of water-repellent treatments.

[0165] The embodiments disclosed herein should be considered in all respects as illustrative and not restrictive. Indeed, the embodiments described above can be embodied in a variety of forms. Furthermore, the embodiments described above may be omitted, replaced, or modified in various ways without departing from the scope and spirit of the appended claims. Each embodiment can be combined as appropriate, provided that the content is not contradictory.

[0166] 6. Wafer Processing Unit (Example of Substrate Processing Unit) 12. Control Unit 231. Substrate Holding Unit 233. Rotation Drive Unit 240. Chemical Supply Unit 241, 245. Nozzle M. Modifying Group S. Silyl Group W. Wafer (Example of Substrate)

Claims

1. A substrate processing method comprising: a first step of supplying a first chemical solution to the surface of a substrate to deposit modifying groups onto the exposed silicon oxide; a second step of supplying a second chemical solution to the surface of the substrate to deposit silyl groups onto the modifying groups; and a third step of drying the substrate on which the silyl groups are deposited.

2. The substrate treatment method according to claim 1, wherein the first chemical solution is an aqueous solution of HF or an aqueous solution of HCl.

3. The substrate processing method according to claim 2, wherein the concentration of the HF aqueous solution is 0.1 wt% to 1.0 wt%.

4. The substrate processing method according to claim 2, wherein in the first step, the amount of etching of the silicon oxide by the HF aqueous solution is 0.4 nm to 10 nm.

5. The substrate processing method according to claim 2, wherein the concentration of the HCl aqueous solution is 0.1 wt% to 1.0 wt%.

6. The substrate treatment method according to any one of claims 1 to 5, wherein the second chemical solution comprises HMDS (hexamethyldisilazane) and PGMEA (propylene glycol monomethyl ether acetate).

7. A substrate processing method according to any one of claims 1 to 5, further comprising a fourth step performed between the second step and the third step, in which IPA (isopropyl alcohol) is supplied to the substrate to which the silyl groups are attached.

8. A substrate processing method according to any one of claims 1 to 5, further comprising a fifth step performed before the first step, wherein a cleaning solution is supplied to the surface of the substrate.

9. A substrate processing apparatus comprising: a substrate holding unit for holding a substrate; a rotation drive unit for rotating the substrate holding unit; a chemical supply unit having a plurality of nozzles for supplying a first chemical solution and a second chemical solution to the upper surface of the substrate; and a control unit for controlling each unit, wherein the control unit performs: a first treatment of supplying the first chemical solution to the surface of the substrate to deposit modifying groups on the exposed silicon oxide; a second treatment of supplying the second chemical solution to the surface of the substrate to deposit silyl groups on the modifying groups; and a third treatment of drying the substrate to which the silyl groups have been deposited.

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