Semiconductor device, power conversion device, and control system

Abstract

Provided is a semiconductor device in which a defect caused by electric field concentration hardly occurs.　More specifically, a semiconductor device comprises: a semiconductor layer containing a crystalline oxide semiconductor that includes gallium and having a trench formed on an upper surface thereof; an insulating layer containing an oxide and positioned in the trench; and an electrode positioned on the semiconductor layer and the insulating layer. An upper surface of a portion of the semiconductor layer adjacent to the trench and the entire upper surface of the insulating layer are positioned within a range of less than 0.1 μm in a vertical direction.

Description

Semiconductor devices, power converters, and control systems

[0001] This disclosure relates to a semiconductor device, a power conversion device equipped therewith, and a control system.

[0002] Patent Document 1 discloses a Schottky barrier diode. The Schottky barrier diode comprises an n-type semiconductor layer made of a gallium oxide-based semiconductor, an anode electrode formed on the upper surface of the n-type semiconductor layer, and a cathode electrode formed on the lower surface of the n-type semiconductor layer. The n-type semiconductor layer includes a guard ring formed by ion implantation of acceptor impurities.

[0003] Japanese Patent Publication No. 2023-037565

[0004] In semiconductor devices as described above, it is desirable that, for example, when a reverse voltage is applied, electric field concentration is less likely to occur in the n-type semiconductor layer. It should be noted that mere inclusion in the background information does not automatically mean that something is considered prior art.

[0005] The purpose of this disclosure is to provide a semiconductor device that is less prone to malfunctions caused by electric field concentration.

[0006] To solve the above problems, in one embodiment of the present disclosure, a semiconductor device comprises a semiconductor layer containing a crystalline oxide semiconductor containing gallium, an electrode formed on the semiconductor layer, and an electric field relaxation layer provided between the electrode and the semiconductor layer to alleviate electric field concentration in the semiconductor layer, wherein the upper surface of a first portion of the electric field relaxation layer adjacent to the semiconductor layer is located above a position 0.1 μm below the upper surface of a second portion of the semiconductor layer adjacent to the first portion.

[0007] According to the present invention, it is possible to reduce the likelihood of malfunctions occurring in semiconductor devices due to electric field concentration.

[0008] Figure 1 is a schematic cross-sectional view of a semiconductor device according to one embodiment. Figure 2 is an enlarged view of part A in Figure 1. Figure 3 is an enlarged view of part B in Figure 1. Figure 4 is a diagram corresponding to Figure 2 of the reference example. Figure 5 is a diagram corresponding to Figure 3 of the reference example. Figure 6 is a schematic cross-sectional view of a laminated structure used in the manufacture of a semiconductor device. Figure 7 is a schematic cross-sectional view of a laminated structure in which a trench is formed. Figure 8 is a schematic cross-sectional view of a laminated structure in which an electric field relaxation layer is formed. Figure 9 is a schematic cross-sectional view of a laminated structure in which a first electrode is formed. Figure 10 is a graph showing the step dimensions of the examples and comparative examples. Figure 11 is a photograph showing a cross-section of the boundary portion between the first semiconductor layer and the electric field relaxation layer in the semiconductor device of the example. Figure 12 is a schematic cross-sectional view of a semiconductor device of modified example 1. Figure 13 is a schematic cross-sectional view of a semiconductor device of modified example 2. Figure 14 is a schematic cross-sectional view of a semiconductor device of modified example 3. Figure 15 is a schematic cross-sectional view of a semiconductor device of modified example 4. Figure 16 is a schematic cross-sectional view of the semiconductor device of Modification 5. Figure 17 is a schematic cross-sectional view of the semiconductor device of Modification 6. Figure 18 is an enlarged view of section C in Figure 17. Figure 19 is a block diagram showing an example of a control system. Figure 20 is a circuit diagram showing an example of a control system. Figure 21 is a block diagram showing another example of a control system. Figure 22 is a circuit diagram showing yet another example of a control system.

[0009] Embodiments of the semiconductor device described herein will be explained below with reference to the drawings. However, the invention claimed is not limited to these embodiments. Furthermore, not all combinations of configurations described in the embodiments are considered essential for solving the problem. Each configuration in this disclosure is described to the extent that it does not hinder the solution of the problem of this disclosure. Additionally, identical components are denoted by the same reference numerals to avoid redundant explanations.

[0010] As will be apparent to those skilled in the art, features shown in the drawings are not necessarily depicted to a constant scale, even if not explicitly stated herein. Furthermore, it should be noted that a feature in one embodiment may be used in another. Descriptions of well-known elements and manufacturing techniques may be omitted so as not to unnecessarily obscure the embodiments of this disclosure. The examples used herein are solely for the purpose of aiding understanding of this disclosure and enabling those skilled in the art to implement the embodiments. Therefore, the embodiments and examples herein are not to be construed as being limited to the scope of this disclosure, but are determined solely by the claims and applicable law.

[0011] The terms "first," "second," etc., are used to describe various elements used herein, but the elements are not limited by these terms. The terms "first," "second," etc., are used solely to distinguish one element from another. For example, without departing from the scope of this disclosure, the first element may be referred to as the second element, and the second element may be referred to as the first element. As used herein, the term "and / or" encompasses one or more, or any combination of all, of the listed items.

[0012] In this disclosure, each of the terms “equipment,” “possess,” and “include” indicates the presence of the described element, and does not exclude the presence of one or more other elements. Where the expression “connected” or “combined” an element is used in this disclosure, it should be understood that the element may be directly connected to or combined with another element, or there may be an intervening element.

[0013] The semiconductor device described herein is useful for various semiconductor elements, and in particular for power devices. The semiconductor device may be a lateral device in which electrodes are formed only on one side of the semiconductor layer, or a vertical device in which electrodes are formed on both the front and back sides of the semiconductor layer. The semiconductor device may be, for example, a diode or a transistor. The semiconductor device may also be part of an element structure. Examples of diodes include Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSs), or light-emitting diodes. Examples of transistors include metal-semiconductor field-effect transistors (MESFETs), metal-insulating semiconductor field-effect transistors (MISFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), high electron-mobility transistors (HEMTs), or IGBTs (Insulated Gate Bipolar Transistors).

[0014] (Embodiment) Figure 1 is a schematic cross-sectional view of the semiconductor device 100 of this embodiment. The semiconductor device 100 is a diode. More specifically, the semiconductor device 100 is a vertical Schottky barrier diode and is used as a power device. The semiconductor device 100 comprises a semiconductor layer 2, an electrode 5 provided on the semiconductor layer 2, and an electric field relaxation layer 4 provided between the semiconductor layer 2 and the electrode 5 to alleviate electric field concentration in the semiconductor layer 2. The semiconductor device 100 may further comprise another semiconductor layer 3 formed below the semiconductor layer 2. The semiconductor device 100 may further comprise another electrode 6 formed below the semiconductor layer 3. Hereinafter, the semiconductor layer 2 will be referred to as the "first semiconductor layer 2," and the semiconductor layer 3 will be referred to as the "second semiconductor layer 3." The electrode 5 will be referred to as the "first electrode 5," and the electrode 6 will be referred to as the "second electrode 6." The first semiconductor layer 2 is an example of a semiconductor layer.

[0015] In this disclosure, the thickness direction of the first semiconductor layer 2 is defined as the "vertical direction." One direction parallel to the vertical direction is defined as "upward," and the direction opposite to upward is defined as "downward." These directions do not limit the direction of gravity or the direction of attachment to a substrate, etc., when mounting a semiconductor device. In this disclosure, of a layer, substrate, or other component, the surface facing upward is described as the upper surface, and the surface facing downward is described as the lower surface. When expressions such as a layer, region, or substrate exist "on top of" or "below" another element are used, it should be understood that it may exist directly on top of or below another element, or the element may exist between other elements.

[0016] The first semiconductor layer 2 is an n-type semiconductor. The first semiconductor layer 2 contains a crystalline oxide semiconductor. More specifically, the first semiconductor layer 2 contains a crystalline oxide semiconductor as its main component. In this disclosure, "main component" means that it makes up 50% or more of the total atomic ratio. The first semiconductor layer 2 may contain 70% or more of the crystalline oxide semiconductor as its atomic ratio, or 90% or more. The first semiconductor layer 2 may also be a crystalline oxide semiconductor. In this case, it is also included in the statement that it contains a crystalline oxide semiconductor as its main component. Furthermore, the first semiconductor layer 2 may also be a p-type semiconductor.

[0017] The second semiconductor layer 3 is formed on the underside of the first semiconductor layer 2 and is in contact with the first semiconductor layer 2. The conductivity type of the second semiconductor layer 3 is the same as that of the first semiconductor layer 2. In this example, the second semiconductor layer 3 is an n-type semiconductor. The carrier density of the second semiconductor layer 3 is greater than that of the first semiconductor layer 2. That is, the second semiconductor layer 3 is an n+-type semiconductor, and the first semiconductor layer 2 is an n--type semiconductor. The main component of the second semiconductor layer 3 is the same as that of the first semiconductor layer 2. That is, the second semiconductor layer 3 mainly contains a crystalline oxide semiconductor. The second semiconductor layer 3 may contain 70% or more, or 90% or more, of crystalline oxide semiconductors by atomic ratio. The second semiconductor layer 3 may also be a crystalline oxide semiconductor. Hereinafter, unless otherwise specified, the crystalline oxide semiconductors of the first semiconductor layer 2 and the second semiconductor layer 3 will simply be referred to as "crystalline oxide semiconductors". Furthermore, the main component of the second semiconductor layer 3 may differ from the main component of the first semiconductor layer 2. The second semiconductor layer 3 may also be a p-type semiconductor. The second semiconductor layer 3 is optional. In this case, the first semiconductor layer 2 may be in direct contact with the second electrode 6.

[0018] Crystalline oxide semiconductors are metal oxides containing gallium. Crystalline oxide semiconductors may also contain metals other than gallium. These metals are, for example, one or more metals selected from aluminum (Al), indium (In), iron (Fe), chromium (Cr), vanadium (V), titanium (Ti), rhodium (Rh), nickel (Ni), cobalt (Co), and iridium (Ir). Crystalline oxide semiconductors may also be InAlGaO-based semiconductors containing indium and / or aluminum in addition to gallium. In this disclosure, InAlGaO-based semiconductors refer to In Ｘ Al Ｙ Ga Ｚ O ３ This means (0 ≤ X ≤ 2, 0 ≤ Y ≤ 2, 0 ≤ Z ≤ 2, X + Y + Z = 1.5 to 2.5).

[0019] The crystalline oxide semiconductor is a single crystal. Note that the crystalline oxide semiconductor may be polycrystalline. The crystalline oxide semiconductor has a corundum structure as its crystal structure. Note that the crystal structure is not limited to the corundum structure. The crystal structure of the crystalline oxide semiconductor may be, for example, a beta-gallia structure, a hexagonal crystal structure (e.g., epsilon-type structure), an orthorhombic crystal structure (e.g., kappa-type structure), or a cubic crystal structure (e.g., gamma-type structure or delta-type structure).

[0020] The crystalline oxide semiconductor may be gallium oxide (Ga ２ O ３ ), or a mixed crystal containing gallium oxide and another metal oxide. The crystalline oxide semiconductor is preferably alpha-Ga ２ O ３ , or a mixed crystal containing alpha-Ga ２ O ３ and another metal oxide. The other metal oxide is, for example, aluminum oxide (Al ２ O ３ ), indium oxide (In ２ O ３ ), iridium oxide (IrO ２ ), rhodium oxide (Rh ２ O ３ ), chromium oxide (Cr ２ O ３ ), or iron oxide (Fe ２ O ３ ). The crystalline oxide semiconductor may contain the other metal oxide at an atomic ratio of 1% or more. The crystalline oxide semiconductor may contain the other metal oxide at an atomic ratio of 5% or more, or 10% or more. In this example, the crystalline oxide semiconductor is gallium oxide (Ga ２ O ３ ).

[0021] Each of the first semiconductor layer 2 and the second semiconductor layer 3 may contain a dopant. In this disclosure, a dopant means a material that is used for donor or acceptor formation. The dopant may be a known dopant. If each of the first semiconductor layer 2 and the second semiconductor layer 3 is an n-type semiconductor, each of the first semiconductor layer 2 and the second semiconductor layer 3 may contain, as an n-type dopant, for example, tin (Sn), germanium (Ge), silicon (Si), titanium (Ti), zirconium (Zr), vanadium (V), or niobium (Nb), or two or more of these elements. The n-type dopant is preferably tin, germanium, or silicon. If each of the first semiconductor layer 2 and the second semiconductor layer 3 is a p-type semiconductor, each of the first semiconductor layer 2 and the second semiconductor layer 3 may contain, as a p-type dopant, for example, magnesium (Mg), zinc (Zn), calcium (Ca), hydrogen (H), lithium (Li), sodium (Na), potassium (K), rubidium (Rb), cesium (Cs), francium (Fr), beryllium (Be), strontium (Sr), barium (Ba), radium (Ra), manganese (Mn), iron (Fe), cobalt (Co), nickel (Ni), palladium (Pd), copper (Cu), silver (Ag), gold (Au), cadmium (Cd), mercury (Hg), thallium (Tl), lead (Pb), nitrogen (N), or phosphorus (P), or two or more of these elements. The dopant content of each of the first semiconductor layer 2 and the second semiconductor layer 3 may be 0.0000001 atomic percent or more, or 0.000001 atomic percent or more. The dopant content of each of the first semiconductor layer 2 and the second semiconductor layer 3 may be 20 atomic percent or less, or 10 atomic percent or less.

[0022] The carrier density of each of the first semiconductor layer 2 and the second semiconductor layer 3 can be appropriately set, for example, by adjusting the doping amount. The carrier density in each of the first semiconductor layer 2 and the second semiconductor layer 3 is uniform. In the present disclosure, "uniform" includes not only the case of being completely uniform but also the case of being slightly different. That is, the uniformity only needs to be substantially uniform. The carrier density of each of the first semiconductor layer 2 and the second semiconductor layer 3 may be non-uniform. Considering both the forward loss and the withstand voltage of the semiconductor device 100, the carrier density of the first semiconductor layer 2 is 1×10 １５ / cm ３ or more and 1×10 １７ / cm ３ or less. The carrier density of the first semiconductor layer 2 may exceed 1×10 １７ / cm ３ , or may be less than 1×10 １５ / cm ３ . Considering the forward loss of the semiconductor device 100, the carrier density of the second semiconductor layer 3 is 1×10 １７ / cm ３ or more and 1×10 ２２ / cm ３ or less. The carrier density of the second semiconductor layer 3 may exceed 1×10 ２２ / cm ３ , or may be less than 1×10 １７ / cm ３ .

[0023] Each of the first semiconductor layer 2 and the second semiconductor layer 3 has a thickness. The thickness of each of the first semiconductor layer 2 and the second semiconductor layer 3 is preferably 1 μm or more, and more preferably 3 μm or more. The thickness of each of the first semiconductor layer 2 and the second semiconductor layer 3 may be less than 1 μm.

[0024] The area of each of the first semiconductor layer 2 and the second semiconductor layer 3 is 10 mm ２ or more and 300 cm ２ or less, preferably 100 mm ２ or more and 100 cm ２The following is even more preferable. In this disclosure, the area of ​​the first semiconductor layer 2 and the second semiconductor layer 3 refers to the area when viewed in the vertical direction. The area of ​​the first semiconductor layer 2 and the second semiconductor layer 3 is 10 mm². ２ It can be less than 300 cm. ２ It is acceptable to exceed this limit.

[0025] The field relaxation layer 4 is embedded in the semiconductor layer 2. In this example, a trench 21 is formed on the upper surface of the semiconductor layer 2, and the field relaxation layer 4 is formed inside the trench 21. Hereinafter, the trench 21 will be referred to as the "first trench 21". The first trench 21 is formed in an annular shape when viewed from above. The first trench 21 is located below the outer peripheral end of the first electrode 5. The first trench 21 extends downward from the upper surface of the first semiconductor layer 2 and opens upward. The portion of the upper surface of the first semiconductor layer 2 excluding the first trench 21 is a substantially flat surface that is substantially perpendicular to the vertical direction. The shape of the first trench 21 is not limited.

[0026] The electric field relaxation layer 4 is located entirely or substantially entirely within the first trench 21. The upper end of the electric field relaxation layer 4 may be located above the upper surface of the first semiconductor layer 2. Even when only the upper end of the electric field relaxation layer 4 is located above the upper surface of the first semiconductor layer 2, it is still considered that "the electric field relaxation layer 4 is formed inside the first trench 21." In this example, the entire or substantially entire interior of the first trench 21 is filled with the electric field relaxation layer 4. The interior of the electric field relaxation layer 4 may be formed from a different material or may be empty. The electric field relaxation layer 4 is in contact with the inner surface of the first trench 21 of the first semiconductor layer 2. More specifically, the electric field relaxation layer 4 is in contact with the bottom surface and both sides of the first trench 21. The upper surface of the electric field relaxation layer 4 is a substantially plane substantially perpendicular to the vertical direction.

[0027] The electric field relaxation layer 4 is preferably a high-resistivity layer. The resistivity of the high-resistivity layer is 1.0 × 10⁻⁶. ６ It is Ω·cm or greater. Here, resistivity can be measured, for example, by forming measuring electrodes in the field relaxation layer 4 and passing a current through them. The resistivity of the field relaxation layer 4 is 1.0 × 10⁻⁶. ８It may be greater than Ω·cm. The resistivity of the field relaxation layer 4 is 1.0 × 10⁻⁶. １０ It may be greater than Ω·cm, or 1.0 × 10 １２ It may be greater than Ω·cm. In this example, the electric field relaxation layer 4 has a resistivity of 1.0 × 10⁻⁶. ８ This is an insulating layer with a resistivity of Ω·cm or higher. The field relaxation layer 4 is an example of an insulating layer. The resistivity of the field relaxation layer 4 is 1.0 × 10⁻⁶. １５ It may be less than Ω·cm, or 1.0 × 10 １４ It may be less than or equal to Ω·cm. Also, the resistivity of the field relaxation layer 4 is 1.0 × 10⁻⁶. ６ It may be less than Ω·cm.

[0028] The main component of the field relaxation layer 4 is different from the main component of the first semiconductor layer 2. The field relaxation layer 4 preferably contains an oxide. The field relaxation layer 4 may contain an oxide as its main component. The field relaxation layer 4 may contain 70% or more of oxide by atomic ratio, or 90% or more. The field relaxation layer 4 may also contain an oxide. For example, silicon dioxide (SiO₂) ２ ), phosphorus-added SiO ２ (PSG), boron-doped SiO ２ , phosphorus-boron added SiO ２ It is either (BPSG) or alumina (aluminum oxide).

[0029] The field relaxation layer 4 may be a semiconductor. Preferably, the semiconductor has a conductivity type different from that of the first semiconductor layer 2. That is, if the first semiconductor layer 2 is an n-type semiconductor as in this embodiment, the conductivity type of the semiconductor that is the field relaxation layer 4 is preferably p-type. Preferably, the semiconductor contains an inorganic compound, and more preferably contains an inorganic compound as its main component. Examples of inorganic compounds are metal compounds such as metal oxides, metal sulfides, metal nitrides, metal halides, metal selenides, or metal tellurides. From the viewpoint of improving breakdown voltage and suppressing leakage current, the inorganic compound is preferably a metal oxide or metal sulfide.

[0030] The metal oxide contains one or more metals selected from, for example, copper (Cu), rhodium (Rh), tin (Sn), nickel (Ni), silver (Ag), antimony (Sb), vanadium (V), and titanium (Ti). The metal oxide is preferably delafossite, rhodium oxide, or oxycalcogenide. For example, when A, B, A', and B' are arbitrary element symbols, the delafossite is ABO ２ (A is Cu, Pd, Ag, Pt or Hg, and B is Al, Fe, Sc, Y, La, Ce, Pr, Nd, Sm, Er, Tm, Yb, Lu, B, Ga, Cr, In or Tl, or Co or Rh with Ti, Zr, Hf, Si, Ge, Sn or Pb added.) Among these, A'B'O ２ (A' is preferably Cu or Ag, and B' is preferably Al, Ga, In, Sc, Y, or La.) Rhodium oxide is, for example, α-Rh ２ O ３ or ZnRh2O ４ The oxychalcogenide is, for example, LaCuOCh, where Ch is, for example, S, Se, or Te. The metal oxide is, for example, SrCu. ２ O ２ , PbCd ２ O ２ SnO, Cu ２ O, ZnO, NiO, or Ag ２ It may also be O. The metal sulfide contains, for example, zinc (Zn) and / or aluminum (Al). The metal sulfide is ZnS or CuAlS ２ It is preferable that this be the case.

[0031] The field relaxation layer 4 may be a crystalline oxide semiconductor. The field relaxation layer 4 may contain 70% or more of oxide semiconductor by atomic ratio, or 90% or more. The field relaxation layer 4 may be an oxide semiconductor. The main component of the field relaxation layer 4 may be the same as the main component of the first semiconductor layer 2. That is, the field relaxation layer 4 may be a gallium-containing metal oxide, as exemplified as the crystalline oxide semiconductor of the first semiconductor layer 2. The field relaxation layer 4 may contain a dopant. The dopant is, for example, a dopant exemplified as the dopant of the first semiconductor layer 2. Note that the material of the field relaxation layer 4 is not limited to the semiconductors and oxides described above.

[0032] The hardness of the field relaxation layer 4 and the hardness of the first semiconductor layer 2 may be different. The hardness of the field relaxation layer 4 and the first semiconductor layer 2 can be compared, for example, by Mohs hardness. In this example, the first semiconductor layer 2 is harder than the field relaxation layer 4. However, the field relaxation layer 4 may be harder than the first semiconductor layer 2, or the hardness of the first semiconductor layer 2 and the hardness of the field relaxation layer 4 may be the same.

[0033] The first electrode 5 is formed on the upper surface of the first semiconductor layer 2 and the upper surface of the field relaxation layer 4. The outer edge of the first electrode 5 is located above the field relaxation layer 4, and a portion of the field relaxation layer 4 is located outside the first electrode 5 when viewed from above. The first electrode 5 is in contact with the first semiconductor layer 2 and the field relaxation layer 4. The lower surface of the central part of the first electrode 5 is Schottky junctioned with the upper surface of the first semiconductor layer 2. That is, the first electrode 5 in this example functions as a Schottky electrode. The lower surface of the outer peripheral end of the first electrode 5 is in contact with the upper surface of the field relaxation layer 4.

[0034] The second electrode 6 is formed beneath the second semiconductor layer 3. The upper surface of the second electrode 6 is ohmic-junctioned with the lower surface of the second semiconductor layer 3. In other words, the second electrode 6 functions as an ohmic electrode.

[0035] Each of the first electrode 5 and the second electrode 6 is formed from a conductive inorganic material or a conductive organic material. Preferably, each of the first electrode 5 and the second electrode 6 is a metal. The metal includes one or more metals selected from Groups 4 to 10 of the periodic table. In this disclosure, "periodic table" means the periodic table defined by the International Union of Pure and Applied Chemistry (IUPAC). Examples of Group 4 metals are titanium (Ti), zirconium (Zr), or hafnium (Hf). Examples of Group 5 metals are vanadium (V), niobium (Nb), or tantalum (Ta). Examples of Group 6 metals are chromium (Cr), molybdenum (Mo), or tungsten (W). Examples of Group 7 metals are manganese (Mn), technetium (Tc), or rhenium (Re). Metals in Group 8 include, for example, iron (Fe), ruthenium (Ru), or osmium (Os). Metals in Group 9 include, for example, cobalt (Co), rhodium (Rh), or iridium (Ir). Metals in Group 10 include, for example, nickel (Ni), palladium (Pd), or platinum (Pt).

[0036] The thickness of the first electrode 5 and the second electrode 6 is preferably 0.1 nm or more and 10 μm or less. More preferably, the thickness of the first electrode 5 and the second electrode 6 is 5 nm or more and 500 nm or less, and even more preferably 10 nm or more and 200 nm or less. However, the thickness of the first electrode 5 and the second electrode 6 is not particularly limited. Furthermore, the first electrode 5 and the second electrode 6 may each be a single layer or formed from multiple layers. For example, the first electrode 5 may include a first electrode layer formed on the first semiconductor layer 2 and a second electrode layer formed on the first electrode layer. In this case, the thickness of the first electrode layer is preferably smaller than the thickness of the second electrode layer. Furthermore, the work function of the first electrode layer is preferably larger than the work function of the second electrode layer. By adopting such a preferred configuration for the first electrode layer, it is possible not only to obtain a semiconductor device with better Schottky characteristics, but also to better exhibit the effect of improving reverse breakdown voltage.

[0037] The semiconductor device 100 may further include other layers different from those described above. These other layers may be, for example, an insulating layer, a semi-insulating layer, a conductive layer, a semiconductor layer, a buffer layer, or other intermediate layers.

[0038] Figure 2 is an enlarged view of section A in Figure 1. If the portion of the field relaxation layer 4 adjacent to the first semiconductor layer 2 is designated as the first portion 43, and the portion of the first semiconductor layer 2 adjacent to the first portion 43 is designated as the second portion 23, then the upper surface of the first portion 43 is located above a point 0.1 μm below the upper surface of the second portion 23. That is, as shown in Figure 2, if a straight line passing 0.1 μm below the upper surface of the second portion 23 is designated as the reference line L, then the upper surface of the first portion 43 is located above the reference line L. Specifically, on the inner circumference side of the field relaxation layer 4, the inner circumference end of the field relaxation layer 4 is the first portion 43, and the outer circumference end of the portion of the first semiconductor layer 2 located inside the field relaxation layer 4 is the second portion 23. The first portion 43 and the second portion 23 are adjacent in a direction perpendicular to the vertical direction.

[0039] The upper surface of the first portion 43 and the upper surface of the second portion 23 are preferably located within a range of less than 0.1 μm in the vertical direction, and more preferably within a range of less than 0.05 μm in the vertical direction.

[0040] Figure 3 is an enlarged view of section B in Figure 1. As shown in Figure 3, even on the outer periphery of the field relaxation layer 4, it is preferable that the upper surface of the portion of the field relaxation layer 4 adjacent to the first semiconductor layer 2 is located above a position 0.1 μm below the upper surface of the portion of the first semiconductor layer 2 adjacent to the field relaxation layer 4. On the outer periphery of the field relaxation layer 4, it is even more preferable that the upper surface of the portion of the field relaxation layer 4 adjacent to the first semiconductor layer 2 and the upper surface of the portion of the first semiconductor layer 2 adjacent to the field relaxation layer 4 are located within a range of less than 0.1 μm in the vertical direction, and even more preferable that they are located within a range of less than 0.05 μm. Furthermore, on the outer periphery of the field relaxation layer 4, the upper surface of the portion of the field relaxation layer 4 adjacent to the first semiconductor layer 2 may be located below a position 0.1 μm below the upper surface of the portion of the first semiconductor layer 2 adjacent to the field relaxation layer 4. Alternatively, only the upper surface of the first portion 43 of the upper surface of the field relaxation layer 4 may be located above a position 0.1 μm below the upper surface of the second portion 23, while the entire upper surface of the field relaxation layer 4 other than the upper surface of the first portion 43 may be located below a position 0.1 μm below the upper surface of the second portion 23.

[0041] Figure 4 is a cross-sectional view showing a reference example and corresponds to Figure 2. Figure 5 is a cross-sectional view showing a reference example and corresponds to Figure 3. The fact that the upper surface of the portion of the field relaxation layer 4 adjacent to the first semiconductor layer 2 and the upper surface of the portion of the first semiconductor layer 2 adjacent to the field relaxation layer 4 are located within a range of less than 0.1 μm in the vertical direction means that no step difference of 0.1 μm or more is formed between the upper surface of the portion of the field relaxation layer 4 adjacent to the first semiconductor layer 2 and the upper surface of the portion of the first semiconductor layer 2 adjacent to the field relaxation layer 4. The same applies when the upper surface of the portion of the field relaxation layer 4 adjacent to the first semiconductor layer 2 and the upper surface of the portion of the first semiconductor layer 2 adjacent to the field relaxation layer 4 are located within a range of less than 0.05 μm in the vertical direction. Here, the "step difference" is the surface connecting the upper surface of the first semiconductor layer 2 and the upper surface of the field relaxation layer 4, for example, the portion indicated by the symbol s in Figures 4 and 5. Furthermore, the dimension of the step is the vertical dimension of the step, and in Figures 4 and 5, for example, it is the dimension indicated by the symbol d.

[0042] In this example, the entire upper surface of the portion of the first semiconductor layer 2 surrounded by the annular field relaxation layer 4, in other words, the entire portion of the upper surface of the first semiconductor layer 2 that contacts the first electrode 5, is located above a position 0.1 μm below the upper surface of the second portion 23 on the inner circumference side of the field relaxation layer 4. More specifically, the entire upper surface of the field relaxation layer 4 and the entire upper surface of the first semiconductor layer 2 are located within a range of less than 0.01 μm in the vertical direction, and the upper surface of the field relaxation layer 4 and the upper surface of the first semiconductor layer 2 are flush with each other on both the outer and inner circumference sides of the field relaxation layer 4.

[0043] Next, an example of a method for manufacturing the semiconductor device 100 will be described. Figures 6 to 9 are cross-sectional views showing the method for manufacturing the semiconductor device 100 in order. The method for manufacturing the semiconductor device 100 includes a preparation step of preparing a stacked structure 8 having a first semiconductor layer 2, a field relaxation layer formation step of forming a field relaxation layer 4 on the first semiconductor layer 2, and an electrode formation step of forming a first electrode 5 and a second electrode 6 on the stacked structure 8.

[0044] In the preparation step, the laminated structure 8 shown in Figure 6 is prepared. The laminated structure 8 further includes a second semiconductor layer 3 and a substrate 9 in addition to the first semiconductor layer 2. In the laminated structure 8, the second semiconductor layer 3 is formed on the substrate 9, and the first semiconductor layer 2 is formed on the second semiconductor layer 3. Each of the first semiconductor layer 2 and the second semiconductor layer 3 in the stacked structure 8 is processed by, for example, CVD (Chemical Vapor Deposition), MOCVD (Metal Organic Chemical Vapor Deposition), MOVPE (Metalorganic Vapor Phase Epitaxy), mist CVD, mist epitaxy, MBE (Molecular Beam Epitaxy), HVPE (Hydride Vapor Phase Epitaxy), PLD (Pulsed Laser Deposition), or ALD (Atomic Layer The second electrode 6 is formed by the Deposition method or other known methods. The second electrode 6 is formed, for example, by a dry method or a wet method. Dry methods include, for example, sputtering, vacuum deposition, or CVD. Wet methods include, for example, screen printing or die coating.

[0045] The first semiconductor layer 2 and the second semiconductor layer 3 are preferably formed by a mist CVD method or a mist epitaxy method. The first semiconductor layer 2 and the second semiconductor layer 3 are formed, for example, by the semiconductor layer formation method shown below. In the following description, "semiconductor layer" refers to the first semiconductor layer and the second semiconductor layer 3, respectively.

[0046] The method for forming a semiconductor layer includes an atomization step of atomizing a raw material solution containing a metal to generate atomized droplets consisting of mist or droplets, and a film formation step of transporting the obtained atomized droplets to the vicinity of a substrate using a carrier gas and reacting the atomized droplets to form a semiconductor layer on the substrate.

[0047] The raw material solution used in the atomization process contains metals contained in the semiconductor layer. The raw material solution may contain inorganic materials or organic materials. The raw material solution may also contain dopants contained in the semiconductor layer.

[0048] The raw material solution can preferably be one in which the metal contained in the semiconductor layer is dissolved or dispersed in an organic solvent or water in the form of a complex or salt. Examples of complexes include acetylacetonate complexes, carbonyl complexes, ammine complexes, or hydride complexes. Examples of salts include organometallic salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphorylated salts, or metal halide salts (e.g., metal chloride salts, metal bromide salts, metal iodide salts, etc.).

[0049] The raw material solution may contain additives such as hydrohalic acid or an oxidizing agent. Examples of hydrohalic acid include hydrobromic acid, hydrochloric acid, or hydroiodic acid. Examples of oxidizing agents include hydrogen peroxide (H ２ O ２ ), sodium peroxide (Na ２ O ２ ), barium peroxide (BaO ２ ) or benzoyl peroxide (C ６ H ５ CO) ２ O ２ These include peroxides such as hypochlorous acid (HClO), perchloric acid, nitric acid, ozonated water, peracetic acid, or nitrobenzene, as well as other organic peroxides. The raw material solution may also contain the aforementioned dopants.

[0050] The solvent in the raw material solution is not particularly limited and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. The solvent preferably contains water, and more preferably is water or a mixed solvent of water and alcohol.

[0051] In the atomization process, a raw material solution containing metal is prepared, and the prepared raw material solution is atomized. As a result, atomized droplets are suspended in the air. The atomization means for atomizing the raw material solution is not particularly limited and may be known means. Preferably, the atomization means is a means for atomizing the raw material solution using ultrasonic vibration. The atomized droplets generated in the atomization process are suspended in the air and are preferably droplets that have zero initial velocity and can float in space and be transported as a gas, rather than being sprayed, for example. The size of the atomized droplets is not particularly limited and may be droplets of a few millimeters, but preferably 50 μm or less, and more preferably 1 μm to 10 μm.

[0052] In the film formation process, atomized droplets are transported to the substrate by a carrier gas. The substrate is not particularly limited as long as it can support the semiconductor layer. Examples of substrate shapes include flat plates or discs, fibrous shapes, rod shapes, cylindrical shapes, prismatic shapes, tubular shapes, spiral shapes, spherical shapes, and ring shapes. When forming the second semiconductor layer 3, the substrate is, for example, a substrate 9. When forming the first semiconductor layer 2, the substrate is, for example, a substrate 9 and the second semiconductor layer 3 formed on the substrate 9.

[0053] The substrate 9 is preferably a crystal growth substrate suitable for crystal growth of a film that will become a semiconductor layer. Although the substrate 9 is an insulating substrate, it may also be a semiconductor substrate or a conductive substrate.

[0054] The substrate 9 may be a single-crystal substrate or a polycrystalline substrate. The material of the substrate 9 may be an organic compound or an inorganic compound. The substrate 9 may be, for example, a sapphire substrate or a gallium oxide substrate, or Ga ２ O ３ and Al ２ O ３ It is a mixed crystal substrate containing [the specified material].

[0055] The substrate 9 is preferably a substrate containing a material having a corundum structure, a substrate containing a material having a β-gallia structure, or a substrate containing a material having a hexagonal crystal structure. The substrate 9 preferably contains a substrate material having a corundum structure, a β-gallia structure or a hexagonal crystal structure as a main component, and particularly preferably contains a material having a corundum structure as a main component. The substrate 9 may contain 70% or more, or 90% or more of a material having a corundum structure, a β-gallia structure or a hexagonal crystal structure. The substrate 9 may be formed only of a material having a corundum structure, a β-gallia structure or a hexagonal crystal structure.

[0056] Examples of the material having a corundum structure include α-Al ２ O ３ (sapphire substrate) or α-Ga ２ O ３ and the like. The substrate having a corundum structure is, for example, an a-plane sapphire substrate, an m-plane sapphire substrate, an r-plane sapphire substrate, a c-plane sapphire substrate, or an α-type gallium oxide substrate (a-plane, m-plane, r-plane, or c-plane) and the like. The substrate having a β-gallia structure is, for example, a β-Ga ２ O ３ substrate, or a Ga ２ O ３ and Al ２ O ３ and containing Al ２ O ３ in an amount of more than 0 wt% and 60 wt% or less, such as a mixed crystal substrate and the like. Further, the substrate having a hexagonal crystal structure is, for example, a SiC substrate, a ZnO substrate, a GaN substrate, or the like.

[0057] The carrier gas is, for example, oxygen, ozone, an inert gas (such as nitrogen, argon, etc.) or a reducing gas (such as hydrogen gas, forming gas, etc.). The type of the carrier gas may be one type, or two or more types. The type of the carrier gas is not particularly limited.

[0058] As a carrier gas, a dilution gas with a changed carrier gas concentration (for example, a 10-fold dilution gas) may be used as a second carrier gas. Also, there may be two or more carrier gas supply points, not just one. The flow rate of the carrier gas is not particularly limited, but is preferably 0.01 L / min or more and 20 L / min or less, and more preferably 1 L / min or more and 10 L / min or less. In the case of a dilution gas, the flow rate of the dilution gas is preferably 0.001 L / min or more and 2 L / min or less, and more preferably 0.1 L / min or more and 1 L / min or less.

[0059] In the film formation process, a semiconductor layer is formed on the substrate by the reaction of atomized droplets on the substrate. The reaction is not particularly limited as long as it is a reaction that forms a film from atomized droplets, but a thermal reaction is preferred. In a thermal reaction, it is sufficient for the atomized droplets to react with heat, and the reaction conditions are not particularly limited. The thermal reaction is usually carried out at a temperature above the evaporation temperature of the solvent in the raw material solution, but a relatively low temperature is preferred, specifically at a temperature of 650°C or lower, and more preferably at a temperature of 300°C or higher and 650°C or lower. The thermal reaction may be carried out under any atmosphere, such as under vacuum, a non-oxygen atmosphere, a reducing gas atmosphere, or an oxygen atmosphere, and may also be carried out under any conditions of atmospheric pressure, pressurized, or reduced pressure. Carrying the thermal reaction under atmospheric pressure is preferred because it makes it easier to calculate the evaporation temperature and simplifies the equipment. The thickness of the semiconductor layer formed in the film formation process can be set by adjusting the film formation time.

[0060] After the film formation process, an annealing treatment may be performed. The annealing treatment temperature is, for example, 300°C to 650°C. Preferably, the annealing treatment temperature is 350°C to 550°C. However, the annealing treatment temperature is not limited to the temperatures mentioned above. The annealing treatment time is, for example, 1 minute to 48 hours. Preferably, the annealing treatment time is 10 minutes to 24 hours, and more preferably 30 minutes to 12 hours. However, the annealing treatment time is not limited to the times mentioned above. Furthermore, the annealing treatment may be performed under any atmosphere as long as it does not hinder the purpose of this disclosure. It may be under a non-oxygen atmosphere or under an oxygen atmosphere. Examples of a non-oxygen atmosphere include an inert gas atmosphere (e.g., under a nitrogen atmosphere) or a reducing gas atmosphere. It is preferable that the annealing treatment be performed under an inert gas atmosphere or a nitrogen atmosphere. Note that each of the first semiconductor layer 2 and the second semiconductor layer 3 may be formed by other known formation methods.

[0061] The field relaxation layer formation process is performed after the preparation process. In the field relaxation layer formation process, a field relaxation layer 4 is formed on the first semiconductor layer 2. The field relaxation layer 4 is formed, for example, inside a trench 21 formed on the upper surface of the first semiconductor layer 2, as shown in Figure 7.

[0062] The trench 21 is formed, for example, in the insulating layer formation process. The trench 21 is formed by etching, for example, the RIE (Reactive Ion Etching) method. In the method for forming the trench 21 using the RIE method, for example, the first semiconductor layer 2 is etched using a plasma-generated etching gas. The etching gas preferably contains at least halogen. The plasma-generated etching gas preferably contains oxygen. Etching may also be performed in a halogen gas atmosphere. Note that the method for forming the trench 21 is not limited to the RIE method, but may also be other known methods.

[0063] In the field relaxation layer formation process, a field relaxation layer 4 is formed in the trench 21, as shown in Figure 8. The field relaxation layer 4 is formed by, for example, CVD, atmospheric pressure CVD, plasma CVD, or mist CVD. It is preferable that the field relaxation layer 4 is formed by mist CVD or atmospheric pressure CVD. The field relaxation layer 4 may also be formed by other known methods, such as ion implantation or impurity doping.

[0064] The field relaxation layer formation step preferably includes a polishing step for polishing the first semiconductor layer 2 and the field relaxation layer 4. In the polishing step, for example, the first semiconductor layer 2 and the field relaxation layer 4 are polished by CMP (Chemical Mechanical Planarization) so that the upper surface of the first semiconductor layer 2 and the upper surface of the field relaxation layer 4 become flush or substantially flush. In addition, the first semiconductor layer 2 and the field relaxation layer 4 may be polished by a method other than CMP in the polishing step.

[0065] The electrode formation process is performed after the field relaxation layer formation process. In the electrode formation process, a first electrode 5 is formed on the upper surface of the first semiconductor layer 2 and the upper surface of the field relaxation layer 4 (see Figure 9), and a second electrode 6 is formed on the lower surface of the second semiconductor layer 3. The second electrode 6 may be formed, for example, after the substrate 9 has been removed from the laminated structure 8. The first electrode 5 and the second electrode 6 are formed, for example, by a dry method or a wet method. Dry methods include, for example, sputtering, vacuum deposition, or CVD. Wet methods include, for example, screen printing or die coating. By forming the first electrode 5 and the second electrode 6 in this way, the semiconductor device 100 shown in Figure 1 is formed.

[0066] When a forward voltage is applied to the semiconductor device 100, the energy barrier at the interface between the first semiconductor layer 2 and the first electrode 5 decreases, and current flows from the first electrode 5 to the second electrode 6 through the first semiconductor layer 2 and the second semiconductor layer 3. On the other hand, when a reverse voltage is applied to the semiconductor device 100, the depletion layer of the first semiconductor layer 2 expands away from the interface between the first semiconductor layer 2 and the first electrode 5. As a result, the current in the semiconductor device 100 is interrupted. At this time, the field relaxation layer 4 functions as a guard ring, and the electric field concentration in the portion of the first semiconductor layer 2 near the outer end of the first electrode 5 is mitigated.

[0067] In the semiconductor device 100 described above, the upper surface of the first portion 43 of the field relaxation layer 4 adjacent to the first semiconductor layer 2 is located above a position 0.1 μm below the upper surface of the second portion 23 of the first semiconductor layer 2, which is adjacent to the first portion 43. Therefore, when a reverse voltage is applied to the semiconductor device 100, electric field concentration is less likely to occur in the second portion 23 of the first semiconductor layer 2 adjacent to the field relaxation layer 4. Consequently, malfunctions associated with electric field concentration are less likely to occur, and in particular, leakage current can be reduced.

[0068] Furthermore, if the upper surface of the first portion 43 and the upper surface of the second portion 23 are located within a range of less than 0.1 μm or less than 0.05 μm in the vertical direction, or if there is no step between the upper surface of the first portion 43 and the upper surface of the second portion 23 and the upper surface of the first portion 43 and the upper surface of the second portion 23 are flush, the electric field concentration of the semiconductor device 100 can be further mitigated. In addition, the first electrode 5 can be formed with high precision on the first semiconductor layer 2 and the electric field relaxation layer 4. Moreover, variations in the thickness of the first electrode 5 formed on the first semiconductor layer 2 and the electric field relaxation layer 4 can be suppressed, stabilizing the electrical characteristics and improving mechanical strength.

[0069] In this embodiment, when the first semiconductor layer 2 is formed from a harder material than the field relaxation layer 4, generally, the field relaxation layer 4 is more easily polished than the first semiconductor layer 2, making it easier for a step to form between the upper surface of the first semiconductor layer 2 and the upper surface of the field relaxation layer 4. Furthermore, for example, when a cleaning solution such as buffered hydrofluoric acid is used to clean the first semiconductor layer 2 and the field relaxation layer 4, the etch rates of the first semiconductor layer 2 and the field relaxation layer 4 with respect to the cleaning solution may differ, which may also lead to the formation of a step between the upper surface of the first semiconductor layer 2 and the upper surface of the field relaxation layer 4. Moreover, when a high voltage is applied to the semiconductor device 100, even if the step between the upper surface of the first semiconductor layer 2 and the upper surface of the field relaxation layer 4 is not large, problems associated with electric field concentration are more likely to occur. Therefore, reducing the step between the upper surface of the first portion 43 and the upper surface of the second portion 23, as in this embodiment, and making it less likely for problems associated with electric field concentration to occur is particularly effective when the first semiconductor layer 2 is formed from a harder material than the field relaxation layer 4, or when the semiconductor device 100 is a power device.

[0070] (Examples) The preparation step, the field relaxation layer formation step, and the polishing step in the manufacturing method shown in the embodiment were performed in order to obtain laminated structures of Examples 1 to 4 having a structure similar to the laminated structure shown in Figure 8. In the semiconductor devices of Examples 1 to 4, the first semiconductor layer and the second semiconductor layer are each α-Ga ２ O ３ The field relaxation layer is made of silicon dioxide. In Examples 1 to 4, the film deposition temperature for forming the field relaxation layer was set to 400°C.

[0071] (Comparative Example) The laminated structures of Comparative Examples 1 to 4 were obtained by the same method as in Examples 1 to 4, except that the film deposition temperature when forming the electric field relaxation layer was set to 350°C.

[0072] (Evaluation) For the laminated structures of Examples 1 to 4 and Comparative Examples 1 to 4, the step height between the upper surface of the first portion of the field relaxation layer and the upper surface of the second portion of the first semiconductor layer was measured. For the laminated structure of Example 4, a scanning electron microscope (SEM) was used to photograph the cross-section of the boundary between the first semiconductor layer and the field relaxation layer.

[0073] FIG. 10 is a graph showing the dimensions of the step in Examples 1 to 4 and Comparative Examples 1 to 4. As is clear from FIG. 10, the step in Comparative Examples 1 to 4 exceeded 0.12 μm, while the step in Examples 1 to 4 was less than 0.02 μm. FIG. 11 is a photograph showing a cross section of the boundary portion between the first semiconductor layer and the electric field relaxation layer of Example 4. As is clear from FIG. 11, the dimension of the step in Example 4 was approximately 0 μm, and the upper surface of the first semiconductor layer and the upper surface of the electric field relaxation layer were flush with each other.

[0074] (Simulation) In order to confirm the effect of the present disclosure, a simulation was performed on a semiconductor device having the same structure as the semiconductor device 100 shown in FIG. 1, and the leak current value was calculated for each of a case where no step is formed between the upper surface of the first semiconductor layer and the electric field relaxation layer, and a case where a step of 0.1 μm is formed between the upper surface of the first semiconductor layer and the electric field relaxation layer. In the simulation, each of the first semiconductor layer and the second semiconductor layer was set to α-Ga ２ O ３ , and the electric field relaxation layer was set to silicon dioxide. As a result of the simulation, when no step is formed between the upper surface of the first semiconductor layer and the electric field relaxation layer, a reduction in leak current in the portion of the first semiconductor layer near the electric field relaxation layer was confirmed, and the value of the leak current was 1×10 ―７ A / cm ２ . On the other hand, when a step of 0.1 μm is formed between the upper surface of the first semiconductor layer and the electric field relaxation layer, the leak current in the portion of the first semiconductor layer near the electric field relaxation layer is larger than the leak current in other portions, and the value thereof was 1×10 ５ A / cm ２ . From this, it is understood that the leak current can be significantly reduced when a step of 0.1 μm or more is not formed between the upper surface of the first semiconductor layer and the upper surface of the electric field relaxation layer.

[0075] In the example, the film deposition temperature for forming the field relaxation layer was higher than in the comparative example for the following reason: the etching rate when the upper surface of the first semiconductor layer and the upper surface of the field relaxation layer are polished or cleaned with a cleaning solution can vary depending on the hardness of the first semiconductor layer and the field relaxation layer, respectively. Therefore, if the hardness of the first semiconductor layer and the hardness of the field relaxation layer are different, a difference will occur between the etching rate of the first semiconductor layer and the etching rate of the field relaxation layer, which is expected to result in the formation of a step between the upper surface of the first semiconductor layer and the upper surface of the field relaxation layer after polishing or cleaning. Therefore, in the example, the film deposition temperature of the field relaxation layer was increased to increase the density of the field relaxation layer after deposition, thereby bringing the etching rate of the field relaxation layer closer to that of the first semiconductor layer. The results of the above example demonstrate that the etching rate of the field relaxation layer and the etching rate of the first semiconductor layer can be adjusted by adjusting the film deposition temperature of the field relaxation layer and the film deposition temperature of the first semiconductor layer. Furthermore, this shows that even if the materials of the first semiconductor layer and the field relaxation layer are different from those in the example, the step difference formed between the upper surface of the first semiconductor layer and the upper surface of the field relaxation layer can be reduced, similar to the example, by adjusting the deposition temperature of the first semiconductor layer and the field relaxation layer.

[0076] (Modifications) Next, modifications of the embodiment will be described. In the following description of modifications, we will describe the differences from the embodiment, and omit the explanation of matters that are common to the embodiment.

[0077] (Modification 1) Figure 12 is a schematic cross-sectional view of the semiconductor device 101 of Modification 1, and corresponds to Figure 1. In this example, the semiconductor device 101 has a first portion 43 of the field relaxation layer 4 that is adjacent to the first semiconductor layer 2, which protrudes above the second portion 23 of the first semiconductor layer 2 that is adjacent to the first portion 43. Specifically, the entire upper surface of the field relaxation layer 4 is located above the upper surface of the first semiconductor layer 2. The step difference between the first portion 43 and the second portion 23 may be less than 0.1 μm, less than 0.05 μm, or 0.1 μm or more.

[0078] In this example, since the first electrode 5 does not have a portion embedded in the first semiconductor layer 2, when a reverse voltage is applied to the semiconductor device 100, electric field concentration is less likely to occur in the portion of the first semiconductor layer 2 adjacent to the electric field relaxation layer 4. Therefore, in this example as well, malfunctions associated with electric field concentration are less likely to occur in the semiconductor device 101.

[0079] (Modification 2) Figure 13 is a schematic cross-sectional view of the semiconductor device 102 of Modification 2, corresponding to Figure 1. The semiconductor device 102 of this example further comprises an insulating layer 11 formed on the first semiconductor layer 2 and the field relaxation layer 4. The insulating layer 11 is formed from, for example, the material exemplified as the material for the field relaxation layer 4. The insulating layer 11 is located around the first electrode 5. The insulating layer 11 is in contact with the upper surface of the field relaxation layer 4 and the upper surface of the portion of the first semiconductor layer 2 located outside the field relaxation layer 4. The outer edge of the first electrode 5 is located on the insulating layer 11. The outer end of the first electrode 5 is in contact with the inner end of the field relaxation layer 4. The insulating layer 11 is formed, for example, by CVD, atmospheric pressure CVD, plasma CVD, or mist CVD. In this example, the insulating layer 11 can further improve the breakdown voltage characteristics of the semiconductor device 102. Furthermore, the field relaxation layer 4 in this example may protrude above the upper surface of the first semiconductor layer 2, similar to the field relaxation layer 4 in Modification 1.

[0080] (Modification 3) Figure 14 is a schematic cross-sectional view of the semiconductor device 103 of Modification 3, corresponding to Figure 1. In the semiconductor device 103 of this example, the field relaxation layer 4 includes a first layer 41 formed along the inner surface of the trench 21 of the first semiconductor layer 2, and a second layer 42 embedded in the first layer 41. Each of the first layer 41 and the second layer 42 is, for example, a high-resistance layer and is formed from the material exemplified as the material for the field relaxation layer 4 of the embodiment. By including the first layer 41 and the second layer 42 in this way, it becomes possible to obtain desired characteristics by appropriately selecting the materials of each of the first layer 41 and the second layer 42. For example, by making the first layer 41 a layer that is epitaxially grown based on the crystal structure of the first semiconductor layer 2, defects that tend to occur at the interface between the field relaxation layer 4 and the first semiconductor layer 2 can be reduced, and the semiconductor device 103 can be made to withstand higher voltage. Furthermore, the field relaxation layer 4 in this example may protrude above the upper surface of the first semiconductor layer 2, similar to the field relaxation layer 4 in Modification 1. Also, the semiconductor device 103 in this example may further include an insulating layer 11 similar to that in Modification 2.

[0081] (Modification 4) Figure 15 is a schematic cross-sectional view of the semiconductor device 104 of Modification 4, corresponding to Figure 1. The semiconductor device 104 of this example further includes a passivation film 12 covering the outer end of the first electrode 5. The passivation film 12 is formed from, for example, the material exemplified as the material for the field relaxation layer 4. The passivation film 12 is located around the first electrode 5. The passivation film 12 is in contact with the upper surface of the field relaxation layer 4, the upper surface of the portion of the first semiconductor layer 2 located outside the field relaxation layer 4, and the outer end of the first electrode 5. The inner edge of the passivation film 12 is located on the first electrode 5. The passivation film 12 is formed, for example, by CVD, atmospheric pressure CVD, plasma CVD, or mist CVD. In this example, the passivation film 12 can further reduce the leakage current when a reverse voltage is applied. Furthermore, it is preferable that the passivation film 12 covers the entire portion of the upper surface of the first semiconductor layer 2 that is located outside the field relaxation layer 4. The field relaxation layer 4 in this example may protrude above the upper surface of the first semiconductor layer 2, similar to the field relaxation layer 4 in Modification 1. Also, the field relaxation layer 4 in this example may include a first layer 41 and a second layer 42, similar to the field relaxation layer 4 in Modification 3.

[0082] (Modification 5) Figure 16 is a schematic cross-sectional view of the semiconductor device 105 of Modification 5, corresponding to Figure 1. The semiconductor device 105 in this example is a junction barrier Schottky diode (JBS). The semiconductor device 105 further comprises a semiconductor layer 7 provided between the first semiconductor layer 2 and the first electrode 5. Hereinafter, the semiconductor layer 7 will be referred to as the third semiconductor layer 7. In this example, the semiconductor device 105 comprises a plurality of semiconductor layers 7. Each third semiconductor layer 7 is embedded in the first semiconductor layer 2. Note that part or all of the third semiconductor layer 7 may be located above the upper surface of the first semiconductor layer 2.

[0083] Specifically, a trench 22 separate from the trench 21 in which the field relaxation layer 4 is embedded is formed on the upper surface of the first semiconductor layer 2. In this example, multiple trenches 22 are formed on the upper surface of the first semiconductor layer 2. Each trench 22 is formed inward from the trench 21 when viewed from above.

[0084] The third semiconductor layer 7 is formed inside the trench 22. The third semiconductor layer 7 is located inside the field relaxation layer 4 when viewed from above. The conductivity type of the third semiconductor layer 7 is different from that of the first semiconductor layer 2. In this example, the conductivity type of the third semiconductor layer 7 is p-type. The third semiconductor layer 7 is formed from, for example, the material exemplified as the material for the first semiconductor layer 2 in the embodiment, or the material exemplified as the material for the field relaxation layer 4, which is a semiconductor in the embodiment.

[0085] In this example, when a reverse voltage is applied to the semiconductor device 105, the depletion layer in the first semiconductor layer 2 extends to the periphery of the third semiconductor layer 7, mitigating electric field concentration. As a result, the breakdown voltage of the semiconductor device 105 is improved, and leakage current is suppressed. The electric field relaxation layer 4 in this example may protrude above the upper surface of the first semiconductor layer 2, similar to the electric field relaxation layer 4 in Modification 1. The semiconductor device 103 in this example may further include an insulating layer 11 similar to that in Modification 2. The electric field relaxation layer 4 in this example may include a first layer 41 and a second layer 42, similar to the electric field relaxation layer 4 in Modification 3. The semiconductor device 105 in this example may also include a passivation film 12 similar to that in Modification 4.

[0086] (Modification 6) Figure 17 is a schematic cross-sectional view of the semiconductor device 106 of Modification 6, and corresponds to Figure 1. Figure 18 is an enlarged view of section C in Figure 17. In this example, a second trench 22 is formed at the boundary between the first semiconductor layer 2 and the field relaxation layer 4, and the bottom surface of the second trench 22 includes the first portion 43 and the second portion 23.

[0087] The semiconductor device 106 further comprises a fourth semiconductor layer 13 located inside the field relaxation layer 4 and adjacent to the field relaxation layer 4. The fourth semiconductor layer 13 has a conductivity type different from that of the first semiconductor layer 2. In this example, the fourth semiconductor layer 13 is a p-type semiconductor. The field relaxation layer 4 is a high-resistance layer or insulating layer as exemplified in the embodiment, and the field relaxation layer 4 and the fourth semiconductor layer 13 form a junction termination structure that mitigates electric field concentration in the semiconductor device 106.

[0088] The second trench 22 is formed in the first semiconductor layer 2 and the field relaxation layer 4, and the fourth semiconductor layer 13 is formed inside the second trench 22. All or almost all of the fourth semiconductor layer 13 is embedded in the first semiconductor layer 2 and the field relaxation layer 4.

[0089] Specifically, the first semiconductor layer 2 and the field relaxation layer 4 have two second trenches 22 that are spaced apart in a direction perpendicular to the vertical direction, and the fourth semiconductor layer 13 is formed in each second trench 22. The second trenches 22 have a length direction and a width direction. The two second trenches 22 are spaced apart in the width direction of the second trenches 22. The second trenches 22 are located at the boundary between the first semiconductor layer 2 and the field relaxation layer 4. When viewed from above, the second trenches 22 extend linearly along the inner surface of the field relaxation layer 4. A portion of the second trenches 22, more specifically, the portion of the second trenches 22 that is located on the outside in the width direction of the second trenches 22, penetrates into the field relaxation layer 4. The bottom surface of the second trenches 22 is located above the bottom surface of the field relaxation layer 4.

[0090] The bottom surface of the second trench 22 is formed by a part of the field relaxation layer 4 and a part of the first semiconductor layer 2. The portion of the bottom surface of the second trench 22 formed by the field relaxation layer 4 is the first portion 43, and the portion formed by the first semiconductor layer 2 is the second portion 23. On the bottom surface of the second trench 22, similar to the first portion 43 and the second portion 23 in the embodiment, the upper surface of the first portion 43 is located above a position 0.1 μm below the upper surface of the second portion 23. Specifically, the upper surface of the first portion 43 and the upper surface of the second portion 23 are flush. Note that the first portion 43 on the bottom surface of the second trench 22 may protrude above the second portion 23, similar to the first portion 43 in Modification 1.

[0091] The fourth semiconductor layer 13 extends along the entire length of the second trench 22. The cross-sectional shape of the fourth semiconductor layer 13 is U-shaped, following the inner surface of the second trench 22, and opens upward. A portion of the fourth semiconductor layer 13 overlaps the field relaxation layer 4. Specifically, the portion of the fourth semiconductor layer 13 located on the outside in the width direction overlaps the inner end of the field relaxation layer 4 and is in contact with the portion of the field relaxation layer 4 that forms the inner surface of the second trench 22. The portion of the fourth semiconductor layer 13 located on the inside in the width direction overlaps the first semiconductor layer 2 and is in contact with the portion of the first semiconductor layer 2 that forms the inner surface of the second trench 22. The upper end surface of the fourth semiconductor layer 13 is substantially flush with the upper surfaces of the field relaxation layer 4 and the first semiconductor layer 2, respectively. The upper end surface of the fourth semiconductor layer 13 may be located above or below the upper surfaces of the field relaxation layer 4 and the first semiconductor layer 2, respectively. The cross-sectional shape of the fourth semiconductor layer 13 is not limited to a U-shape. For example, in this embodiment, the fourth semiconductor layer 13 is formed from a material exemplified as the material for the field relaxation layer 4, which is a p-type semiconductor. A portion of the first electrode 5 is embedded in an upwardly opening recess formed in the U-shaped fourth semiconductor layer 13 and is in contact with the inner surface of the fourth semiconductor layer 13.

[0092] The method for manufacturing the semiconductor device 106 further includes a fourth semiconductor layer formation step of forming a fourth semiconductor layer 13 in the first semiconductor layer 2 and the field relaxation layer 4. The fourth semiconductor layer formation step is performed, for example, after the field relaxation layer formation step. In the fourth semiconductor layer formation step, for example, after a second trench 22 is formed in the first semiconductor layer 2 and the field relaxation layer 4, the fourth semiconductor layer 13 is formed in the second trench 22. The second trench 22 is formed, for example, in the same way as the first trench 21 formed in the field relaxation layer formation step described above. The fourth semiconductor layer 13 is formed, for example, in the same way as the first semiconductor layer 2, by CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, PLD, or ALD, or other known methods. Preferably, the fourth semiconductor layer 13 is formed by mist CVD or mist epitaxy.

[0093] In this example, when a reverse voltage is applied to the semiconductor device 106, the depletion layer of the first semiconductor layer 2 also expands in a direction away from the interface between the first semiconductor layer 2 and the fourth semiconductor layer 13. At this time, since the outer corner of the bottom of the fourth semiconductor layer 13 is covered with the electric field relaxation layer 4, the electric field concentration in the first semiconductor layer 2 is relaxed.

[0094] In this modified example, the upper surface of the first portion 43 is located above a point 0.1 μm below the upper surface of the second portion 23 at the bottom of the second trench 22. Therefore, when a reverse voltage is applied to the semiconductor device 100, electric field concentration is less likely to occur in the portion of the first semiconductor layer 2 near the bottom of the second trench 22. As a result, malfunctions associated with electric field concentration are less likely to occur.

[0095] The semiconductor devices 100 to 106 described above can be applied to power conversion devices such as inverters and converters in order to perform the functions described above.

[0096] (Control System) Figure 19 is a block diagram showing an example of a control system 500 using any of the semiconductor devices 100 to 106. The control system 500 is a system suitable for installation in, for example, an electric vehicle. The control system 500 includes a battery (power source) 501, a boost converter 502, a buck converter 503, an inverter 504, a motor (driven object) 505, and a drive control unit 506, all of which are installed in an electric vehicle. The battery 501 is a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores power through charging at a power supply station or regenerative energy during deceleration, and can output a DC voltage necessary for the operation of the electric vehicle's drive system and electrical system. The boost converter 502 is a voltage converter equipped with, for example, a chopper circuit, and can boost a DC voltage of, for example, 200V supplied from the battery 501 to, for example, 650V by the switching operation of the chopper circuit, and output it to the drive system such as a motor. Similarly, the step-down converter 503 is a voltage conversion device equipped with a chopper circuit, but it can step down a DC voltage of, for example, 200V supplied from the battery 501 to, for example, about 12V, and output it to the electrical system including power windows, power steering, or on-board electrical equipment.

[0097] The inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching operation and outputs it to the motor 505. The motor 505 is a three-phase AC motor that constitutes the drive system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504, and this rotational driving force is transmitted to the wheels of the electric vehicle via a transmission (not shown) and the like.

[0098] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as wheel rotation speed, torque, and accelerator pedal depression (accelerator amount) from the electric vehicle while it is in motion, and these measurement signals are input to the drive control unit 506. At the same time, the output voltage value of the inverter 504 is also input to the drive control unit 506. The drive control unit 506 functions as a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as memory. It generates control signals using the input measurement signals and outputs them as feedback signals to the inverter 504, thereby controlling the switching operation of the switching elements. As a result, the AC voltage supplied by the inverter 504 to the motor 505 is corrected instantaneously, enabling accurate operation control of the electric vehicle and realizing safe and comfortable operation of the electric vehicle. It is also possible to control the output voltage to the inverter 504 by supplying the feedback signal from the drive control unit 506 to the boost converter 502.

[0099] Figure 20 shows the circuit configuration excluding the step-down converter 503 in Figure 19, i.e., the configuration for driving the motor 505. The semiconductor devices 100-106 are used for switching control by being employed, for example, as Schottky barrier diodes in the step-up converter 502 and inverter 504. In the step-up converter 502, they are incorporated into a chopper circuit to perform chopper control, and in the inverter 504, they are incorporated into a switching circuit including an IGBT to perform switching control. In addition, current stabilization is achieved by interposing an inductor (such as a coil) at the output of the battery 501, and voltage stabilization is achieved by interposing capacitors (such as electrolytic capacitors) between the battery 501, step-up converter 502, and inverter 504.

[0100] Furthermore, as shown by the dotted line in Figure 20, the drive control unit 506 is equipped with a calculation unit 507 consisting of a CPU (Central Processing Unit) and a storage unit 508 consisting of non-volatile memory. Signals input to the drive control unit 506 are provided to the calculation unit 507, which generates feedback signals for each semiconductor element by performing programmed calculations as needed. The storage unit 508 temporarily holds the calculation results from the calculation unit 507 and stores physical constants and functions necessary for drive control in the form of a table, outputting them to the calculation unit 507 as appropriate. The calculation unit 507 and the storage unit 508 can employ known configurations, and their processing capabilities can be arbitrarily selected.

[0101] As shown in Figures 19 and 20, in the control system 500, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the switching operation of the boost converter 502, the buck converter 503, and the inverter 504. ２ O ３ ), especially corundum-type gallium oxide (α-Ga ２ O ３ By using ) as the material, the switching characteristics are significantly improved. Furthermore, by applying semiconductor devices 100 to 106, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be achieved. In other words, the boost converter 502, the buck converter 503, and the inverter 504 can each be expected to benefit from the effects of this disclosure, and the effects of this disclosure can be expected in any one of these, any combination of two or more, or in any configuration including the drive control unit 506.

[0102] Furthermore, the control system 500 described above can be applied not only to the control systems of electric vehicles using semiconductor devices 100-106, but also to control systems for a wide range of applications, such as boosting or stepping down power from a DC power source, or converting DC to AC power. It is also possible to use a power source such as a solar cell as the battery.

[0103] Figure 21 is a block diagram showing another example of a control system employing any of the semiconductor devices 100 to 106. The control system 600 is a system suitable for installation in infrastructure equipment and home appliances that operate on power from an AC power source. The control system 600 receives power supplied from, for example, an external three-phase AC power source (power supply) 601, and includes an AC / DC converter 602, an inverter 604, a motor (to be driven) 605, and a drive control unit 606, which can be installed in various devices (described later). The three-phase AC power source 601 is, for example, a power generation facility of an electric power company (thermal power plant, hydroelectric power plant, geothermal power plant, nuclear power plant, etc.), and its output is supplied as AC voltage after being stepped down via a substation. Alternatively, it may be installed in a building or nearby facility in the form of a private generator and supplied via a power cable. The AC / DC converter 602 is a voltage conversion device that converts AC voltage to DC voltage, converting the 100V or 200V AC voltage supplied from the three-phase AC power source 601 into a predetermined DC voltage. Specifically, the voltage is converted to a commonly used desired DC voltage such as 3.3V, 5V, or 12V. If the driven object is a motor, the voltage is converted to 12V. It is also possible to use a single-phase AC power supply instead of a three-phase AC power supply, and in that case, a similar system configuration can be achieved by using a single-phase input AC / DC converter.

[0104] The inverter 604 converts the DC voltage supplied from the AC / DC converter 602 into a three-phase AC voltage by switching operation and outputs it to the motor 605. The form of the motor 605 varies depending on the controlled object, but if the controlled object is a train, it drives the wheels; if it is factory equipment, it drives pumps and various power sources; and if it is home appliances, it drives compressors, etc. It is a three-phase AC motor that is rotationally driven by the three-phase AC voltage output from the inverter 604 and transmits that rotational driving force to the driven object (not shown).

[0105] In addition, many home appliances, for example, can be driven directly by the DC voltage output from the AC / DC converter 602 (e.g., personal computers, LED lighting equipment, video equipment, audio equipment, etc.). In such cases, the inverter 604 is not required in the control system 600, and the AC / DC converter 602 supplies the DC voltage to the driven device. In this case, for example, a 3.3V DC voltage is supplied to personal computers, and a 5V DC voltage is supplied to LED lighting equipment, etc.

[0106] Meanwhile, various sensors (not shown) are used to measure actual values ​​such as the rotational speed and torque of the driven object, as well as the temperature and flow rate of the surrounding environment of the driven object. These measurement signals are input to the drive control unit 606. At the same time, the output voltage value of the inverter 604 is also input to the drive control unit 606. Based on these measurement signals, the drive control unit 606 provides a feedback signal to the inverter 604, controlling the switching operation of the switching element. This instantly corrects the AC voltage supplied by the inverter 604 to the motor 605, enabling accurate operation control of the driven object and achieving stable operation of the driven object. Furthermore, as described above, if the driven object can be driven with a DC voltage, it is also possible to use feedback control of the AC / DC converter 602 instead of feedback to the inverter 604.

[0107] Figure 22 shows the circuit configuration of Figure 21. Semiconductor devices 100-106 are used for switching control by being employed, for example, as Schottky barrier diodes in the AC / DC converter 602 and inverter 604. The AC / DC converter 602 uses, for example, a Schottky barrier diode configured in a bridge circuit, and performs DC conversion by converting the negative voltage component of the input voltage to a positive voltage and rectifying it. The inverter 604 is incorporated into the switching circuit of the IGBT to perform switching control. Voltage stabilization is achieved by interposing a capacitor (such as an electrolytic capacitor) between the AC / DC converter 602 and the inverter 604.

[0108] Furthermore, as shown by the dotted line in Figure 22, the drive control unit 606 is equipped with a calculation unit 607 consisting of a CPU and a storage unit 608 consisting of non-volatile memory. Signals input to the drive control unit 606 are provided to the calculation unit 607, which generates feedback signals for each semiconductor element by performing programmed calculations as needed. The storage unit 608 temporarily holds the calculation results from the calculation unit 607 and stores physical constants and functions necessary for drive control in the form of a table, outputting them to the calculation unit 607 as appropriate. The calculation unit 607 and the storage unit 608 can employ known configurations, and their processing capabilities can be arbitrarily selected.

[0109] In such a control system 600, as with the control system 500 shown in Figures 19 and 20, diodes and switching elements such as thyristors, power transistors, IGBTs, and MOSFETs are used for the rectification and switching operations of the AC / DC converter 602 and inverter 604. ２ O ３ ), especially corundum-type gallium oxide (α-Ga ２ O ３ By using ) as the material, the switching characteristics are improved. Furthermore, by applying semiconductor devices 100 to 106, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be achieved. In other words, the AC / DC converter 602 and the inverter 604 can each be expected to benefit from the effects of this disclosure, and the effects of this disclosure can be expected in any one of them, a combination thereof, or in a configuration that also includes the drive control unit 606.

[0110] Although Figures 21 and 22 illustrate the motor 605 as the target to be driven, the target to be driven is not necessarily limited to mechanically operating devices, and can be many devices that require AC voltage. The control system 600 is applicable as long as it drives the target to be driven by inputting power from an AC power source, and can be installed for drive control of infrastructure equipment (e.g., power equipment in buildings and factories, communication equipment, traffic control equipment, water and wastewater treatment equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.).

[0111] [Note] The embodiments described above are described below.

[0112] (Note 1) A semiconductor device comprising a semiconductor layer containing a crystalline oxide semiconductor containing gallium, an electrode formed on the semiconductor layer, and an electric field relaxation layer provided between the semiconductor layer and the electrode to alleviate electric field concentration in the semiconductor layer, wherein the upper surface of a first portion of the electric field relaxation layer adjacent to the semiconductor layer is located above a position 0.1 μm below the upper surface of a second portion of the semiconductor layer adjacent to the first portion.

[0113] (Note 2) The semiconductor device described in Note 1, wherein the field relaxation layer is an insulating layer.

[0114] (Note 3) The insulating layer is a semiconductor device according to Note 1 or Note 2, comprising an oxide.

[0115] (Note 4) The insulating layer is a semiconductor device according to any one of Notes 1 to 3, comprising silicon dioxide.

[0116] (Note 5) The insulating layer is a semiconductor device according to any one of Notes 1 to 4, comprising aluminum oxide.

[0117] (Note 6) The semiconductor device according to any one of Notes 1 to 5, wherein the electric field relaxation layer is formed inside the first trench formed on the upper surface of the semiconductor layer.

[0118] (Note 7) A semiconductor device according to any one of Notes 1 to 6, wherein a second trench is formed at the boundary between the semiconductor layer and the field relaxation layer, and the bottom surface of the second trench is the first portion and the second portion.

[0119] (Note 8) The semiconductor device according to any one of Notes 1 to 7, wherein the upper surface of the first part and the upper surface of the second part are located within a range of less than 0.1 μm in the vertical direction.

[0120] (Note 9) The semiconductor device according to any one of Notes 1 to 8, wherein the upper surface of the first part and the upper surface of the second part are located within a range of less than 0.05 μm in the vertical direction.

[0121] (Note 10) The semiconductor device described in any of Notes 1 to 9, wherein the upper surface of the first part and the upper surface of the second part are flush.

[0122] (Note 11) The semiconductor device described in any of Notes 1 to 9, wherein the first part protrudes above the second part.

[0123] (Note 12) The crystalline oxide semiconductor is a semiconductor device according to any one of Notes 1 to 11, having a corundum structure or a β-gallia structure.

[0124] (Note 13) A semiconductor device described in any of Notes 1 to 12, which is a diode.

[0125] (Note 14) A semiconductor device that is a power device, as described in any of Notes 1 to 13.

[0126] (Note 15) A power conversion device including a semiconductor device described in any one of Notes 1 to 14.

[0127] (Note 16) A control system including a semiconductor device described in any one of Notes 1 to 15.

[0128] The semiconductor device of the present invention can be used in a wide range of fields, including semiconductors (e.g., compound semiconductor electronic devices), electronic components, electrical equipment components, optical and electrophotographic equipment, and industrial materials, but is particularly useful as a power device.

[0129] 2 First semiconductor layer (semiconductor layer) 3 Second semiconductor layer 4 Field relaxation layer 5 First electrode (electrode) 6 Second electrode 7 Third semiconductor layer 8 Laminated structure 9 Substrate 11 Insulator layer 12 Passivation film 13 Fourth semiconductor layer 21 First trench 22 Second trench 23 Second section 41 First layer 42 Second layer 43 First section 100 Semiconductor device 101 Semiconductor device 102 Semiconductor device 103 Semiconductor device 104 Semiconductor device 105 Semiconductor device 106 Semiconductor device 500 Control system 501 Battery 502 Boost converter 503 Buck converter 504 Inverter 505 Motor 506 Drive control unit 507 Calculation unit 508 Memory unit 600 Control system 601 Three-phase AC power supply 602 AC / DC converter 604 Inverter 605 Motor 606 Drive control unit 607 Calculation unit 608 Memory unit L Reference line

Claims

1. A semiconductor device comprising: a semiconductor layer containing a crystalline oxide semiconductor containing gallium; an electrode formed on the semiconductor layer; and an electric field relaxation layer provided between the semiconductor layer and the electrode for mitigating electric field concentration in the semiconductor layer, wherein the upper surface of a first portion of the electric field relaxation layer adjacent to the semiconductor layer is located above a position 0.1 μm below the upper surface of a second portion of the semiconductor layer adjacent to the first portion.

2. The semiconductor device according to claim 1, wherein the field relaxation layer is an insulating layer.

3. The semiconductor device according to claim 2, wherein the insulating layer comprises an oxide.

4. The semiconductor device according to claim 3, wherein the insulating layer comprises silicon dioxide.

5. The semiconductor device according to claim 3, wherein the insulating layer comprises aluminum oxide.

6. The semiconductor device according to claim 1, wherein the field relaxation layer is formed inside a first trench formed on the upper surface of the semiconductor layer.

7. The semiconductor device according to claim 1, wherein a second trench is formed at the boundary between the semiconductor layer and the field relaxation layer, and the bottom surface of the second trench includes the first portion and the second portion.

8. The semiconductor device according to any one of claims 1 to 7, wherein the upper surface of the first portion and the upper surface of the second portion are located within a range of less than 0.1 μm in the vertical direction.

9. The semiconductor device according to any one of claims 1 to 7, wherein the upper surface of the first portion and the upper surface of the second portion are located within a range of less than 0.05 μm in the vertical direction.

10. The semiconductor device according to any one of claims 1 to 7, wherein the upper surface of the first part and the upper surface of the second part are flush.

11. The semiconductor device according to any one of claims 1 to 7, wherein the first portion protrudes above the second portion.

12. The semiconductor device according to any one of claims 1 to 7, wherein the crystalline oxide semiconductor has a corundum structure or a β-gallia structure.

13. A semiconductor device according to any one of claims 1 to 7, which is a diode.

14. A semiconductor device according to any one of claims 1 to 7, which is a power device.

15. A power conversion device including a semiconductor device according to any one of claims 1 to 7.

16. A control system including a semiconductor device according to any one of claims 1 to 7.

Images