Circuit board and semiconductor package comprising same

Abstract

Disclosed are a circuit board and a semiconductor package comprising same enabling the effective inhibition of the occurrence, propagation, or expansion / growth of edge chipping, cracks, and / or substrate separation on the outer surface of a glass layer of a circuit board individualized by a singulation process. The circuit board, according to one embodiment of the present invention, comprises: a glass layer; a build-up layer disposed on the glass layer and having a width greater than the horizontal width of the glass layer; and a resin layer disposed so as to surround at least a portion of the outer surface of the build-up layer, and the outer surface of the glass layer. The resin layer comprises: a first resin layer portion overlapping the glass layer in the horizontal direction; and a second resin layer portion overlapping the build-up layer in the horizontal direction. The outer surface of the second resin layer portion comprises: a flat surface disposed on the peripheral portion of a first surface of at least one of the upper surface and the lower surface of the glass layer; and an inclined surface disposed on the outer surface of the build-up layer.

Description

Circuit board and semiconductor package including the same

[0001] The present invention relates to a circuit board, and more specifically, to a circuit board for a semiconductor package.

[0002] Semiconductor packages are used to protect semiconductor devices, such as chips and dies, and to electrically connect them to electronic components, such as main boards of electronic products. Semiconductor packages improve mounting area efficiency and enable high-speed signal transmission through short signal paths; consequently, they are utilized in a wide range of applications, including not only mobile devices but also autonomous vehicles, high-performance servers, and Internet of Things (IoT) products.

[0003] Semiconductor packages need to be designed to safely protect semiconductor devices, which are small in size and sensitive to physical shock, moisture, humidity, and heat, while ensuring the smooth implementation of functions such as signal and power transmission. As the demand for improved semiconductor device performance increases, the number or size of required semiconductor devices grows, and as semiconductor devices are divided into functional units, semiconductor chiplet technology is expanding. In semiconductor chiplet technology, semiconductor devices such as CPUs, GPUs, memory controllers, and interface (I / O) chips are manufactured separately and integrated into the semiconductor package.

[0004] The circuit board of a semiconductor package is a core component used to physically support and electrically connect electronic components. The circuit board must be designed to perform functions that ensure stable operation, such as accurately transmitting electrical signals between electronic components, fixing components in designated positions, and dissipating heat generated by the components. Circuit boards can be classified into core boards and coreless boards depending on the presence or absence of a core layer. Core boards, due to the presence of a core layer, are structurally robust and highly durable, with minimal warping or deformation, resulting in excellent stability during manufacturing and assembly, as well as ease of handling.

[0005] Core substrates can be classified into plastic core substrates, ceramic substrates, glass core substrates, etc., depending on the material of the core layer. The Young's modulus of glass core substrates is four times that of organic core substrates, and due to their excellent elastic modulus performance, they exhibit superior warping and deformation characteristics. Furthermore, glass core substrates have a low coefficient of thermal expansion (CTE), which provides excellent compatibility with silicon chips and offers the advantage of enabling the fine formation of through-glass vias (TGVs). In addition, glass core substrates have smooth surface characteristics, which are advantageous for forming microcircuits; they also exhibit low signal loss; and their excellent temperature-dependent deformation and signal characteristics make them suitable for semiconductor miniaturization and large-area applications.

[0006] A build-up layer may be disposed on the upper and / or lower surface of a glass core substrate. The build-up layer may include one or more circuit layers disposed on the core substrate and an insulating layer that insulates the circuit layers from each other. A plating layer may be formed on the upper or lower surface of the glass core substrate by chemical plating, electrolytic plating, etc., to which an upper circuit layer or a lower circuit layer may be disposed. A protective layer, such as a solder resist layer, may be disposed on the upper or lower surface of the build-up layer.

[0007] When a large substrate, such as a panel substrate, is manufactured by placing a build-up layer and a protective layer on a glass core substrate, the large substrate can be cut by a singulation process to obtain multiple individual circuit boards. The singulation process can be performed by mechanical cutting using a dicing saw, laser cutting using a UV laser or IR laser, etc.

[0008] Mechanical shock, cutting stress, or vibration caused by the dicing saw during the individualization process, or thermal stress and thermal expansion imbalance resulting from localized heating during laser cutting, can cause problems such as microcracks or delamination in individualized circuit boards. In particular, impacts and stresses acting on the sides of the glass core substrate during the individualization process can lead to defects such as chipping or cracking, where the edges of the glass core substrate break or shatter. If these defects propagate and grow due to impacts occurring during subsequent transfer or packaging processes, they can cause problems such as shortened semiconductor package lifespan, performance degradation of electronic components, and errors in electrical connections.

[0009] Furthermore, the glass core substrate, the plating layer, the upper circuit layer (or lower circuit layer) on the glass core substrate, and the insulating layer have different coefficients of thermal expansion; consequently, stress may occur during the substrate processing due to the difference in coefficients of thermal expansion between adjacent layers. Stress caused by the mismatch in the coefficients of thermal expansion between materials in adjacent layers can be a factor in causing a substrate separation problem known as the 'seware' phenomenon, where the core substrate splits vertically at the side. The background technology described above refers to the background in which the present invention was derived and does not imply that it is known technology prior to the filing of the present invention.

[0010] One objective of the present invention is to provide a circuit board and a semiconductor package including the same that can effectively suppress edge chipping, cracking, and / or substrate separation occurring, propagating, or expanding / growing on the side portions of the glass layer of a circuit board singulated by a singulation process.

[0011] In addition, the present invention has one objective of providing a circuit board capable of effectively suppressing the seware phenomenon in which a glass layer cracks due to tension stress acting on the side portion of a glass layer of an individualized circuit board, and a semiconductor package including the same.

[0012] In addition, the present invention has one objective of providing a circuit board capable of reducing defects in a glass layer by reducing stress caused by the difference in the coefficient of thermal expansion between a glass layer of an individualized circuit board, a resin layer covering the side portion of the glass layer, a metal layer (seed layer) on the glass layer, a plating layer, and / or an insulating layer, and a semiconductor package including the same.

[0013] In addition, the present invention has one objective of providing a circuit board and a semiconductor package including the same, which can protect the side portion of the glass layer and / or suppress the occurrence of defects in the side portion by improving the adhesion of the glass layer of the individualized circuit board and the resin layer disposed on the edge portion of the upper and / or lower surface of the glass layer.

[0014] In addition, the present invention has one objective of providing a circuit board and a semiconductor package including the same, which can improve the protection performance of the corner portions of the glass layer of an individualized circuit board and effectively suppress the occurrence of defects and seware phenomena at the corner portions.

[0015] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0016] A circuit board according to an embodiment of the present invention may include: a glass layer; a build-up layer disposed on the glass layer and having a width greater than the width in the horizontal direction of the glass layer; and a resin layer disposed to surround at least a portion of the outer surface of the build-up layer and the outer surface of the glass layer. The resin layer may include a first resin layer portion that overlaps the glass layer in the horizontal direction and a second resin layer portion that overlaps the build-up layer in the horizontal direction. The outer surface of the second resin layer portion may include a flat surface disposed on the periphery portion of at least one of the upper and lower surfaces of the glass layer and a slanted surface disposed on the outer surface of the build-up layer.

[0017] The inclined surface of the second resin layer may have an inclination angle different from the outer surface of the first resin layer with respect to the first surface.

[0018] The inclined surface of the second resin layer may have an inclination angle of 70° or more and 89° or less with respect to the first surface.

[0019] At least one of the outer surface and inner surface of the first resin layer may have a curved structure or a chamfered structure.

[0020] The outer surface of the glass layer has a first non-rectangular structure, and the first resin layer may have a second non-rectangular structure different from the first non-rectangular structure.

[0021] One of the outer surface of the glass layer and the first resin layer may have a curved structure, and the other may have a chamfered structure.

[0022] A circuit board according to an embodiment of the present invention may further include a protective layer disposed on the build-up layer; and a third resin layer disposed to cover the upper or lower surface of the protective layer and the outer surface of the protective layer.

[0023] The surface roughness of the first resin layer may be higher than the surface roughness of at least one of the second resin layer and the third resin layer.

[0024] The first resin layer has a surface roughness of 0.3 μm or more and 1.0 μm or less, and at least one of the second resin layer and the third resin layer may have a surface roughness of 0.003 μm or more and 0.01 μm or less.

[0025] The second resin layer may be extended horizontally from the outer surface of the glass layer toward the center of the upper surface or the center of the lower surface of the glass layer with a width of 500 μm or more and 3000 μm or less.

[0026] The above resin layer may have a coefficient of thermal expansion of 5 ppm / ℃ or higher and 25 ppm / ℃ or lower.

[0027] The above resin layer may have a thickness of 30 μm or more and 400 μm or less.

[0028] The thickness of the resin layer may vary along the perimeter of the glass layer.

[0029] The resin layer may include a first resin layer disposed to surround the perimeter of the glass layer; and a second resin layer disposed on the first resin layer in at least a portion of the perimeter region of the glass layer.

[0030] In addition, according to an embodiment of the present invention, a semiconductor package comprising the circuit board and a semiconductor element disposed on the circuit board is provided.

[0031] According to an embodiment of the present invention, a circuit board and a semiconductor package including the same are provided, which can effectively suppress the occurrence, propagation, or expansion / growth of edge chipping, cracking, and / or substrate separation, etc., on the side portions of the glass layer of a circuit board singulated by a singulation process.

[0032] In addition, according to an embodiment of the present invention, the seware phenomenon, in which the glass layer cracks due to tension stress acting on the side portion of the glass layer of an individualized circuit board, can be effectively suppressed.

[0033] In addition, according to an embodiment of the present invention, the stress caused by the difference in the coefficient of thermal expansion between the glass layer, the resin layer covering the side portion of the glass layer, the metal layer (seed layer) on the glass layer, the plating layer, and / or the insulating layer can be reduced, thereby reducing defects in the glass layer.

[0034] In addition, according to an embodiment of the present invention, the adhesion of a resin layer disposed on the edge portion of the upper and / or lower surface of the glass layer and the glass layer of a individually formed circuit board can be improved to protect the side portion of the glass layer and suppress the occurrence of defects in the side portion.

[0035] In addition, according to an embodiment of the present invention, the protection performance of the corner portion of the glass layer of an individualized circuit board can be improved, and the occurrence of defects and the seware phenomenon at the corner portion can be effectively suppressed.

[0036] The effects that the present invention aims to achieve are not limited to those mentioned above, and other unmentioned effects can be clearly understood by those skilled in the art from the description below.

[0037] FIG. 1a is a cross-sectional view showing the internal structure of a circuit board according to a first embodiment of the present invention.

[0038] Figure 1b is a conceptual diagram showing an individualization process for cutting a large substrate into a number of individual circuit boards.

[0039] FIGS. 1C and FIGS. 1D are perspective views for explaining the process of manufacturing a circuit board according to an embodiment of the present invention.

[0040] FIG. 2a is a cross-sectional view showing the edge region of a circuit board according to an embodiment of the present invention.

[0041] FIG. 2b is a cross-sectional view showing an enlarged view of part 'A' of FIG. 2a.

[0042] FIG. 2c is a conceptual diagram for explaining the operation and effect of a circuit board according to an embodiment of the present invention.

[0043] FIGS. 3 to 8 are cross-sectional views showing the edge portions of a circuit board according to the second to seventh embodiments of the present invention.

[0044] FIG. 9 is a cross-sectional view showing the edge portion of a circuit board according to the eighth embodiment of the present invention.

[0045] FIG. 10 is a cross-sectional view showing a circuit board according to the ninth embodiment of the present invention.

[0046] FIG. 11a is a cross-sectional view showing a circuit board according to the 10th embodiment of the present invention.

[0047] FIG. 11b is a longitudinal section view showing an enlarged view of section 'B' of FIG. 11a.

[0048] FIG. 12 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.

[0049] The terms used in this specification will be briefly explained, and the present invention will be described in detail. The terms used in this specification have been selected to be as generally used as possible, taking into account their functions in the present invention; however, these terms may vary depending on the intent of those skilled in the art to which the present invention pertains, case law, the emergence of new technologies, etc. Additionally, in specific cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in the present invention should be defined not merely by their names, but based on the meanings they possess and the content of the present invention as a whole.

[0050] The following describes embodiments with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. In the drawings, parts unrelated to the explanation have been omitted to clearly explain the present invention, and similar parts throughout the specification are denoted by similar reference numerals.

[0051] In this specification, terms such as "first ~" and "second ~" are used solely for the purpose of distinguishing components from other components and are not limited to meaning the order of arrangement of components. In this specification, the meaning that another component is placed, stacked, or formed "on" a component should be understood to encompass not only a state in which the component and the other component are in direct contact, but also a state in which the component is placed, stacked, or formed with another component interposed therein.

[0052] When a component is referred to as being "connected" to another component, this should be understood to encompass not only cases where the components are directly connected to each other, but also cases where they are indirectly connected through the existence of another component between them. When a component is referred to as being "directly" connected, connected (contacted), or positioned to another component, this should be understood to mean that the components are directly connected, connected (contacted), or positioned without the existence of another component between them.

[0053] FIG. 1a is a cross-sectional view showing the internal structure of a circuit board according to a first embodiment of the present invention. FIG. 1b is a conceptual diagram showing a singulation process in which a large board is cut into a plurality of individual circuit boards. FIG. 1a shows the internal structure of a large board (10) (an unsingulated circuit board), such as a panel board, in a state where the singulation process as shown in FIG. 1b has not been performed, or the internal structure of a circuit board that has been singulated by the singulation process. FIG. 1a shows a cross-section of an internal region, not a periphery region, of a large board or circuit board.

[0054] A circuit board according to an embodiment of the present invention may be an individual circuit board that has been individualized by an individualization process. An individualization process is a process of obtaining a plurality of individual circuit boards by cutting a panel substrate, etc., and can be performed by mechanical cutting using a dicing saw, laser cutting using a UV laser or an IR laser, etc. In the embodiment of FIG. 1b, a large substrate (10) is cut into a plurality of circuit boards (100) along a cutting line (CL) of a lattice pattern structure, but the cutting pattern of the individualization process can be varied in various ways, such as an I-shape, a Z-shape, an L-shape, or an irregular pattern, in addition to the lattice structure.

[0055] The circuit board (100) according to an embodiment of the present invention may be applied to semiconductor packages such as, for example, a Ball Grid Array (BGA) package, a Chip-Scale Package (CSP), a System in Package (SiP), a Multi-Chip Module (MCM) package, a semiconductor chiplet package, a Flip Chip package, and a Package on Package (PoP), but the application field is not limited to the examples listed above. Examples of semiconductor devices mounted on the circuit board (100) include an input / output processor (IOP) chip, an application processor (AP) chip including a central processing unit (CPU) and / or a graphics processing unit (GPU), a digital signal processing unit, a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc., but are not limited thereto.

[0056] A circuit board (100) according to a first embodiment of the present invention may include a glass layer (110), a build-up layer (130, 140) disposed on the upper and / or lower portion of the glass layer (110), and a protective layer (135, 145) disposed on the build-up layer (130, 140). The circuit board (100) may be a component of a semiconductor package that performs the function of supporting and electrically connecting semiconductor devices.

[0057] The glass layer (110) can form a core substrate made of glass material. The glass layer (110) is a plate-shaped insulating layer made of glass material and can serve as a core of the circuit board (100) to provide a function of improving the rigidity of the circuit board (100). The glass layer (110) can have a high dielectric constant and a low surface roughness compared to an organic core layer equipped with glass fibers, thereby improving the rigidity of the circuit board (100) while minimizing signal transmission loss, which can improve the electrical reliability and / or mechanical reliability of the circuit board (100) and the semiconductor package including it.

[0058] In this specification, the glass layer (110) may be referred to by other terms such as 'core layer', 'glass core', 'glass core layer', 'glass core substrate', and 'glass substrate', which serve as the core of the circuit board (100). In order to secure the rigidity required for the circuit board (100), miniaturize the size of the semiconductor product, and prevent excessive signal loss, the glass layer (110) may be provided with a thickness of 200 μm to 1500 μm, or a thickness thinner or thicker than this.

[0059] The glass layer (110) may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., but is not limited thereto. In addition to silicon-based glass compositions, the glass layer (110) may include fluorine glass, phosphate glass, chalcogen glass, etc. Furthermore, the glass layer (110) may include other additives to form a glass having specific physical properties. These additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these elements and other elements.

[0060] The glass layer (110) may have an upper surface (111) and a lower surface (112), and may have a plurality of through holes (113) penetrating between the upper surface (111) and the lower surface (112). Hereinafter, two directions parallel to the upper surface (111) of the glass layer (110) and perpendicular to each other will be described as the first direction (X) and the second direction (Y), respectively, and the vertical direction (or thickness direction) perpendicular to both the first direction (X) and the second direction (Y) will be described as the third direction (Z). The first direction (X) and the second direction (Y) may also be referred to as the horizontal direction, the side direction, or the vertical direction.

[0061] A through-hole (113) of the glass layer (110) may have a through-electrode (151) disposed therein. The through-electrode (151) may electrically connect the upper build-up layer (130) and the lower build-up layer (140), or electrically connect the build-up layers (130, 140) to other circuit boards, interposers, semiconductor devices, main boards, etc. The through-hole (113) of the glass layer (110) and the through-electrode (151) may have a horizontal width of approximately 10 μm to 100 μm for stable signal transmission and semiconductor miniaturization, or may have a width smaller or larger than this.

[0062] In the illustrated example, an upper build-up layer (130) and a lower build-up layer (140) are respectively disposed on the upper surface (111) and lower surface (112) of the glass layer (110), but either of the build-up layers (130 or 140) may be omitted. In this case, a protective layer (135 or 145) is disposed on the upper surface (111) or lower surface (112) of the glass layer (110), and can be electrically connected to another circuit board, interposer, semiconductor device, main board, etc. by solder bumps, etc. through the opening (135a or 145a) of the protective layer (upper protective layer or lower protective layer).

[0063] In this specification, a hole that penetrates the glass layer (110) entirely in the vertical direction (thickness direction) is called a "through hole" (113), and a hole that penetrates from the upper surface (or lower surface) of the insulating layer (134a, 134b, 134c, 144a, 144b, 144c) of the build-up layer (130, 140) to the upper surface (or lower surface) of the circuit layer (131, 132a, 132b, 132c, 141, 142a, 142b, 142c) is called a "blind via hole," and both are described using distinct terms.

[0064] The through hole (113) in the glass layer (110) can be formed by a laser process using, for example, a CO2 laser. For example, the crystallization of the region of the glass layer (110) irradiated with a CO2 laser is altered, and then the region of the glass layer (110) with altered crystallization is removed through wet etching using hydrofluoric acid (HF), etc., thereby forming the through hole (113). The through hole (113) formed by the laser process can be provided in the shape of an hourglass, with the width gradually decreasing from the surface (upper and / or lower surface) of the glass layer (110) toward the center, as shown in FIG. 1a. The through hole (113) in the glass layer (110) may also be formed by a method other than the laser process. For example, the through hole (113) in the glass layer (110) can be formed using a mechanical drill. In this case, the through hole (113) may be formed in a cylindrical shape such that its inner surface (inner wall) is perpendicular to the upper surface (one side) (111) and / or lower surface (other side) (112) of the glass layer (110).

[0065] If the inner surface of the through hole (113) is perpendicular to the upper surface (111) and / or lower surface (112) of the glass layer (110), it may be difficult to densely fill the interior of the through hole (113) with a metallic material during the plating process of filling the through hole (113) with a conductive material. Additionally, if the through hole (113) is formed in the glass layer (110) using a mechanical drill, damage such as the glass layer (110) breaking may occur during the process of using the mechanical drill, and the product yield may be reduced accordingly.

[0066] If a cavity is created in the through electrode (151) filled in the through hole (113), electrical problems such as increased resistance, signal delay, signal attenuation, and open circuit may occur, or mechanical problems such as reduced reliability due to damage caused by external impact and thermal change, increased thermal stress due to bending, reduced heat dissipation performance due to reduced heat conduction, and cracks due to unbalanced thermal expansion may occur.

[0067] Accordingly, when it is necessary to ensure electrical, mechanical and / or thermal performance and reliability in the glass layer (110), as shown in FIG. 1a, it may be preferable for the through hole (113) to be formed in a slanted shape such that its width in the horizontal direction gradually decreases toward the center from the upper surface (111) and / or lower surface (112) of the glass layer (110). Alternatively, if the width of the through hole (113) is large so that there is no problem in filling the metal layer (120) and / or plating layer (150) within the through hole (113), or if it is necessary to sufficiently secure the horizontal width at the center of the through hole (113) with respect to the vertical direction to improve signal transmission performance, a cylindrical through hole (113) may be formed within the glass layer (110).

[0068] The build-up layer (130, 140) may be implemented as a single layer or multiple layers. The build-up layer (130, 140) may also be referred to as a redistribution layer (RDL) (upper RDL layer or lower RDL layer). The build-up layer (130, 140) may be formed with a thickness of at least 100 μm to 400 μm, and as the number of terminals of semiconductor devices placed on the circuit board (100) increases, the wiring becomes more complex and the number of layers increases, so it may be formed with a thickness of 1000 μm or less, or a thickness exceeding this.

[0069] The upper build-up layer (130) may include an upper circuit layer (131), a plurality of circuit layers (132a, 132b, 132c), a plurality of via electrodes (133a, 133b, 133c), and a plurality of insulating layers (134a, 134b, 134c). Each layer of the upper build-up layer (130) may include a circuit layer (or upper circuit layer) (131, 132a, 132b, 132c), an insulating layer (134a, 134b, 134c) covering the circuit layer (131, 132a, 132b, 132c), and via electrodes (133a, 133b, 133c) disposed in blind via holes of the insulating layer (134a, 134b, 134c).

[0070] An upper circuit layer (131) may be disposed on the upper surface (111) of the glass layer (110). The upper circuit layer (131) may be formed through a plating process by an upper metal layer (120a) disposed on the upper surface (111) of the glass layer (110), which is a metal layer (120) serving as a seed layer for plating the plating layer (150). A plurality of insulating layers (134a, 134b, 134c) may be sequentially stacked on the upper surface (111) of the glass layer (110). A plurality of circuit layers (132a, 132b, 132c) may be sequentially disposed in a direction moving upward away from the upper surface (111) of the glass layer (110). The circuit wiring of the upper circuit layer (131) and the circuit layers (132a, 132b, 132c) may be formed from at least one metal material selected from copper (Cu), gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), and zinc (Zn), but is not limited to these materials.

[0071] A plurality of insulating layers (134a, 134b, 134c) may be disposed between the upper circuit layer (131) and the plurality of circuit layers (132a, 132b, 132c) to insulate between the upper circuit layer (131) and the plurality of circuit layers (132a, 132b, 132c). The upper circuit layer (131) and the plurality of circuit layers (132a, 132b, 132c) may function as electrically connected to a semiconductor device disposed on a circuit board (100).

[0072] Via electrodes (133a, 133b, 133c) may be placed in blind via holes of insulating layers (134a, 134b, 134c) to connect between an upper circuit layer (131) and a plurality of circuit layers (132a, 132b, 132c). The blind via holes and via electrodes (133a, 133b, 133c) of the insulating layers (134a, 134b, 134c) may have a horizontal width of approximately 10 μm to 100 μm for stable signal transmission and semiconductor miniaturization, and may have a width smaller or larger than this. The via electrodes (133a, 133b, 133c) may have a slope that narrows in width toward the glass layer (110), that is, toward the upper surface of the insulating layer (134a, 134b, 134c) toward the upper surface of the circuit layer (131) or the circuit layer (132a, 132b, 132c), or may have a constant width in the vertical direction.

[0073] The through electrode (151) inside the through hole (113) can be placed simultaneously in the process of placing the upper circuit layer (131) on the upper surface (111) of the glass layer (110). The through electrode (151) and the upper circuit layer (131) can be placed simultaneously inside the through hole (113) and on the upper surface (111) of the glass layer (110) by a plating layer (150) formed by electroplating using, for example, a metal layer (120) that acts as a seed layer.

[0074] A metal layer (120) may be placed on the upper surface (111) and / or lower surface (112) of a glass layer (110) and on the inner surface (inner wall) of a through hole (113) to form a plating layer (150). The metal layer (120) may be placed by depositing a metal material, such as titanium (Ti), chromium (Cr), or copper (Cu), by means of sputtering, chemical plating, etc. In addition to the metal material mentioned above, other materials such as tungsten (W), molybdenum (Mo), nickel (Ni), nichrome (NiCr), palladium (Pd), platinum (Pt), or silver (Ag) may be used as the metal layer (120).

[0075] Among the materials that can be used for the metal layer (120), copper has poor adhesion to glass and may cause peeling from the glass layer (110). Accordingly, it may be preferable for the metal layer (120) to be formed from a material with excellent adhesion to the glass layer (110), such as titanium (Ti) or chromium (Cr). Alternatively, the metal layer (120) may be provided as a multi-metal layer, such that titanium (Ti) and / or chromium (Cr) is deposited on the glass layer (110), and another material such as copper (Cu) is deposited thereon, or a chemical plating layer may be disposed thereon.

[0076] The metal layer (120) can be formed on the inner wall of the through hole (113) of the glass layer (110) by sputtering, ion beam assisted sputtering, atomic layer deposition (ALD), or other methods of electroless plating (chemical plating). If an insulating material is placed on the inner wall of the through hole (113) of the glass layer (110), a copper material may be placed as a metal layer on the insulating material within the through hole (113).

[0077] An upper circuit layer (131) or a lower circuit layer (141) may be formed by an upper plating layer or a lower plating layer formed by an electrolytic plating process using an upper metal layer (120a) placed on the upper surface (111) of the glass layer (110) or a lower metal layer (120b) placed on the lower surface (112). At the same time, a through electrode (151) may be formed by an inner plating layer formed by an electrolytic plating process using an inner metal layer (120c) within the through hole (113).

[0078] via electrodes (133a, 133b, 133c) can be placed simultaneously in the process of placing circuit layers (132a, 132b, 132c). For example, in the process of placing a first circuit layer (132a) on a first insulating layer (134a), a blind via hole is formed in the first insulating layer (134a) to expose the upper part of the first insulating layer (134a), and then the first circuit layer (132a) is placed on the upper surface of the first insulating layer (134a), and at the same time, a first via electrode (133a) that electrically connects the first circuit layer (132a) and the first upper circuit layer (131) can be placed in the blind via hole of the first insulating layer (134a).

[0079] Likewise, a second to third circuit layer (132b, 132c) may be formed on the upper surface of the second insulating layer (134b, 134c), and at the same time, a second to third via electrode (133b, 133c) may be placed in the blind via hole of the second to third insulating layer (134b, 134c). Each circuit layer (132a, 132b, 132c) may be electrically connected to another upper circuit layer (131) or circuit layer (132a, 132b) placed in a lower layer adjacent to the circuit layer (132a, 132b, 132c) by means of the via electrode (133a, 133b, 133c) placed in the blind via hole.

[0080] An upper circuit layer (131) disposed on the upper surface of the glass layer (110) can be connected to a through electrode (151) disposed in a through hole (113) of the glass layer (110). A first insulating layer (134a), a second insulating layer (134b), a third insulating layer (134c), and an upper protective layer (135) can be sequentially stacked upward from the upper surface (111) of the glass layer (110). The upper protective layer (135) can be disposed on the uppermost insulating layer (134c) among the plurality of insulating layers (134a, 134b, 134c).

[0081] The insulating layers (134a, 134b, 134c) arranged for vertical insulation between the upper circuit layer (131) and the plurality of circuit layers (132a, 132b, 132c) may, for example, be made of a thermosetting insulating material containing inorganic fillers in a resin, or may be arranged by a Semi-Additive Process (SAP) using a build-up film called Ajinomoto Build-up Film (ABF) of Ajinomoto Corporation. However, they are not limited thereto, and the insulating layers (134a, 134b, 134c) may be arranged using a photo-imageable dielectric (PID) or the like to form a fine pattern.

[0082] The upper protective layer (135) protects the upper surface of the upper build-up layer (130), performs an insulating function between the wiring electrodes of the uppermost circuit layer (132c), and can protect the circuit layer (132c) from external moisture or contaminants. When a semiconductor device is placed on a circuit board (100) using a material such as solder, the upper protective layer (135) can prevent short circuits between solders due to low wettability with the solder.

[0083] The upper protective layer (135) may be a photocurable insulating material and, for example, may be a solder resist layer comprising an organic polymer material. The upper protective layer (135) may include, for example, an epoxy acrylate-based resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic-based monomer, but is not limited thereto, and may be formed of a photosolder resist layer, a cover-lay, a polymer material, or other insulating material. The upper protective layer (135) may have an opening (135a) that exposes a circuit layer (132c) disposed on the uppermost insulating layer (134c).

[0084] A lower build-up layer (140) may be disposed on the lower part of the glass layer (110). Similar to the upper build-up layer (140), the lower build-up layer (140) may include a lower circuit layer (141), a plurality of circuit layers (142a, 142b, 142c), a plurality of via electrodes (143a, 143b, 143c), and a plurality of insulating layers (144a, 144b, 144c). The lower circuit layer (141), circuit layers (142a, 142b, 142c), via electrodes (143a, 143b, 143c), and insulating layer (144a, 144b, 144c) of the lower build-up layer (140), and the lower protective layer (145) disposed below the lower build-up layer (140) can be arranged in a symmetrical form with respect to the upper circuit layer (131), circuit layers (132a, 132b, 132c), via electrodes (133a, 133b, 133c), insulating layer (134a, 134b, 134c), and upper protective layer (135) of the upper build-up layer (130) and the glass layer (110), and the above description of the upper build-up layer (130) and upper protective layer (135) is compared with the lower build-up layer (140) and lower The same or similar application can also be applied to the protective layer (145).

[0085] In this specification, the protective layer (135, 145) may be a component distinct from the build-up layer (130, 140) and not a component included in the build-up layer (130, 140). The upper build-up layer (130) and the upper protective layer (135) disposed on the upper build-up layer (130) may be components constituting the upper layer (UL). Similarly, the lower build-up layer (140) and the lower protective layer (145) disposed on the lower build-up layer (140) may be components constituting the lower layer (LL). The structure of the circuit board (100) described above is merely an example for explaining the present invention, and the technical concept of the present invention is not limited to the stacked structure of this example.

[0086] FIGS. 1C and 1D are perspective views illustrating the process of manufacturing a circuit board according to an embodiment of the present invention. FIG. 1C shows an individual circuit board (100) obtained by cutting a large substrate (10) shown in FIG. 1B by an individualization process. In FIGS. 1C and 1D, detailed drawings of openings in the protective layer, insulating layers of the build-up layer, etc., are omitted. For example, unit circuit boards having a size of about 10 mm to 60 mm can be obtained by cutting a panel substrate, such as a circular or square one, having a size of about 300 mm to 800 mm by an individualization process.

[0087] A circuit board (100) according to an embodiment of the present invention may have an inclined surface (130a, 140b) having an angle of inclination of about 70° or more and less than 90° with respect to the upper surface (111) or lower surface (112) of the glass layer (110), wherein the width in the horizontal direction of the glass layer (110), i.e., the width in the first direction (X) and / or the second direction (Y), is greater than the width in the horizontal direction of the build-up layer (130, 140) of the upper layer (UL) and / or lower layer (LL). This is intended to improve the protection performance and anti-seware performance of the edge portion of the circuit board (100) by the resin layer (200), as described below.

[0088] Various methods may be considered for forming inclined surfaces (130a, 140b) on the outer surface of the build-up layer (130, 140). For example, inclined surfaces (130a, 140b) can be formed by removing the side portion of the build-up layer (130, 140) with a laser using a UV laser, CO2 laser, etc., by laser ablation. Alternatively, inclined surfaces (130a, 140b) can be formed on the outer surface of the build-up layer (130, 140) by controlling the exposure amount of the photoresist process, using a heating temperature control method, using a mechanical polishing method, or using a stepwise build-up method. The inclined surfaces (130a, 140b) of the build-up layer (130, 140) may be formed simultaneously with the individualization process, formed in advance before the individualization process, or formed after the individualization process.

[0089] Referring to FIG. 1d, a resin layer (200) may be disposed on the edge portion of a circuit board (110). The resin layer (200) may be disposed on the edge portion of a circuit board (100) by forming a coating layer by coating a resin material along the perimeter of the circuit board (110) in various ways, such as spray coating, dispensing, screen printing, or slot-die coating.

[0090] FIG. 2a is a cross-sectional view showing an edge region of a circuit board according to an embodiment of the present invention. FIG. 2b is a cross-sectional view showing an enlarged view of section 'A' of FIG. 2a. Referring to FIG. 1d, FIG. 2a, and FIG. 2b, a resin layer (200) may be disposed on the edge portion (side portion, and perimeter portion of the upper / lower surface) of a circuit board (100). The resin layer (200) may be disposed to cover the edge portion of the circuit board (100) along the perimeter surface of the circuit board (100).

[0091] The resin layer (200) can be arranged to protect the edge portion of the circuit board (100) to suppress the occurrence of defects such as chipping or cracking, and to suppress the seware shape in which the glass layer (110) splits vertically at the side portion of the glass layer (110) due to tensile stress acting on the circuit board (100). The resin layer (200) may also be referred to as an 'edge coating layer', an 'edge protection layer', etc.

[0092] The resin layer (200) may be arranged to cover the outer surface (side portion) (114) of the glass layer (110), the perimeter portion of the upper surface (111) and / or lower surface (112) of the glass layer (110), and the inclined surface (130a, 140b) of the outer surface of the upper build-up layer (130) and / or lower build-up layer (140). That is, the resin layer (200) may include a first resin layer portion (210) arranged to cover the outer surface of the glass layer (110), and a second resin layer portion (220, 230) arranged to cover the perimeter portion of the glass layer (110) and the outer surface of the build-up layer (130, 140).

[0093] The first resin layer (210) may be arranged to cover the outer surface (114) of the glass layer (110) along the periphery of the glass layer (110). The first resin layer (210) may be arranged across a first region (A1) that overlaps horizontally with the glass layer (110). The first resin layer (210) may be arranged to cover the outer surface (114) connecting the edge portion of the flat upper surface (111) of the glass layer (110) and the edge portion of the flat lower surface (112) of the glass layer (110).

[0094] More specifically, the first resin layer (210) may overlap with the through hole (113) of the glass layer (110) in the first direction (X) and the second direction (Y). The outer surface (114) of the glass layer (110) and / or the first resin layer (210) may be joined perpendicularly to the upper surface (111) or lower surface (112) of the glass layer (110) to form a right-angle structure, or the outer surface may form a non-right-angle structure such as a curved structure or a chamfered structure.

[0095] The second resin layer (220, 230) may include a second upper resin layer (220) disposed above the first resin layer (210) and / or a second lower resin layer (230) disposed below the first resin layer (210). The second resin layer (220, 230) may be disposed across a second region (A2, A3) that overlaps horizontally with the build-up layer (130, 140). That is, the second resin layer (220, 230) may overlap horizontally with one or more insulating layers (134) laminated between the glass layer (110) and the uppermost protective layer (e.g., solder resist layer) on the glass layer (110). The second resin layer (220, 230) may include a flat portion (221, 231) disposed in the edge perimeter area of ​​the glass layer (110) and an inclined portion (222, 232) disposed on the outer surface of the build-up layer (130, 140).

[0096] The flat portion (221, 231) may be arranged to cover the periphery portion of the upper surface (111) and / or lower surface (112) of the glass layer (110) along the periphery direction of the glass layer (110). The outer periphery portion of the flat portion (221, 231) may be connected to the upper or lower portion of the first resin layer (210). The upper surface of the flat portion (221, 231) may have a flat surface. The upper surface of the flat portion (221, 231) may be a flat surface parallel to the upper surface (111) and / or lower surface (112) of the glass layer (110).

[0097] The flat portion (221, 231) may be a portion that does not overlap horizontally with the glass layer (110) but overlaps horizontally with the lower portion of the build-up layer (130, 140). The flat portion (221, 231) may extend from the top and / or bottom of the first resin layer (210) toward the center of the upper surface (111) and / or the center of the lower surface (112) of the glass layer (110). The flat portion (221, 231) may be positioned to have a width (L11) within the range of about 0.5 mm to 2.0 mm from the outer surface (114) of the glass layer (110). In order to ensure that the width (L11) of the flat portion (221, 231) is secured at an appropriate level, the build-up layer (130, 140) may be spaced apart from the outer surface (114) of the glass layer (110) by a distance (L3) within the range of approximately 0.5 mm to 2.5 mm. That is, the glass layer (110) may protrude from the bottom portion of the build-up layer (130, 140) by a distance (L3) within the range of approximately 0.5 mm to 2.5 mm.

[0098] The second resin layer (220, 230) may be provided with an inclined surface having an angle of inclination (θ1, θ2) equal to the outer surface of the build-up layer (130, 140) along the circumferential direction of the build-up layer (130, 140) on the outer surface of the inclined portion (222, 232). The outer surface of the inclined portion (222, 232) may be positioned at an angle of inclination (θ1, θ2) of approximately 70° or more and less than 90° with respect to the upper surface (111) or lower surface (112) of the glass layer (110). Accordingly, the horizontal width of the second resin layer (220, 230), which has the shape of a roughly truncated square pyramid, may be reduced in the direction away from the glass layer (110).

[0099] The third resin layer (240, 250) may be positioned to extend from the top or bottom of the second resin layer (220, 230) to cover the outer surface of the protective layer (135, 145) and the perimeter of the upper / lower surface (135b, 145b). The third resin layer (240, 250) may be positioned in a third region (A4, A5) that partially overlaps the protective layer (135, 145) without overlapping horizontally with the glass layer (110) and the build-up layer (130, 140). The third resin layer (240, 250) may include a side resin layer (241, 251) arranged to cover the outer surface of the protective layer (135, 145), and a flat resin layer (242, 252) arranged to cover the upper / lower surface (135b, 145b) of the protective layer (135, 145).

[0100] The side resin layers (241, 251) may be arranged in a shape such as a square ring along the outer surface of the protective layer (135, 145) to wrap the protective layer (135, 145). The flat resin layers (242, 252) may extend from the top of the side resin layers (241, 251) toward the center of the upper surface or the center of the lower surface of the protective layer (135, 145). An opening is formed in the shape such as a square at the center of the flat resin layers (242, 252), and a semiconductor device, etc., may be mounted by means of solder bumps, etc., through connection pads exposed through the opening of the flat resin layers (242, 252).

[0101] In order to effectively relieve tensile stress acting in the vertical direction on the edge portion of the circuit board (100), the flat resin layer (242, 252) may be extended from the outer surface of the protective layer (135, 145) by a width (L12) greater than 0 mm and less than or equal to 1.5 mm, and more preferably may be protruded by a width (L12) within the range of about 0.5 mm to 1 mm. If the width (L12) of the flat resin layer (242, 252) is 1.5 mm or less, more preferably 1 mm or less, it is possible to prevent the effective design area of ​​the circuit terminal pattern of the protective layer (135, 145) from being excessively reduced.

[0102] As described above, the resin layer (200) can be arranged to cover not only the outer surface (114) of the glass layer (110) along the perimeter of the circuit board (100), but also the outer portion of the glass layer (110) (upper perimeter portion and / or lower perimeter portion) that contacts the upper and / or lower portion of the outer surface (114) of the glass layer (110), the outer surface (inclined surface) of the upper build-up layer (130) and / or lower build-up layer (140), and the outer surface and upper / lower surface (135b, 145b) of the protective layer (135, 145).

[0103] In order to effectively suppress the seware phenomenon of the glass layer (110), the flat portion (221, 231) of the second resin layer (220, 230) has a thickness (T) in the vertical direction. 21 , T 31 It may be extended from the outer surface (114) of the glass layer (110) toward the center of the upper surface and / or the center of the lower surface so as to have a width (L3) greater than that. Accordingly, the flat portions (221, 231) disposed on the periphery of the upper / lower surfaces (111, 112) of the glass layer (110) may have ring-shaped plate structures facing each other.

[0104] FIG. 2c is a conceptual diagram illustrating the operation and effects of a circuit board according to an embodiment of the present invention. The glass layer (110) may have a relatively low coefficient of thermal expansion (CTE) of approximately 3 ppm / °C to 8 ppm / °C, depending on the type of glass material. In contrast, the metal layer serving as a seed layer for electroplating or the upper circuit layer placed for electroplating may have a relatively high CTE of approximately 8 ppm / °C to 20 ppm / °C. The insulating layer of the build-up layer (130, 140) placed on the glass layer (110) may have a higher CTE of approximately 15 ppm / °C to 30 ppm / °C.

[0105] During the manufacturing process, packaging process, and / or transfer process of the circuit board, compressive stress (CP) and tensile stress (TS) may be induced in the glass layer (110) due to a difference in the coefficient of thermal expansion between the glass layer (110) and the upper / lower metal layer or upper / lower circuit layer of the upper / lower build-up layer (130, 140) and / or a difference in the coefficient of thermal expansion between the glass layer (110) and the insulating layer of the upper / lower build-up layer (130, 140).

[0106] That is, as the upper / lower build-up layers (130, 140) are placed on the upper surface (111) and lower surface (112) of the glass layer (110), compressive stress (CS) acts from the upper / lower perimeter region of the glass layer (110) toward the center region in the horizontal direction on the upper surface (111) and lower surface (112) of the glass layer (110), and tensile stress (TS) can act in the third direction (Z) from the upper / lower perimeter region of the glass layer (110) toward the upper / lower perimeter region on the outer surface (114) of the glass layer (110). The resin layer (200) can be arranged in a structure suitable for effectively suppressing deformation of the glass layer (110) caused by the compressive stress (CS) and tensile stress (TS) acting on the upper / lower surface (111, 112) and outer surface (114) of the glass layer (110).

[0107] That is, the second resin layer portion (220, 230) and the third resin layer portion (240, 250) of the resin layer (200) are extended with a long width (L1, L2) toward the center of the glass layer (110), and can have a wide contact area extending to the upper / lower perimeter area of ​​the glass layer (110), the outer surface of the build-up layer (130, 140), and the upper / lower surface of the protective layer (135, 145). In this way, the resin layer (200) can effectively suppress deformation caused by stress acting on the upper / lower surface (111, 112) and outer surface (114) of the glass layer (110) by resisting compressive stress on the upper / lower surface (111, 112) of the glass layer (110) through the expanded contact area with the glass layer (110), the build-up layer (130, 140), and the protective layer (135, 145).

[0108] In addition, the resin layer (200) can function to suppress tensile stress (CS) acting on the outer surface (114) of the glass layer (110). Since the resin layer (200) has a cross-sectional shape in the form of a hanger with approximately multiple steps along the entire perimeter area of ​​the glass layer (110), it can apply an elastic restoring force that suppresses deformation in the vertical direction of the glass layer (110) by resisting tensile stress (TS) when it occurs in the vertical direction on the outer surface (114) of the glass layer (110), and / or the second resin layer portion (220, 230) and / or the third resin layer portion (240, 250) overlap with the glass layer (110) in the vertical direction.

[0109] Although a bending moment is applied to cause the second resin layer (220, 230) and / or the third resin layer (240, 250) to spread apart vertically due to the tensile stress (TS) acting on the outer surface (114) of the glass layer (110), due to factors such as resistance to the tensile force acting on the resin layer (200) by the bending moment, bending stiffness of the resin layer (200), resistance due to shear stiffness at the connection between the first resin layer (210), the second resin layer (220, 230), and the third resin layer (240, 250), and fixed boundary conditions of the outer region of the resin layer (200), cracking of the glass layer (110) due to the tensile stress (TS) acting on the outer surface (114) of the glass layer (110) Deformation or defects such as those of the back can be suppressed by a resin layer (200) covering the edge portion of the circuit board (100).

[0110] In addition, regarding the deformation in which the glass layer (110) splits in the vertical direction due to the bending moment caused by the tensile stress (TS) of the glass layer (110), the inclined portion (222, 232) of the second resin layer (220, 230) applies a restraining force (F1, F2) that resists the deformation of the glass layer (110) to the inclined surface (130a, 140b) of the build-up layer (130, 140), thereby relieving the tensile stress (TS) of the glass layer (110), so the deformation of the glass layer (110) can be effectively suppressed by the inclined portion (222, 232) of the second resin layer (220, 230).

[0111] As described above, according to an embodiment of the present invention, the edge portions of the glass layer (110), the build-up layer (130, 140), and the protective layer (135, 145) can be structurally and stably supported within a ring-shaped multi-stage groove structure of a resin layer (200) having a deep horizontal depth in all directions along the circumference of the glass layer (110), and by protecting the edge portions of the glass layer (110) by the resin layer (200), the seware phenomenon in which the glass layer (110) splits up and down on the outer surface (114) can be effectively prevented. For example, if the breaking load of the glass layer (110) that is not coated with the resin layer (200) is about 20 to 40 N, when the resin layer (200) is coated on the edge portion of the glass layer (110), the breaking load of the circuit board (100) can be increased to 30 to 60 N or more.

[0112] In addition, according to an embodiment of the present invention, the outer surface (114) of the glass layer (110) is protected by the first resin layer (210), and the upper / lower perimeter area of ​​the glass layer (110) and the outer surface of the build-up layer (130, 140) are protected by the second resin layer (220, 230), so that the edge area of ​​the glass layer (110) and the build-up layer (130, 140) can be protected from external impact over a wide area, and defects such as cracks or chipping can be effectively suppressed in the edge area of ​​the glass layer (110).

[0113] In addition, a resin layer (200) can be formed by forming a thin coating layer with a thickness of less than several hundred micrometers on the outer surface (114) of the glass layer (110), the upper / lower surface (111, 112), the outer surface of the build-up layer (130, 140), and the outer surface and upper / lower surface of the protective layer (135, 145), thereby reducing the material cost required to form the resin layer (200) on the perimeter of the glass layer (110) and increasing the efficiency of processes such as coating the resin layer (200).

[0114] In order to achieve the performance and functional effects of the present invention as described above, the outer surface of the inclined portion (222, 232) of the second resin layer (220, 230) may include an inclined surface having an angle of inclination different from that of the outer surface of the first resin layer (210) with respect to the upper / lower surface (first surface) (111, 112) of the glass layer (110). As previously explained, in order to effectively relieve stress acting on the glass layer (110), it may be preferable for the inclined portion (222, 232) to be arranged to have an angle of inclination of about 70°-89° with respect to the upper / lower surface (111, 112) of the glass layer (110), and more preferably, to have an angle of inclination of about 75°-85°. If the angle of inclination of the inclined portion (222, 232) is reduced to less than 70°, the area of ​​the effective circuit wiring layer in the upper region of the build-up layer (130, 140) may be reduced. Conversely, as the angle of inclination of the inclined portion (222, 232) approaches 90°, the stress relief effect and seware suppression performance by the inclined portion (222, 232) may be reduced.

[0115] Additionally, it may be preferable for the second resin layer (220, 230) and the third resin layer (240, 250) to be arranged to have a width (L1, L2) within the range of about 500 μm to 3000 μm in a direction from the outer surface (114) of the glass layer (110) toward the center of the upper surface of the glass layer (110). If the horizontal width (L1, L2) of the second resin layer (220, 230) and the third resin layer (240, 250) is reduced to less than 500 μm, it is difficult to secure a sufficient contact area between the resin layer (200) and the glass layer (110), and it becomes difficult to sufficiently suppress the tensile stress (TS) applied to the outer surface (114) of the glass layer (110) by the resin layer (200), and the risk of seware occurring in the glass layer (110) may increase.

[0116] The reason the width (L1, L2) in the horizontal direction of the second resin layer (220, 230) and the third resin layer (240, 250) is limited to 3000 μm or less is that even with a width of 3 mm or less (or groove depth of the resin layer), sufficient restraining force to prevent seware on the glass layer (110) can be applied without increasing unnecessary material costs or decreasing process efficiency, and if the resin layer (200) is arranged with a width exceeding this, the designable effective area of ​​the terminals and circuit layers of the build-up layer (130, 140) may be reduced.

[0117] The glass layer (110) applied to the semiconductor package may have a thickness of approximately 400 μm to 1500 μm in the vertical direction. It may be preferable for the resin layer (200) to be arranged to have a width (L1, L2) of approximately 1 / 4 to 2 times the thickness of the glass layer (110) based on the thickness of the glass layer (110) in the vertical direction. More preferably, the resin layer (200) may have a width (L1, L2) of approximately 1 / 3 to 1 time the thickness of the glass layer (110).

[0118] The thickness (T1, T) of the resin layer (200) 21 , T 22 , T 31 , T 32T1, T4, T5) is another factor that influences securing appropriate protective performance and sufficient resistance to compressive stress and / or tensile stress of the glass layer (110). To achieve sufficient effect for preventing seware of the glass layer (110), it may be desirable for the resin layer (200) to have a thickness within the range of 30 μm to 400 μm. A more desirable thickness of the resin layer (200) is 40 μm to 300 μm, and even more preferably, it may have a thickness of 50 μm to 200 μm. It may be desirable for the thickness (T1, T2, T3) of the resin layer (200) to be designed to have an appropriate range based on the thickness of the glass layer (110). The resin layer (200) may have a thickness of about 1 / 40 to 1 / 10 times based on the thickness of the glass layer (110).

[0119] As the thickness of the resin layer (200) decreases, the seware suppression effect by the resin layer (200) may decrease; therefore, as described above, it is necessary to ensure the thickness of the resin layer (200) is at or above an appropriate level. Conversely, as the thickness of the resin layer (200) increases, the material cost increases proportionally and the process time for coating the resin layer (200) also increases; therefore, it may be desirable to limit the thickness of the resin layer (200) as described above.

[0120] The second resin layer (220, 230) may partially overlap with the first resin layer (210) in the vertical direction. The second resin layer (220, 230) may overlap with the first resin layer (210) in the vertical direction at the outer perimeter. The second resin layer (220, 230) may not overlap with the first resin layer (210) in the vertical direction at the inner perimeter, but may overlap with the edge portion of the glass layer (110) in the vertical direction. In order to secure a sufficient contact area with the upper / lower surfaces (111, 112) of the glass layer (110), the inner perimeter portion that overlaps with the glass layer (110) in the vertical direction may be extended to a width of approximately 5 to 10 times the width of the outer perimeter portion that does not overlap with the glass layer (110).

[0121] The resin layer (200) may preferably be formed from a resin material having a thermal expansion coefficient difference that is as small as possible compared to the glass layer (110) or the insulation layer of the build-up insulation layer (130, 140), etc., so as to relieve stress caused by the difference in thermal expansion at the interface of heterogeneous materials during the manufacturing and transfer process of the circuit board (100). Considering the thermal expansion coefficient of the glass layer (110) (about 3-8 ppm / ℃) and the thermal expansion coefficient of the insulation layer (134, 144) (about 15-30 ppm / ℃), the resin layer (200) may preferably be formed from a resin material having a thermal expansion coefficient within the range of about 5-25 ppm / ℃, but a material having a thermal expansion coefficient smaller or larger than this may also be applied.

[0122] After the resin layer (200) is placed on the glass layer (110), the build-up layer (130, 140), and the protective layer (135, 145), it may be desirable for the resin layer (200) to have chemical resistance and corrosion resistance to materials for substrate processing so as to protect the edges of the glass layer (110), the build-up layer (130, 140), and the protective layer (135, 145) throughout the subsequent substrate processing and packaging processes. For example, it may be desirable for the resin layer (200) to be a material that has corrosion resistance to chemicals such as sulfuric acid, NaOH, TMAH (Tetramethylammonium Hydroxide), etc. Among the resin materials that can be applied as the resin layer (200), examples of materials having the aforementioned coefficient of thermal expansion and corrosion resistance include PDMS, urethane acrylate, epoxy, etc., but the resin material of the resin layer (200) is not limited to the listed materials.

[0123] The resin layer (200) may have an elastic modulus within the range of approximately 1 MPa to 5 GPa depending on the type of resin material. By placing a resin layer (200) having appropriate elasticity, the impact applied to the glass layer (110) or the build-up layer (130, 140), etc., by the resin layer (200) can be reduced, thereby properly protecting the circuit board (100) without causing damage to the circuit board (100). For example, using PDMS can improve shock absorption performance through the flexible resin layer (200). As another example, using epoxy can provide high resistance to stress on the glass layer (110) through the resin layer (200) having relatively high rigidity. Additionally, the resin layer (200) containing urethane acrylate can protect the glass layer (110) while maintaining a proper balance of flexibility and rigidity, and can prevent breakage and cracking of the glass layer (110). In addition to the mentioned resin material, the resin layer (200) may also be made of materials such as acrylic, silicone, and fluoropolymer.

[0124] The surface roughness of the resin layer (200) placed at the edge of the circuit board (100) can be considered as another important factor that may affect the adhesion performance and stress / sewage relief effect with the glass layer (110), the build-up layer (130, 140), and / or the protective layer (135, 145). Increasing the surface roughness of the resin layer (200) can increase the adhesion strength between the resin layer (200) and the circuit board (100), and can be advantageous for suppressing crack propagation by dispersing stress through fine irregularities. However, if the surface roughness of the resin layer (200) is excessively increased, cracks may be induced due to localized stress concentration, and pores or fine defects may be created within the resin layer (200), which may degrade the protective performance and stress relief performance.

[0125] If the surface roughness of the resin layer (200) is reduced within an appropriate range, a uniform and continuous layer can be formed, which can reduce the number of crack occurrence points. Additionally, it can facilitate the control of the resin liquid flow and film thickness for the placement of the resin layer (200). However, if the surface roughness of the resin layer (200) is excessively low, the mechanical bonding strength of the resin layer (200) is reduced and the stress transfer path is simplified, which may lead to a problem where crack propagation becomes easier.

[0126] In terms of improving the adhesion of the resin layer (200), relieving stress, and preventing cracks and smudging, it is necessary to arrange the resin layer (200) to have an appropriate level of fine roughness. Accordingly, it may be desirable for the resin layer (200) to have a surface roughness in the range of 0.003 μm to 1.0 μm. More preferably, the first resin layer (210) may have a surface roughness in the range of 0.3 μm to 1.0 μm, and the second resin layer (220, 230) and / or the third resin layer (240, 250) may have a surface roughness in the range of 0.003 μm to 0.01 μm. In this specification, surface roughness (surface roughness) may follow the definition and measurement method of the ISO 21920 international standard.

[0127] If the surface roughness of the first resin layer (210) is made higher than that of the second resin layer (220, 230) and / or the third resin layer (240, 250), stress can be dispersed by fine irregularities on the outer surface (114) of the glass layer (110) where external impact, thermal stress, and mechanical stress are concentrated, thereby reducing the starting point of cracks and lowering the crack propagation speed. In addition, the adhesion of the resin layer (200) is improved on the outer surface of the glass layer (110), where the resin material is prone to lifting, and peeling of the first resin layer (210) can be suppressed. At the same time, if the surface roughness of the second resin layer (220, 230) and / or the third resin layer (240, 250) is made lower, the diffusion of moisture or foreign substances in the surrounding area close to the build-up layer (130, 140) can be suppressed, thereby improving electrical reliability and preventing insulation breakdown. In addition, it is possible to prevent the film thickness from becoming uneven during spray coating and to uniformly control the thickness of the resin layer, thereby securing the required protection and anti-sewer performance.

[0128] The surface roughness of the resin layer (200) can be controlled overall or by region by controlling the viscosity of the resin liquid to be coated, controlling the temperature and / or controlling the curing speed by ultraviolet rays, etc. (e.g., forming surface irregularities by rapid curing or forming a smooth surface by slow curing), controlling the spraying / application method of the resin liquid (forming fine particles by a spray method or forming a smooth surface by a dispenser method, etc.), controlling the binder or additive of the resin liquid, and physical / chemical treatment (e.g., inducing fine roughness by plasma treatment, forming uniform irregularities by sandblasting / fine polishing, or forming a precise microstructure by laser microtexturing, etc.).

[0129] FIGS. 3 to 8 are cross-sectional views showing the edge portions of a circuit board according to the second to seventh embodiments of the present invention. In describing the following embodiments, descriptions of components that overlap with previously described embodiments will be omitted as much as possible, and descriptions will focus on the parts that differ. The embodiments illustrated in FIGS. 8 to 8 differ from the previously described embodiments in that the outer surface of the glass layer (110) and / or the resin layer (200) has a non-rectangular structure. For example, at least one of the outer surface of the glass layer (110) and the outer surface of the first resin layer (210) may have a curved surface structure or a chamfered edge structure, rather than a right-angle structure.

[0130] In the present specification, the ‘rectangular structure’ of the glass layer (110) or resin layer (200) refers to a structure in the form of a rectangle in which the corner angle between the upper surface and the outer surface of the edge portion and the corner angle between the outer surface and the lower surface form a 90° angle, and the ‘non-rectangular structure’ may refer to a structure in which the corner angle between the upper surface and the outer surface of the glass layer (110) or resin layer (200) or the corner angle between the lower surface and the outer surface exceeds 90°, or in which at least a portion of the upper / lower surface and / or outer surface forms a curved surface rather than a flat surface. Various methods may be considered for processing the glass layer (110) into a curved surface or a chamfered structure, for example, grinding using a CNC grinder, grinding wheel, etc., laser machining using a CO2 laser or UV laser, chemical etching using photoresist, polishing process, etc. may be used.

[0131] For example, either the outer surface (114) of the glass layer (110) and the outer surface of the resin layer (200) may have a right-angle structure, while the other may have a curved structure or a chamfered structure (see embodiments in FIG. 3 and FIG. 4). As another example, both the outer surface of the glass layer (110) and the outer surface of the resin layer (200) may have a curved structure or a chamfered structure (see embodiments in FIG. 5 and FIG. 6). As yet another example, the outer surface of the glass layer (110) may have a first non-right-angle structure, and the resin layer (200) may have a second non-right-angle structure different from the first non-right-angle structure of the glass layer (110). For example, either the outer surface (114) of the glass layer (110) and the outer surface of the resin layer (200) may have a curved structure, while the other may have a chamfered structure.

[0132] According to the embodiment of FIG. 5, the thickness (T) increased in the central region in the vertical direction of the glass layer (110) by the curved resin layer (200) is 13 Having ), reduced thickness (T in the upper / lower regions 11 , T 12 It can have ). Therefore, an increased thickness (T) in the central region of the resin layer (200). 13 The protective performance of the outer surface (114) of the glass layer (110) can be improved by ).

[0133] In addition, the outer surface of the resin layer (200) protrudes in a curved shape along the vertical direction, so that when an impact is applied, the curved surface deforms to absorb energy, and the load is distributed along the outer surface of the curved resin layer (200), thereby alleviating stress concentration. Furthermore, the outer surface of the resin layer (200) is smoothly connected without abrupt step differences, so the possibility of cracks occurring is low, and thermal stress caused by temperature changes is distributed, thereby preventing delamination between the resin layer (200) and the glass layer (110).

[0134] In the case of the embodiment of FIG. 6, the resin layer (200) has an increased thickness (T) in the central region in the vertical direction of the glass layer (110) by the first resin layer portion (210) of the chamfered structure (211, 212, 213). 16 Having ), reduced thickness (T in the upper / lower regions 14 , T 15 It can have ). Therefore, an increased thickness (T) in the central region of the resin layer (200). 16 The protective performance of the outer surface (114) of the glass layer (110) can be increased by means of the chamfered structure (211, 212, 213) of the resin layer (200), which absorbs energy from impact and distributes the load along the chamfered structure (211, 212, 213) of the resin layer (200), thereby relieving stress concentration. Additionally, the outer surface of the first resin layer (210) is smoothly connected at an angle of approximately 120° to approximately 150° without a sharp step of 90° on the outer surface of the resin layer (200), thereby reducing the risk of cracking and dispersing thermal stress caused by temperature changes, which can prevent delamination between the resin layer (200) and the glass layer (110).

[0135] According to the embodiments of FIGS. 3 and 4, a functional effect similar to that of FIGS. 5 and 6 can be provided. In addition, since the glass layer (110) and the first resin layer (210) are formed with the same non-rectangular structure, the thickness (T1) of the first resin layer (210) changes gradually without a section where the thickness (T1) of the first resin layer (210) changes abruptly along the perimeter of the glass layer (110) and the resin layer (200), thereby preventing stress and thermal expansion imbalance caused by abrupt changes in the thickness of the resin layer (200), strengthening the adhesion between the resin layer (200) and the glass layer (110), and effectively preventing delamination between the glass layer (110) and the resin layer (200).

[0136] According to the embodiments of FIGS. 7 and 8, a functional effect similar to that of FIGS. 5 and 6 can be provided, and the protective performance can be improved by the heterogeneous bonding structure of the glass layer (110) and the resin layer (200). For example, in the case of the embodiment of FIG. 7, the risk of cracking in the corner portion can be reduced due to the rounded curved structure of the outer surface (114) of the glass layer (110), and stress can be dispersed by the first resin layer portion (210) having an outer surface with a chamfered structure (211, 212, 213) to prevent cracking or breakage.

[0137] In the embodiment of FIG. 8, the outer surface of the glass layer (110) may include upper / lower chamfered surfaces (114a, 114b) that are inclined with respect to the upper surface (111) and lower surface (112) of the glass layer (110) and have a chamfered structure, and a vertical surface (114c) positioned vertically with respect to the upper surface (111) or lower surface (112) of the glass layer (110) between the upper / lower chamfered surfaces (114a, 114b). According to the embodiment of FIG. 8, the adhesion between the first resin layer (210) and the glass layer (110) can be strengthened by the chamfered structure (114a, 114b, 114c) of the glass layer (110) and the stress of the glass layer (110) and / or the resin layer (200) can be effectively dispersed, and the load can be smoothly distributed by the first resin layer (210) having an outer surface of the curved structure (210a) to improve the protective performance.

[0138] FIG. 9 is a cross-sectional view showing an edge portion of a circuit board according to the eighth embodiment of the present invention. In the circuit board according to the eighth embodiment of the present invention, the inclined portion (222) of the second resin layer portion (220) has a thickness (T) in the first direction (X). 23 , T 24 It differs from the previously described embodiments in that the thickness increases as it moves downward toward the glass layer (110). For example, the upper portion of the inclined portion (222) of the second resin layer (220) has a thickness (T) within the range of approximately 50 μm to 100 μm. 23While having ), the lower part has a thickness greater than 100 µm and less than or equal to 400 µm (T 24 Can have ).

[0139] When the insulating layers of the build-up layer (130) are made of the same insulating material, the stress caused by the difference in thermal expansion coefficients between the insulating layers within the build-up layer (130) is relatively low, and greater stress may occur at the interface between the build-up layer (130) and the glass layer (110). Accordingly, by increasing the thickness of the second resin layer (222) at the interface between the build-up layer (130) and the glass layer (110), defects such as chipping and cracking caused by stress due to the difference in thermal expansion coefficients between the layers of the circuit board (100) can be effectively prevented, and the seware phenomenon of the glass layer (110) can be effectively suppressed.

[0140] Meanwhile, if the lower protective layer (145) is disposed without a lower build-up layer being provided at the bottom of the glass layer (110), the inclined portion of the second resin layer covering the outer surface of the lower build-up layer may be omitted. In this case, the third lower resin layer (250) may include a flat portion (253) covering the lower surface of the glass layer (110), a side resin layer (251) covering the inclined outer surface of the lower protective layer (145), and a flat resin layer (252) disposed to cover the flat lower surface of the lower protective layer (145).

[0141] The second lower resin layer (230) and the third lower resin layer (250) of the lower resin layer (230, 250) may be arranged with the same thickness as the second upper resin layer (220) and the third upper resin layer (240) of the upper resin layer (220, 240), but may also be arranged with a thicker thickness. If the lower resin layer (230, 250) is made thicker than the upper resin layer (220, 240), the glass layer (110) can be more effectively protected from impact caused by contact with a supporting member, etc., that supports the lower side of the circuit board (100), and the increased self-weight of the lower resin layer (230, 250) increases the force with which the upper resin layer (220, 240) presses downward on the upper surface perimeter area of ​​the glass layer (110), thereby more effectively preventing bending deformation of the smile-shaped (concave) glass layer (110) or deformation of the edge portion upward.

[0142] FIG. 10 is a cross-sectional view showing a circuit board according to a ninth embodiment of the present invention. Referring to FIG. 10, the circuit board according to the ninth embodiment of the present invention has a thickness (T) of a resin layer (200) along the circumferential direction of a glass layer (110). 17 , T 18 ) can change. That is, the first resin layer portion (210b) disposed in the first periphery region of the glass layer (110) has a relatively thin first thickness (T 17 Having ), the second resin layer portion (210c) disposed in the second periphery region of the glass layer (110) has a first thickness (T 17 The second thickness (T) thicker than ) 18It may have a thickness such as chipping and cracking that may occur intensively at the corner portions of the glass layer (110), and a relatively thin thickness in the area between the corner portions of the glass layer (110). According to the embodiment of FIG. 10, defects such as chipping and cracking that may occur intensively at the corner portions of the glass layer (110), and the seware phenomenon that is prone to occur due to stress concentration at the corner portions of the glass layer (110) can be effectively prevented.

[0143] FIG. 11a is a cross-sectional view showing a circuit board according to the 10th embodiment of the present invention. FIG. 11b is a longitudinal section showing an enlarged view of section 'B' of FIG. 11a. Referring to FIG. 11a and FIG. 11b, the circuit board (100) according to the 10th embodiment of the present invention may include a first resin layer (200d; 210d, 220d, 230d, 240d, 250d) disposed over the entire area along the periphery direction of a glass layer (110), and a second resin layer (200e; 210e, 220e, 230e, 240e, 250e) disposed only on a part of the first resin layer (200d). Accordingly, the second thickness (T) of the resin layer (200) in the second area where the second resin layer (200e) is disposed 19 ) is the first thickness (T) of the resin layer (200) in the first region where the second resin layer (200e) is not disposed. 17 It can be larger than )

[0144] For example, the second resin layer (200e) may be disposed on the first resin layer (200d) at the corner portion of the glass layer (110). The second resin layer (200e) may include a second side resin layer (210e) disposed on the first side resin layer (210d), a second upper / lower resin layer (220e, 230e) disposed on the first upper / lower resin layer (220d, 230d), and a second flat resin layer (240e, 250e) disposed on the first flat resin layer (240d, 250d). Accordingly, the resin layer (200) may have a thick thickness at the corner portion of the glass layer (110) and a thin thickness between the corner portions of the glass layer (110). The second resin layer (200e) may be made of a second resin material having greater rigidity (hardness) than the first resin material of the first resin layer (200d). According to the embodiments of FIG. 11a and FIG. 11b, defects such as chipping and cracks that may occur intensively in the corner portions of the glass layer (110) and the seware phenomenon that is prone to occur due to stress concentration in the corner portions of the glass layer (110) can be effectively prevented.

[0145] A circuit board according to embodiments of the present invention can be manufactured by cutting a panel board, etc., through an individualization process. After subsequent substrate processing is performed with a resin layer (200) disposed on the edge portion of the circuit board, a process of mounting a semiconductor device on the circuit board is performed to manufacture a semiconductor package. According to an embodiment of the present invention, the growth of defects such as chipping and cracks caused by stress applied to the cut surface during the cutting process of the panel board in the individualization process can be suppressed by the resin layer (200) for protecting the individual circuit board, and the seware phenomenon of the glass layer (110) can be effectively prevented.

[0146] FIG. 12 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. A circuit board (100) according to an embodiment of the present invention may form a semiconductor package (20) together with one or more semiconductor elements (300). The semiconductor package (20) may be an electronic component that constitutes an electronic element. The electronic element may be, for example, an electronic terminal of a vehicle, a smartphone, a tablet, a laptop, a high-performance server, a smart watch, a personal digital assistant (PDA), an Internet of Things (IOT) terminal, a digital camera, etc., but is not limited thereto, and may be provided as any other electronic device having one or more semiconductor elements (300) and one or more circuit boards (100).

[0147] The semiconductor device (300) may be an integrated circuit (IC) semiconductor chip (semiconductor die) in which various active and / or passive devices are integrated within a single chip. The semiconductor device (300) may be provided as a sub-semiconductor package that constitutes a higher-level semiconductor package in which a plurality of sub-semiconductor packages are combined. The semiconductor package (20) may be mounted on a circuit board (100) such as a main board (400) of an electronic device. The main board (400) may be electrically connected to various electronic components. The semiconductor package (20) may further include one or more interposers, in which case the circuit board (100) may not be directly connected to the semiconductor device but may be connected to the semiconductor device via one or more interposers, or may be directly connected to some of the semiconductor devices and connected to others via interposers.

[0148] A circuit board (100) according to an embodiment of the present invention may be a package board constituting a semiconductor package (20). The circuit board (100) may also be an interposer board that performs the function of an interposer coupled to another circuit board. The circuit board (100) may be provided as a bridge board including a redistribution layer. The circuit board (100) may have a space in which one or more semiconductor devices and / or one or more interposers (not shown) can be mounted. The circuit board (100) may be coupled to the semiconductor devices and / or interposers by bumps (180, 190) provided on a first surface (e.g., top surface) and / or a second surface (e.g., bottom surface).

[0149] In one embodiment, the circuit board (100) may be coupled to the terminals (310) of the semiconductor device (300) by means of bumps (180) provided on the upper surface, and may be coupled to the terminals (410) of the main board (400) of the electronic device by means of bumps (190) through electrode pads provided on the lower surface. When the circuit board (100) performs the function of an interposer, the circuit board (100) may be referred to as a first circuit board, and the package board or another interposer board on which the circuit board (100) is mounted may be referred to as a second circuit board.

[0150] The foregoing description is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented by dividing it into multiple elements, and likewise, components described as multiple elements may also be implemented as a single unit.

[0151] The components of the various embodiments may be combined and implemented as long as they do not conflict with one another. Accordingly, it should be understood that new embodiments combining the various embodiments described above are also included in this disclosure. The scope of the present invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of the present invention.

Claims

1. Glass layer; A build-up layer disposed on the above glass layer; and A resin layer arranged to surround at least a portion of the outer surface of the above-mentioned build-up layer and the outer surface of the above-mentioned glass layer; comprising The horizontal width of the glass layer is greater than the horizontal width of the build-up layer, and The above resin layer is, It includes the glass layer and the first resin layer portion superimposed in the horizontal direction, and the build-up layer and the second resin layer portion superimposed in the horizontal direction, The outer surface of the second resin layer above is, A flat surface disposed on the periphery portion of at least one first surface among the upper and lower surfaces of the glass layer, and an inclined surface disposed on the outer surface of the build-up layer, Circuit board.

2. In Claim 1, A circuit board in which the inclined surface of the second resin layer has an inclination angle different from the outer surface of the first resin layer with respect to the first surface.

3. In Claim 1, The above resin layer is, A circuit board in which the inclined surface of the second resin layer has an inclination angle of 70° or more and 89° or less with respect to the first surface.

4. In Claim 1, At least one of the outer surface and inner surface of the first resin layer has a curved surface structure or a chamfered structure, A circuit board having an outer surface of the glass layer having a first non-rectangular structure, and a first resin layer having a second non-rectangular structure different from the first non-rectangular structure.

5. In Claim 4, A circuit board in which one of the outer surface of the glass layer and the first resin layer is a curved structure and the other is a chamfered structure.

6. In Claim 1, A protective layer disposed on the above-mentioned build-up layer; and It further includes a third resin layer portion disposed to cover the upper or lower surface of the protective layer and the outer surface of the protective layer; The surface roughness of the first resin layer is higher than the surface roughness of at least one of the second resin layer and the third resin layer, and The first resin layer has a surface roughness of 0.3 μm or more and 1.0 μm or less, and A circuit board having at least one of the second resin layer and the third resin layer having a surface roughness of 0.003 μm or more and 0.01 μm or less.

7. In Claim 1, A circuit board, wherein the second resin layer extends horizontally from the outer surface of the glass layer toward the center of the upper surface or the center of the lower surface of the glass layer with a width of 500 μm or more and 3000 μm or less.

8. In Claim 1, The above resin layer has a coefficient of thermal expansion of 5 ppm / ℃ or higher and 25 ppm / ℃ or lower, and A circuit board having a resin layer having a thickness of 30 μm or more and 400 μm or less.

9. In Claim 1, The above resin layer has a thickness that varies along the perimeter of the glass layer, and The above resin layer is, A first resin layer arranged to surround the perimeter of the glass layer; and A circuit board comprising: a second resin layer disposed on the first resin layer in at least a portion of the periphery region of the glass layer.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9, and a semiconductor element disposed on said circuit board.

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