Circuit board and semiconductor package comprising same

Abstract

Disclosed are a circuit board and a semiconductor package including same, the circuit board being capable of preventing or reducing peeling of a circuit layer and improving electrical reliability by sufficiently securing adhesion between a glass layer and a metal layer serving as a seed layer. A circuit board according to an embodiment of the present invention, comprises: a glass layer; a metal layer disposed on the glass layer to plate a plating layer on the glass layer; and an adhesive layer disposed between the glass layer and the metal layer. The adhesive layer includes a first adhesive layer disposed between the glass layer and the metal layer, and a second adhesive layer disposed between the first adhesive layer and the metal layer.

Description

Circuit board, and semiconductor package including the same

[0001] The present invention relates to a circuit board and a semiconductor package including the same.

[0002] Semiconductor packages are used to protect semiconductor devices, such as chips and dies, and to electrically connect them to electronic components, such as main boards of electronic products. Semiconductor packages improve mounting area efficiency and enable high-speed signal transmission through short signal paths; consequently, they are utilized in a wide range of applications, including not only mobile devices but also autonomous vehicles, high-performance servers, and Internet of Things (IoT) products.

[0003] Semiconductor packages need to be designed to safely protect semiconductor devices, which are small in size and sensitive to physical shock, moisture, humidity, and heat, while ensuring the smooth implementation of functions such as signal and power transmission. As the demand for improved semiconductor device performance increases, the number or size of required semiconductor devices grows, and as semiconductor devices are divided into functional units, semiconductor chiplet technology is expanding. In semiconductor chiplet technology, semiconductor devices such as CPUs, GPUs, memory controllers, and interface (I / O) chips are manufactured separately and integrated into the semiconductor package.

[0004] The circuit board of a semiconductor package is a core component of electronic devices used to physically support and electrically connect electronic components. The circuit board must be designed to perform functions that ensure stable operation, such as accurately transmitting electrical signals between electronic components, fixing components in designated positions, and dissipating heat generated by the components. Circuit boards can be classified into core boards and coreless boards depending on the presence or absence of a core layer. Core boards, due to the presence of a core layer, are structurally robust and highly durable, exhibit minimal warping or deformation, and offer excellent stability and ease of handling during manufacturing and assembly.

[0005] Core substrates can be classified into plastic core substrates, ceramic substrates, glass core substrates, etc., depending on the material of the core layer. The Young's modulus of glass core substrates is four times that of organic core substrates, and due to their excellent elastic modulus performance, they exhibit superior warping and deformation characteristics. Furthermore, glass core substrates have a low coefficient of thermal expansion (CTE), which provides excellent compatibility with silicon chips and offers the advantage of enabling the fine formation of through-glass vias (TGVs). In addition, glass core substrates have smooth surface characteristics, which are advantageous for forming microcircuits; they also exhibit low signal loss; and their excellent temperature-dependent deformation and signal characteristics make them suitable for semiconductor miniaturization and large-area applications.

[0006] To form a circuit layer on a glass core substrate, methods such as electroplating with a metallic material like copper (Cu) may be utilized. In order to form a plating layer on a glass core substrate by electroplating, a seed layer is first formed on the glass core substrate using methods such as sputtering or electroless plating. However, if sufficient adhesion is not secured between the glass layer of the glass core substrate and the seed layer, problems such as delamination of the circuit layer or reduced electrical reliability may occur. The background technology described above refers to the background in which the present invention was derived and does not imply that it is known technology prior to the filing of the present invention.

[0007] One objective of the present invention is to provide a circuit board and a semiconductor package including the same, which can prevent or reduce delamination of the circuit layer and improve electrical reliability by ensuring sufficient adhesion between a glass layer and a metal layer acting as a seed layer.

[0008] In addition, the present invention has one objective of providing a circuit board and a semiconductor package that can sufficiently secure adhesion strength between a glass layer and a seed layer through the physical bonding force and chemical bonding force of the adhesion layer between the glass layer and the seed layer.

[0009] In addition, the present invention aims to improve the adhesion performance between the glass layer and the seed layer by strengthening the wettability of the glass layer and the physical and chemical bonding strength of the adhesive layer through a triple treatment of a hydrophilic group, an inorganic layer coating, and an organic layer coating by plasma treatment.

[0010] In addition, the present invention has the purpose of improving the adhesion and conductivity of a seed layer disposed on a glass layer by the shape of the surface irregular structure of the adhesive layer between the glass layer and the metal layer.

[0011] In addition, the present invention has one objective of improving conductivity in the central region of the through-hole electrode within the through-hole by varying the thickness of the adhesive layer in the vertical direction along the through-hole of the glass layer.

[0012] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0013] A circuit board according to an embodiment of the present invention comprises: a glass layer; a metal layer disposed on the glass layer to plate a plating layer on the glass layer; and an adhesive layer disposed between the glass layer and the metal layer. The adhesive layer comprises a first adhesive layer disposed between the glass layer and the metal layer, and a second adhesive layer disposed between the first adhesive layer and the metal layer.

[0014] The first adhesive layer comprises a first material, and the second adhesive layer may comprise a second material different from the first material.

[0015] The first adhesive layer comprises an inorganic layer, and the second adhesive layer may comprise an organic layer.

[0016] The first adhesive layer may include a silicon oxide layer formed by curing a coating layer containing polysilazane.

[0017] The second adhesive layer may include a silane coating layer having a bonding group that bonds with the metal material of the metal layer.

[0018] The first adhesive layer may have a thickness in the range of 200 nm to 500 nm, and the second adhesive layer may have a thickness in the range of 30 nm to 100 nm.

[0019] The second adhesive layer may have a thickness of 1 / 3 to 1 / 10 of the thickness of the first adhesive layer.

[0020] The first adhesive layer may have a surface roughness of greater than 0.03 μm and less than or equal to 0.5 μm.

[0021] The surface of the above glass layer may have hydrophilic groups arranged by plasma treatment.

[0022] The upper surface of the first adhesive layer may have a surface irregularity structure.

[0023] The upper surface of the second adhesive layer may have a surface irregularity structure corresponding to the surface irregularity structure of the first adhesive layer.

[0024] The surface irregularity structure of the first adhesive layer may have at least one irregularity shape among a triangular protrusion, a square protrusion, a semicircular protrusion, and an elliptical protrusion.

[0025] The glass layer may have a through hole penetrating between the upper surface and the lower surface of the glass layer. The adhesive layer may include an upper adhesive layer disposed on the upper surface of the glass layer, a lower adhesive layer disposed on the lower surface of the glass layer, and an inner adhesive layer disposed on the inner wall of the through hole.

[0026] According to an embodiment of the present invention, a semiconductor package comprising a circuit board and a semiconductor element disposed on the circuit board is provided.

[0027] According to an embodiment of the present invention, a circuit board and a semiconductor package including the same are provided, which can prevent or reduce peeling of the circuit layer and improve electrical reliability by sufficiently ensuring adhesion between a glass layer and a metal layer acting as a seed layer.

[0028] In addition, according to an embodiment of the present invention, the adhesive strength between the glass layer and the seed layer can be improved by the physical bonding force and chemical bonding force of the adhesion layer between the glass layer and the seed layer.

[0029] In addition, according to an embodiment of the present invention, the wettability of the glass layer and the physical and chemical bonding strength of the adhesive layer can be enhanced by triple treatment of a hydrophilic group, an inorganic layer coating, and an organic layer coating by plasma treatment, thereby improving the adhesion performance between the glass layer and the seed layer.

[0030] In addition, according to an embodiment of the present invention, the adhesion and conductivity of a seed layer disposed on a glass layer can be improved by the shape of the surface roughness structure of the adhesive layer between the glass layer and the metal layer.

[0031] In addition, according to an embodiment of the present invention, the thickness of the adhesive layer can be varied in the vertical direction along the through hole of the glass layer to improve conductivity in the central region of the through electrode within the through hole.

[0032] The effects that the present invention aims to achieve are not limited to those mentioned above, and other unmentioned effects can be clearly understood by those skilled in the art from the description below.

[0033] FIG. 1a is a cross-sectional view showing a circuit board according to a first embodiment of the present invention.

[0034] FIG. 1b is a cross-sectional view showing a circuit board according to a second embodiment of the present invention.

[0035] Figure 2 is a cross-sectional view showing an enlarged view of section 'A' of Figure 1.

[0036] FIGS. 3 to 10 are drawings for explaining the process of forming a seed layer on a glass layer constituting a circuit board according to an embodiment of the present invention.

[0037] FIG. 3 is a diagram showing a glass layer constituting a circuit board according to an embodiment of the present invention that has hydrophilic groups arranged by plasma treatment.

[0038] FIG. 4 is a cross-sectional view showing a first adhesive layer formed on a glass layer constituting a circuit board according to an embodiment of the present invention.

[0039] FIG. 5a is a diagram showing the chemical structure of poly-silazane coated on a glass layer to form a first adhesive layer constituting a circuit board according to an embodiment of the present invention.

[0040] FIG. 5b is a diagram showing the chemical structure of silicon oxide of a first adhesive layer formed by coating and curing poly-silazane on a glass layer constituting a circuit board according to an embodiment of the present invention.

[0041] Figure 6 is a cross-sectional view showing an enlarged view of section 'B' of Figure 4.

[0042] FIG. 7 is a cross-sectional view showing a second adhesive layer formed on a glass layer and a first adhesive layer constituting a circuit board according to an embodiment of the present invention.

[0043] Figure 8 is a cross-sectional view showing an enlarged view of section 'C' of Figure 7.

[0044] FIG. 9 is a cross-sectional view showing a metal layer formed on a glass layer, a first adhesive layer, and a second adhesive layer constituting a circuit board according to an embodiment of the present invention.

[0045] FIG. 10 is a cross-sectional view showing a chemical plating layer formed on a glass layer and a seed layer constituting a circuit board according to an embodiment of the present invention.

[0046] FIGS. 11a and FIGS. 11b are drawings showing images of a through-hole region and an upper surface region of a glass layer of a circuit board manufactured according to an embodiment of the present invention.

[0047] FIG. 11c is a Fourier Transform Infrared Spectroscopy (FT-IR) graph measured for a circuit board manufactured according to an embodiment of the present invention.

[0048] FIG. 11d is a Focused Ion Beam (FIB) SEM image measured on a circuit board manufactured according to an embodiment of the present invention.

[0049] FIGS. 12a and 12b show images of the through-hole region and the upper surface region of the glass layer when the surface roughness of the first adhesive layer is formed to 0.7 μm.

[0050] FIGS. 13a to 13c are cross-sectional views showing a first adhesive layer disposed on a glass layer constituting a circuit board according to various embodiments of the present invention.

[0051] FIG. 14 is a cross-sectional view showing an adhesive layer coated on a glass layer constituting a circuit board according to another embodiment of the present invention.

[0052] FIG. 15 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.

[0053] The terms used in this specification will be briefly explained, and the present invention will be described in detail. The terms used in this detailed description have been selected to be as generally used as possible, taking into account their functions in the present invention; however, these terms may vary depending on the intent of those skilled in the art to which the present invention pertains, case law, the emergence of new technologies, etc. Additionally, in specific cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant part of the description of the invention. Therefore, the terms used in the present invention should be defined not merely by their names, but based on the meanings they convey and the content of the invention as a whole.

[0054] The following describes embodiments with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0055] Throughout the specification, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. In this specification, terms such as "first ~" and "second ~" are used solely for the purpose of distinguishing components from other components and are not limited to meaning the order of arrangement of components. In this specification, the meaning that another component is placed, stacked, or formed "on" a component should be understood to encompass not only a state in which the component and the other component are in direct contact, but also a state in which the component is placed, stacked, or formed with another component interposed therein.

[0056] Where one component is described as being "connected," "connected (contacted)," or "placed" to another component, this should be understood to encompass the fact that the components may be directly connected or connected to each other, but are indirectly connected, connected (contacted), or placed through the existence of another component between them. Where one component is described as being "directly" connected, connected (contacted), or placed to another component, this should be understood to mean that the components are directly connected, connected (contacted), or placed without the existence of another component between them.

[0057] FIG. 1a is a cross-sectional view showing a circuit board according to a first embodiment of the present invention. FIG. 1b is a cross-sectional view showing a circuit board according to a second embodiment of the present invention. Referring to FIG. 1a and FIG. 1b, a circuit board (100) according to an embodiment of the present invention may include a glass layer (110), a seed layer (120) disposed on the glass layer (110), a build-up layer (130, 140) disposed on the upper and / or lower portion of the glass layer (110), and a plating layer (150) disposed on the seed layer (120) in a through hole (113) of the glass layer (110).

[0058] The glass layer (110) can form a core substrate made of glass material. The glass layer (110) is a plate-shaped insulating layer made of glass material and functions to improve the rigidity of the circuit board (100) by acting as a core of the circuit board (100). The glass layer (110) can have a high dielectric constant and a low surface roughness compared to an organic core layer equipped with glass fibers, thereby improving the rigidity of the circuit board (100) while minimizing signal transmission loss, which can improve the electrical reliability and / or mechanical reliability of the circuit board (100) and the semiconductor package including it.

[0059] In this specification, the glass layer (110) may be referred to by other terms such as 'core layer', 'glass core', 'glass core layer', 'glass core substrate', and 'glass substrate', which serve as the core of the circuit board (100). In order to ensure appropriate rigidity of the circuit board (100), miniaturize the size of the semiconductor product, and prevent excessive signal loss, the glass layer (110) may be provided with a thickness of 200 μm to 1500 μm, or a thickness thinner or thicker than this.

[0060] The glass layer (110) may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, alumino-silicate glass, etc., but is not limited thereto, and may include fluorine glass, phosphate glass, chalcogen glass, etc. in addition to silicon-based glass compositions. Additionally, the glass layer (110) may further include other additives to form a glass having specific physical properties. These additives may include calcium carbonate (e.g., lime) and sodium carbonate (e.g., soda), as well as magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, and carbonates and / or oxides of these elements and other elements.

[0061] The glass layer (110) may have an upper surface (111) and a lower surface (112), and may have a plurality of through holes (113) penetrating between the upper surface (111) and the lower surface (112). Hereinafter, two directions parallel to the upper surface (111) of the glass layer (110) and perpendicular to each other will be described as the first direction (X) and the second direction (Y), respectively, and the vertical direction (or thickness direction) perpendicular to both the first direction (X) and the second direction (Y) will be described as the third direction (Z). The first direction (X) and the second direction (Y) may also be referred to as the horizontal direction, the side direction, or the vertical direction.

[0062] A seed layer (120) may be placed on the upper surface (111), lower surface (112) of the glass layer (110), and / or the inner surface (inner wall) of the through hole (113) to form a plating layer (150). The seed layer (120) may be formed by depositing a seed material, such as titanium (Ti), chromium (Cr), or copper (Cu), by means of sputtering, chemical plating, etc. In addition to the metal materials mentioned above, other materials such as tungsten (W), molybdenum (Mo), nickel (Ni), nichrome (NiCr), palladium (Pd), platinum (Pt), or silver (Ag) may be used as the seed layer (120).

[0063] Among the materials that can be used as the seed layer (120), copper has poor adhesion to glass and may cause peeling from the glass layer (110). Accordingly, it may be preferable for the seed layer (120) to be formed from a material with excellent adhesion to the glass layer (110), such as titanium (Ti) or chromium (Cr). Alternatively, the seed layer (120) may be provided as a multi-seed layer, such that titanium (Ti) and / or chromium (Cr) is deposited on the glass layer (110), and another material such as copper (Cu) is deposited thereon.

[0064] The seed layer (120) can be formed on the inner wall of the through hole (113) of the glass layer (110) by sputtering, ion beam assisted sputtering, or other methods of electroless plating. If an insulating layer is placed on the inner wall of the through hole (113) of the glass layer (110), a copper material may be placed as a seed layer on the insulating layer within the through hole (113). The plating layer (150) formed on the seed layer (120) by the electrolytic plating process within the through hole (113) can form a through electrode (150a).

[0065] The through electrode (150a) can electrically connect the upper build-up layer (130) and the lower build-up layer (140), or electrically connect the build-up layers (130, 140) to other circuit boards, interposers, semiconductor devices, main boards, etc. The through hole (113) and the through electrode (150a) of the glass layer (110) may have a horizontal width of approximately 10 μm to 100 μm for stable signal transmission and semiconductor miniaturization, or may have a width smaller or larger than this.

[0066] In the illustrated example, an upper build-up layer (130) and a lower build-up layer (140) are respectively disposed on the upper and lower surfaces of the glass layer (110), but either of these build-up layers (130, 140) may be omitted. In this case, a protective layer is disposed on the upper or lower surface of the glass layer (110), and can be electrically connected to another circuit board, interposer, semiconductor device, main board, etc. by solder bumps, etc. through the opening of the protective layer (upper protective layer or lower protective layer).

[0067] In this specification, a hole that penetrates the glass layer (110) entirely in the vertical direction (thickness direction) is called a "through hole" (113), and a hole that penetrates from the upper surface of the insulating layer (134a, 134b, 134c, 144a, 144b, 144c) of the build-up layer (130, 140) to the upper surface of the circuit layer (131, 132a, 132b, 132c, 141, 142a, 142b, 142c) is called a "blind via hole," and both are described using distinct terms.

[0068] The through hole (113) of the glass layer (110) can be formed by a laser process using a CO2 laser or the like. For example, the crystallization of the region of the glass layer (110) irradiated with a CO2 laser is altered, and then the through hole (113) can be formed by removing the region of the glass layer (110) with altered crystallization through wet etching using hydrofluoric acid (HF) or the like. The through hole (113) formed by the laser process can be provided in the shape of an hourglass, with the width gradually decreasing from the surface (upper and / or lower surface) of the glass layer (110) toward the center, as shown in FIG. 1a.

[0069] The through hole (113) in the glass layer (110) may be formed by a method other than a laser process. For example, the through hole (113) in the glass layer (110) may be formed using a mechanical drill. In this case, as shown in FIG. 1b, the through hole (113) may be formed such that its inner surface (inner wall) is perpendicular to the upper surface (one side) (111) and / or lower surface (other side) (112) of the glass layer (110).

[0070] If the inner surface of the through hole (113) is perpendicular to the upper surface (111) and / or lower surface (112) of the glass layer (110), it may be difficult to densely fill the interior of the through hole (113) with a metallic material during the plating process of filling the through hole (113) with a conductive material. Additionally, if the through hole (113) is formed in the glass layer (110) using a mechanical drill, damage such as the glass layer (110) breaking may occur during the process of using the mechanical drill, and the product yield may be reduced accordingly.

[0071] If a cavity is created in the through electrode (150a) filled in the through hole (113), electrical problems such as increased resistance, signal delay, signal attenuation, and open circuit may occur, or mechanical problems such as reduced reliability due to damage caused by external impact and thermal change, increased thermal stress due to bending, reduced heat dissipation performance due to reduced heat conduction, and cracks due to unbalanced thermal expansion may occur.

[0072] Accordingly, when it is necessary to ensure electrical, mechanical, and / or thermal performance and reliability in the glass layer (110), as shown in FIG. 1a, it may be preferable for the through hole (113) to be formed in a slanted shape such that its width in the horizontal direction gradually decreases toward the center from the upper surface (111) and / or lower surface (112) of the glass layer (110). Alternatively, if the width of the through hole (113) is large so that there is no problem in filling the seed layer (120) and / or plating layer (150) within the through hole (113), or if it is necessary to sufficiently secure the horizontal width at the center of the through hole (113) with respect to the vertical direction to improve signal transmission performance, a cylindrical through hole (113) as shown in FIG. 1b may be formed within the glass layer (110).

[0073] The build-up layer (130, 140) may be implemented as a single layer or multiple layers. The build-up layer (130, 140) may also be referred to as a redistribution layer (RDL) (upper RDL layer or lower RDL layer). The build-up layer (130, 140) may be formed with a thickness of at least 100 μm to 400 μm, and as the number of terminals of semiconductor devices placed on the circuit board (100) increases, the wiring becomes more complex and the number of layers increases, so it may be formed with a thickness of 1000 μm or less, or a thickness exceeding this.

[0074] The upper build-up layer (130) may include an upper circuit layer (131), a plurality of insulating layers (134a, 134b, 134c), a plurality of circuit layers (132a, 132b, 132c), and a protective layer (135). Each layer of the upper build-up layer (130) may include a circuit layer (or upper circuit layer) (131, 132a, 132b, 132c), an insulating layer (134a, 134b, 134c) covering the circuit layer, and via electrodes (133a, 133b, 133c) disposed in blind via holes of the insulating layers (134a, 134b, 134c).

[0075] An upper circuit layer (131) may be formed on the upper surface (111) of the glass layer (110). The upper circuit layer (131) may be formed through a plating process by an upper seed layer (120a) disposed on the upper surface (111) of the glass layer (110) among the seed layers (120). A plurality of insulating layers (134a, 134b, 134c) may be sequentially stacked on the upper surface (111) of the glass layer (110). A plurality of circuit layers (132a, 132b, 132c) may be sequentially arranged in a direction moving upward away from the upper surface (111) of the glass layer (110). The circuit wiring of the upper circuit layer (131) and the circuit layers (132a, 132b, 132c) can be formed from at least one metal material selected from copper (Cu), gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), and zinc (Zn).

[0076] A plurality of insulating layers (134a, 134b, 134c) may be disposed between the upper circuit layer (131) and the plurality of circuit layers (132a, 132b, 132c) to insulate between the upper circuit layer (131) and the plurality of circuit layers (132a, 132b, 132c). The upper circuit layer (131) and the plurality of circuit layers (132a, 132b, 132c) may function as electrical connections with semiconductor devices disposed on the circuit board (100).

[0077] via electrodes (133a, 133b, 133c) may be placed in blind via holes of insulating layers (134a, 134b, 134c) to connect between the upper circuit layer (131) and a plurality of circuit layers (132a, 132b, 132c). The blind via holes and via electrodes (133a, 133b, 133c) of the insulating layers (134a, 134b, 134c) may have a horizontal width of approximately 10 μm to 100 μm for stable signal transmission and semiconductor miniaturization, or may have a width smaller or larger than this. The via electrodes (133a, 133b, 133c) may have a slope that narrows in width toward the glass layer (110), that is, toward the upper surface of the insulating layer (134a, 134b, 134c) toward the upper surface of the circuit layer (131) or the circuit layer (132a, 132b, 132c), or may have a constant width in the vertical direction.

[0078] via electrodes (133a, 133b, 133c) can be placed simultaneously in the process of placing circuit layers (132a, 132b, 132c). For example, in the process of placing a first circuit layer (132a) on a first insulating layer (134a), a blind via hole is formed in the first insulating layer (134a) to expose the upper part of the first insulating layer (134a), and then the first circuit layer (132a) is placed on the upper surface of the first insulating layer (134a), and at the same time, a first via electrode (133a) that electrically connects the first circuit layer (132a) and the first upper circuit layer (131) can be placed in the blind via hole.

[0079] Likewise, the second and third via electrodes (133b, 133c) can each form the second and third circuit layers (132b, 132c) on the upper surface of the second insulating layer (134b, 134c) and can also be disposed in the blind via holes of the second insulating layer (134b, 134c). Each circuit layer (132a, 132b, 132c) can be electrically connected to another upper circuit layer (131) or circuit layer (132a, 132b) disposed in a lower layer adjacent to the circuit layer (132a, 132b, 132c) by means of the via electrode (133a, 133b, 133c) disposed in the blind via hole.

[0080] The upper circuit layer (131) may be disposed on the upper surface of the glass layer (110). The upper circuit layer (131) may be connected to a through electrode (150a) disposed in a through hole (113) of the glass layer (110). The first insulating layer (134a), the second insulating layer (134b), the third insulating layer (134c), and the upper protective layer (135) may be sequentially stacked upward from the upper surface (111) of the glass layer (110). The upper protective layer (135) may be disposed on the uppermost insulating layer (134c) among the plurality of insulating layers (134a, 134b, 134c).

[0081] The upper protective layer (135) may be a solder resist layer containing an organic polymer material. The upper protective layer (135) may include an epoxy acrylate-based resin. For example, the upper protective layer (135) may include, but is not limited to, a resin, a curing agent, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic-based monomer, etc., and may be formed of a photosolder resist layer, a cover-lay, a polymer material, or other insulating material.

[0082] Insulating layers (134a, 134b, 134c) may be arranged for vertical insulation between the upper circuit layer (131) and a plurality of circuit layers (132a, 132b, 132c). For example, the insulating layers (134a, 134b, 134c) may be made of a thermosetting insulating material containing inorganic fillers in a resin, or may be made using a build-up film called ABF (Ajinomoto Build-up Film) of Ajinomoto Corporation. However, not limited thereto, the insulating layers (134a, 134b, 134c) may also be made using a photo-imageable dielectric (PID) or the like to form a fine pattern.

[0083] The upper protective layer (135) protects the upper surface of the upper build-up layer (130), performs an insulating function between the wiring electrodes of the circuit layer (132c), and can serve to protect the uppermost circuit layer (132c) from external moisture or contaminants. When a semiconductor device is placed on a circuit board (100) using a material such as solder, the upper protective layer (135) can function to prevent short circuits between solders due to low wettability with the solder. The upper protective layer (135) may be made of a photocurable insulating material, and, for example, may be made of solder resist. The upper protective layer (135) may be provided with an opening (135a) that exposes the circuit layer (132c) placed on the insulating layer (134c) of the uppermost layer.

[0084] A lower build-up layer (140) may be disposed on the lower part of the glass layer (110). Similar to the upper build-up layer (130), the lower build-up layer (140) may include a lower circuit layer (141), a plurality of circuit layers (142a, 142b, 142c), a plurality of via electrodes (143a, 143b, 143c), a plurality of insulating layers (144a, 144b, 144c), and a lower protective layer (145). The lower circuit layer (141), circuit layer (142a, 142b, 142c), via electrode (143a, 143b, 143c), insulating layer (144a, 144b, 144c), and lower protective layer (145) of the lower build-up layer (140) may be arranged in a symmetrical form with respect to the upper circuit layer (131), circuit layer (132a, 132b, 132c), via electrode (133a, 133b, 133c), insulating layer (134a, 134b, 134c), and upper protective layer (135) of the upper build-up layer (130) and the glass layer (110), and the description of the upper build-up layer (130) described above may be applied to the lower build-up layer (140) in the same or similar way. The structure of the circuit board (100) described above is merely an example for explaining the present invention, and the technical concept of the present invention is not limited to the stacked structure of this example.

[0085] In forming a plating layer (150) on a glass layer (110) by electroplating, it is necessary to place a seed layer (120) on the glass layer (110) to ensure that the electroplating of the plating layer (150) is performed smoothly. Since the glass layer (110) does not have good adhesion to a metal layer such as copper (Cu) or titanium (Ti) that acts as the seed layer (120), it is necessary to interpose an adhesion layer or an inter-layer to increase the adhesion strength between the glass layer (110) and the metal layer. For example, in the case of copper, since it is difficult to form copper oxide or to form a bond between copper and silicon oxide, it is necessary to interpose an adhesion layer to improve the bonding strength between the copper acting as the seed layer and the glass layer (110).

[0086] FIG. 2 is a cross-sectional view showing an enlarged view of section 'A' of FIG. 1. Referring to FIG. 1 and FIG. 2, a circuit board (100) according to an embodiment of the present invention may include a glass layer (110), a seed layer (120) disposed on the glass layer (110), and a plating layer (150) disposed by plating on the seed layer (120). The seed layer (120) may be disposed on the upper surface (111) and / or lower surface (112) of the glass layer (110) and on the inner wall of a through hole (113).

[0087] The seed layer (120) may include a plurality of adhesive layers (intermediate layers or buffer layers) (121, 122) disposed on the glass layer (110), and a metal layer (123) disposed on the plurality of adhesive layers (121, 122). The plurality of adhesive layers (121, 122) may include a first adhesive layer (121) disposed on the upper surface (111) and / or lower surface (112) of the glass layer (110), and a second adhesive layer (122) disposed on the first adhesive layer (121). The first adhesive layer (121) may be a coating layer of a first material, and the second adhesive layer (122) may be a coating layer of a second material different from the first material of the first adhesive layer (121).

[0088] In an embodiment of the present invention, the first adhesive layer (121) may include an inorganic layer, and the second adhesive layer (122) may include an organic layer. If the first adhesive layer (121) is an inorganic layer, the surface roughness of the inorganic layer can be easily controlled to effectively improve the physical / mechanical adhesive strength between the glass layer (110) and the seed layer (120). Additionally, by forming the second adhesive layer (122) as an organic layer, the chemical bonding strength with the glass layer (110) and / or the metal layer (123) can be improved by the bonding groups of the organic layer constituting the second adhesive layer (122).

[0089] The first adhesive layer (121) may be a silicon oxide layer formed by, for example, coating and curing polysilazane. The silicon oxide formed by coating and curing a polysilazane solution has the advantage of being able to produce a first adhesive layer (121) with an appropriate surface roughness by controlling the curing temperature, curing time, and the concentration of the polysilazane solution.

[0090] Accordingly, by controlling the concentration of the poly-silazane solution, the surface roughness of the SiO2 coating layer on the glass layer (110) can be formed, thereby increasing the physical bonding strength between the glass layer (110) and the seed layer (120). Additionally, by forming the first adhesive layer (121) with the poly-silazane coating layer, the deviation in the upper / lower surface components of the glass layer (110) can be offset, thereby stably securing the bonding strength between the glass layer (110) and the seed layer (120). The first adhesive layer (121) not only has the function of securing the adhesion strength of the through-hole (113) area of ​​the glass layer (110), but can also perform the role of supporting the circuit wiring layer formed by the plating layer (150) after the plating layer (150) is formed by the metal layer (123).

[0091] FIGS. 3 to 10 are drawings for explaining the process of forming a seed layer on a glass layer constituting a circuit board according to an embodiment of the present invention. FIG. 3 is a drawing showing a glass layer constituting a circuit board according to an embodiment of the present invention that has hydrophilic groups arranged by plasma treatment. First, referring to FIGS. 1 and FIGS. 3, before forming the first adhesive layer (121) of the seed layer (120) on the glass layer (110), a treatment may be performed in advance to arrange hydrophilic groups (114) that increase the surface wettability of the glass layer (110) by plasma (P) treatment of the surface of the glass layer (110).

[0092] When a hydrophilic group (114) is placed on the upper surface (111) and / or lower surface (112) of the glass layer (110) and the inner surface of the through hole (113) by plasma treatment, the first adhesive layer (121) can react with the hydrophilic group (114) to increase the bonding strength with the glass layer (110). In addition, if the glass layer (110) is cleaned with a cleaning solution such as acetone or IPA, and then the surface of the glass layer (110) is cleaned, and then plasma treatment is performed to add a hydrophilic group to the glass layer (110), the surface reactivity of the glass layer (110) can be further improved, thereby further enhancing the adhesion / bonding strength of the seed layer (120). Hydrophilic functional groups that can be placed on the glass layer (110) by plasma treatment include, for example, hydroxyl groups (-OH), carboxyl groups (-COOH), carbonyl groups (-C=O), epoxy groups (-COC-), amine groups (-NH2), but are not limited thereto.

[0093] FIG. 4 is a cross-sectional view showing a first adhesive layer formed on a glass layer constituting a circuit board according to an embodiment of the present invention. FIG. 5a is a diagram showing the chemical structure of poly-silazane coated on a glass layer to form a first adhesive layer constituting a circuit board according to an embodiment of the present invention. FIG. 5b is a diagram showing the chemical structure of silicon oxide of the first adhesive layer formed by coating and curing poly-silazane on a glass layer constituting a circuit board according to an embodiment of the present invention. FIG. 6 is a cross-sectional view showing an enlarged view of section 'B' of FIG. 4.

[0094] Referring to FIGS. 1, 4, 5a, 5b and 6, a first adhesive layer (121) may be formed on a glass layer (110) in which hydrophilic groups are disposed on the inner wall of the upper surface (111) and / or lower surface (112) and through hole (113) by plasma treatment. The first adhesive layer (121) may be an adhesive layer (first intermediate layer or first buffer layer) interposed between the glass layer (110) and the second adhesive layer (122). For example, if polysilazane is coated on the surface of the glass layer (110) and then cured, the polysilazane coating layer is cured by the reaction of moisture (H2O), oxygen (O2), and the polysilazane coating layer, thereby removing ammonia (NH3) and hydrogen (H2), and the first adhesive layer (121) of the silicon oxide (SiO2) inorganic coating layer may be formed. In this process, a surface irregular structure (a structure in which protrusions and grooves are repeatedly formed) (121e) may be formed on the upper surface (121d) of the first adhesive layer (121).

[0095] The physical bonding strength between the glass layer (110) and the seed layer (120) can be improved by the surface roughness structure (121e) of the first adhesive layer (121) as described above. In order to form an appropriate surface roughness on the glass layer (110) and secure sufficient adhesion with the glass layer (110), the first adhesive layer (121) may be provided with a thickness of 200 nm to 500 nm. To provide physical bonding strength on the glass layer (110), the first adhesive layer (121) may be provided to have a surface roughness greater than 0.03 μm and less than or equal to 0.5 μm. More preferably, the first adhesive layer (121) may have a surface roughness greater than 0.04 μm and less than or equal to 0.3 μm. The first adhesive layer (121) may be placed on the glass layer (110) by means such as spray coating or spin coating.

[0096] Poly-silazane is (-Si-N-Si-) nIt consists of a basic structure and can be converted into silicon oxide (SiO2) by reacting with moisture (H2O) and oxygen (O2) in the air during the heat treatment (curing) process. During this process, the poly-silazane solution may undergo reactions such as hydrolysis and condensation, volume shrinkage and stress generation, release of byproducts and surface expansion, non-uniform oxidation, and surface tension and material rearrangement. When poly-silazane reacts with moisture, the Si-N bonds are hydrolyzed, releasing ammonia (NH3) and forming silanol (Si-OH) groups. The water (H2O) released during the condensation reaction between silanols, which creates Si-O-Si bonds, can induce further hydrolysis and reactions. Consequently, Si-N bonds are broken and Si-O bonds are formed, which can lead to the creation of a silicon oxide (SiO2) network.

[0097] During the process of converting poly-silazane into silicon oxide, the density increases, and volume shrinkage may occur during curing. At this time, due to the difference in reaction rates between the surface and the interior, uniform shrinkage does not occur, and local stress differences may arise, forming an uneven structure on the surface of the first adhesive layer (121). Additionally, gaseous byproducts such as NH3 and H2O released during the process of converting poly-silazane into silicon oxide expand the surface and form a micropore (porous) structure, causing some areas of the surface of the first adhesive layer (121) to swell while other areas contract, thereby forming a surface uneven structure on the first adhesive layer (121).

[0098] In addition, the difference in oxidation rates between the surface and the interior can also be a factor in the formation of a surface roughness structure in the first adhesive layer (121). That is, the volume decreases more in the areas with faster reactions (areas where moisture penetrates well), and shrinks relatively less in the areas with slower reactions; as these minute differences accumulate, a rough surface can be formed. Furthermore, due to the difference in surface tension in the liquid state, silicon oxide may locally aggregate, and the surface roughness may increase as the material rearranges to lower the surface energy during heat treatment.

[0099] It is thought that the surface roughness structure of the first adhesive layer (121) can be controlled, for example, by the concentration of the poly-silazane solution, the curing temperature, humidity, oxygen concentration, the amount of solution applied (coating thickness), etc. If the curing temperature is increased, the oxidation reaction proceeds rapidly, and many micropores can be formed along with volume shrinkage. Accordingly, a rough surface can be formed on the first adhesive layer (121). Conversely, if the curing temperature is lowered, the oxidation reaction slows down, and the surface of the first adhesive layer (121) can become less rough.

[0100] As another example, if the reaction is allowed to occur in a high-humidity environment, the hydrolysis reaction is accelerated, which can increase the surface roughness of the first adhesive layer (121). Additionally, increasing the oxygen concentration can induce more uniform oxidation, which can affect the surface roughness of the first adhesive layer (121). As yet another example, if the thickness of the adhesive material applied to form the first adhesive layer (121) is increased, the difference in oxidation rates between the interior and the surface increases, which may be advantageous for forming a rough surface. Conversely, if the adhesive material is applied in a thin layer, uniform oxidation proceeds, which can reduce the surface roughness.

[0101] The molecular weight or viscosity of the adhesive material can also be a factor in changing the surface roughness of the first adhesive layer (121). For example, if a high molecular weight silazane is used, the reaction occurs uniformly due to the high viscosity, which can reduce the surface roughness of the first adhesive layer (121). Conversely, if a low molecular weight silazane is used, the difference in reaction rate increases due to the low viscosity and the amount of volatile byproducts released increases, which can be advantageous for forming a rough surface on the first adhesive layer (121).

[0102] FIG. 7 is a cross-sectional view showing a second adhesive layer formed on a glass layer and a first adhesive layer constituting a circuit board according to an embodiment of the present invention. FIG. 8 is a cross-sectional view showing an enlarged view of section 'C' of FIG. 7. Referring to FIG. 1, FIG. 7 and FIG. 8, after the first adhesive layer (121) is coated on the glass layer (110), a second adhesive layer (122) can be coated on the first adhesive layer (121).

[0103] The first adhesive layer (121) may include a first upper adhesive layer (121a) disposed on the upper surface (111) of the glass layer (110), a first lower adhesive layer (121b) disposed on the lower surface (112) of the glass layer (110), and a first inner adhesive layer (121c) disposed on the inner wall of the through hole (113). The second adhesive layer (122) may include a second upper adhesive layer (122a) disposed on the first upper adhesive layer (121a), a second lower adhesive layer (122b) disposed on the first lower adhesive layer (121b), and a second inner adhesive layer (122c) disposed on the first inner adhesive layer (121c) on the inner wall of the through hole (113).

[0104] The first upper adhesive layer (121a) and the second upper adhesive layer (122a) may be buffer layers interposed between the upper surface (111) of the glass layer (110) and a metal layer acting as a seed to form a plating layer of the upper circuit layer (131). The first lower adhesive layer (121b) and the second lower adhesive layer (122b) may be buffer layers interposed between the lower surface (112) of the glass layer (110) and a metal layer acting as a seed to form a plating layer of the lower circuit layer (141). The first inner adhesive layer (121c) and the second inner adhesive layer (122c) may be buffer layers interposed between the inner surface of the through hole (113) of the glass layer (110) and a metal layer acting as a seed to form a plating layer of the through electrode (150a).

[0105] For example, the second adhesive layer (122) may be a silane coating layer having a bonding group capable of bonding with a plating material. Examples of bonding groups include azole groups, thiol groups, etc., which have high affinity with plating materials such as copper. The second adhesive layer (122) may be an adhesive layer (second intermediate layer or second buffer layer) interposed between the first adhesive layer (121) and the metal layer (123). The second adhesive layer (122) may serve to strengthen the chemical bonding force with the metal layer (123), which is made of a metal material corresponding to the seed material.

[0106] The second adhesive layer (122) may be a chemical bonding layer formed by, for example, coating with silane, and the adhesion of the metal layer (123) can be improved by the chemical bonding force. Examples of silane-based adhesive materials include APTMS (3-Aminopropyltrimethoxysilane), MPTS (3-Mercaptopropyltrimethoxysilane), GPTMS (3-Glycidoxypropyltrimethoxysilane), etc., but are not limited to such exemplified materials. In addition to silane, the second adhesive layer (122) may include an oxide-based material (Ti / Zr-based binder) such as organic titanate (e.g., titanium alcohol) or organic zirconate; an organic polymer such as epoxy, polyurethane, or phenolic resin; an organic compound such as a phosphate derivative or an amine-based compound; carbon nanotubes; and / or an adhesive material such as graphene oxide.

[0107] The second adhesive layer (122) may be formed with a second thickness (T2) that is thinner than the first thickness (T1) of the first adhesive layer (121). The second adhesive layer (122) may have a thickness within the range of 30 nm to 100 nm. Preferably, the second adhesive layer (122) may be arranged to have a thickness (T2) of about 1 / 3 to 1 / 10 of the thickness (T1) of the first adhesive layer (121). If the thickness of the second adhesive layer (122) becomes thinner than this, it may become difficult to sufficiently secure the bonding strength with the first adhesive layer (121) or the chemical bonding strength with the metal layer (123). When the second adhesive layer (122) is formed with a thin film thickness, the upper surface (122d) of the second adhesive layer (122) is formed as a surface irregular structure (122e) according to the irregular shape of the first adhesive layer (121), thereby increasing the physical bonding strength with the metal layer (123). In addition, the chemical bonding strength with the metal layer (123) can also be further increased due to the increased bonding area according to the irregular shape of the second adhesive layer (122).

[0108] Conversely, if the thickness of the second adhesive layer (122) becomes excessively large, the physical bonding force due to the surface roughness of the first adhesive layer (121) may be weakened, and the bonding force with the metal layer (123) may be weakened, and the chemical bonding force may also be reduced due to the reduction in the bonding area with the metal layer (123). If the thickness (T2) of the second adhesive layer (122) is made sufficiently thin, the surface roughness of the second adhesive layer (122) can be arranged to have a surface roughness greater than 0.03 μm and less than or equal to 0.5 μm, similar to that of the first adhesive layer (121).

[0109] According to an embodiment of the present invention, sufficient adhesion of the metal layer (123) on the glass layer (110) can be secured not only by the chemical bonding force of the second adhesive layer (122) but also by the physical bonding force due to the surface roughness of the first adhesive layer (121) and the second adhesive layer (122). Accordingly, peeling of the circuit layer due to peeling of the glass layer (110) and the seed layer (120) can be prevented, and the electrical reliability of the circuit board can be improved.

[0110] In addition, according to an embodiment of the present invention, the adhesion between the glass layer (110) and the metal layer (123) is improved by the first and second adhesive layers (121, 122) to suppress interlayer delamination, and at the same time, the stress applied by the metal layer (123), such as copper (Cu), to the glass layer (110) can be relieved. Accordingly, the first and second adhesive layers (121, 122) can suppress the seware phenomenon in which the glass layer (110) splits vertically due to the compression stress acting on the upper and lower surfaces of the glass layer (110) and the tension stress acting on the side portions of the glass layer (110) caused by the difference in the coefficient of thermal expansion between the glass layer (110) and the metal layer (123).

[0111] The glass layer (110) may have a thermal expansion coefficient of about 3 ppm / ℃ to 8 ppm / ℃, and the metal layer (123) may have a thermal expansion coefficient of about 8 ppm / ℃ to 20 ppm / ℃. In this way, when the metal layer (123) has a thermal expansion coefficient greater than that of the glass layer (110), if the second adhesive layer (122) placed on the metal layer (123) side has a greater thermal expansion coefficient than the first adhesive layer (121) placed on the glass layer (110) side between the glass layer (110) and the metal layer (123), the stress caused by the difference in thermal expansion coefficients between the glass layer (110) and the metal layer (123) can be effectively relieved to prevent the seware phenomenon.

[0112] FIG. 9 is a cross-sectional view showing a metal layer formed on a glass layer, a first adhesive layer, and a second adhesive layer constituting a circuit board according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 9, when a first adhesive layer (121) is coated on a glass layer (110) and a second adhesive layer (122) is coated on the first adhesive layer (121), a metal layer (123) can be placed on the second adhesive layer (122).

[0113] The metal layer (123) is a seed layer for forming a plating layer (150) by electroless plating and / or electroplating, and may be formed from a metal material such as copper (Cu), titanium (Ti), or chromium (Cr). The metal layer (123) may include an upper metal layer (123a) disposed on the upper part of the glass layer (110), a lower metal layer (123b) disposed on the lower part of the glass layer (110), and an inner metal layer (123c) disposed on the inner wall of the through hole (113).

[0114] To ensure proper plating performance of the plating layer (150), the metal layer (123) may be formed with a thickness within the range of 100 nm to 2000 nm. The plating layer (150) formed by plating with the metal layer (123) may include a chemical plating layer (151) and an electroplating layer (152). The chemical plating layer (151) may be placed on the metal layer (123) by electroless plating. The chemical plating layer (151) may provide a function that enables the electroplating layer (152) to be performed efficiently. The electroplating layer (152) may be formed by electroplating based on the chemical plating layer (151).

[0115] FIG. 10 is a cross-sectional view showing a chemical plating layer formed on a glass layer and a seed layer constituting a circuit board according to an embodiment of the present invention. Referring to FIG. 1 and FIG. 10, when a seed layer (120) including an adhesive layer (121, 122) and a metal layer (123) is disposed on a glass layer (110), a chemical plating layer (131a, 141a, 151) can be formed by the metal layer (123) of the seed layer (120).

[0116] The plating layer (150) may include a through electrode (150a) within a through hole (113) and an upper circuit layer (131) and / or a lower circuit layer (141) of the glass layer (110). The upper circuit layer (131) and / or the lower circuit layer (141) may include a chemical plating layer (131a, 141a) disposed on the upper surface (111) and / or lower surface (112) of the glass layer (110), and an electroplating layer (131b, 141b) disposed on the chemical plating layer (131a, 141a).

[0117] The laminated structure of the glass layer (110), the first adhesive layer (121), the second adhesive layer (122), the metal layer (123), and the plating layer (150), as well as the upper surface position and shape thereof, can be distinguished by various analysis methods. For example, each layer can be distinguished by comparing image conditions (e.g., the illuminance of the optical microscope image) in a vertical cross-sectional image obtained by an optical microscope, or through the through electrode, the power distribution electrode structure of the upper circuit layer, etc.

[0118] Hereinafter, an experiment to verify the performance and effects of a circuit board according to an embodiment of the present invention is described. After cleaning the glass layer (110), a hydrophilic group was attached by plasma treatment, and a first adhesive layer (121) was formed by spray coating or spin coating poly-silazane (-Si-NH2-) on the glass layer (110), which had improved wettability due to hydrophilic treatment. After coating the poly-silazane solution, the poly-silazane solution was cured by heat treatment at a temperature of 300°C to 400°C. During the curing process, the poly-silazane solution reacted with oxygen and moisture to oxidize into silicon oxide, thereby forming the first adhesive layer (121) of a SiO2 thin film. A second adhesive layer (122) was formed by coating a silane solution on the first adhesive layer (121) and curing it, and a metal layer (123) was formed by forming a seed material on the second adhesive layer (122). Chemical copper plating layer and electroplated copper plating layer were formed by the metal layer (123).

[0119] FIGS. 11a and 11b are drawings showing images of a through-hole region and an upper surface region of a glass layer of a circuit board manufactured according to an embodiment of the present invention. FIGS. 11a and 11b show the through-hole (113) region and the upper surface region of a glass layer (110) when the surface roughness of the first adhesive layer (121) is formed to 0.1 μm (100 nm). FIG. 11c is a Fourier Transform Infrared Spectroscopy (FT-IR) graph measured for a circuit board manufactured according to an embodiment of the present invention. FIG. 11d is a Focused Ion Beam (FIB) SEM image measured for a circuit board manufactured according to an embodiment of the present invention.

[0120] The FT-IR in FIG. 11c is the result of measurements taken for the first adhesive layer (121). The values ​​indicated in the FIB SEM image in FIG. 11d are thickness measurements obtained for the first adhesive layer (121). 1000 cm of the FT-IR in FIG. 11c -1 - 1100 cm -1 From the strong peak appearing at the wavenumber, it can be confirmed that the poly-silazane has been thermally cured and transformed into silicon oxide. From the Focused Ion Beam (FIB) SEM image of FIG. 11d, it can be confirmed that a rough surface has been formed on the upper surface of the first adhesive layer (121). The measured surface roughness was 0.1 μm. In this specification, surface roughness may follow the definition and measurement method of the ISO 21920 international standard or the CLSM (Confocal Laser Scanning Microscopy)-based 3D non-contact optical measurement method defined in the ISO 25178 international standard. If the surface roughness measured according to at least one of the methods of ISO 21920 and ISO 25178 is within the surface roughness range of the present invention, it may be interpreted as falling within the scope of the rights of the present invention.

[0121] The second adhesive layer (122) can be formed, for example, using a silane coupling agent having an RSi(OR′)3 structure. In the RSi(OR′)3 structure of the silane coupling agent, R can be an organic functional group such as an epoxy group (-COC-), an amine group (-NH2), or a methoxy group (O-CH3), and OR' can be an alkoxy functional group (-OCH3, -OC2H5), etc. In FT-IR for the second adhesive layer (122), the wavenumber (approx. 1000 - 1100 cm⁻¹) associated with the vibrational mode of Si-O stretching -1 ) and wavenumber associated with Si-C elongation (approx. 1250 - 1350 cm⁻¹) -1 ), rupture of membranes related to CH3 / CH2 elongation (approx. 2800 - 3000 cm) -1 Peaks according to functional groups (R-group), such as epoxy groups (-COC-), amine groups (-NH2), and carbonyl groups (-C=O), can be detected.

[0122] FIGS. 12a and FIGS. 12b show images of a through-hole region and an upper surface region of a glass layer when the surface roughness of the first adhesive layer is formed to 0.7 μm. FIGS. 12a and FIGS. 12b respectively show a through-hole (113) region and an upper surface region of a glass layer (110) when the surface roughness of the first adhesive layer (121) is formed to 0.7 μm. If the surface roughness of the first adhesive layer (121) is made too thick (e.g., a surface roughness of 0.7 μm), the adhesion of the catalyst is reduced during plating, resulting in unplated areas, excessive stress on the circuit board, and signal loss may increase due to the high surface roughness of the plating layer.

[0123] Conversely, if the surface roughness of the first adhesive layer (121) is excessively low (e.g., surface roughness of 0.03 μm), the physical anchoring performance is reduced and the adhesive strength is reduced, and accordingly, it may be preferable for the first adhesive layer (121) to have a surface roughness greater than 0.03 μm and less than or equal to 0.5 μm.

[0124] FIGS. 13a to 13c are cross-sectional views showing a first adhesive layer disposed on a glass layer constituting a circuit board according to various embodiments of the present invention. It was confirmed that physical properties such as the shape of the coating film of the adhesive layer (121, 122) (uneven shape and uneven spacing (D)), film density, and surface roughness can be controlled by varying the solution mixing and spraying conditions of the first adhesive layer (121) and / or the second adhesive layer (122), and by adjusting the nozzle shape and / or curing conditions.

[0125] FIG. 13a shows that the surface irregularity structure (121f) formed on the upper surface (121d) of the first adhesive layer (121) has a triangular protrusion shape. FIG. 13b shows that the surface irregularity structure (121g) formed on the upper surface (121d) of the first adhesive layer (121) has a semicircular, elliptical, or curved protrusion shape. FIG. 13c shows that the surface irregularity structure (121h) formed on the upper surface (121d) of the first adhesive layer (121) has a square protrusion shape.

[0126] Methods for controlling the surface irregularity shape of the first adhesive layer (121) may include a coating method, a heat treatment / drying method, and / or a method for controlling the concentration / viscosity of the solution. For example, coating methods may include dip-coating, spin-coating, and spray-coating. When using dip-coating, the surface irregularity shape of the first adhesive layer (121) can be controlled by controlling the tensile speed. For example, slowing down the tensile speed of the dip-coating can form a smooth, curved surface structure. Conversely, increasing the tensile speed of the dip-coating can induce a rapid change in shape on the surface.

[0127] When using spin-coating, the surface irregularity shape of the first adhesive layer (121) can be controlled by the rotation speed. For example, the slower the spin-coating rotation speed, the more advantageous it may be for creating a triangular irregularity shape or a sharp boundary layer. Conversely, if the spin-coating rotation speed is fast, it may be advantageous for forming a uniform curved surface irregularity shape. When using spray-coating, the surface irregularity shape of the first adhesive layer (121) can be controlled by adjusting the height and / or angle during spray-coating.

[0128] The surface irregular shape of the first adhesive layer (121) can also be controlled by a heat treatment or drying method. For example, slow heat treatment may be advantageous for stably maintaining a curved shape on the surface of the first adhesive layer (121) and relieving internal stress. Conversely, fast heat treatment may be advantageous for forming curves on the surface of the first adhesive layer (121) to arrange irregular shapes such as triangles. As for the drying method, a method may be considered to create an uneven irregular shape and / or a triangular shape on the surface of the first adhesive layer (121) by rapid drying, or to create a curved irregular shape on the surface of the first adhesive layer (121) by relieving stress and increasing uniformity through gradual drying.

[0129] As a method utilizing the concentration and / or viscosity of the adhesive solution, a method may be considered in which the concentration and / or viscosity of the adhesive solution is lowered to place thin, uniform curved irregularities on the surface of the first adhesive layer (121). Conversely, if an adhesive solution with a high concentration and / or viscosity is used, a triangular protruding structure may be formed on the surface of the first adhesive layer (121) during the ceramicization process.

[0130] The physical and quantitative influences and behaviors according to the coating layer shape of the first adhesive layer (121) and / or the second adhesive layer (122) are described as follows. When an uneven structure with a curved shape is placed on the surface of the first adhesive layer (121) and / or the second adhesive layer (122), current loss can be reduced by preventing current loss from occurring at sharp corners. To improve the adhesive strength of the first adhesive layer (121) having a curved uneven structure, it may be desirable to arrange the first adhesive layer (121) to have a surface roughness greater than 0.03 μm and less than or equal to 0.5 μm. The first adhesive layer (121) having a triangular protrusion-shaped uneven structure may be advantageous for securing high adhesive strength compared to a curved protrusion-shaped uneven structure. Therefore, even if the first adhesive layer (121) is positioned to have a surface roughness in the range of 0.03 μm to 0.5 μm within the limits where there is no problem with current loss, sufficient adhesion can be secured between the glass layer (110) and the seed layer (120).

[0131] FIG. 14 is a cross-sectional view showing an adhesive layer coated on a glass layer constituting a circuit board according to another embodiment of the present invention. In the circuit board according to the embodiment of FIG. 14, the thickness (T1, T2) of the adhesive layer (121, 122) decreases as it moves from the upper surface (111) and / or lower surface (112) of the glass layer (110) toward the center of the through hole (113). If the thickness of the adhesive layer (121, 122) is formed uniformly according to the depth of the through hole (113), the width (W1) at the center of the through hole (113) becomes narrower as shown by the dotted line, making it difficult to secure a sufficient area for the through electrode.

[0132] However, according to the embodiment of FIG. 14, even if the width of the through hole (113) of the glass layer (110) decreases at the center, the thickness of the adhesive layer (121, 122) at the center of the through hole (113) is reduced, thereby mitigating / reducing the decrease in the width (W2) or area of ​​the through electrode at the center of the through hole (113). Accordingly, the problem of reduced conductivity performance at the center of the through hole (113) of the glass layer (110) can be prevented or reduced.

[0133] In an embodiment of the present invention, the thickness of the first adhesive layer (121) at the upper opening and / or lower opening of the through hole (113) may be 300 to 500 nm, and the thickness of the first adhesive layer (121) at the center of the through hole (113) may be 200 to 400 nm. The center of the through hole (113) may be, for example, a central location where the angle of inclination of the inner wall of the through hole (113) changes, such as when the upper and lower openings of the through hole (113) are wide and the central opening is narrow.

[0134] The difference between the thickness on the side of the opening (upper opening and / or lower opening) of the through hole (113) and the thickness at the center of the through hole (113) may be 50 nm to 150 nm. By forming a thickness slope in the upper and lower directions of the through hole (113) in this way, the effect of expanding the width (W2) corresponding to the inner diameter of the adhesive layer (121, 122) at the center of the through hole (113) by about 100 nm to 300 nm can be obtained.

[0135] FIG. 15 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention. According to an embodiment of the present invention, a semiconductor package can be manufactured by carrying out a process of mounting a semiconductor element on a circuit board. A circuit board (100) according to an embodiment of the present invention can form a semiconductor package (10) together with one or more semiconductor elements (200). The semiconductor package (10) may be an electronic component that constitutes an electronic element. The electronic element may be, for example, an electronic terminal of a vehicle, a smartphone, a tablet, a laptop, a high-performance server, a smart watch, a personal digital assistant (PDA), an Internet of Things (IOT) terminal, a digital camera, etc., but is not limited thereto and may be provided as any other electronic device having one or more semiconductor elements and one or more circuit boards.

[0136] The semiconductor package may be implemented as, for example, a BGA (Ball Grid Array) package, a CSP (Chip-Scale Package), a SiP (System in Package), an MCM (Multi-Chip Module) package, a semiconductor chiplet package, a flip chip package, a PoP (Package on Package), etc., but is not limited to the examples listed above. The semiconductor device (200) may be provided as various semiconductor chips such as an input / output processor (IOP) chip, an application processor (AP) chip including a central processing unit (CPU) and / or a graphics processing unit (GPU), a digital signal processing unit, a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, etc., but is not necessarily limited thereto.

[0137] The semiconductor device (200) may be an integrated circuit (IC) semiconductor chip (semiconductor die) in which various active and / or passive devices are integrated within a single chip. The semiconductor device (200) may also be provided as a sub-semiconductor package that constitutes a higher-level semiconductor package in which a plurality of sub-semiconductor packages are combined. The semiconductor package (10) may be mounted on a circuit board (100) such as a main board of an electronic device. The main board may be electrically connected to various electronic components. The semiconductor package may further include one or more interposers, in which case the circuit board (100) may not be directly connected to the semiconductor device (200) but may be connected to the semiconductor device (200) via one or more interposers, or may be directly connected to some of the semiconductor devices and connected to others via interposers.

[0138] A circuit board (100) according to an embodiment of the present invention may be a package board constituting a semiconductor package (10). The circuit board (100) may also be an interposer board that performs the function of an interposer coupled with another circuit board. The circuit board (100) may be provided as a bridge board including a redistribution layer. The circuit board (100) may have a space in which one or more semiconductor devices (200) and / or one or more interposers (not shown) can be mounted. The circuit board (100) may be coupled with the semiconductor devices (200) and / or interposers by bumps provided on a first surface (e.g., top surface) and / or a second surface (e.g., bottom surface).

[0139] In one embodiment, the circuit board (100) may be coupled to the terminals (210) of the semiconductor device (200) by bumps (160) provided on the upper surface, and may be coupled to the terminals (310) of the main board (300) of the electronic device by bumps (170) through electrode pads provided on the lower surface. When the circuit board (100) performs the function of an interposer, the circuit board (100) may be referred to as a first circuit board, and the package board or another interposer board on which the circuit board (100) is mounted may be referred to as a second circuit board.

[0140] The bumps (160) can serve to transmit signals and / or power between the circuit board (100) and the semiconductor device (200). Additionally, the bumps (160) may be connection parts that electrically connect the circuit board (100) and the semiconductor device (200). In addition to the electrical connection function, the bumps (160) can also perform a support and coupling function by physically supporting the semiconductor device (200) against the circuit board (100) to maintain the semiconductor device (200) in a stably fixed state on the circuit board (100) and to prevent it from being easily separated in the event of an external impact.

[0141] Bumps (160) can electrically connect the electrodes of the circuit board (100) and the terminals of the semiconductor device (200) using various methods such as solder bonding, plating, and metal-to-metal bonding. Solder bonding can be performed using materials such as Cu, Sn, and Ag, for example. The plating method may be a method of forming a plating layer by electroplating and / or electroless plating. The metal-to-metal bonding method may be a method of bonding bumps by applying heat and pressure to recrystallize them. At least some of the bumps (160) may be protrusions that protrude upward from the insulating layer of the circuit board (100). Accordingly, the protrusions of the bumps (160) may be referred to as pillars or posts.

[0142] The foregoing description is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented by being divided into multiple elements, and likewise, components described as multiple elements may be implemented as a single unit. The components of various embodiments may be combined and implemented together, provided they do not conflict with one another. Accordingly, it should be understood that new embodiments combining the various embodiments described above are also included in this disclosure. The scope of the invention is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and their equivalents should be interpreted as being included within the scope of the invention.

Claims

1. Glass layer; A metal layer disposed on the glass layer to plate a plating layer on the glass layer; and It includes an adhesive layer disposed between the glass layer and the metal layer, The adhesive layer comprises: a first adhesive layer disposed between the glass layer and the metal layer; and a second adhesive layer disposed between the first adhesive layer and the metal layer. Circuit board.

2. In Claim 1, The first adhesive layer comprises a first material, and the second adhesive layer comprises a second material different from the first material, A circuit board in which the first adhesive layer comprises an inorganic layer and the second adhesive layer comprises an organic layer.

3. In Claim 1, The circuit board, wherein the first adhesive layer comprises a silicon oxide layer formed by curing a coating layer containing polysilazane.

4. In Claim 1, A circuit board comprising a silane coating layer having a bonding group that bonds with a metal material of the metal layer, wherein the second adhesive layer comprises the above-mentioned second adhesive layer.

5. In Claim 1, The second adhesive layer has a second thickness that is thinner than the first thickness of the first adhesive layer, A circuit board having a first adhesive layer having a first thickness of 200 nm or more and 500 nm or less, and a second adhesive layer having a second thickness of 30 nm or more and 100 nm or less.

6. In Claim 1, A circuit board having a first adhesive layer having a surface roughness of greater than 0.03 μm and less than or equal to 0.5 μm.

7. In Claim 1, A circuit board having a hydrophilic group arranged by plasma treatment on the surface of the above glass layer.

8. In Claim 1, The upper surface of the first adhesive layer has a surface irregularity structure, The upper surface of the second adhesive layer has a second surface irregularity structure corresponding to the first surface irregularity structure of the first adhesive layer, A circuit board in which the surface irregularity structure of the first adhesive layer is at least one irregularity shape among a triangular protrusion, a square protrusion, a semicircular protrusion, and an elliptical protrusion.

9. In Claim 1, The above glass layer has a through hole penetrating between the upper surface and the lower surface of the above glass layer, The adhesive layer comprises an upper adhesive layer disposed on the upper surface of the glass layer and an inner adhesive layer disposed on the inner wall of the through hole. The first adhesive layer comprises a first upper adhesive layer disposed on the upper surface of the glass layer and a first inner adhesive layer disposed on the inner wall of the through hole. A circuit board comprising a second adhesive layer, wherein the second adhesive layer comprises a second upper adhesive layer disposed on the first upper adhesive layer and a second inner adhesive layer disposed on the first inner adhesive layer.

10. A semiconductor package comprising a circuit board according to any one of claims 1 to 9 and a semiconductor element disposed on said circuit board.

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