Method for manufacturing three-dimensional semiconductor device using atomic layer etching process

Abstract

The present invention relates to a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process. According to an embodiment, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, the method comprising: a first step of preparing a semiconductor device structure including a dielectric thin film, an etch stopper thin film, and a lower thin film through an atomic layer deposition (ALD) process; and a second step of atomic layer etching the dielectric thin film by performing an atomic layer etching (ALE) process including at least one etching cycle on the prepared semiconductor device structure.

Description

Method for manufacturing a 3D semiconductor device using an atomic layer etching process

[0001] The present invention relates to a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

[0002] Atomic layer etching (ALE) technology removes thin films layer by layer through self-limiting sequential reaction steps and offers the advantage of achieving uniform etching in 3D structures.

[0003] In particular, integrating this technology with area-selective atomic layer deposition (AS-ALD) can further improve selectivity by reducing surface chemical adsorption of precursors, and thanks to these advantages, ALE is recognized as a key process technology for realizing 3D structures in the DRAM field.

[0004] In addition, as the thickness of the dielectric thin film decreases, it has been reported that crystallinity degradation and an increase in the proportion of interfacial layers, such as low-dielectric (low-k) layers, occur, resulting in a decrease in capacitor performance. These problems can be solved by integrating ALD and ALE processes into a 3D structure. By depositing a sufficiently thick thin film using ALD and then performing precise etching using ALE, the target ultra-thin film thickness can be achieved even in a 3D structure, while maintaining excellent thin film characteristics.

[0005] Meanwhile, existing ALE processes have been studied primarily based on fluoride chemistry for metal oxide thin films. Metal fluorides can form surfaces that are thermodynamically more stable and reactive than metal oxides.

[0006] Specifically, all reported ALE processes for ZrO2 thin films and most oxide thin film processes to date have used HF as the first reactant to induce surface fluorination. However, due to handling difficulties, high toxicity, and corrosive properties, HF can cause problems that are difficult to resolve in process integration and equipment maintenance.

[0007] To overcome these problems, the present invention aims to provide a ZrO2ALE process utilizing NF3 plasma and TiCl4.

[0008] A method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to one embodiment of the present invention is proposed to solve the above-mentioned problems, and in the existing manufacturing process of a three-dimensional semiconductor device, it is possible to minimize the degradation of device performance caused by the reduction in crystallinity of the dielectric thin film and the increase in the ratio of the low dielectric constant interface layer.

[0009] In addition, the limitations associated with handling HF can be overcome by replacing the fluorination process using HF, which is toxic and corrosive, with a fluorination process using NF3 plasma.

[0010] According to one embodiment, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, comprising: a first step of preparing a semiconductor device structure including a dielectric thin film, an etch stopper thin film, and a bottom thin film through an atomic layer deposition (ALD) process; and a second step of performing an atomic layer etching process (ALE) including at least one etching cycle on the prepared semiconductor device structure to atomic layer etch the dielectric thin film.

[0011] In addition, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, wherein in the first step, the dielectric thin film comprises any one material selected from the group consisting of zirconia oxide (ZrO2), hafnium oxide (HfO2), and beryllium oxide (BeO), the etch stopper thin film comprises aluminum oxide (Al2O3), and the lower thin film comprises titanium nitride (TiN).

[0012] In addition, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, wherein in the second step above, the process temperature of the atomic layer etching process satisfies a temperature range of 100 to 300°C.

[0013] Additionally, the second step comprises: a fluorination step of exposing the dielectric thin film to a plasma-enhanced first reactant gas containing fluorine radicals (F*); a first purging step of purging the dielectric thin film exposed to the plasma-enhanced first reactant gas using an inert gas; an etching step of exposing the first purged dielectric thin film to a second reactant gas; and a second purging step of purging the dielectric thin film exposed to the second reactant gas using an inert gas; thereby providing a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

[0014] In addition, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, wherein the second step further comprises a plasma activation step in which, prior to the fluorination step, the semiconductor device structure and the first reactant gas are placed in a reaction chamber and RF high-frequency power is applied to induce plasma formation of the first reactant gas.

[0015] In addition, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, wherein the fluorination step is a step of forming a fluorinated atomic layer on the surface of the dielectric thin film through a fluorination reaction between the dielectric thin film and the fluorine radical (F*).

[0016] In addition, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, wherein the etching step is a step of forming a volatile etching byproduct through a ligand exchange reaction between the fluorinated atomic layer and the second reactant gas.

[0017] In addition, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, wherein in the fluorination step, the first reactant gas is NF3 gas, and in the etching step, the second reactant gas is any one material selected from the group consisting of methyl aluminum chloride (DMAC), silicon tetrachloride (SiCl4), and titanium tetrachloride (TiCl4).

[0018] Additionally, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, wherein the exposure process time of the fluorination step is performed for 1 to 5 seconds, the purging process time of the first purging step is performed for 80 to 120 seconds, the exposure process time of the etching step is performed for 8 to 12 seconds, and the purging process time of the second purging step is performed for 80 to 120 seconds.

[0019] In addition, a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process may be provided, further comprising: a third step of performing a first post-processing step of heat-treating an atomic layer etched dielectric thin film under preset heat treatment conditions after the second step; and a fourth step of performing a second post-processing step of plasma-treating the surface of the heat-treated dielectric thin film under preset plasma treatment conditions.

[0020] A method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to one embodiment of the present invention has the effect of minimizing the degradation of device performance caused by the reduction in crystallinity of dielectric thin films and the increase in the ratio of low dielectric constant interface layers in a conventional manufacturing process of a three-dimensional semiconductor device.

[0021] In addition, by replacing the fluorination process using HF, which is toxic and corrosive, with a fluorination process using NF3 plasma, it is possible to overcome the limitations associated with handling HF.

[0022] FIG. 1 is a flowchart briefly illustrating a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to one embodiment of the present invention.

[0023] FIG. 2 is a flowchart for explaining in detail a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to one embodiment of the present invention.

[0024] Figure 3 is a diagram showing the etching characteristics of a dielectric thin film according to an atomic layer etching process.

[0025] Figure 4 is a diagram showing the change in area density of the dielectric thin film and the change in area density of Ti according to the atomic layer etching process.

[0026] Figure 5 is a diagram showing the AES analysis results of a three-dimensional semiconductor device according to an atomic layer etching process.

[0027] Figure 6 is a diagram showing the electrical characteristics of a three-dimensional semiconductor device according to an atomic layer etching process.

[0028] Figure 7 is a diagram showing the etching characteristics of a dielectric thin film according to the process temperature of the atomic layer etching process.

[0029] In order to fully understand the structure and effects of the present invention, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

[0030] The present invention is not limited to the embodiments disclosed below, but can be implemented in various forms and subject to various modifications and changes. The description of the embodiments is provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention. In the attached drawings, the components are depicted enlarged from their actual size for convenience of explanation, and the proportions of each component may be exaggerated or reduced.

[0031] The terms used in this specification are for describing embodiments and are not intended to limit the invention. Furthermore, unless otherwise defined, the terms used in this specification may be interpreted in the sense commonly known to those skilled in the art. In this specification, the singular form includes the plural form unless specifically stated otherwise in the text. As used in this specification, 'comprises' and / or 'comprising' do not exclude the presence or addition of one or more other components, steps, actions, and / or elements to the mentioned components, steps, actions, and / or elements.

[0032] Where in this specification a layer is referred to as being 'on' another layer, it may be formed directly on the upper surface of the other layer, or a third layer may be interposed between them. Although terms such as first, second, etc., have been used in this specification to describe various regions, layers, etc., these regions and layers should not be limited by such terms. These terms are used merely to distinguish one specific region or layer from another region or layer. Accordingly, a part referred to as the first part in one embodiment may be referred to as the second part in another embodiment. The embodiments described and illustrated herein also include their complementary embodiments. Throughout the specification, parts indicated by the same reference numeral represent the same components.

[0033] The present invention relates to a method for fabricating a three-dimensional semiconductor device that can secure precise thickness control and improved electrical performance by performing an atomic layer etching process on a dielectric thin film.

[0034] Specifically, unlike conventional atomic layer etching processes utilizing HF, the present invention can precisely etch dielectric thin films using NF3 plasma and TiCl4.

[0035]

[0036] Method for manufacturing a 3D semiconductor device using an atomic layer etching process

[0037] FIG. 1 is a flowchart for briefly explaining a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to one embodiment of the present invention, and FIG. 2 is a flowchart for explaining in detail a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to one embodiment of the present invention.

[0038] First, referring to FIGS. 1 and 2, a method (S10) for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to an embodiment of the present invention includes a first step (S100) of preparing a semiconductor device structure including a dielectric thin film, an etch stopper thin film, and a bottom thin film through an atomic layer deposition process (ALD), and a second step (S200) of atomic layer etching (ALE) including at least one etching cycle on the prepared semiconductor device structure to atomic layer etch the dielectric thin film.

[0039] First, in a method (S10) for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to one embodiment of the present invention, the first step (S100) is a step of preparing a semiconductor device structure to perform an atomic layer etching process.

[0040] The semiconductor device structure may include various device structures formed by an atomic layer deposition (ALD) process. For example, the semiconductor device structure may have the structure of a Dynamic Random Access Memory (DRAM) cell transistor, 3D-NAND Flash Memory, Fin Field-Effect Transistor (FinFET), Multi-Bridge Channel Field-Effect Transistor (MBCFET), Gate-All-Around (GAA) type semiconductor, and DRAM capacitor, and specifically includes a dielectric thin film, an etch stopper thin film, and a bottom thin film.

[0041] In a preferred embodiment of the present invention, the semiconductor device structure may be a capacitor structure having the structure of a DRAM capacitor.

[0042] The lower thin film may be a substrate or a lower electrode, and the substrate may include a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, InGaAs, or InP. Additionally, the lower electrode may include titanium nitride (TiN).

[0043] In a preferred embodiment of the present invention, the lower thin film is a lower electrode and may include titanium nitride (TiN).

[0044] The etch stopper thin film can be placed on the lower thin film and can prevent damage to the lower thin film during the atomic layer etching process.

[0045] The etch stopper thin film is not etched by the fluorination reaction and ligand exchange reaction described later when the atomic layer etching process is performed, and specifically, it may include a material that is resistant to chemicals such as fluorine radicals (F*) and titanium tetrachloride (TiCl4) used in the atomic layer etching process.

[0046] In a preferred embodiment of the present invention, the etch stopper thin film may include aluminum oxide (Al2O3).

[0047] The dielectric thin film is an etching target layer that is etched through an atomic layer etching process, and can be selectively etched by the fluorination reaction and ligand exchange reaction described later.

[0048] In a preferred embodiment of the present invention, the dielectric thin film may comprise any one material selected from the group consisting of zirconia oxide (ZrO2), hafnium oxide (HfO2), and beryllium oxide (BeO).

[0049] In one embodiment of the present invention, the first step (S100) is described as follows: an aluminum oxide (Al2O3) thin film, which is an etch stopper thin film, can be deposited on the underlying thin film through an atomic layer deposition process before the dielectric thin film is deposited. Trimethylaluminum (TMA, Al(CH3)3) can be used as the Al precursor and H2O as the reactant, and the Al2O3 deposition can be completed by sequentially performing the processes of Al injection (0.1 sec), Ar purging (30 sec), H2O injection (0.5 sec), and Ar purging (30 sec) at 200°C.

[0050] After this, the dielectric thin film can be deposited on the aluminum oxide (Al2O3) thin film.

[0051] When the dielectric thin film is zirconia oxide (ZrO2), cyclopentadienyl tris(dimethylamino) zirconium (ZAC, CpZr(N(CH3)2)3) is used as the Zr precursor, and O3 (200 g / m²) is used as the reactant. 3 ) can be used. ZrO2 deposition can be completed by sequentially performing the processes of Zr injection (6 seconds), Ar purging (10 seconds), O3 injection (6 seconds), and Ar purging (15 seconds) at 300°C.

[0052] In addition, to ensure high crystallinity of the ZrO2 thin film deposited on the Al2O3 thin film, rapid thermal annealing (RTA) can be performed in an N2 atmosphere at 600°C for 1 minute after ZrO2 deposition.

[0053] Next, in a method (S10) for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to one embodiment of the present invention, the second step (S200) is a step of performing an atomic layer etching process on a prepared semiconductor device structure.

[0054] The atomic layer etching process of the present invention can be applied to the manufacture of three-dimensional semiconductor devices including a structure in which a metal, a dielectric thin film, and a metal are stacked. For example, it can be applied to the manufacture of devices such as capacitors having a Metal-Insulator-Metal (MIM) structure. Furthermore, the atomic layer etching process of the present invention can be applied without limitation to form oxide films in various three-dimensional semiconductor devices including metal thin films and dielectric thin films.

[0055] In the second step (S200), the atomic layer etching process may be carried out in at least one etching cycle, and the process temperature of the atomic layer etching process satisfies a temperature range of 100 to 300°C, and in a preferred embodiment, the process temperature of the atomic layer etching process may be 200 to 250°C.

[0056] Specifically, in one embodiment of the present invention, the second step (S200) may include a fluorination step (S210) of exposing the dielectric thin film to a plasma-enhanced first reactant gas containing fluorine radicals (F*), a first purging step (S220) of purging the dielectric thin film exposed to the plasma-enhanced first reactant gas using an inert gas, an etching step (S230) of exposing the first purged dielectric thin film to a second reactant gas, and a second purging step (S240) of purging the dielectric thin film exposed to the second reactant gas using an inert gas.

[0057] The fluorination step (S210) may refer to a process of supplying fluorine radicals (F*) through a plasma-formed first reactant gas on a dielectric thin film to convert the surface of the dielectric thin film into a fluorinated atomic layer.

[0058] Specifically, the fluorination step (S210) may be a step of forming a fluorinated atomic layer on the surface of the dielectric thin film through a fluorination reaction between the dielectric thin film and the fluorine radical (F*). Here, the first reactant gas may be NF3 gas, and the fluorinated atomic layer may be composed of a metal fluoride.

[0059] For example, if the dielectric thin film is zirconia oxide (ZrO2), the above-mentioned fluorination reaction may proceed according to the following chemical formula 1, and the fluorinated atomic layer is zirconia fluoride (ZrF4).

[0060]

[0061] [Chemical Formula 1]

[0062] ZrO2(s) + 4F - (g) → ZrF4(s) + O2(g) + 4e -

[0063]

[0064] In addition, the plasma-formed first reactant gas may contain various components such as radicals, electrons, and ions, and the radicals may be electrically polarized fluorine radicals. Furthermore, when the radicals are used in the etching process, other components excluding the relevant components may be removed, and only the radicals required for the etching process may be supplied to the reaction chamber.

[0065] In addition, in one embodiment of the present invention, the exposure process time of the fluorination step (S210) is preferably performed for 1 to 5 seconds.

[0066] The first purging step (S220) is a step of supplying inert gas after the fluorination step (S210).

[0067] The first purging step (S220) uses an inert gas to purge the interior of the reaction chamber where the atomic layer etching process is performed, thereby removing residual gas, dispersions, etc. The inert gas may include N2, Ne, Ar, Kr, Xe, and Rn, and is preferably argon (Ar) gas.

[0068] In addition, in one embodiment of the present invention, the purging process time of the first purging step (S220) is preferably performed for 80 to 120 seconds.

[0069] The etching step (S230) may refer to a process of supplying a second reactant gas onto a first-purged dielectric thin film after the first-purging step (S220) to convert a fluorinated atomic layer into a volatile etching byproduct.

[0070] Specifically, the etching step (S230) may be a step of forming a volatile etching byproduct through a ligand exchange reaction between the fluorinated atomic layer and the second reactant gas. Here, the second reactant gas may be any one of the substances selected from the group consisting of methyl aluminum chloride (DMAC), silicon tetrachloride (SiCl4), and titanium tetrachloride (TiCl4), and the volatile etching byproduct may consist of metal fluoride and metal chloride.

[0071] For example, when the fluorinated atomic layer is zirconia fluoride (ZrF4) and the second reactant gas is titanium tetrachloride (TiCl4), the ligand exchange reaction may proceed according to the following chemical formula 2, and the volatile etching byproduct may consist of titanium fluoride (TiF4) and zirconia chloride (ZrCl4).

[0072]

[0073] [Chemical Formula 2]

[0074] ZrF4(s) + TiCl4(g) → TiF4(g) + ZrCl4(g)

[0075]

[0076] When the fluorinated atomic layer is completely removed in the etching step (S230), the ligand exchange reaction is terminated, and since the volatile etching byproduct is a gaseous phase, no additional solid phase or impurities remain on the surface of the dielectric thin film.

[0077] In addition, in one embodiment of the present invention, the exposure process time of the etching step (S230) is preferably performed for 8 to 12 seconds.

[0078] The second purging step (S240) is a step of supplying an inert gas after the etching step (S230).

[0079] The second purging step (S240) uses an inert gas to purge the interior of the reaction chamber where the atomic layer etching process is performed, thereby removing residual gas, dispersions, etc. The inert gas may include N2, Ne, Ar, Kr, Xe, and Rn, and is preferably argon (Ar) gas.

[0080] In addition, in one embodiment of the present invention, the purging process time of the second purging step (S240) is preferably performed for 80 to 120 seconds.

[0081] Thus, as the second step (S200) is performed, the surface of the dielectric thin film can be etched to an atomic scale level, which means that the thickness of the dielectric thin film can be controlled to an atomic scale level.

[0082] A second step (S200) according to one embodiment of the present invention may further include a plasma activation step (S205) prior to the fluorination step (S210), wherein the semiconductor device structure and the first reactant gas are placed in a reaction chamber and RF high-frequency power is applied to induce plasma formation of the first reactant gas.

[0083] In the plasma activation step (S205), the RF high frequency power can satisfy the range of 250 to 350 W, and the supply rate of the first reactant gas can satisfy the range of 15 to 25 sccm.

[0084] In the plasma activation step (S205), plasma formation of the first reactant gas can be performed by igniting with 100 sccm of argon gas and supplying 15 to 25 sccm of the first reactant gas.

[0085] Meanwhile, in the second step (S200), there is a possibility that the lower thin film may be damaged as fluorine radicals (F*) react with TiN through the plasma-generated first reactant gas to form volatile compounds such as titanium fluoride (TiF4), but the etch stopper thin film of the present invention can effectively prevent such damage to the lower thin film.

[0086] For example, when the etch stopper thin film is aluminum oxide (Al2O3) and the second reactant gas is titanium tetrachloride (TiCl4), the ligand exchange reaction can proceed according to Chemical Formula 3 below, but the reaction according to Chemical Formula 3 below is thermodynamically difficult to occur spontaneously because the change in free energy at the process temperature of the atomic layer etching process is greater than 0.

[0087]

[0088] [Chemical Formula 3]

[0089] 4 / 3AlF3(s) + TiCl4(g) → 4 / 3AlCl3(g) + TiF4(g)

[0090]

[0091] That is, since the etch stopper thin film is not etched by the fluorination reaction and ligand exchange reaction in the second step (S200), damage to the underlying thin film can be effectively prevented.

[0092] In addition, the atomic layer etching process in the second step (S200) can reduce the oxidized titanium nitride (TiON) in the underlying thin film.

[0093] The above oxidized titanium nitride (TiON) is generated as the titanium nitride (TiN) is oxidized by exposure to O3 through the atomic layer deposition process of the first step (S100), and the atomic layer etching process of the second step (S200) can reduce the oxidized titanium nitride (TiON) to minimize the degradation of the physical properties of the underlying thin film.

[0094] A method (S10) for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to one embodiment of the present invention may further include, after the second step (S200), a third step (S300) of performing a first post-processing process of heat-treating an atomic layer etched dielectric thin film under a preset heat treatment condition, and a fourth step (S400) of performing a second post-processing process of plasma-treating the surface of the heat-treated dielectric thin film under a preset plasma treatment condition.

[0095] Step 3 (S300) may refer to a process of annealing the atomic layer etched dielectric thin film after Step 2 (S200) to improve the crystallinity of the dielectric thin film.

[0096] Specifically, the third step (S300) may perform a first post-processing step of heat-treating the atomic layer-etched dielectric thin film at a heat treatment temperature of 500 to 700°C for 0.5 to 2 minutes under a nitrogen atmosphere. Here, the first post-processing step may be rapid thermal annealing (RTA).

[0097] Accordingly, since the crystallinity of the dielectric thin film etched atomic layer through the third step (S300) is restored, the deterioration of the electrical performance of the dielectric thin film can be prevented.

[0098] Step 4 (S400) may refer to a process of reducing oxygen defects within the dielectric thin film by plasma treating the surface of the heat-treated dielectric thin film after Step 3 (S300).

[0099] Specifically, the fourth step (S400) may perform a second post-processing process in which the heat-treated dielectric thin film is plasma treated under conditions satisfying RF high-frequency power of 250 to 350 W, oxygen gas supply rate of 80 to 120 sccm, and plasma process temperature of 200 to 300°C. Here, the second post-processing process may be an oxygen plasma treatment process.

[0100] Accordingly, through the fourth step (S400), oxygen defects in the atomic layer etched dielectric thin film can be reduced, thereby minimizing the occurrence of leakage current.

[0101]

[0102] Example 1: Manufacture of a capacitor using an atomic layer etching process 1

[0103] S100: Trimethylaluminum (TMA, Al(CH3)3) was used as the Al precursor and H2O was used as the reactant. The Al precursor injection (0.1 sec), Ar purging (30 sec), H2O injection (0.5 sec), and Ar purging (30 sec) processes were performed sequentially at 200°C to deposit an Al2O3 thin film on a TiN bottom thin film through ALD.

[0104] Subsequently, Cyclopentadienyl tris(dimethylamino) zirconium (ZAC, CpZr(N(CH3)2)3) was used as the Zr precursor, and O3 (200 g / m²) was used as the reactant. 3 Using ), the process of Zr precursor injection (6 seconds), Ar purging (10 seconds), O3 injection (6 seconds), and Ar purging (15 seconds) was performed sequentially at 300℃ to deposit a ZrO2 thin film on an Al2O3 thin film through ALD.

[0105] In addition, to ensure high crystallinity of the ZrO2 thin film deposited on the Al2O3 thin film, rapid thermal annealing (RTA) was performed in an N2 atmosphere at 600°C for 1 minute after ZrO2 deposition to prepare a capacitor structure composed of ZrO2 / Al2O3 / TiN.

[0106] S200: An atomic layer etching process including multiple etching cycles was performed on a prepared capacitor structure (ZrO2 / A2O3 / TiN) to atomic layer etch a ZrO2 thin film. Here, the process temperature of the atomic layer etching process was carried out to satisfy a temperature of 250°C.

[0107] Specifically, the atomic layer etching process involved introducing a prepared capacitor structure (ZrO2 / Al2O3 / TiN) and NF3 gas, a first reactant gas, into a reaction chamber, applying 300W of RF high-frequency power to induce plasma formation of the NF3 gas, exposing the ZrO2 thin film to the plasma-formed NF3 gas containing fluorine radicals (F*) for 3 seconds, performing a first purging of the ZrO2 thin film exposed to the plasma-formed NF3 gas using argon gas for 100 seconds, exposing the first-purged ZrO2 thin film to titanium tetrachloride (TiCl4) gas for 10 seconds, and performing a second purging of the ZrO2 thin film exposed to titanium tetrachloride (TiCl4) gas using argon gas for 100 seconds to produce a capacitor sample containing an atomic layer etched ZrO2 thin film (Example 1).

[0108]

[0109] Example 2: Fabrication of a capacitor using an atomic layer etching process 2

[0110] S100, S200: Steps S100 and S200 were performed in the same manner as in Example 1 to prepare a capacitor sample containing an atomic layer etched ZrO2 thin film.

[0111] S300: A capacitor sample containing a heat-treated ZrO2 thin film was prepared by RTA treatment of the prepared capacitor sample at 600°C for 1 minute under a nitrogen (N2) atmosphere (Example 2).

[0112]

[0113] Example 3: Manufacture of a capacitor using an atomic layer etching process 3

[0114] S100, S200, S300: A capacitor sample containing a heat-treated ZrO2 thin film was prepared by performing steps S100, S200, and S300 in the same manner as in Example 1.

[0115] S400: A capacitor sample was prepared by treating the prepared capacitor sample with oxygen (O2) plasma under conditions satisfying RF high frequency power of 300 W, oxygen gas supply rate of 100 sccm, and plasma process temperature of 250℃ to prepare a capacitor sample containing a plasma-treated ZrO2 thin film (Example 3).

[0116]

[0117] Comparative Example 1: Manufacture of a capacitor using an atomic layer etching process 1

[0118] S100: Cyclopentadienyl tris(dimethylamino) zirconium (ZAC, CpZr(N(CH3)2)3) is used as the Zr precursor, and O3 (200 g / m²) is used as the reactant. 3 Using ), the process of Zr precursor injection (6 seconds), Ar purging (10 seconds), O3 injection (6 seconds), and Ar purging (15 seconds) was performed sequentially at 300℃ to deposit a ZrO2 thin film on a Si bottom thin film through ALD.

[0119] In addition, to ensure high crystallinity of the deposited ZrO2 thin film, a capacitor structure made of ZrO2 / Si was prepared by performing rapid thermal annealing (RTA) in an N2 atmosphere at 600°C for 1 minute after ZrO2 deposition.

[0120] S200: An atomic layer etching process including multiple etching cycles was performed on a prepared capacitor structure (ZrO2 / Si) to atomic layer etch a ZrO2 thin film. Here, the process temperature of the atomic layer etching process was carried out to satisfy a temperature of 250°C.

[0121] Specifically, the atomic layer etching process involved introducing a prepared capacitor structure (ZrO2 / Si) and NF3 gas, a first reactant gas, into a reaction chamber, applying 300W of RF high-frequency power to induce plasma formation of the NF3 gas, exposing the ZrO2 thin film to plasma-formed NF3 gas containing fluorine radicals (F*) for 3 seconds, performing a first purging of the ZrO2 thin film exposed to the plasma-formed NF3 gas using argon gas for 100 seconds, exposing the first-purged ZrO2 thin film to titanium tetrachloride (TiCl4) gas for 10 seconds, and performing a second purging of the ZrO2 thin film exposed to titanium tetrachloride (TiCl4) gas using argon gas for 100 seconds to produce a capacitor sample containing an atomic layer etched ZrO2 thin film (Comparative Example 1).

[0122]

[0123] Comparative Example 2: Manufacture of a capacitor using an atomic layer etching process 2

[0124] S100: Cyclopentadienyl tris(dimethylamino) zirconium (ZAC, CpZr(N(CH3)2)3) is used as the Zr precursor, and O3 (200 g / m²) is used as the reactant. 3 Using ), the process of Zr precursor injection (6 seconds), Ar purging (10 seconds), O3 injection (6 seconds), and Ar purging (15 seconds) was performed sequentially at 300℃ to deposit a ZrO2 thin film on a TiN bottom thin film through ALD.

[0125] In addition, to ensure high crystallinity of the deposited ZrO2 thin film, a capacitor structure made of ZrO2 / TiN was prepared by performing rapid thermal annealing (RTA) in an N2 atmosphere at 600°C for 1 minute after ZrO2 deposition.

[0126] S200: An atomic layer etching process including multiple etching cycles was performed on a prepared capacitor structure (ZrO2 / TiN) to atomic layer etch a ZrO2 thin film. Here, the process temperature of the atomic layer etching process was carried out to satisfy temperatures of 150℃, 200℃, 250℃, and 300℃.

[0127] Specifically, the atomic layer etching process involved introducing a prepared capacitor structure (ZrO2 / TiN) and NF3 gas, a first reactant gas, into a reaction chamber, applying 300W of RF high-frequency power to induce plasma formation of the NF3 gas, exposing the ZrO2 thin film to plasma-formed NF3 gas containing fluorine radicals (F*) for 3 seconds, performing a first purging of the ZrO2 thin film exposed to the plasma-formed NF3 gas using argon gas for 100 seconds, exposing the first-purged ZrO2 thin film to titanium tetrachloride (TiCl4) gas for 10 seconds, and performing a second purging of the ZrO2 thin film exposed to titanium tetrachloride (TiCl4) gas using argon gas for 100 seconds to produce a capacitor sample containing an atomic layer etched ZrO2 thin film (Comparative Example 2).

[0128] Here, the capacitor sample with an atomic layer etching process temperature of 150°C is Sample A of Comparative Example 2, the capacitor sample with an atomic layer etching process temperature of 200°C is Sample B of Comparative Example 2, the capacitor sample with an atomic layer etching process temperature of 250°C is Sample C of Comparative Example 2, and the capacitor sample with an atomic layer etching process temperature of 300°C is Sample D of Comparative Example 2.

[0129]

[0130] Experimental Example 1: Evaluation of Etching Amount and Thickness Change of Dielectric Thin Film

[0131] Samples of Example 1 were prepared, and the etching amount per cycle of the dielectric thin film, the thickness of the dielectric thin film per cycle, and the area density of the dielectric thin film were analyzed, and the results are shown in Figure 3. The thickness of the dielectric thin film was analyzed using an ellipsometer, and the area density of the dielectric thin film was analyzed using X-ray fluorescence analysis.

[0132] Figure 3 is a diagram showing the etching characteristics of a dielectric thin film according to an atomic layer etching process.

[0133] Figure 3a) is a diagram showing the amount of etching of a dielectric thin film according to the exposure time of plasma-enhanced NF3 gas, Figure 3b) is a diagram showing the amount of etching of a dielectric thin film according to the exposure time of titanium tetrachloride (TiCl4) gas, Figure 3c) is a diagram showing the amount of etching of a dielectric thin film according to the exposure time of argon gas, and Figure 3d) is a diagram showing the change in thickness of a dielectric thin film according to the cycle of the atomic layer deposition process.

[0134] As shown in Figure 3, the etching amount of the ZrO2 thin film increased as the exposure time of the plasma-generated NF3 gas increased, and it was confirmed that the etching amount of the ZrO2 thin film did not increase further when the exposure time was 3 seconds or more. In addition, it was confirmed that the etching amount of the ZrO2 thin film was highest when the exposure time of titanium tetrachloride (TiCl4) gas was 10 seconds, and the etching amount of the ZrO2 thin film was highest when the purge time of argon gas was 100 seconds.

[0135] In addition, it was confirmed that as the number of cycles of the atomic layer etching process increases, the change in thickness and area density of the ZrO2 thin film increases linearly.

[0136]

[0137] Experimental Example 2: Change in Area Density of Dielectric Thin Film and Evaluation of Ti Area Density

[0138] Sample C of Comparative Example 2 and samples of Comparative Example 1, Example 1, and Example 2 were prepared, and after analyzing the change in area density per cycle and the Ti area density per dielectric thin film thickness, the results are shown in Fig. 4.

[0139] Figure 4 is a diagram showing the change in area density of the dielectric thin film and the change in area density of Ti according to the atomic layer etching process.

[0140] FIG. 4a) is a graph showing the change in area density of dielectric thin films according to samples of comparative examples and examples, and FIG. 4b) is a graph showing the Ti area density according to samples of comparative examples and examples.

[0141] As shown in Fig. 4a), it was confirmed that the change in area density of the ZrO2 thin film increases linearly as the number of cycles of the atomic layer etching process increases in Sample C of Comparative Example 1 and Comparative Example 2, and Samples of Example 1 and Example 2.

[0142] As shown in Fig. 4b), Sample C of Comparative Example 2 exhibited a characteristic where the area density of Ti decreased as the thickness of the ZrO2 thin film decreased. This can be interpreted through the chemical reaction mechanism of TiN during the atomic layer deposition process; specifically, during the atomic layer deposition process, the oxidizing agent O3 oxidizes the TiN surface, and during the atomic layer etching process, fluoride radicals react with the oxidized titanium nitride (TiON) to form TiF x It can form volatile compounds such as.

[0143] In other words, this means that atomic layer etching, which should only occur in ZrO2 thin films, can also occur in the TiN underlying thin film.

[0144] On the other hand, in the case of Examples 1 and 2, it was confirmed that the area density of Ti remained the same even when the thickness of the ZrO2 thin film was reduced, which means that the Al2O3 thin film, which is an etch stopper thin film, effectively prevented damage to the TiN underlying thin film.

[0145]

[0146] Experimental Example 3: Evaluation of Atomic Concentration in Capacitor Samples

[0147] Sample C of Comparative Example 2 and Sample C of Comparative Example 2 were each prepared before the atomic layer etching process, and after analyzing the atomic concentration of the prepared samples, the results are shown in FIG. 5.

[0148] In addition, samples of Example 1 and samples of Example 1 were prepared separately before the atomic layer etching process, and after analyzing the atomic concentration and surface roughness of the prepared samples, the results are shown in Fig. 5.

[0149] Figure 5 is a diagram showing the AES analysis results of a three-dimensional semiconductor device according to an atomic layer etching process.

[0150] FIG. 5a) is the result of an AES depth profile analysis according to sample C of Comparative Example 2 before the atomic layer etching (ALE) process, FIG. 5b) is the result of an AES depth profile analysis according to sample C of Comparative Example 2, FIG. 5c) is the result of an AES depth profile analysis according to the sample of Example 1 before the atomic layer etching (ALE) process, and FIG. 5d) is the result of an AES depth profile analysis according to the sample of Example 1.

[0151] As shown in FIGS. 5a) and 5b), when examining Sample C of Comparative Example 2 before the atomic layer etching (ALE) process, it can be confirmed that the oxidizing agent O3 oxidizes the TiN surface during the atomic layer deposition process, and that oxidized titanium nitride (TiON) exists on the surface of the TiN underlying thin film. In addition, it was confirmed that active interdiffusion of atoms occurs between the ZrO2 thin film and the TiN underlying thin film after ALE.

[0152] As shown in FIGS. 5a) and 5c), when examining the sample of Example 1 before the atomic layer etching (ALE) process, it can be confirmed that the oxidizing agent O3 oxidizes the TiN surface during the atomic layer deposition process, and that oxidized titanium nitride (TiON) exists on the surface of the TiN underlying film. However, after ALE, it was confirmed that the Al2O3 film, which is an etch stopper film, effectively suppresses the interdiffusion of atoms between the ZrO2 film and the TiN underlying film.

[0153] In addition, looking at Figures 5b) and 5d), it was confirmed that some of the oxidized titanium nitride (TiON) was reduced after ALE, and this reduction effect was more clearly observed in the sample of Example 1.

[0154] In other words, since the reduction of oxidized titanium nitride (TiON) generally causes a degradation of the capacitor's physical properties, it was confirmed that the presence of an Al2O3 thin film, which is an etch stopper thin film, can suppress the degradation of the capacitor's physical properties in ALE.

[0155] In addition, as a result of analyzing the surface roughness of the sample of Example 1 before the atomic layer etching process and the sample of Example 1, the surface roughness of the ZrO2 thin film before the atomic layer etching process was 0.826 nm, and the surface roughness of the ZrO2 thin film after the atomic layer etching process was 1.708 nm.

[0156]

[0157] Experimental Example 4: Evaluation of Electrical Characteristics

[0158] Sample C of Comparative Example 2, Sample C of Comparative Example 2, Sample of Example 1, Sample of Example 1, Sample of Example 2, Sample of Example 2, Sample of Example 3, and Sample of Example 3 were each prepared before the atomic layer etching process, and after analyzing the electrical characteristics of the prepared samples, the results are shown in FIG. 6.

[0159] Figure 6 is a diagram showing the electrical characteristics of a three-dimensional semiconductor device according to an atomic layer etching process.

[0160] To evaluate the electrical characteristics of the prepared samples, metal-dielectric-metal capacitor samples were fabricated using Au as the top thin film (top electrode).

[0161] FIG. 6a) is a graph showing the electrical characteristics according to sample C of Comparative Example 2, FIG. 6b) is a graph showing the electrical characteristics according to the sample of Example 1, FIG. 6c) is a graph showing the electrical characteristics according to the sample of Example 2, and FIG. 6d) is a graph showing the electrical characteristics according to the samples of Comparative Example and Example.

[0162] As shown in FIG. 6a), sample C of Comparative Example 2 is t ox wa t phy It was confirmed that linearity did not appear in the relationship.

[0163] In other words, generally t ox is the t of the ZrO2 thin film phy As it decreases, it decreases linearly, but Sample C of Comparative Example 2 did not show leading tendency.

[0164] As shown in Figs. 6b) and 6c), the samples of Example 1 and Example 2 exhibited electrical characteristics showing excellent linearity after ALE due to the presence of an Al2O3 thin film, which is an etch stopper thin film.

[0165] As shown in Fig. 6d), it was confirmed that as the ALE cycle increases, the leakage current generally increases due to the decrease in the thickness of the dielectric thin film, the degradation of the Al2O3 thin film, and the increase in oxygen defects within the dielectric thin film.

[0166] On the other hand, in the case of the sample of Example 3, the leakage current density was clearly reduced as oxygen plasma treatment was performed as a post-processing step, thereby confirming that oxygen plasma treatment is an effective method to reduce oxygen defects in the ZrO2 thin film and mitigate leakage current.

[0167]

[0168] Experimental Example 5: Evaluation of Etching Amount by Process Temperature

[0169] Samples A to D of Comparative Example 2 were prepared, and the etching amount of the prepared samples according to process temperature was analyzed, and the results are shown in FIG. 7.

[0170] Figure 7 is a diagram showing the etching characteristics of a dielectric thin film according to the process temperature of the atomic layer etching process.

[0171] As shown in Figure 7, it was confirmed that the etching amount per cycle of the ZrO2 thin film depends on the process temperature of the ALE. The etching amount was lowest when the process temperature of the ALE was 150°C, which means that an incomplete etching process occurs.

[0172] In addition, the etching amount was highest when the process temperature of ALE was 300℃, but given that the etching amount increased rapidly, it means that it exhibits sputtering behavior rather than a self-limiting surface reaction.

[0173] That is, it was confirmed that the process temperature of the ALE of the present invention preferably satisfies the range of 200 to 250℃.

[0174]

[0175] Although a method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process according to an embodiment of the present invention has been described as a specific embodiment, this is merely an example and the present invention is not limited thereto, and should be interpreted as having the broadest scope in accordance with the basic concept disclosed in this specification. Those skilled in the art may implement unspecified embodiments by combining or substituting the disclosed embodiments, and this also does not deviate from the scope of the rights of the present invention. In addition, those skilled in the art may easily change or modify the embodiments disclosed based on this specification, and it is evident that such changes or modifications also fall within the scope of the rights of the present invention.

Claims

1. A first step of preparing a semiconductor device structure including a dielectric thin film, an etch stopper thin film, and a bottom thin film through an atomic layer deposition (ALD) process; and A second step of atomic layer etching (ALE) including at least one etching cycle on a prepared semiconductor device structure to atomic layer etch the dielectric thin film; comprising Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

2. In Paragraph 1, In the first step above, The above dielectric thin film comprises any one material selected from the group consisting of zirconia oxide (ZrO2), hafnium oxide (HfO2), and beryllium oxide (BeO). The above etch stopper thin film comprises aluminum oxide (Al2O3), and The above lower thin film comprises titanium nitride (TiN), Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

3. In Paragraph 2, In the second step above, The process temperature of the above atomic layer etching process satisfies a temperature range of 100 to 300℃, Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

4. In Paragraph 3, The above second step is, A fluorination step of exposing the above dielectric thin film to a plasma-enhanced first reactant gas containing fluorine radicals (F*); A first purging step of primary purging a dielectric thin film exposed to a plasma-activated first reactant gas using an inert gas; An etching step of exposing a primary purged dielectric thin film to a second reactant gas; and A second purging step comprising a dielectric thin film exposed to a second reactant gas and a second purging step using an inert gas; Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

5. In Paragraph 4, The above second step is, A plasma activation step further comprising, prior to the fluorination step, introducing the semiconductor device structure and the first reactant gas into a reaction chamber and applying RF high-frequency power to induce plasma formation of the first reactant gas; Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

6. In Paragraph 5, The above fluorination step is, A step of forming a fluorinated atomic layer on the surface of the dielectric thin film through a fluorination reaction between the dielectric thin film and the fluorine radical (F*), Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

7. In Paragraph 6, The above etching step is, A step of forming a volatile etching byproduct through a ligand exchange reaction between the fluorinated atomic layer and the second reactant gas, Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

8. In Paragraph 7, In the above fluorination step, The first reactant gas is NF3 gas, and In the above etching step, The second reactant gas is any one substance selected from the group consisting of methyl aluminum chloride (DMAC), silicon tetrachloride (SiCl4), and titanium tetrachloride (TiCl4), Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

9. In Paragraph 7, The exposure process time of the above fluorination step is performed for 1 to 5 seconds, and The purging process time of the first purging step is performed for 80 to 120 seconds, and The exposure process time of the above etching step is performed for 8 to 12 seconds, and The purging process time of the second purging step above is performed for 80 to 120 seconds, Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

10. In Paragraph 1, After the above second step, A third step of performing a first post-processing step of heat-treating an atomic layer-etched dielectric thin film under preset heat treatment conditions; and A fourth step of performing a second post-processing step of plasma treating the surface of a heat-treated dielectric thin film under preset plasma treatment conditions; further comprising Method for manufacturing a three-dimensional semiconductor device using an atomic layer etching process.

Images