Method for etching group iii-v materials

Abstract

An embodiment of the present invention provides a method for etching Group III-V materials stacked on a substrate. According to an embodiment of the present invention, the method comprises a damage region removal step for performing atomic layer etching in order to remove ion damage on the surface of Group III-V materials, and thus has the advantage of being able to remove damaging regions more efficiently than conventional wet-etching processes.

Description

Etching method for III-V group materials

[0001] The present invention relates to an etching method, and more specifically, to a method for etching a III-V group material within a device.

[0002] As the pattern CD (Critical Dimension) decreases, dry etching is being used to replace wet etching in displays.

[0003] However, during dry etching using a plasma process, the performance of the Multi-Quantum Well (MQW) layer degrades due to ion damage, adversely affecting the performance of the applied display. Therefore, there is a need for a method to eliminate such ion damage in order to perform dry etching.

[0004] Previously, ion damage was removed through wet etching using KOH, but this method was dangerous due to long process times and the use of various liquids, and the damage removal was not perfect. Accordingly, there is a need for a method that can reliably remove damage to the MQW layer while having a short process time and avoiding dangerous processes.

[0005]

[0006] [Prior Art Literature]

[0007] (Patent Document 0001) Republic of Korea Registered Patent Publication No. 10-1471621

[0008] The present invention aims to improve the characteristics of a finally manufactured device by removing ion damage formed during the plasma etching process through a plasma atomic layer etching process, as a method to solve the problems of the aforementioned prior art.

[0009] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the present invention belongs from the description below.

[0010] To achieve the above technical problem, one embodiment of the present invention provides a method for etching a III-V group material stacked on a substrate.

[0011] An etching method according to one embodiment of the present invention is characterized by comprising: a plasma etching step of etching the III-V group material using plasma; and a damage region removal step of performing atomic layer etching to remove ion damage on the surface of the III-V group material formed by the plasma etching.

[0012] In an embodiment of the present invention, the damaged region removal step may include an adsorption step of exposing the damaged region to a plasma containing a halogen gas; and a desorption step of applying a bias voltage to the substrate while exposing the damaged region to a plasma containing an inert gas.

[0013] In an embodiment of the present invention, the adsorption step may be provided with a source power of 50 W to 300 W for plasma generation, and the desorption step may be provided with a source power of approximately 50 W to 150 W for plasma generation.

[0014] In an embodiment of the present invention, a wet etching step may be further included between the plasma etching step and the damaged area removal step.

[0015] In an embodiment of the present invention, the halogen gas may be chlorine (Cl2), chlorine triboride (BCl3), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), iodide heptafluoride (IF7), sulfur hexafluoride (SF6), bromine (Br2), carbon tetrachloride (CCl4), or a combination thereof.

[0016] In an embodiment of the present invention, the inert gas may be Ar (argon), Ne (neon), Xe (xenon), Kr (krypton), or He (helium).

[0017] In an embodiment of the present invention, the III-V group material may include a multilayer stacked structure of a nitride, an arsenic compound, a phosphide, or an antimony compound.

[0018] In an embodiment of the present invention, the III-V group material may include a multiple quantum well structure.

[0019] In an embodiment of the present invention, the continuous wave plasma etching step can be performed in a source power of 200 to 2000 W and a bias voltage of -500 V to -100 V.

[0020] In an embodiment of the present invention, the continuous wave plasma etching step may use an etching gas containing chlorine gas or boron trichloride.

[0021] The etching method according to an embodiment of the present invention has the characteristic of being able to improve the characteristics of a device by minimizing ion damage after etching a device structure based on a III-V group material. In particular, compared to the wet etching process applied to remove etching damage caused by conventional ions, it has the advantage of being able to remove damaged regions more efficiently through atomic layer etching using plasma.

[0022] Through this, a stable etching damage removal process can be performed even on next-generation ultra-small electronic devices.

[0023] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the configuration of the invention described in the detailed description of the invention or the claims.

[0024] FIG. 1 shows a cross-sectional view of a plasma device that can be used in an etching method according to one embodiment of the present invention.

[0025] FIG. 2 is a diagram showing an example of process conditions for a step of performing atomic layer etching in an etching method according to an embodiment of the present invention.

[0026] Figure 3 is an SEM image showing an MQW structure formed on a substrate in an etching method according to one embodiment of the present invention.

[0027] Figure 4 is an SEM image showing the result of etching a barrier layer within a device through a CW etching process in an etching method according to one embodiment of the present invention.

[0028] Figure 5 is an image of the MQW structure observed by TEM after performing various etching processes in an etching method according to one embodiment of the present invention.

[0029] Figure 6 is a graph showing the percentage of atoms in InGaN and GaN included in the MQW structure after the etching process in an etching method according to one embodiment of the present invention.

[0030] Figure 7 is a Raman shift measurement result of a device after performing various etching processes in an etching method according to an embodiment of the present invention.

[0031] Figure 8 is a graph showing the same area measured by PL in a device having a multiple quantum well structure with patterns of various sizes.

[0032] The present invention will be described below with reference to the attached drawings. However, the present invention may be implemented in various different forms and is therefore not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been given similar reference numerals.

[0033] Throughout the specification, when it is stated that a part is "connected (connected, in contact, combined)" with another part, this includes not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other members interposed between them. Furthermore, when it is stated that a part "includes" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but rather allows for the inclusion of additional components.

[0034] The terms used herein are merely for describing specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0035] Embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0036] One embodiment of the present invention provides a method for etching a III-V group material on a substrate.

[0037] First, a plasma etching step (S100) is performed to etch a III-V group material using plasma.

[0038] Continuous and uniform plasma etching is essential for fine patterning of a device. Therefore, the plasma etching step (S100) in the present invention may refer to a continuous wave etching process (Continuous wave, hereinafter CW process) in which plasma is continuously supplied to etch III-V group materials within the device. For such a CW process, known plasma etching technologies such as ICP-RIE (Inductively Coupled Plasma-Reactive Ion Etching) or ECR (Electron Cyclotron Resonance) may be used.

[0039] FIG. 1 shows a cross-sectional view of a plasma device that can be used in an etching method according to one embodiment of the present invention. That is, the etching method of the present invention may use a plasma system such as the above, for example, a plasma system that includes an APC valve capable of controlling gas injection and process pressure, can independently control the source, bias and gas injection degree, and can apply DC to RF power and control temperature.

[0040] In the case of the above plasma etching, it may be performed by including a chlorine-containing gas as the etching gas. For example, the chlorine-containing gas may be chlorine gas (Cl2), boron trichloride (BCl3), etc. In one embodiment of the present invention to be described later, a mixture of chlorine gas (Cl2) and boron trichloride (BCl3) was used, but is not limited thereto.

[0041] In addition, the etching gas may further include an inert gas. For example, the inert gas may be Ar (argon), Ne (neon), Xe (xenon), Kr (krypton), etc.

[0042] The above plasma etching can be appropriately controlled within the source / bias power range of a general RIE process. For example, the source power can be set to 200 to 2000 W, and the bias voltage to -500 V to -100 V. However, this is an exemplary condition for a generally used plasma etching process and is not limited to the range described above. In one embodiment of the present invention to be described later, an etching process was performed for 10 minutes under conditions of a source power of 800 W, a DC bias of -300 V, 9 mtorr, and 10°C.

[0043] In an embodiment of the present invention, the III-V group material is a compound having at least one Group III element and at least one Group V element. For example, the III-V group compound may be a nitride or arsenic compound or a phosphide or antimony compound such as GaN (gallium nitride), GaAs (gallium arsenide), GaP (gallium phosphide), InP (indium phosphide), InGaN (Indium gallium nitride), InGaP (Indium gallium phosphide), AlInP (aluminum indium phosphide), AlGaInP (aluminum gallium indium phosphide), InGaAs (indium gallium arsenide), GaSb (gallium antimonide), InSb (indium antimonide), InAlAs (indium aluminum arsenide), and AlGaAs (aluminum gallium arsenide), and may include a multilayer structure thereof.

[0044] Next, to remove ion damage on the device surface formed by a continuous wave etching process, a damage area removal step (S200) is performed by performing plasma atomic layer etching on the damaged area.

[0045] Plasma etching has the advantage of enabling fast and uniform etching, but it is necessary to address damage caused by excessive plasma density. That is, damage regions are formed on the surface of a device etched by injecting high-density plasma. For example, in the process of etching a device with a multi-quantum well structure containing III-V group materials, the damage regions may mainly be formed in the PN junction or barrier layer.

[0046] Accordingly, in the present invention, the above problem was solved by removing the damaged area through additional atomic layer etching (ALE).

[0047] The damaged region removal step (S200) is performed via atomic layer etching (ALE), which is a technique for removing thin layers of material using sequential self-limiting reactions. Since ALE enables precise process control and low surface damage, it can be effective for precisely removing damaged regions after a fast and uniform plasma etching process. ALE can be performed using any known suitable technique.

[0048] For example, the atomic layer etching may include an adsorption step (S210) for adsorbing a reaction material; and a desorption step (S220) for removing a surface atomic layer modified by the reaction material.

[0049] The adsorption step exposes the surface of the damaged area, which is an area ion-damaged by the continuous wave etching step, to a reactive material. The reactive material is a halogenated gas, for example, chlorine (Cl2), chlorine triboride (BCl3), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), iodide heptafluoride (IF7), sulfur hexafluoride (SF6), bromine (Br2), carbon tetrachloride (CCl4), or a combination thereof. The supplied reactive material forms a plasma within the chamber to react with the damaged area or is adsorbed onto the surface.

[0050] The source power of the adsorption step (S210) can be set to 50 W to 300 W, preferably 80 W to 120 W. A bias voltage may be applied to the substrate, but generally, no bias is applied or it is set to a very low bias.

[0051] Additionally, the adsorption step (S210) may be further purged after modification. That is, active reaction materials not surface-bound may be removed from the reaction chamber through purging. Purging may be performed using any inert gas such as N2, Ar, Ne, He, and combinations thereof.

[0052] The above desorption step (S220) is a step of removing a damaged area whose surface has been modified by exposure to a reaction material. Desorption is performed using a plasma containing an inert gas, and the inert gas may be, for example, Ar (argon), Ne (neon), Xe (xenon), Kr (krypton), He (helium), etc.

[0053] The source power of the above detachment step (S220) can be set to about 50 W to 150 W, preferably 80 W to 120 W. The bias applied to the substrate can be set to -10 V to -50 V.

[0054] Likewise, the above detachment step (S220) may perform additional purging.

[0055] In addition, in an embodiment of the present invention, an additional wet etching step may be included between the damaged area removal step and the continuous wave etching step. The wet etching step may be performed in a range of about 60 to 100°C using a 30 to 50 wt% KOH aqueous solution that is generally adopted. The concentration and temperature of this KOH aqueous solution may be factors determining the etching rate and directionality.

[0056] The etching of III-V group materials to which the etching method of the present invention is applied may be performed, for example, during the manufacturing process of a device having a multiple quantum well structure (hereinafter referred to as an MQW structure). The multiple quantum well structure may include, for example, a quantum well layer and a barrier layer formed on the quantum well layer. The multiple quantum well structure may be a structure in which the quantum well layer and the barrier layer are repeatedly stacked. For example, through the etching method of the present invention, a barrier layer composed of a III-V group material can be etched and a damaged region removed, thereby enabling the manufacturing of a device having excellent characteristics.

[0057]

[0058] The present invention will be explained in more detail below through manufacturing examples, comparative examples, and experimental examples. However, the present invention is not limited to the following manufacturing examples and experimental examples.

[0059]

[0060] Example: Multi-quantum well structure etching process

[0061] Figure 3 is an SEM image showing an MQW structure formed on a substrate in an etching method according to one embodiment of the present invention.

[0062] In Figure 3 above, it can be seen that a hard mask and photoresist of various sizes are deposited on the top of a multi-quantum well structure in which a quantum well layer and a barrier layer (GaN) are formed on a sapphire substrate.

[0063] First, GaN with a multiple quantum well structure was etched using a CW process. The process conditions are as follows.

[0064] (ICP power 800 W, DC bias: -300 V, BCl3 / Cl2 / Ar: 15 / 75 / 10 sccm, 9 mtorr, substrate temperature 10℃, processing time 10 min)

[0065] Figure 4 is an SEM image showing the result of etching a barrier layer within a device through a CW etching process in an etching method according to one embodiment of the present invention.

[0066]

[0067] Next, wet etching was performed. The wet etching conditions are as follows.

[0068] (Ethylene glycol solution mixed with 45% KOH at 100°C.)

[0069] It was confirmed that the damage was removed after the CW process through wet etching.

[0070]

[0071] In addition, plasma atomic layer etching was performed to remove the damaged area. The plasma atomic layer etching conditions are as follows.

[0072] (Adsorption: Source Power: 100 W, Adsorption Time: 30 sec, Cl250sccm, 5mTorr

[0073] Detachment: Source Power: 100 W, DC Bias: -50 V, Detachment Time 30 sec, Ar 100 sccm, 8 mTorr

[0074] The substrate temperature is the same at 10℃)

[0075] Similarly, it was confirmed that damage was removed after the CW process through plasma atomic layer etching.

[0076]

[0077] Figure 5 is an image of the MQW structure observed by TEM after performing various etching processes in an etching method according to one embodiment of the present invention.

[0078] Referring to Figure 5 above, it can be seen that after etching using the CW process, the layers in the InGaN / GaN stack are not clearly distinguishable and have suffered etching damage from ions.

[0079] On the other hand, when wet etching (WET) was performed, the layers were separated to some extent, so it was confirmed that the damage had been removed, but the distinction between the layer boundaries was not clear.

[0080] However, when plasma atomic layer etching is performed on the damaged area as in the present invention, the boundary portion of the quantum well layer is clearly visible, and it is possible to visually confirm that the damaged area has been reliably removed.

[0081]

[0082] Figure 6 is a graph showing the percentage of atoms in InGaN and GaN included in the MQW structure measured using XPS after the etching process in an etching method according to an embodiment of the present invention.

[0083] Referring to Figure 6 above, it can be seen that in the case of GaN, the N / Ga ratio changed during the CW process compared to the reference. Subsequently, when damage is removed through wet etching, the ratio improves, but it is not similar to the reference. However, when the etching damage caused by ions is removed by performing atomic layer etching using plasma according to the present invention, it can be seen that the ratio is similar to the reference.

[0084] Similarly, when calculating the Ga / In and N / Ga ratios in InGaN, the ratios changed compared to the reference during CW etching, and the degree to which they returned to the original ratio was greater when performing atomic layer etching than when performing wet etching.

[0085] Through this, it was confirmed that when atomic layer etching is performed using plasma, the original reference ratio and the composition of all atoms become similar, so the damaged area is removed.

[0086]

[0087] Figure 7 is a Raman shift measurement result of a device after performing various etching processes in an etching method according to an embodiment of the present invention.

[0088] In Figure 7 above, the laser spot size of the Raman microscope is 2*2 µm.

[0089] Similar to XPS, it can be observed that the Raman shift increases during CW etching under all size conditions. Subsequently, it can be seen that damage is removed to some extent through wet etching, but this is not perfect. However, when atomic layer etching is performed as in the present invention, the reference and peak regions become similar, so it can be confirmed that the damage has been removed.

[0090]

[0091] Figure 8 is a graph showing photoluminescence (PL) measured over the same area in a device having a multi-quantum well structure with patterns of various sizes.

[0092] When etching is performed using the CW process, the intensity of PL decreases as the device size decreases due to damage from ions. However, as shown in Figure 8 above, since the etching damage is removed to some extent when the wet process is performed, it can be confirmed that the intensity of PL increases as the size decreases when the same area is measured using PL.

[0093] Meanwhile, when etching damage is removed through atomic layer etching using plasma, the damage is removed more effectively than with wet etching, so it can be observed that the intensity increases rapidly as the size becomes smaller.

[0094] Through this, as the device size becomes smaller in next-generation processes, if damage is removed through atomic layer etching, damage to the MQW layer will be completely eliminated, allowing for more effective light emission. Therefore, the removal of damaged areas through atomic layer etching can be adopted as an essential process for next-generation etching.

[0095]

[0096] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0097] The scope of the present invention is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present invention.

Claims

1. A method for etching a III-V group material stacked on a substrate, A plasma etching step for etching the above III-V group material using plasma; and An etching method characterized by including a damaged region removal step of performing atomic layer etching to remove ion damage on the surface of a III-V group material formed by the above plasma etching.

2. In Paragraph 1, The above-mentioned step of removing the damaged area is, An adsorption step of exposing the above-mentioned damaged area to a plasma containing a halogen gas; and An etching method characterized by including a detachment step of applying a bias voltage to the substrate while exposing the damaged area to a plasma containing an inert gas.

3. In Paragraph 2, The above adsorption step has a source power for plasma generation of 50 W to 300 W, The above detachment step is an etching method characterized by applying a source power of about 50 W to 150 W for plasma generation.

4. In Paragraph 1, An etching method characterized by further including a wet etching step between the plasma etching step and the damaged area removal step.

5. In Paragraph 2, An etching method characterized in that the above-mentioned halogen gas is chlorine (Cl2), chlorine triboride (BCl3), nitrogen trifluoride (NF3), chlorine trifluoride (ClF3), iodide heptafluoride (IF7), sulfur hexafluoride (SF6), bromine (Br2), carbon tetrachloride (CCl4), or a combination thereof.

6. In Paragraph 2, An etching method characterized in that the above-mentioned inert gas is Ar (argon), Ne (neon), Xe (xenon), Kr (krypton), or He (helium).

7. In Paragraph 1, An etching method characterized in that the above III-V group material comprises a multilayer stacked structure of nitride, arsenic compound, phosphide, or antimony compound.

8. In Paragraph 1, An etching method characterized in that the above III-V group material includes a multiple quantum well structure.

9. In Paragraph 1, An etching method characterized in that the above plasma etching step is performed at a source power of 200 to 2000 W for plasma generation and a bias voltage in the range of -500 V to -100 V.

10. In Paragraph 1, An etching method characterized in that the above plasma etching step uses an etching gas containing chlorine gas or boron trichloride.

Images