Method and apparatus for ai-based digital predistortion for digital dual-input power amplifiers in a wireless communication system

Abstract

The present disclosure relates to a 5G communication system or a 6G communication system for supporting higher data rates beyond a 4G communication system such as long term evolution (LTE). Apparatuses and methods for operating a power amplifier are provided. In some embodiments, the method includes receiving a first carrier signal and a first peaking signal, generating a first predistorted carrier signal by applying a first predistortion to the first carrier signal, and generating a first predistorted peaking signal by applying a second predistortion to the first peaking signal. The method further includes providing the first predistorted carrier signal to a first power amplifier and the first predistorted peaking signal to a second power amplifier, generating an amplified carrier signal using the first power amplifier, generating an amplified peaking signal using the second power amplifier, and combining the amplified carrier signal and the amplified peaking signal into an output signal.

Description

METHOD AND APPARATUS FOR AI-BASED DIGITAL PREDISTORTION FOR DIGITAL DUAL-INPUT POWER AMPLIFIERS IN A WIRELESS COMMUNICATION SYSTEM

[0001] This disclosure relates generally to power amplifiers (PAs) in a wireless communication system. More specifically, this disclosure relates to apparatuses and methods for adding predistortion is dual input power PAs in a wireless communication system.

[0002] Considering the development of wireless communication from generation to generation, the technologies have been developed mainly for services targeting humans, such as voice calls, multimedia services, and data services. Following the commercialization of 5G (5th generation) communication systems, it is expected that the number of connected devices will exponentially grow. Increasingly, these will be connected to communication networks. Examples of connected things may include vehicles, robots, drones, home appliances, displays, smart sensors connected to various infrastructures, construction machines, and factory equipment. Mobile devices are expected to evolve in various form-factors, such as augmented reality glasses, virtual reality headsets, and hologram devices. In order to provide various services by connecting hundreds of billions of devices and things in the 6G (6th generation) era, there have been ongoing efforts to develop improved 6G communication systems. For these reasons, 6G communication systems are referred to as beyond-5G systems.

[0003] 6G communication systems, which are expected to be commercialized around 2030, will have a peak data rate of tera (1,000 giga)-level bit per second (bps) and a radio latency less than 100μsec, and thus will be 50 times as fast as 5G communication systems and have the 1 / 10 radio latency thereof.

[0004] In order to accomplish such a high data rate and an ultra-low latency, it has been considered to implement 6G communication systems in a terahertz (THz) band (for example, 95 gigahertz (GHz) to 3THz bands). It is expected that, due to severer path loss and atmospheric absorption in the terahertz bands than those in mmWave bands introduced in 5G, technologies capable of securing the signal transmission distance (that is, coverage) will become more crucial. It is necessary to develop, as major technologies for securing the coverage, Radio Frequency (RF) elements, antennas, novel waveforms having a better coverage than Orthogonal Frequency Division Multiplexing (OFDM), beamforming and massive Multiple-input Multiple-Output (MIMO), Full Dimensional MIMO (FD-MIMO), array antennas, and multiantenna transmission technologies such as large-scale antennas. In addition, there has been ongoing discussion on new technologies for improving the coverage of terahertz-band signals, such as metamaterial-based lenses and antennas, Orbital Angular Momentum (OAM), and Reconfigurable Intelligent Surface (RIS).

[0005] Moreover, in order to improve the spectral efficiency and the overall network performances, the following technologies have been developed for 6G communication systems: a full-duplex technology for enabling an uplink transmission and a downlink transmission to simultaneously use the same frequency resource at the same time; a network technology for utilizing satellites, High-Altitude Platform Stations (HAPS), and the like in an integrated manner; an improved network structure for supporting mobile base stations and the like and enabling network operation optimization and automation and the like; a dynamic spectrum sharing technology via collision avoidance based on a prediction of spectrum usage; an use of Artificial Intelligence (AI) in wireless communication for improvement of overall network operation by utilizing AI from a designing phase for developing 6G and internalizing end-to-end AI support functions; and a next-generation distributed computing technology for overcoming the limit of UE computing ability through reachable super-high-performance communication and computing resources (such as Mobile Edge Computing (MEC), clouds, and the like) over the network. In addition, through designing new protocols to be used in 6G communication systems, developing mechanisms for implementing a hardware-based security environment and safe use of data, and developing technologies for maintaining privacy, attempts to strengthen the connectivity between devices, optimize the network, promote softwarization of network entities, and increase the openness of wireless communications are continuing.

[0006] It is expected that research and development of 6G communication systems in hyper-connectivity, including person to machine (P2M) as well as machine to machine (M2M), will allow the next hyper-connected experience. Particularly, it is expected that services such as truly immersive eXtended Reality (XR), high-fidelity mobile hologram, and digital replica could be provided through 6G communication systems. In addition, services such as remote surgery for security and reliability enhancement, industrial automation, and emergency response will be provided through the 6G communication system such that the technologies could be applied in various fields such as industry, medical care, automobiles, and home appliances.

[0007] The present disclosure provides method and apparatus for ai-based digital predistortion for digital dual-input power amplifiers in a wireless communication system.

[0008] According to an aspect of an exemplary embodiment, there is provided method and apparatus for ai-based digital predistortion for digital dual-input power amplifiers in a wireless communication system.

[0009] Aspects of the present disclosure provide efficient communication methods in a wireless communication system.

[0010] For a more complete understanding of this disclosure and its advantages, reference is now made to the following description, taken in conjunction with the accompanying drawings, in which:

[0011] FIG. 1 illustrates an example wireless network according to embodiments of the present disclosure;

[0012] FIG. 2 illustrates an example BS according to embodiments of the present disclosure;

[0013] FIG. 3 illustrates an example of a UE according to embodiments of the present disclosure;

[0014] FIG. 4 illustrates an example power amplifier (PA) according to embodiments of the present disclosure;

[0015] FIG. 5 illustrates a flowchart for an example method for training a PA according to an embodiment of the present disclosure;

[0016] FIG. 6 illustrates an example artificial intelligence (AI) model according to embodiments of the present disclosure;

[0017] FIG. 7 illustrates an example PA according to embodiments of the present disclosure;

[0018] FIG. 8 illustrates a flowchart for an example method for training a PA according to an embodiment of the present disclosure;

[0019] FIG. 9 is a block diagram of a terminal or user equipment (UE) according to an embodiment of the disclosure;

[0020] FIG. 10 is a block diagram of a base station (BS) according to an embodiment of the disclosure; and

[0021] FIG. 11 is a block diagram of a network entity according to an embodiment of the disclosure.

[0022] This disclosure provides apparatuses and methods for operating a power amplifier.

[0023] In one embodiment, a method for operating a power amplifier is provided. The method includes receiving a first carrier signal and a first peaking signal, generating a first predistorted carrier signal by applying a first predistortion to the first carrier signal, and generating a first predistorted peaking signal by applying a second predistortion to the first peaking signal. The method further includes providing the first predistorted carrier signal to a first power amplifier and the first predistorted peaking signal to a second power amplifier, generating an amplified carrier signal using the first power amplifier, generating an amplified peaking signal using the second power amplifier, and combining the amplified carrier signal and the amplified peaking signal into an output signal.

[0024] In another embodiment, a power amplifier is provided. The power amplifier includes a first digital predistortion (DPD) circuitry configured to receive a first carrier signal and a first peaking signal, generate a first predistorted carrier signal by applying a first predistortion to the first carrier signal, and generate a first predistorted peaking signal by applying a second predistortion to the first peaking signal, wherein the first predistortion and second predistortion are generated by at least one artificial intelligence (AI) model. The power amplifier further includes a first power amplifier configured to receive the first predistorted carrier signal and generate an amplified carrier signal, a second power amplifier configured to receive the first predistorted peaking signal and generate an amplified peaking signal, and an output combiner circuitry configured to combine the amplified carrier signal and the amplified peaking signal into an output signal.

[0025] In another embodiment, a non-transitory computer readable medium include program code is provide that when executed by a power amplifier, causes the power amplifier to receive a first carrier signal and a first peaking signal, generate a first predistorted carrier signal by applying a first predistortion to the first carrier signal, and generate a first predistorted peaking signal by applying a second predistortion to the first peaking signal. The program code further causes the power amplifier to provide the first predistorted carrier signal to a first power amplifier and the first predistorted peaking signal to a second power amplifier, generate an amplified carrier signal using the first power amplifier, generate an amplified peaking signal using the second power amplifier, and combine the amplified carrier signal and the amplified peaking signal into an output signal.

[0026] This application claims priority under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 63 / 790,960 filed on April 18, 2025. The above-identified provisional patent application is hereby incorporated by reference in its entirety.

[0027] Hereinafter, embodiments of the disclosure will be described in detail with reference to the accompanying drawings.

[0028] In describing the embodiments, while numerous details are set forth for the purpose of illustration, it is understood that some aspects of the disclosure may be practiced with less than all of these details. Numerous variations and alternatives to the details provided herein are possible and are considered within the scope of the disclosure. In some instances, descriptions related to technical contents well-known in the art may be omitted so as to not obscure an understanding of the disclosure, and such omitted descriptions are understood to be within the scope of the disclosure.

[0029] For the same reason, in the accompanying drawings, some elements may be exaggerated, omitted, or schematically illustrated. Further, the size of each element does not completely reflect the actual size. In the drawings, identical or corresponding elements are provided with identical reference numerals or different reference numerals.

[0030] The advantages and features of the disclosure and ways to achieve them will be apparent by making reference to embodiments as described herein in detail in conjunction with the accompanying drawings. However, the disclosure is not limited to the embodiments set forth herein, but may be implemented in various different forms. Other features, aspects, and advantages of the subject matter described herein will become apparent from the disclosure. The following embodiments are merely examples to aid in an understanding of the disclosure and should not be construed to narrow the scope or spirit of the subject matter described herein in any way, but on the contrary, the disclosure covers all modifications, equivalents and alternatives falling within the spirit and scope of the subject matter as defined by the appended claims and equivalents thereof. Throughout the specification, the same or like reference numerals designate the same or like elements. Furthermore, terms which will be described herein are terms defined in consideration of the functions in the disclosure, and may be different according to users, intentions of the operators, or customs. Therefore, the definitions of the terms should be made based on the contents throughout the specification.

[0031] Herein, it will be understood that each block of flowchart illustrations, and combinations of blocks in the flowchart illustrations, may be performed based on computer program instructions. These computer program instructions may be loaded collectively onto at least one processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which perform through any one of, or in any combination of, the at least one processor of the computer or other programmable data processing apparatus, create means for performing the functions specified in the flowchart block(s). These computer program instructions may also be stored in a non-transitory computer usable or computer-readable memory that may direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer usable or computer-readable memory produce an article of manufacture including instruction means that perform the function specified in the flowchart block(s). The computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable data processing apparatus to produce a computer executed process such that the instructions that perform on the computer or other programmable data processing apparatus provide steps for executing the functions specified in the flowchart block(s).

[0032] Further, each block may represent a module, segment, or portion of code, which includes one or more executable instructions for executing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the blocks may occur out of the order. For example, two blocks(or functions) shown in succession may in fact be performed substantially concurrently or the blocks may sometimes be performed in the reverse order, depending upon the functionality involved.

[0033] As used in embodiments of the disclosure, a “~unit / module” may refer to a software element or a hardware element, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC), which performs a predetermined function. However, the term including the word “~unit / module” does not always have a meaning limited to software or hardware. The “~unit / module” may be constructed either to be stored in an addressable storage medium or to execute one or more processors. Therefore, the “~unit / module” includes, for example, software elements, object-oriented software elements, components such as class elements and task elements, processes, functions, properties, procedures, sub-routines, segments of a program code, drivers, firmware, micro-codes, circuits, data, database, data structures, tables, arrays, and parameters. The components and functions provided by the “~unit / module” may be either combined into a smaller number of components and a “~unit / module,” or divided into additional components and a “~unit / module.” Moreover, the components and “~units / modules” may be implemented to reproduce one or more central processing units (CPUs) within a device or a security multimedia card. Further, in the embodiments, the “~unit / module” may include one or more processors.

[0034] The entirety of the one or more computer programs may be stored in a single memory device or the one or more computer programs may be divided with different portions stored in different multiple memory devices.

[0035] Any of the functions or operations described herein can be processed by one processor or a combination of processors. The one processor or the combination of processors is circuitry performing processing and includes circuitry like an application processor (AP, e.g. a CPU), a communication processor (CP, e.g., a modem), a graphics processing unit (GPU), a neural processing unit (NPU) (e.g., an artificial intelligence (AI) chip), a Wi-Fi chip, a Bluetooth® chip, a global positioning system (GPS) chip, a near field communication (NFC) chip, connectivity chips, a sensor controller, a touch controller, a finger-print sensor controller, a display driver integrated circuit (IC), an audio CODEC chip, a universal serial bus (USB) controller, a camera controller, an image processing IC, microprocessors, microcontrollers, digital signal processors, FPGA, ASIC, a microprocessor unit (MPU), a system on chip (SoC), an IC, or the like. The one processor or the combination of processors executes instructions that can be stored in a memory, such as the operating system, in order to control the overall operation of the device. Also, the one processor or the combination of processors is also capable of executing other processes and programs resident in the memory, such as processes for the disclosure.

[0036] It will be appreciated that various embodiments of the disclosure according to the claims and description in the specification can be realized in the form of hardware, software or a combination of hardware and software.

[0037] Any such software may be stored in non-transitory computer readable storage media. The non-transitory computer readable storage media store one or more computer programs (software modules), the one or more computer programs include computer-executable instructions that, when executed by one or more processors of an electronic device individually or collectively, cause the electronic device to perform a method of the disclosure. Additionally, or alternatively, such software may be a computer program [product] comprising instructions which, when executed by one or more processors of an electronic device individually or collectively, cause the electronic device to perform a method of the disclosure.

[0038] Any such software may be stored in the form of volatile or non-volatile storage such as, for example, a storage device like read only memory (ROM), whether erasable or rewritable or not, or in the form of memory such as, for example, random access memory (RAM), memory chips, device or integrated circuits or on an optically or magnetically readable medium such as, for example, a compact disk (CD), digital versatile disc (DVD), magnetic disk or magnetic tape or the like. It will be appreciated that the storage devices and storage media are various embodiments of non-transitory machine-readable storage that are suitable for storing a computer program or computer programs comprising instructions that, when executed, implement various embodiments of the disclosure. Accordingly, various embodiments of the present disclosure may provide a program comprising code for implementing apparatus or a method as claimed in any one of the claims of this specification and a non-transitory machine-readable storage storing such a program.

[0039] Hereinafter, the determination of priority between A and B in the present disclosure may refer to various actions such as selecting the one having a higher priority based on a predefined priority rule and performing an operation corresponding thereto, or omitting or dropping an operation corresponding to the one having a lower priority.

[0040] Hereinafter, "A or B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0041] In addition, "at least one of A, B, and C" as described in the present disclosure may be understood to include A, or B, or C, or any combination of A, B, and C.

[0042] In addition, "at least one of A, B, or C" as described in the present disclosure may be understood to include A, or B, or C, or any combination of A, B, and C.

[0043] Furthermore, "A / B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0044] Furthermore, "A, B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0045] Furthermore, "A and B" as described in the present disclosure may be understood as "A and / or B," which may include A, or B, or both A and B.

[0046] Furthermore, “if condition A and condition B are satisfied,” as described in the present disclosure, may not be limited to a case where both condition A and condition B are satisfied, but may be understood to include a case where either condition A or condition B is individually satisfied, both condition A and condition B are satisfied, or one or more additional conditions are satisfied in combination.

[0047] Furthermore, throughout this disclosure, ordinal terms such as "first," "second," "third," etc., (and similar qualifiers) are used merely to distinguish between different instances, occurrences, configurations, messages, stages, elements or aspects of elements, operations, or information as described herein. Unless the context clearly dictates otherwise, the use of such ordinal terms does not itself require that the elements, operations, or information distinguished by these terms be structurally different, numerically distinct, or substantively dissimilar. For example, a "first signal" and a "second signal" may refer to instances of the same signal transmitted at different times or containing the same core information despite minor variations, or they may refer to signals with different content or characteristics, depending on the specific context. Similarly, a "first value" and a "second value" may represent the same magnitude but measured or applied in different circumstances, or they may represent different magnitudes. The interpretation should be guided by the specific technical context, function, and relationship described in the relevant portion of the specification and claims.

[0048] Furthermore, the terms “first ~”, “second ~”, etc., as described in the present disclosure with respect to various elements (e.g., information, objects, operation, sequences, or the like), should not limit those elements. These terms may only be intended to distinguish one element from another, and may not be intended to indicate a specific order. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element.

[0049] Furthermore, even if “first ~” and “second ~” are described in the present disclosure, it may be understood that element(s) referred to by “first ~” and “second ~” may be the same or different. For example, in case of element(s) being information, first information and second information may both be same information and, in some cases, are separate and different information.

[0050] In addition, the terms “if ~” and “in case that ~” as used in the disclosure or claims may be interpreted to include the meanings of “when (or upon) ~,” “in response to ~,” “based on ~,” or “according to ~,” and may be used interchangeably with these expressions. In addition, expressions other than those exemplified herein may also be used, as long as they have substantially the same meaning and do not impair the technical features of the present disclosure. If a method step (e.g. transmit a signal) is performed according to the disclosure of the application in connection with one of the above terms (such as “in case that ~” or the like), it may be interpreted to include the meanings (disclosure) of a prior determination that a feature has a specific state “~” (e.g. a bit length is above X), and then perform the method step in response to said determination.

[0051] For example, the physical layer signaling may be referred to as Layer 1 (L1) signaling and may include downlink control information (DCI). In addition, the higher layer signaling may include a medium access control (MAC) control message, a radio resource control (RRC) signaling message, a non-access stratum (NAS) signaling message, or an application layer message. The RRC signaling message may be referred to as L3 (layer 3) signaling. It should be noted, however, that the higher layer signaling is not limited to the aforementioned examples.

[0052] In addition, the term "not perform" as used in the present disclosure or claims may, in context, be understood to mean that the corresponding step is omitted or skipped. Such a term may be replaced with other terms having the same or substantially equivalent meaning.

[0053] In addition, "transmitting a message including A and B" as described in the present disclosure, may be understood as encompassing both (i) transmitting A and B in a single message, and (ii) transmitting A and B separately via multiple messages (e.g., transmitting a first message including A and a second message including B). This interpretation may also apply to messages that include two or more items (e.g., A, B, C), transmitted either together or separately.

[0054] In addition, "transmitting a message including A and transmitting a message including B" may also be interpreted as transmitting a message including A and B in a single message.

[0055] In the embodiments of the present disclosure described herein, terms or components included in the disclosure may be expressed in singular or plural form depending on the specific embodiments presented. However, such singular or plural expressions are selected appropriately for convenience of description, and the present disclosure is not limited to a singular or plural number of components. A component expressed in the plural form may be implemented as a single component, and a component expressed in the singular form may be implemented as multiple components.

[0056] The drawings or flowcharts described herein illustrate example methods that may be implemented according to the principles of the present disclosure, and various modifications may be made to the methods illustrated in the flowcharts of the present disclosure. For example, although illustrated as a series of steps, various steps in each drawing or flowchart may overlap, occur in parallel, occur in a different order, or be repeated. In other examples, any step may be omitted or replaced with another step.

[0057] The process of the flowchart may be performed by a device. One or more of the steps of the flowchart can be implemented by one or more processors / computer programs executing instructions to perform the noted functions.

[0058] The methods and apparatuses proposed in the embodiments of the present disclosure may be disclosed in connection with drawings disclosing flowcharts to illustrate example methods that may be implemented according to the principles of the present disclosure. Such flowcharts may contain different branches and / or sub-branches. It is understood that the principles of the present disclosure do not only contain the combination of all branches / sub-branches disclosed in the embodiment, but the present disclosure also contains at least one isolated branch / isolated sub-branch, in particular to a single branch / single sub-branch.

[0059] The methods and apparatuses proposed in the embodiments of the present disclosure are not limited to each embodiment individually, but may also be applied in combination of all or some of the embodiments proposed in the disclosure. Therefore, the embodiments of the present disclosure may be modified and applied without significantly departing from the scope of the present disclosure, as would be understood by those skilled in the art.

[0060] In this case, even if certain wordings are described differently across embodiments, they may be used interchangeably or in substitution or in combination if their underlying concepts are equivalent. For example, for the same or equivalent concept, even if one embodiment uses the expression "A" and another embodiment uses the expression "B", such expressions may be understood interchangeably, in substitution, or in combination.

[0061] The terms used in the following description to refer to access nodes, network entities, messages, interfaces between network entities, various types of identification information, and the like, are provided merely for the convenience of explanation by way of example. Therefore, the present disclosure is not limited to the terms describedherein, and other terms having equivalent technical meanings may also be used. Such terms may also be interchangeable with terms defined in any 3rd generation partnership project (3GPP) technical specifications (TS) or similar technical specifications, e.g., from the European telecommunications standards institute (ETSI), where appropriate.

[0062] Hereinafter, a base station (BS) is an entity that allocates resources to terminals, and may be at least one of a gNode B, an eNode B, a Node B, a wireless access unit, a BS controller, or a node on a network.

[0063] Furthermore, the base station of the present disclosure may include a split architecture comprising a central unit (CU) and a distributed unit (DU). In this structure, the CU is configured to process the higher layers of the control and user planes, while the DU is configured to process lower-layer radio resource functions. The embodiments of the present disclosure may be equally applicable to 5th generation (5G) base station architectures in which such CU and DU functional splits are implemented.

[0064] A terminal may include a user equipment (UE), a mobile station (MS), a cellular phone, a smartphone, a computer, a tablet, a wearable device, an Internet of Things (IoT) device, or any other device / system capable of performing communication functions.

[0065] In the disclosure, a downlink (DL) refers to a radio link through which a BS transmits a signal to a terminal, and an uplink (UL) refers to a radio link through which a terminal transmits a signal to a BS.

[0066] Furthermore, hereinafter, 5G mobile communication technologies (e.g., 5G new radio (NR)), 6th generation (6G) mobile communication technologies may be described by way of example, but the embodiments of the present disclosure may also be applied to other communication systems having similar technical backgrounds or channel types. For example, newly evolved mobile communication systems developed after 5G and 6G may be included. Furthermore, based on determinations by those skilled in the art, the embodiments of the present disclosure may also be applied to other communication systems (e.g., Wi-Fi systems) through some modifications without significantly departing from the scope of the present disclosure

[0067] In the following description, the terms physical channel and signal may be used interchangeably with data or control signal. For example, the term physical downlink shared channel (PDSCH) refers to a physical channel through which data is transmitted, but the term PDSCH may also be used to refer to the data itself. That is, in the present disclosure, the expression "transmit a physical channel" may be interpreted as being equivalent to the expression "transmit data or a signal via a physical channel."

[0068] Hereinafter, in the context of the present disclosure, higher layer signaling may refer to signaling corresponding to at least one or any combination of the following: master information block (MIB), system information block (SIB) or SIB M (M = 1, 2, ...), RRC, or MAC control element (CE), or a non-access stratum (NAS) signaling message, or an application layer message. The RRC signaling message may be referred to as Layer 3 (L3) signaling.

[0069] In addition, L1 signaling may refer to signaling corresponding to at least one or any combination of signaling techniques using the at least one or any combination of the following physical layer channels or signaling: physical downlink control channel (PDCCH), DCI, UE-specific DCI, group-common DCI, common DCI, scheduling DCI (e.g., DCI used for scheduling downlink or uplink data), non-scheduling DCI (e.g., DCI not used for scheduling downlink or uplink data) physical uplink control channel (PUCCH), or uplink control information (UCI). The L1 signaling message may be referred to as a physical layer signaling.

[0070] Hereinafter, the expression that information is configured by the BS, as used in the present disclosure or claims, may, in context, be understood to mean that the terminal receives the corresponding information from the BS via a physical layer signaling or a higher layer signaling. Such an expression may be replaced with other terms having the same or substantially equivalent meaning.

[0071] Hereinafter, the operational principle of the present disclosure will be described in detail with reference to the accompanying drawings.

[0072] Before undertaking the DETAILED DESCRIPTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The term “couple” and its derivatives refer to any direct or indirect communication between two or more elements, whether or not those elements are in physical contact with one another. The terms “transmit,” “receive,” and “communicate,” as well as derivatives thereof, encompass both direct and indirect communication. The terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation. The term “or” is inclusive, meaning and / or. The phrase “associated with,” as well as derivatives thereof, means to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, have a relationship to or with, or the like. The term “controller” means any device, system or part thereof that controls at least one operation. Such a controller may be implemented in hardware or a combination of hardware and software and / or firmware. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase “at least one of,” when used with a list of items, means that different combinations of one or more of the listed items may be used, and only one item in the list may be needed. For example, “at least one of: A, B, and C” includes any of the following combinations: A, B, C, A and B, A and C, B and C, and A and B and C.

[0073] Moreover, various functions described below can be implemented or supported by one or more computer programs, each of which is formed from computer readable program code and embodied in a computer readable medium. The terms “application” and “program” refer to one or more computer programs, software components, sets of instructions, procedures, functions, objects, classes, instances, related data, or a portion thereof adapted for implementation in a suitable computer readable program code. The phrase “computer readable program code” includes any type of computer code, including source code, object code, and executable code. The phrase “computer readable medium” includes any type of medium capable of being accessed by a computer, such as read only memory (ROM), random access memory (RAM), a hard disk drive, a compact disc (CD), a digital video disc (DVD), or any other type of memory. A “non-transitory” computer readable medium excludes wired, wireless, optical, or other communication links that transport transitory electrical or other signals. A non-transitory computer readable medium includes media where data can be permanently stored and media where data can be stored and later overwritten, such as a rewritable optical disc or an erasable memory device.

[0074] Definitions for other certain words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many if not most instances, such definitions apply to prior as well as future uses of such defined words and phrases.

[0075] Power amplifiers (PAs) play a crucial role in modern mobile communication systems, especially in multiple-input multiple-output (MIMO) configurations, which contain a large quantity of PAs in a single base station. While it is convenient to model PAs as having a fixed gain, there is a nonlinear relationship between input and output power. As the input power increases, a fixed gain is not perfectly maintained. Digital predistortion (DPD) is one of the core techniques to compensate for PA nonlinearity, by applying a correction to the signal before transmission to account for the PA's nonlinear behavior.

[0076] FIGURES 1-8, discussed below, and the various, non-limiting embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system or device.

[0077] Power amplifiers (PAs) play an important role in modern mobile communication systems, especially in massive multiple-input multiple-output (MIMO) configurations, which contain a great number of PAs in a single base station (BS). Digital predistortion (DPD) is one of the core techniques to compensate for PA nonlinearity, by applying a correction to the signal before transmission to account for the PA's nonlinear behavior.

[0078] One PA technology is the Doherty amplifier, which is designed to achieve high power efficiency and linearity, particularly at high output levels. A Doherty amplifier includes two amplifiers: a carrier amplifier and a peaking amplifier. The carrier amplifier operates in Class AB mode, providing a constant output power level, while the peaking amplifier operates in Class C mode, providing additional power when needed. The two amplifiers are connected in parallel, with the output signal being a combination of the signals from both amplifiers. Typically, the peaking amplifier input is just a delayed version of the carrier input.

[0079] Dual drive power amplifiers (DDPAs) are similar to Doherty Amplifiers, but the carrier and peaking paths are freely controlled, usually by two digital input paths. By allowing free control over the relationship between carrier and peaking path signals, the DDPA can have improved power efficiency across multiple bands and even improve adjacent channel leakage ratio (ACLR) of the output signal for modulated waveforms. However, when developing a system with DDPAs, DPD design presents a significant design challenge. DDPAs have two separate amplifiers, each with its own unique characteristics and nonlinearities. Characterizing these amplifiers individually and then combining their responses to create an accurate DPD model can be challenging, especially when using other generalized memory polynomial (GMP) based models.

[0080] For example, the gain and phase mismatch between the carrier and peaking amplifiers can impact the accuracy of the DPD model. These mismatches can cause errors in the compensation process, leading to reduced linearity and increased distortion. Additionally, the load impedance seen by each amplifier in a DPA may vary depending on the operating conditions, which can affect the accuracy of the DPD model. This variability can make it difficult to create a single, accurate DPD model that works across all operating scenarios.

[0081] This disclosure relates to an artificial intelligence (AI) based digital predistortion model that inputs two signals derived from the original transmit signal, optimized for enhanced power efficiency, and jointly predistorts them to address the complexities of PA nonlinearity compensation in dual drive power amplifiers.

[0082] FIG. 1 illustrates an example wireless network according to embodiments of the present disclosure. The embodiment of the wireless network shown in FIG. 1 is for illustration only. Other embodiments of the wireless network 100 could be used without departing from the scope of this disclosure.

[0083] As shown in FIG. 1, the wireless network includes a gNB 101 (e.g., base station, BS), a gNB 102, and a gNB 103. The gNB 101 communicates with the gNB 102 and the gNB 103. The gNB 101 also communicates with at least one network 130, such as the Internet, a proprietary Internet Protocol (IP) network, or another data network.

[0084] The gNB 102 provides wireless broadband access to the network 130 for a first plurality of user equipments (UEs) within a coverage area 120 of the gNB 102. The first plurality of UEs includes a UE 111, which may be located in a small business; a UE 112, which may be located in an enterprise; a UE 113, which may be a WiFi hotspot; a UE 114, which may be located in a first residence; a UE 115, which may be located in a second residence; and a UE 116, which may be a mobile device, such as a cell phone, a wireless laptop, a wireless PDA, or the like. The gNB 103 provides wireless broadband access to the network 130 for a second plurality of UEs within a coverage area 125 of the gNB 103. The second plurality of UEs includes the UE 115 and the UE 116. In some embodiments, one or more of the gNBs 101-103 may communicate with each other and with the UEs 111-116 using 5G / NR, long term evolution (LTE), long term evolution-advanced (LTE-A), WiMAX, WiFi, or other wireless communication techniques.

[0085] Depending on the network type, the term “base station” or “BS” can refer to any component (or collection of components) configured to provide wireless access to a network, such as transmit point (TP), transmit-receive point (TRP), an enhanced base station (eNodeB or eNB), a 5G / NR base station (gNB), a macrocell, a femtocell, a WiFi access point (AP), or other wirelessly enabled devices. Base stations may provide wireless access in accordance with one or more wireless communication protocols, e.g., 5G / NR 3rdgeneration partnership project (3GPP) NR, long term evolution (LTE), LTE advanced (LTE-A), high speed packet access (HSPA), Wi-Fi 802.11a / b / g / n / ac, etc. For the sake of convenience, the terms “BS” and “TRP” are used interchangeably in this patent document to refer to network infrastructure components that provide wireless access to remote terminals. Also, depending on the network type, the term “user equipment” or “UE” can refer to any component such as “mobile station,” “subscriber station,” “remote terminal,” “wireless terminal,” “receive point,” or “user device.” For the sake of convenience, the terms “user equipment” and “UE” are used in this patent document to refer to remote wireless equipment that wirelessly accesses a BS, whether the UE is a mobile device (such as a mobile telephone or smartphone) or is normally considered a stationary device (such as a desktop computer or vending machine).

[0086] Dotted lines show the approximate extents of the coverage areas 120 and 125, which are shown as approximately circular for the purposes of illustration and explanation only. It should be clearly understood that the coverage areas associated with gNBs, such as the coverage areas 120 and 125, may have other shapes, including irregular shapes, depending upon the configuration of the gNBs and variations in the radio environment associated with natural and man-made obstructions.

[0087] As described in more detail below, one or more of the gNBs and / or one or more of the UEs 111-116 include an AI-based digital predistortion for power amplifiers, such as a DDPA.

[0088] Although FIG. 1 illustrates one example of a wireless network, various changes may be made to FIG. 1. For example, the wireless network could include any number of gNBs and any number of UEs in any suitable arrangement. Also, the gNB 101 could communicate directly with any number of UEs and provide those UEs with wireless broadband access to the network 130. Similarly, each gNB 102-103 could communicate directly with the network 130 and provide UEs with direct wireless broadband access to the network 130. Further, the gNBs 101, 102, and / or 103 could provide access to other or additional external networks, such as external telephone networks or other types of data networks.

[0089] FIG. 2 illustrates an example gNB 102 according to embodiments of the present disclosure. The embodiment of the gNB 102 illustrated in FIG. 2 is for illustration only, and the gNBs 101 and 103 of FIG. 1 could have the same or similar configuration. However, gNBs come in a wide variety of configurations, and FIG. 2 does not limit the scope of this disclosure to any particular implementation of a gNB.

[0090] As shown in FIG. 2, the gNB 102 includes multiple antennas 205a-205n, multiple transceivers 210a-210n, a controller / processor 225, a memory 230, and a backhaul or network interface 235. Although not shown in FIG. 2, the gNB 102 of FIG. 2 may include PA 400 of FIG. 4.

[0091] The transceivers 210a-210n receive, from the antennas 205a-205n, incoming RF signals, such as signals transmitted by UEs in the network 100. The transceivers 210a-210n down-convert the incoming RF signals to generate IF or baseband signals. The IF or baseband signals are processed by receive (RX) processing circuitry in the transceivers 210a-210n and / or controller / processor 225, which generates processed baseband signals by filtering, decoding, and / or digitizing the baseband or IF signals. The controller / processor 225 may further process the baseband signals.

[0092] Transmit (TX) processing circuitry in the transceivers 210a-210n and / or controller / processor 225 receives analog or digital data (such as voice data, web data, e-mail, or interactive video game data) from the controller / processor 225. The TX processing circuitry encodes, multiplexes, and / or digitizes the outgoing baseband data to generate processed baseband or IF signals. The transceivers 210a-210n up-converts the baseband or IF signals to RF signals that are transmitted via the antennas 205a-205n.

[0093] The controller / processor 225 can include one or more processors or other processing devices that control the overall operation of the gNB 102. For example, the controller / processor 225 could control the transmission of DL channel signals by the transceivers 210a-210n in accordance with well-known principles. The controller / processor 225 could support additional functions as well, such as more advanced wireless communication functions. For instance, the controller / processor 225 could support beam forming or directional routing operations in which outgoing / incoming signals from / to multiple antennas 205a-205n are weighted differently to effectively steer the outgoing signals in a desired direction. Any of a wide variety of other functions could be supported in the gNB 102 by the controller / processor 225.

[0094] The controller / processor 225 is also capable of executing programs and other processes resident in the memory 230, such as processes for AI-based digital predistortion for power amplifiers as described in greater detail below. The controller / processor 225 can move data into or out of the memory 230 as required by an executing process.

[0095] The controller / processor 225 is also coupled to the backhaul or network interface 235. The backhaul or network interface 235 allows the gNB 102 to communicate with other devices or systems over a backhaul connection or over a network. The interface 235 could support communications over any suitable wired or wireless connection(s). For example, when the gNB 102 is implemented as part of a cellular communication system (such as one supporting 5G / NR, LTE, or LTE-A), the interface 235 could allow the gNB 102 to communicate with other gNBs over a wired or wireless backhaul connection. When the gNB 102 is implemented as an access point, the interface 235 could allow the gNB 102 to communicate over a wired or wireless local area network or over a wired or wireless connection to a larger network (such as the Internet). The interface 235 includes any suitable structure supporting communications over a wired or wireless connection, such as an Ethernet or transceiver.

[0096] The memory 230 is coupled to the controller / processor 225. Part of the memory 230 could include a RAM, and another part of the memory 230 could include a Flash memory or other ROM.

[0097] Although FIG. 2 illustrates one example of gNB 102, various changes may be made to FIG. 2. For example, the gNB 102 could include any number of each component shown in FIG. 2. Also, various components in FIG. 2 could be combined, further subdivided, or omitted and additional components could be added according to particular needs.

[0098] FIG. 3 illustrates an example UE 116 according to embodiments of the present disclosure. The embodiment of the UE 116 illustrated in FIG. 3 is for illustration only, and the UEs 111-115 of FIG. 1 could have the same or similar configuration. However, UEs come in a wide variety of configurations, and FIG. 3 does not limit the scope of this disclosure to any particular implementation of a UE.

[0099] As shown in FIG. 3, the UE　116 includes antenna(s) 305, a transceiver(s) 310, and a microphone 320. The UE　116 also includes a speaker 330, a processor 340, an input / output (I / O) interface (IF) 345, an input 350, a display 355, and a memory 360. The memory 360 includes an operating system (OS) 361 and one or more applications 362. Although not shown in FIG. 3, the UE 116 of FIG. 3 may include PA 400 of FIG. 4.

[0100] The transceiver(s) 310 receives from the antenna(s) 305, an incoming RF signal transmitted by a gNB of the network 100. The transceiver(s) 310 down-converts the incoming RF signal to generate an intermediate frequency (IF) or baseband signal. The IF or baseband signal is processed by RX processing circuitry in the transceiver(s) 310 and / or processor 340, which generates a processed baseband signal by filtering, decoding, and / or digitizing the baseband or IF signal. The RX processing circuitry sends the processed baseband signal to the speaker 330 (such as for voice data) or is processed by the processor 340 (such as for web browsing data).

[0101] TX processing circuitry in the transceiver(s) 310 and / or processor 340 receives analog or digital voice data from the microphone 320 or other outgoing baseband data (such as web data, e-mail, or interactive video game data) from the processor 340. The TX processing circuitry encodes, multiplexes, and / or digitizes the outgoing baseband data to generate a processed baseband or IF signal. The transceiver(s) 310 up-converts the baseband or IF signal to an RF signal that is transmitted via the antenna(s) 305.

[0102] The processor 340 can include one or more processors or other processing devices and execute the OS 361 stored in the memory 360 in order to control the overall operation of the UE 116. For example, the processor 340 could control the reception of DL channel signals by the transceiver(s) 310 in accordance with well-known principles. In some embodiments, the processor 340 includes at least one microprocessor or microcontroller.

[0103] The processor 340 is also capable of executing other processes and programs resident in the memory 360. The processor 340 can move data into or out of the memory 360 as required by an executing process. For example, in various embodiments, the UE 116 uses AI-based digital predistortion.

[0104] In some embodiments, the processor 340 is configured to execute the applications 362 based on the OS 361 or in response to signals received from gNBs or an operator. The processor 340 is also coupled to the I / O interface 345, which provides the UE 116 with the ability to connect to other devices, such as laptop computers and handheld computers. The I / O interface 345 is the communication path between these accessories and the processor 340.

[0105] The processor 340 is also coupled to the input 350 and the display 355. The operator of the UE 116 can use the input 350 to enter data into the UE 116. The display 355 may be a liquid crystal display, light emitting diode display, or other display capable of rendering text and / or at least limited graphics, such as from web sites.

[0106] The memory 360 is coupled to the processor 340. Part of the memory 360 could include a random-access memory (RAM), and another part of the memory 360 could include a Flash memory or other read-only memory (ROM).

[0107] Although FIG. 3 illustrates one example of UE 116, various changes may be made to FIG. 3. For example, various components in FIG. 3 could be combined, further subdivided, or omitted and additional components could be added according to particular needs. As a particular example, the processor 340 could be divided into multiple processors, such as one or more central processing units (CPUs) and one or more graphics processing units (GPUs). In another example, the transceiver(s) 310 may include any number of transceivers and signal processing chains and may be connected to any number of antennas. Also, while FIG. 3 illustrates the UE 116 configured as a mobile telephone or smartphone, UEs could be configured to operate as other types of mobile or stationary devices.

[0108] FIG. 4 illustrates an example PA 400 according to embodiments of the present disclosure. The embodiment of the PA 400 shown in FIG. 4 is for illustration only. Other embodiments of the PA 400 could be used without departing from the scope of this disclosure.

[0109] As shown in FIG. 4, in one or more embodiments, the PA 400 can be a DDPA. The PA 400 includes a signal split circuitry 402, a DPD circuitry 404, a carrier amplifier 406 (also referred to as a “first power amplifier” or “first type amplifier”), a peaking amplifier 408 (also referred to as a “second power amplifier” or “second type amplifier”), an output combiner circuitry 410, a signal split circuitry 412, a DPD circuitry 414, a loss model 416, a combinational circuitry 418, and a combinational circuitry 420.

[0110] In one or more embodiments, an input signal x[n] is provided to and received by the signal split circuitry 402. The input signal x[n] can be any suitable signal processed by the PA 400 such as a discrete transmit signal. The signal split circuitry 402 splits in the input signal x[n] into a first carrier signal sc[n] and a first peaking signal sp[n]. The split signal circuitry 102 transmits the first carrier signal sc[n] and a first peaking signal sp[n] to the DPD circuitry 404.

[0111] As noted above, to compensate for non-linearity in the PAs (the carrier amplifier 406 and the peaking amplifier 408), the DPD circuitry 404 is used to add corrections (predistortion) using at least one AI model. As shown in FIG. 1, the DPD circuitry 404 includes a single AI model. In other embodiments, the DPD circuitry 404 can include separate AI models to add corrections to the first carrier signal sc[n] and a first peaking signal sp[n]. The DPD circuitry 404 receives both the first carrier signal sc[n] and a first peaking signal sp[n] and adds predistortion, generating a first predistorted carrier signal uc[n] and a first predistorted peaking signal up[n]. The DPD circuitry 404 generates the first predistorted carrier signal uc[n] by executing the AI model to add a first predistortion to the first carrier signal sc[n] and generates the first predistorted peaking signal up[n] by executing the AI model to add a second predistortion to the first peaking signal sp[n]. The first predistortion and the second predistortion can be the same or different.

[0112] However as noted above, because the PA 400 includes two different amplifiers there are challenges correcting both the first carrier signal sc[n] and a first peaking signal sp[n] individually to account for the unique characteristics and non-linearities of both the carrier amplifier 406 the peaking amplifier 408. Advantageously, to combat this, the DPD circuitry includes and executes the AI model that is able to jointly predistort the first carrier signal sc[n] and a first peaking signal sp[n] based on the non-linearity of the carrier amplifier 406 the peaking amplifier 408, respectively.

[0113] In one or more embodiments, the AI model include any suitable AI model that can jointly predistort the first carrier signal sc[n] and the first peaking signal sp[n], such as a neural network (NN). The AI model can include any suitable type of NN including but not limited to, a feedforward NN, a convolutional NN (CNN), a recurrent NN (RNN), long short-term memory (LSTM) networks, or the like. An example NN is shown in more detail in FIG. 3 below.

[0114] Referring back to FIG. 1, the first predistorted carrier signal uc[n] is provided to the carrier amplifier 406 and the first predistorted peaking signal up[n] is provided to the peaking amplifier 408. The carrier amplifier 406 and the peaking amplifier 408 can be any suitable type of PA including, but not limited to, switched capacitor power amplifiers (SCPAs), voltage-mode amplifiers, or the like. The carrier amplifier 406 receives the first predistorted carrier signal uc[n], generates an amplified carrier signal, and provides the amplified carrier signal to the output combiner circuitry 410. The peaking amplifier 408 receives the first predistorted peaking signal up[n], generates an amplified peaking signal, and provides the amplified peaking signal to the output combiner circuitry 410. The output combiner circuitry 410 receives the amplified carrier signal and the amplified peaking signal and combines the amplified carrier signal and the amplified peaking signal into an output signal y[n].

[0115] One cycle of training the DPD circuitry 404 includes providing the output signal y[n] to the signal split circuitry 412. The signal split circuitry 412 splits the output signal into a second carrier signal wc[n] and a second peaking signal wp[n]. The signal split circuitry 412 provides the second carrier signal wc[n] and the second peaking signal wp[n] to the DPD circuitry 414. The DPD circuitry 414 includes the same type of AI model as the DPD circuitry 414. In one or more embodiments, as will be shown in more detail below, the DPD circuitry 414 can also include separate AI models.

[0116] The DPD circuitry 414 executes the AI model and outputs a second predistorted carrier signal zc[n] and a second predistorted peaking signal zp[n]. The DPD circuitry 414 generates the second predistorted carrier signal zc[n] by executing the AI model to add a third predistortion to the second carrier signal wc[n] and generates the second predistorted peaking signal zp[n] by executing the AI model to add a second predistortion to the second peaking signal wp[n]. The third predistortion and the fourth predistortion can be the same or different. As will be described in more detail below, loss model 416 is used to train the AI model of the DPD circuitry 414 which is then used to update the AI model of the DPD circuitry 404.

[0117] At initialization, the DPD circuitry 404 and the DPD circuitry 414 include identical AI models. For example, if the AI model is a NN, initially, the AI models included in both DPD circuitry 404 and DPD circuitry 414 have the same coefficients (weights and / or biases). In each cycle, the DPD circuitry 414 is trained as an inverse of the PAs to compensate for nonlinearities. In one or more embodiments, the DPD circuitry 414 is trained by using the output in-phase and quadrature (I / Q) components for both the carrier amplifier 406 and the peaking amplifier 408 as inputs (the second carrier signal wc[n] and a second peaking signal wp[n]) to the DPD circuitry 414 and the respective I / Q components for the carrier amplifier 406 and the peaking amplifier 408 as labels of the outputs (the second predistorted carrier signal zc[n] and the second predistorted peaking signal zp[n]) of the DPD circuitry 414 (according to a given signal split function). Both the DPD circuitry 404 and the DPD circuitry 414 provide their respective inputs to the combinational circuitry 418 and the combinational circuitry 420. The DPD circuitry 404 provides the first predistorted peaking signal up[n] to the combinational circuitry 418 and the first predistorted carrier signal uc[n] to the combinational circuitry 420. The DPD circuitry 414 provides the second predistorted peaking signal zp[n] to the combinational circuitry 418 and the second predistorted carrier signal zc[n] to the combinational circuitry 420.

[0118] The combinational circuitry 418 generates an estimated peaking output signal ep[n] based on a comparison of the first predistorted peaking signal up[n] and the second predistorted peaking signal zp[n]. The combinational circuitry 420 generates an estimated carrier output signal ec[n] based on a comparison of the first predistorted carrier signal uc[n] and the second predistorted carrier signal zc[n]. In one or more embodiments, the combinational circuitry 418 and the combinational circuitry 420 are subtractors. Thus, the estimated peaking output signal ep[n] is a differential signal generated by taking a difference between first predistorted peaking signal up[n] and the second predistorted peaking signal zp[n]. Furthermore, the estimated carrier output signal ec[n] is a differential signal generated by taking a difference between first predistorted carrier signal uc[n] and the second predistorted carrier signal zc[n]. The estimated peaking output signal ep[n] and the estimated carrier output signal ec[n] are provided to the loss model 416 by the combinational circuitry 418 and the combinational circuitry 420, respectively. The estimated peaking output signal ep[n] and the estimated carrier output signal ec[n] account for the non-linearities of the respective, PAs. Although the combinational circuitry 418 and the combinational circuitry 420 are described as subtractors this is for example purposes only. The combinational circuitry 418 and the combinational circuitry 420 can be any suitable type of combinational circuitry.

[0119] The loss model 416 generates and provides a loss model output signal l[n] to the DPD circuitry 414. The loss model output signal l[n] is generated as a function of a performance output metric including the predistorter output convergence, as well as ACLR, error vector magnitude (EVM), power-added efficiency (PAE), PA gain, or the like, depending on implementation needs. The DPD circuitry 414 coefficients (the AI model) are updated based on the loss model output signal l[n]. The DPD circuitry 414 then updates the DPD circuitry 404 coefficients (the AI model) to match coefficients.

[0120] By predistoring the first carrier signal sc[n] and the first peaking signal sp[n] to generate the first predistorted carrier signal uc[n], and the first predistorted peaking signal up[n], respectively, using the AI model of the DPD circuitry 404, the first predistorted carrier signal uc[n], and the first predistorted peaking signal up[n], and the output signal y[n] are updated accordingly, and will be used to retrain the DPD circuitry 404 in a next cycle. In one or more embodiments, the quantity of training epochs per cycle should be chosen long enough such that the AI model coefficients completely converge.

[0121] As will be described in more detail below, in one or more embodiments, the AI model included in the DPD circuitry 404 is trained in one or more cycles (iterations). In one more embodiments, training is performed until the output signal y[n] meets a performance threshold metric. The performance threshold metric can include a threshold ACLR, EVM, PAE, PA gain, or the like. In other embodiments, training is performed until a difference determined by the combinational circuitry 418 and / or the combinational circuitry 420 each meet a respective threshold value.

[0122] FIG. 5 illustrates a flowchart for an example method 500 for training a PA according to an embodiment of the present disclosure. For example, the method 500 can be performed by the PA 400.

[0123] The method 500 begins with building the AI-models within the DPD circuitry 404 (first DPD circuitry) and the DPD circuitry 414 (second DPD circuitry) (202). As noted above, the AI-models are initially identical. Next, the AI-model within the DPD circuitry 414 is trained (504). As shown in FIG. 4, the training includes first splitting the input signal x[n] into the first carrier signal sc[n] and the first peaking signal sp[n] using the signal split circuitry 402. The DPD circuitry 404 receives both the first carrier signal sc[n] and the first peaking signal sp[n] and jointly adds predistortion, generating the first predistorted carrier signal uc[n] and a first predistorted peaking signal up[n]. Stated differently, the DPD circuitry 404 executes the AI model to add the first predistortion to the first carrier signal sc[n] and the second predistortion to the first peaking signal sp[n]. In other embodiments, as shown in FIG. 7, the first predistortion can be added to the first carrier signal sc[n] and the second predistortion can be added to the first peaking signal sp[n] by executing two separate AI models in parallel.

[0124] The first predistorted carrier signal uc[n] is received by the carrier amplifier 406 and the first predistorted peaking signal up[n] is received by the peaking amplifier 408. The carrier amplifier 406 generates the amplified carrier signal, and provides the amplified carrier signal to the output combiner circuitry 410. The peaking amplifier 408 generates the amplified peaking signal, and provides the amplified peaking signal to the output combiner circuitry 410. The output combiner circuitry 410 receives the amplified carrier signal and the amplified peaking signal, and combines the amplified carrier signal and the amplified peaking signal into an output signal y[n] and provides the output signal to the signal split circuitry 412. The signal split circuitry 412 splits the output signal into a second carrier signal wc[n] and a second peaking signal wp[n] and provides the second carrier signal wc[n] and the second peaking signal wp[n] to the DPD circuitry 414. The DPD circuitry 414 executes the AI model (same AI-model as the DPD circuitry 404) and outputs a second predistorted carrier signal zc[n] and a second predistorted peaking signal zp[n]. Stated differently, the DPD circuitry 414 executes the AI model to add the third distortion to the second predistorted carrier signal zc[n] and the fourth distortion the second predistorted peaking signal zp[n].

[0125] The second predistorted peaking signal zp[n] along with the first predistorted peaking signal up[n] are provided to the combinational circuitry 418. The second predistorted carrier signal zc[n] along with the first predistorted carrier signal uc[n] are provided to the combinational circuitry 420. As described above, the combinational circuitry 418 generates estimated peaking output signal ep[n] and the combinational circuitry 420 generates an estimated carrier output signal ec[n], which are provided to the loss model 416. The loss model 416 generates a loss model output signal l[n] based on the outputs of combinational circuitries 418, 420 that is used to train (update) the coefficients of the AI-model in the DPD circuitry 414.

[0126] Next, the DPD circuitry 414 then updates the coefficients of the AI-model in the DPD circuitry 404 (506) to match the coefficients between the DPD circuitries 404 and 414. In a next cycle, after updating the coefficients in the DPD circuitry 404, an output signal y[n] is generated, in the same manner described above, by transmitting through the DPD circuitry 404 (508). A performance output metric of the output signal y[n] is measured and is compared with a performance threshold metric (510). If the performance output metric of the output signal y[n] meets the performance threshold metric, training is complete (512). If the performance output metric of the output signal y[n] does not meet the performance threshold metric, the method 500 returns to step 504. For example, if the ACLR of the output signal y[n] is less than a threshold ACLR (does not meet a threshold ACLR), training continues until the ACLR of the output signal y[n] is greater than or equal to the threshold ACLR. Although FIG. 2 is described as continuing training until the ACLR is greater than or equal to the threshold ACLR (performance threshold metric), this is for example purposes only. Any suitable performance output metric including, but not limited to, EVM, PAE, PA gain, or predistorter output convergence can be used. The output signal y[n] can be trained until one or more of the performance output metrics meets a corresponding performance threshold metric (is greater than or equal to the performance threshold metric (or vice versa depending on the metric used)).

[0127] FIG. 6 illustrates an example AI model 600 according to embodiments of the present disclosure. In one or more embodiments, the AI model 600 is a fully-connected neural network is designed with four input neurons configured to receives, the real part, and the imaginary part of the first carrier signal sc[n] and adds predistortion to the first carrier signal sc[n] as inputs, while four output neurons respectively output the real part and the imaginary part of the first predistorted carrier signal uc[n] and the first predistorted peaking signal up[n]. At least one fully connected hidden layer is required. In one or more embodiments, a rectified linear unit (ReLU) is used as the activation function. However, using a ReLU activation function is for example purposes only. It is understood that any other suitable activation function can be used. Furthermore, the AI model be a more advanced neural network architectures can be, e.g., by adding time-adjacent signal I / Q components as input neurons, adding hidden layers, by applying a CNN, recurrent neural network RNN, LSTM networks, or the like.

[0128] As noted above, the DPD circuitry 404 and the DPD circuitry 414 include the same AI model and initially include the same coefficients. The loss model 416 is used to update the coefficients of the DPD circuitry 414 (AI model) which is then used to update the coefficients of the DPD circuitry 404 (AI model).

[0129] FIG. 7 illustrates an example PA 700 according to embodiments of the present disclosure. The embodiment of the PA 700 shown in FIG. 7 is for illustration only. Other embodiments of the PA 700 could be used without departing from the scope of this disclosure.

[0130] As shown in FIG. 7, in one or more embodiments, the PA 700 can be a DDPA. As noted above, in one or more embodiments, predistortion can be added to the first carrier signal sc[n] and the first peaking signal sp[n]. As shown in FIG. 7, the PA 700 includes a DPD circuitry 702 that includes a carrier AI model (AI-DPDci) and a peaking AI model (AI-DPDpi). The DPD circuitry 702 receives the first carrier signal sc[n] and executes AI-DPDcito add the first predistortion to the first carrier signal sc[n], generating the first predistorted carrier signal uc[n]. The DPD circuitry 702 receives the first peaking signal sp[n] and executes AI-DPDpito add the second predistortion to the first peaking signal sp[n], generating the first predistorted peaking signal up[n]. AI-DPDciand AI-DPDpican be the same or different AI models. For example, AI-DPDciand AI-DPDpican be identical (initially), can be the same type of AI model with different coefficients, or can be different types of AI models. The DPD circuitry 702 provides the first predistorted carrier signal uc[n] to the carrier amplifier 406, and the first predistorted peaking signal up[n] to the peaking amplifier 408.

[0131] The carrier amplifier 406 receives the first predistorted carrier signal uc[n], generates an amplified carrier signal, and provides the amplified carrier signal to the output combiner circuitry 410. The peaking amplifier 408 receives the first predistorted peaking signal up[n], generates an amplified peaking signal, and provides the amplified peaking signal to the output combiner circuitry 410. The output combiner circuitry 410 receives the amplified carrier signal and the amplified peaking signal and combines the amplified carrier signal and the amplified peaking signal into the output signal y[n].

[0132] The signal split circuitry 412 splits the output signal y[n] into the second carrier signal wc[n] and the second peaking signal wp[n]. Because the DPD circuitry 702 includes 2 AI models, the PA 400 includes a DPD circuitry 704 that is also split into a carrier AI model (AI-DPDco) and a peaking model and (AI-DPDpo), and includes a loss model 710 and a loss model 712. As will be described in more detail below, the loss model 710 is used to train AI-DPDcowhich is then used to update AI-DPDci. Additionally, the loss model 712 is used to train AI-DPDpowhich is then used to update AI-DPDpi.

[0133] At initialization, AI-DPDciand AI-DPDcoare identical AI models and AI-DPDpiand AI-DPDpoare identical AI models. In the same manner described above, AI-DPDciadds the third predistortion and outputs the second predistorted carrier signal zc[n], and AI-DPDpoadds the fourth predistortion and outputs the second predistorted peaking signal zp[n].

[0134] The second predistorted carrier signal zc[n] is provided to the loss model 710. The second predistorted peaking signal zp[n] is provided to the loss model 712. The loss model 710 generates and provides the estimated carrier output signal ec[n] to AI-DPDcoand is used to train (update) the AI-DPDcocoefficients. The loss model 712 generates and provides the estimated peaking output signal ep[n] to AI-DPDpowhich is used to train the AI-DPDpocoefficients. AI-DPDcoupdates the AI-DPDcicoefficients to match coefficients. AI-DPDpoalso updates the AI-DPDpicoefficients to match coefficients. As noted above, in one embodiment, each of AI models are trained until the output signal y[n] meets a performance threshold metric. Stated differently, the steps of the method 500 can be performed by the PA 700 to train each of the AI models. In other embodiments, the AI models are trained until a difference determined by the combinational circuitry 418 and / or the combinational circuitry 420 (not shown in FIG. 7) each meet a threshold value. As described above, the second predistorted carrier signal zc[n] and the estimated carrier output signal ec[n] can be provided to the combinational circuitry 720 which can generate a signal that is provided to loss model 710 and is used to train AI-DPDco(FIG. 8). Similarly, the second predistorted peaking signal zp[n] and the estimated peaking output signal ep[n] can be provided to the combinational circuitry 418 which can generate a signal that is provided to loss model 712 and is used to train AI-DPDpo(FIG. 5).

[0135] FIG. 8 illustrates a flowchart for an example method 800 for training a PA according to an embodiment of the present disclosure. For example, the method 800 can be performed by the PA 400 (or the PA 700).

[0136] The method 800 begins with the DPD circuitry 404 receiving the first carrier signal sc[n] and the first peaking signal sp[n] (802). The DPD circuitry 404 adds the first predistortion to the first carrier signal sc[n], by implementing the AI-model, to the generate the first predistorted carrier signal uc[n] (804). The DPD circuitry 404 adds the second predistortion to the first peaking signal sp[n], by implementing the AI-model, to the generate the first predistorted peaking signal up[n] (806). As noted above, the first predistortion and the second predistortion can be the same or different predistortion and can be added jointly. Alternatively, the first predistorted carrier signal uc[n] and the first predistorted peaking signal up[n] can be generated (the first and second predistortion can be added) in parallel using multiple AI models (the method 800 can also be performed by PA 700).

[0137] Next, the first predistorted carrier signal uc[n] is provided to (and received by) the carrier amplifier 406 and the first predistorted peaking signal up[n] is provided to (and received by) the peaking amplifier 408 (808). The carrier amplifier 406 generates the amplified carrier signal (810). The peaking amplifier 408 generates the amplified peaking signal (812). The amplified carrier signal and the amplified peaking signal are combined into an output signal y[n] (814). The output combiner circuitry 410 receives the amplified carrier signal and the amplified peaking signal and combines them into the output signal y[n].

[0138] The output signal y[n] is split into the second carrier signal wc[n] and the second peaking signal wp[n] (816). The signal split circuitry 412 receives and splits the output signal y[n] into the second carrier signal wc[n] and the second peaking signal wp[n]. The DPD circuitry 414 adds the third distortion to the second carrier signal wc[n] to generate the second predistorted carrier signal zc[n] (818). The DPD circuitry 414 adds the fourth distortion to the second peaking signal wp[n] to generate the second predistorted peaking signal zp[n] (820). As noted above, the third predistortion and the fourth predistortion can be the same or different predistortion and can be added jointly. Alternatively, the third predistortion and the fourth predistortion can be added in parallel using multiple AI models (using the PA 700).

[0139] A first difference between the first predistorted carrier signal uc[n] and the second predistorted carrier signal zc[n] is determined (822). The first predistorted carrier signal uc[n] and the second predistorted carrier signal zc[n] are provided to the combinational circuitry 420 which determines the first difference. The combinational circuitry 420 generates the estimated carrier output signal ec[n] based on the first difference. A second difference between the first predistorted peaking signal up[n] and the second predistorted peaking signal zp[n] is determined (824). The first predistorted peaking signal up[n]and the second predistorted peaking signal zp[n] are provided to the combinational circuitry 418 which determines the second difference. The combinational circuitry 418 generates an estimated peaking output signal ep[n] based on the second difference.

[0140] The first difference and the second difference are each compared to a threshold value (826). If either the first difference or the second difference is greater than the threshold value, the respective first predistortion and / or the second predistortion are updated (828). As noted above, the loss model 416 receives the estimated carrier output signal ec[n] and the estimated peaking output signal ep[n] and generates the loss model output signal l[n] which is used to update the coefficients of the AI-model (the third and fourth predistortion) of the DPD circuitry 414. The DPD circuitry 414 then updates the coefficients of the AI-model of the DPD circuitry 404 (updates the first and second predistortion) and another cycle of training is performed (802-828). If the first difference and the second difference are less than the threshold value, training is complete (830). Alternatively, the first difference and second difference can be transmitted to different loss models that are used to update corresponding AI models in parallel (using the PA 700).

[0141] Advantageously, and as noted above, adding predistortion in a PA (such as a PA) using trained AI model(s) accounts for the gain and phase mismatch between the carrier and peaking amplifiers which improves the accuracy of the PA and allows for the formation of an accurate DPD circuitry that works across all operating scenarios.

[0142] FIG. 9 is a block diagram of a terminal or user equipment (UE) 900 according to an embodiment of the disclosure.

[0143] The terminal is an electronic device capable of wireless communication and having various form factors, examples of the terminal may include a UE, a mobile station (MS), a cellular phone, a smartphone, a computer, a tablet, a wearable device, an Internet of Things (IoT) device, or any other device / system capable of performing wireless communication with a base station (BS) and / or another terminal through a wireless channel. Furthermore, the UE 900 of FIG.9 may correspond to the UE 116 of FIG.3.

[0144] Referring to FIG. 9, the UE 900 may include at least one transceiver (hereinafter, referred to as simply “transceiver”) 901, at least one processor (hereinafter, referred to as simply “processor”) 902, and at least one memory (hereinafter, referred to as simply “memory”) 903. According to at least one or a combination of methods corresponding to the embodiments described in the present disclosure, the transceiver 901, the processor 902, and the memory 903 of the UE 900 may operate. However, components of the UE 900 are not limited to the example components illustrated in FIG. 9. In another embodiment, the UE 900 may further include additional components in addition to the above-mentioned components, or some components may be omitted. Further, in some embodiments, any combination of the transceiver 901, the processor 902, or the memory 903 may be integrated in the form of one component. Although not shown in FIG. 9, the UE 900 of FIG. 2 may include PA 400 of FIG. 4.

[0145] The transceiver 901 may be a communication circuit or communication circuitry that enables the UE 900 to perform wireless communication with a node or an entity of a network. For example, the transceiver 901 may enable the UE 900 to transmit or receive a signal to or from a BS through cellular communication, or to transmit or receive a signal to or from another UE through cellular communication. For example, the transceiver 901 may support at least one of various cellular communication technologies including 3rd generation (3G), 4th generation (4G), long term evolution (LTE), 5th generation (5G) NR, 6th generation (6G), and various cellular wireless communication technologies supported by the transceiver (901) may include all subsequent generations of evolved wireless communications.

[0146] According to an embodiment, the UE 900 may include a plurality of transceivers. For example, in the case of supporting evolved-universal terrestrial radio access-new radio (E-UTRA-NR) dual connectivity (EN-DC), the UE 900 may include a first transceiver supporting the 4G LTE wireless communication and a second transceiver supporting the 5G NR wireless communication. According to another embodiment, in the case of supporting NR-dual connectivity (NR-DC), the UE 900 may include a plurality of transceivers supporting the 5G NR wireless communication. According to still another embodiment, in the case of supporting near field wireless communication, the UE 900 may separately include a transceiver supporting at least one standard in the group of wireless communication protocol standards as defined in the protocol standards for Bluetooth®, wireless local area network (WLAN) network (including institute of electrical and electronics engineers (IEEE) 802.11-2016 standard or its amendments, e.g., 802.11ah, 802.11ad, 802.11ay, 802.11ax, 802.11az, 802.11ba, and 802.11be, without being limited thereto).

[0147] According to an embodiment, the transceiver 901 may include various circuit structures used to transmit or receive signals to or from a BS through a wireless channel. The signals may include control information and data. For example, the transceiver 901 may include a radio frequency (RF) transmitter for up-converting and amplifying the frequency of a transmitted signal and an RF receiver for low-noise-amplifying a received signal and down-converting the frequency thereof. The transceiver 901 may output a signal received through a wireless channel to the processor 902 and may transmit, through a wireless channel, a signal output from the processor 902.

[0148] The processor 902 may control general operations of the UE 900 according to embodiments of the disclosure. The processor 902 may be implemented by one or more integrated circuit (or circuitry) (IC) chips and may execute various data processing operations. The processor 902 may include at least one electric circuit, and may execute instructions (or a program, codes, data, etc.) stored in the memory 903, individually, collectively or in any combination thereof. Further, the processor 902 may include a single-core processor or multi-core processor, and may include a processor assembly including a plurality of processing circuits (circuitry) according to a specific implementation scheme.

[0149] The processor 902 may be electrically, operatively, and / or communicatively coupled to the transceiver 901 to control the transceiver 901.

[0150] The processor 902 may include at least one processor (or processing circuitry), and the at least one processor may perform the following operations individually, collectively or in any combination thereof. For example, the processor 902 may include a communication processor (CP) configured to control communication operations and an application processor (AP) configured to control execution of an upper layer (for example, an application layer). In a specific embodiment, at least a part of the processor 902 may be included in one chip (or IC) and the other part of the processor 902 may be included in another chip (or IC). Otherwise, at least one processor may be included in another component, for example, the transceiver 901 or the memory 903.

[0151] The processor 902 may perform or control or cause an operation of the UE 900 for executing at least one or a combination of methods according to embodiments of the disclosure. For example, the processor 902 may control operations of the UE 900 for processing a downlink signal received from a BS or generating and transmitting an uplink signal to a BS. To this end, the processor 902 may execute a computer program, codes, or instructions stored in the memory 903, so as to control other components of the UE 900 to enable execution of various operations.

[0152] The memory 903 corresponds to a hardware storage device capable of temporarily or permanently storing information and may include one or more storage media. For example, the memory 903 may include a memory assembly including one or more storage media. For example, the one or more storage media may include permanent memory, such as a hard drive, flash memory, or read-only memory (ROM), semipermanent memory, such as random access memory (RAM), cache memory, or a combination thereof.

[0153] The memory 903 may be electrically, operatively, and / or communicatively coupled to the processor 902 and may be accessed by the processor 902.

[0154] The memory 903 may store a computer program, codes, or instructions executable by the processor 902. According to an embodiment, a computer program, codes, or instructions executable by the processor 902 may be either stored in a single memory device or separated and distributedly stored in two or more memory devices. By executing the instructions stored in the memory 903, the processor 902 may perform various functions according to an embodiment of the disclosure.

[0155] According to an embodiment of the disclosure, operations of the UE 900 may be caused to be performed based on execution of instructions (or a computer program or codes) stored in the memory 903 by at least one processor (or processing circuitry) configured to execute the same individually, collectively, or in any combination thereof, based on processing circuitry that is not configured to execute instructions, and / or based on components of processing circuitry that is not configured to execute instructions.

[0156] FIG. 10 is a block diagram of a base station (BS) 1000 according to an embodiment of the disclosure.

[0157] The BS 1000 may perform wireless communication with at least one user equipment (UE) located within the area of the BS 1000 through a wireless channel. The BS 1000 may perform communication with a node or an entity of a network through wired or wireless communication. Furthermore, the BS 1000 of FIG.10 may correspond to the gNB 102 of FIG.2.

[0158] Referring to FIG. 10, the BS 1000 may include at least one transceiver (hereinafter, referred to as simply “transceiver”) 1001, at least one processor (hereinafter, referred to as simply “processor”) 1002, and at least one memory (hereinafter, referred to as simply “memory”) 1003. According to at least one or a combination of methods corresponding to the embodiments described in the present disclosure, the transceiver 1001, the processor 1002, and the memory 1003 of the BS 1000 may operate. However, components of the BS 1000 are not limited to the example components illustrated in FIG. 10. In another embodiment, the BS 1000 may further include additional components in addition to the above-mentioned components, or some components may be omitted. Further, in some embodiments, any combination of the transceiver 1001, the processor 1002, or the memory 1003 may be integrated in the form of one component. Although not shown in FIG. 10, the BS 1000 of FIG. 10 may include PA 400 of FIG. 4.

[0159] The transceiver 1001 may be a communication circuit or communication circuitry that enables the BS 1000 to perform wireless communication with a node or an entity of a network. For example, the transceiver 1001 may enable the BS 1000 to transmit or receive a signal to or from the UE 900 through cellular communication, or to transmit or receive a signal to or from another network entity through wireless communication. For example, the transceiver 1001 may support various cellular communication technologies including 3rd generation (3G), 4th generation (4G), long term evolution (LTE), 5th generation (5G) NR, 6th generation (6G), and various cellular wireless communication technologies supported by the transceiver (1001) may include all subsequent generations of evolved wireless communications.. According to an embodiment, the transceiver 1001 may include various circuit structures used to transmit or receive signals to or from a UE through a wireless channel. The signals may include control information and data. For example, the transceiver 1001 may include a radio frequency (RF) transmitter for up-converting and amplifying the frequency of a transmitted signal and an RF receiver for low-noise-amplifying a received signal and down-converting the frequency thereof. The transceiver 1001 may output a signal received through a wireless channel to the processor 1002 and may transmit, through a wireless channel, a signal output from the processor 1002.

[0160] Meanwhile, according to an embodiment of the present disclosure, the BS 1000 may perform communication with a node or an entity of a network through wired or wireless communication. For example, the BS 1000 may perform wired or wireless communication with an adjacent BS, or a node or an entity of a core network through a backhaul network. Although not illustrated in FIG. 10, when the BS 1000 performs wired communication, the BS 1000 may further include a separate network interface for wired communication in addition to the transceiver 1001. The network interface may be referred to as network interface circuitry or communication interface circuitry.

[0161] The processor 1002 may control general operations of the BS 1000 according to embodiments of the disclosure. The processor 1002 may be implemented by one or more integrated circuit (or circuitry) (IC) chips and may execute various data processing operations. The processor 1002 may include at least one electric circuit, and may execute instructions (or a program, codes, data, etc.) stored in the memory 1003, individually, collectively or in any combination thereof. Further, the processor 1002 may include a single-core processor or multi-core processor, and may include a processor assembly including a plurality of processing circuits (circuitry) according to a specific implementation scheme.

[0162] The processor 1002 may be electrically, operatively, and / or communicatively coupled to the transceiver 1001 to control the transceiver 1001.

[0163] The processor 1002 may include at least one processor (or processing circuitry), and the at least one processor may perform the following operations individually, collectively or in any combination thereof. In a specific embodiment, at least a part of the processor 1002 may be included in one chip (or IC) and the other part of the processor 1002 may be included in another chip (or IC). Otherwise, at least one processor may be included in another component, for example, the transceiver 1001 or the memory 1003.

[0164] The processor 1002 may perform or control or cause an operation of the BS 1000 for executing at least one or a combination of methods according to embodiments of the disclosure. For example, the processor 1002 may control operations of the BS 1000 for generating and transmitting a downlink signal to a UE or processing an uplink signal received from a UE. Otherwise, the BS 1000 may transmit or receive a signal to or from a neighboring BS, transfer a signal received from a UE to an upper node of the network, or transmit a signal transferred from an upper node of the network to a UE. To this end, the processor 1002 may execute a computer program, codes, or instructions stored in the memory 1003, so as to control other components of the BS 1000 to enable execution of various operations.

[0165] The memory 1003 corresponds to a hardware storage device capable of temporarily or permanently storing information and may include one or more storage media. For example, the memory 1003 may include a memory assembly including one or more storage media. For example, the one or more storage media may include permanent memory, such as a hard drive, flash memory, or read-only memory (ROM), semipermanent memory, such as random access memory (RAM), cache memory, or a combination thereof.

[0166] The memory 1003 may be electrically, operatively, and / or communicatively coupled to the processor 1002 and may be accessed by the processor 1002.

[0167] The memory 1003 may store a computer program, codes, or instructions executable by the processor 1002. According to an embodiment, a computer program, codes, or instructions executable by the processor 1002 may be either stored in a single memory device or separated and distributedly stored in two or more memory devices. By executing the instructions stored in the memory 1003, the processor 1002 may perform various functions according to an embodiment of the disclosure.

[0168] According to an embodiment of the disclosure, operations of the BS 1000 may be caused to be performed based on execution of instructions (or a computer program or codes) stored in the memory 1003 by at least one processor (or processing circuitry) configured to execute the same individually, collectively, or in any combination thereof, based on processing circuitry that is not configured to execute instructions, and / or based on components of processing circuitry that is not configured to execute instructions.

[0169] The UE or the base station may perform various communication procedures related to the control plane or the user plane by cooperating with one or more network entities based on wireless communication. For example, the UE may communicate with a network entity (for example, an Access and Mobility Management Function (AMF), a Session Management Function (SMF), rtc.) via the base station, or the base station may perform at least one communication procedure by directly transmitting and receiving signals to / from, or relaying signals between, the network entities.

[0170] The structure of the above-described network entity will be described in more detail with reference to the drawings.

[0171] FIG. 11 is a block diagram of a network entity 1100 according to an embodiment of the disclosure.

[0172] The network entity 1100 may include an entity (apparatus, device, or server, etc.) that performs one or more network functions (NFs) or a part of a network function constituting a core network (e.g., a 5th generation (5G) core (5GC)) in a communication system. In this case, multiple NFs may be implemented within a single network entity, or a single NF may be distributed and implemented across a plurality of network entities. In addition, when an NF is implemented within the network entity, the NF may be implemented in the form of software, and in such a case, a program for operating the NF may be stored in memory of the network entity 1100.

[0173] A single NF may be implemented by one or more instances, which may be deployed on the same network entity or distributed across multiple network entities to operate. The instance may be a software unit that logically executes a specific network function, and may be implemented in a form that is decoupled from physical hardware resources. Further, one or more NFs may be implemented in the form of one network slice to operate to satisfy specifications required by a particular service.

[0174] The NF may include at least one of an access and mobility management function (AMF), a session management function (SMF), a local session management function (L-SMF), a user plane function (UPF), a local user plane function (L-UPF), a policy control function (PCF), a unified data management (UDM), a unified data repository (UDR), a network exposure function (NEF), a network repository function (NRF), an application function (AF), a network slice selection function (NSSF), a network data analytics function (NWDAF), a network slice admission control function (NSACF), an authentication server function (AUSF), or a data network (DN), etc.

[0175] Referring to FIG. 11, the network entity 1100 may include at least one network interface 1101, at least one processor 1102 (hereinafter, “processor”), and at least one memory 1103 (hereinafter, “memory”). As described above, a NF may be implemented in the form of a physical device such as the network entity 1100, or may be virtualized and executed in the form of an instance. When implemented as an instance, the NF need not necessarily include physical components as illustrated in FIG. 11. In such a case, the instance may be logically represented as comprising one or more logical functional elements.

[0176] According to at least one or a combination of methods corresponding to the embodiments described in the present disclosure, the network interface 1101, the processor 1102, and the memory 1103 of the network entity 1100 may operate. However, components of the network entity 1100 are not limited to the example components illustrated in FIG. 11. In another embodiment, the network entity 1100 may further include additional components in addition to the above-mentioned components, or some components may be omitted. Further, in an embodiment, the network interface 1101, the processor 1102, or the memory 1103 may be integrated in the form of one component.

[0177] The network interface 1101 is a collective term for a transmitter part of the network entity 1100 and a receiver part of the network entity 1100, and may be a communication circuit for transmitting or receiving a signal to or from a user equipment (UE), a base station (BS), or another network entity. Here, the communication circuit may include both a communication circuit for wireless communication and a communication circuit for a wired communication. For example, the network interface 1101 may include a circuit, logic, hardware, etc., configured to exchange a control plane message or a user plane message with a UE, a BS, or other core network entities through wireless communication or wired communication. The network interface 1101 may operate using various protocols (e.g., non-access stratum (NAS) protocol). The network interface 1101 may also be referred to, for convenience of description or depending on implementation, as communication circuitry, network interface circuitry, or a communication interface circuitry.

[0178] The processor 1102 may control general operations of the network entity 1100 according to embodiments of the disclosure. The processor 1102 may be implemented by one or more integrated circuit (or circuitry) (IC) chips and may execute various data processing operations. The processor 1102 may include at least one electric circuit, and may execute instructions (or a program, codes, data, etc.) stored in the memory 1103, individually, collectively or in any combination thereof. Further, the processor 1102 may include a single-core processor or multi-core processor, and may include a processor assembly including a plurality of processing circuits (circuitry) according to a specific implementation scheme. Further, it should be noted that, according to another embodiment, in a case where NF is implemented in the form of an instance, the network function may be not necessarily configured by physical hardware.

[0179] According to an embodiment, the processor 1102 may be electrically, operatively, and / or communicatively coupled to the network interface 1101 to control the network interface 1101.

[0180] The processor 1102 may include at least one processor (or processing circuitry), and the at least one processor may perform the following operations individually, collectively or in any combination thereof. In a specific embodiment, at least a part of the processor 1102 may be included in one chip (or IC) and the other part of the processor 1102 may be included in another chip (or IC). Otherwise, at least one processor may be included in another component, for example, the network interface 1101 or the memory 1103.

[0181] The processor 1102 may perform or control or cause an operation of the network entity 1100 for executing at least one or a combination of methods according to embodiments of the disclosure. For example, the processor 1102 may control operations of the network entity 1100 for exchanging a control plane message or a user plane message with a UE, a BS, or other core network entities through wireless or wired communication, using various protocols (e.g., NAS protocol). To this end, the processor 1102 may execute a computer program, codes, or instructions stored in the memory 1103, so as to control other components of the network entity 1100 to enable execution of various operations.

[0182] The memory 1103 corresponds to a hardware storage device capable of temporarily or permanently storing information and may include one or more storage media. For example, the memory 1103 may include a memory assembly including one or more storage media. For example, the one or more storage media may include permanent memory, such as a hard drive, flash memory, or read-only memory (ROM), semipermanent memory, such as random access memory (RAM), cache memory, or a combination thereof.

[0183] The memory 1103 may be electrically, operatively, and / or communicatively coupled to the processor 1102 and may be accessed by the processor 1102.

[0184] The memory 1103 may store a computer program, codes, or instructions executable by the processor 1102. According to an embodiment, a computer program, codes, or instructions executable by the processor 1102 may be either stored in a single memory device or separated and distributedly stored in two or more memory devices. By executing the instructions stored in the memory 1103, the processor 1102 may perform various functions according to an embodiment of the disclosure.

[0185] According to an embodiment of the disclosure, operations of the network entity 1100 may be caused to be performed based on execution of instructions (or a computer program or codes) stored in the memory 1103 by at least one processor (or processing circuitry) configured to execute the same individually, collectively, or in any combination thereof, based on processing circuitry that is not configured to execute instructions, and / or based on components of processing circuitry that is not configured to execute instructions.

[0186] In one embodiment, a method for operating a power amplifier is provided. The method includes receiving a first carrier signal and a first peaking signal; generating a first predistorted carrier signal by applying a first predistortion to the first carrier signal; generating a first predistorted peaking signal by applying a second predistortion to the first peaking signal; providing the first predistorted carrier signal to a first power amplifier and the first predistorted peaking signal to a second power amplifier; generating an amplified carrier signal using the first power amplifier; generating an amplified peaking signal using the second power amplifier; and combining the amplified carrier signal and the amplified peaking signal into an output signal.

[0187] In another embodiment, the method for operating a power amplifier is provided. The method further includes splitting the output signal into a second carrier signal and a second peaking signal; generating a second predistorted carrier signal by adding a third predistortion to the second carrier signal; generating, a second predistorted peaking signal by applying a fourth predistortion to the second peaking signal; and determining a first difference between the first predistorted carrier signal and the second predistorted carrier signal and a second difference between the first predistorted peaking signal and the second predistorted peaking signal.

[0188] In another embodiment, the method for operating a power amplifier is provided. The method further includes updating the first predistortion based on determining that the first difference is greater than a threshold value and updating the second predistortion based on determining that the second difference is greater than the threshold value.

[0189] In another embodiment, the method for operating a power amplifier is provided. The method further includes updating the first predistortion based on determining that the first difference is greater than a threshold value.

[0190] In another embodiment, the method for operating a power amplifier is provided. The method further includes updating the second predistortion based on determining that the second difference is greater than a threshold value.

[0191] In another embodiment, the method for operating a power amplifier is provided, wherein the first predistorted carrier signal and the first predistorted peaking signal are generated concurrently.

[0192] In another embodiment, the method for operating a power amplifier is provided, wherein the first predistorted carrier signal and the first predistorted peaking signal are generated in parallel.

[0193] In one embodiment, a power amplifier is provided. The power amplifier includes a first digital predistortion (DPD) circuitry configured to: receive a first carrier signal and a first peaking signal, generate a first predistorted carrier signal by applying a first predistortion to the first carrier signal, and generate a first predistorted peaking signal by applying a second predistortion to the first peaking signal, wherein the first predistortion and second predistortion are generated by at least one artificial intelligence (AI) model, a first power amplifier configured to receive the first predistorted carrier signal and generate an amplified carrier signal; a second power amplifier configured to receive the first predistorted peaking signal and generate an amplified peaking signal; and an output combiner circuitry configured to combine the amplified carrier signal and the amplified peaking signal into an output signal.

[0194] In another embodiment, the power amplifier is provided. The power amplifier further includes a split circuitry configured to receive the output signal and split the output signal into a second carrier signal and a second peaking signal;a second DPD circuitry configured to: generate a second predistorted carrier signal by adding a third predistortion to the second carrier signal, and generate, a second predistorted peaking signal by applying a fourth predistortion to the second peaking signal, wherein the third predistortion and fourth predistortion are generated by at least one artificial intelligence (AI) model, a first combinational circuitry configured to receive the first predistorted carrier signal and the second predistorted carrier signal and determine a first difference between the first predistorted carrier signal and the second predistorted carrier signal; and a second combinational circuitry configured to receive the first predistorted peaking signal and the second predistorted peaking signal and determine a second difference between the first predistorted peaking signal and the second predistorted peaking signal.

[0195] In another embodiment, the power amplifier is provided. The power amplifier further includes a loss model to update the first predistortion and the second predistortion based on the first difference being greater than a threshold value and update the second predistortion based on the second difference being greater than the threshold value.

[0196] In another embodiment, the power amplifier is provided. The power amplifier further includes updating the first predistortion based on determining that the first difference is greater than a threshold value.

[0197] In another embodiment, the power amplifier is provided. The power amplifier further includes updating the second predistortion based on determining that the second difference is greater than a threshold value.

[0198] In another embodiment, the power amplifier is provided, wherein the first predistorted carrier signal and the first predistorted peaking signal are generated by a single AI model or by different AI models.

[0199] In another embodiment, a base station (BS) is provided. The BS includes the power amplifier.

[0200] In one embodiment, a non-transitory computer readable medium is provided. The non-transitory computer readable medium includes program code that, when executed by a power amplifier, causes the power amplifier to: receive a first carrier signal and a first peaking signal; generate a first predistorted carrier signal by applying a first predistortion to the first carrier signal; generate a first predistorted peaking signal by applying a second predistortion to the first peaking signal; provide the first predistorted carrier signal to a first power amplifier and the first predistorted peaking signal to a second power amplifier; generate an amplified carrier signal using the first power amplifier; generate an amplified peaking signal using the second power amplifier; and combine the amplified carrier signal and the amplified peaking signal into an output signal.

[0201] In another embodiment, the non-transitory computer readable medium is provided, wherein the program code further causes the power amplifier to: split the output signal into a second carrier signal and a second peaking signal; generate a second predistorted carrier signal by adding a third predistortion to the second carrier signal; generate a second predistorted peaking signal by applying a fourth predistortion to the second peaking signal; and determine a first difference between the first predistorted carrier signal and the second predistorted carrier signal and a second difference between the first predistorted peaking signal and the second predistorted peaking signal.

[0202] In another embodiment, the non-transitory computer readable medium is provided, wherein the program code further causes the power amplifier to update the first predistortion based on determining that the first difference is greater than a threshold value and update the second predistortion based on determining that the second difference is greater than the threshold value.

[0203] In another embodiment, the non-transitory computer readable medium is provided, wherein the program code further causes the power amplifier to update the second predistortion based on determining that the second difference is greater than a threshold value.

[0204] In another embodiment, the non-transitory computer readable medium is provided, wherein the program code further causes the power amplifier to update the first predistortion based on determining that the first difference is greater than a threshold value.

[0205] In another embodiment, the non-transitory computer readable medium is provided, wherein the first predistorted carrier signal and the first predistorted peaking signal are generated concurrently or in parallel.

[0206] Other technical features may be readily apparent to one skilled in the art from the figures, descriptions, and claims of the present disclosure.

[0207] Any of the above variation embodiments can be utilized independently or in combination with at least one other variation embodiment. The above flowcharts illustrate example methods that can be implemented in accordance with the principles of the present disclosure and various changes could be made to the methods illustrated in the flowcharts herein. For example, while shown as a series of steps, various steps in each figure could overlap, occur in parallel, occur in a different order, or occur multiple times. In another example, steps may be omitted or replaced by other steps.

[0208] Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims. None of the description in this application should be read as implying that any particular element, step, or function is an essential element that must be included in the claim scope. The scope of patented subject matter is defined by the claims.

[0209] Meanwhile, although specific embodiments of the present disclosure have been described in detail, various modifications may be made without departing from the scope of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the described embodiments, but should be defined by the claims and equivalents thereof.

Claims

1.A method for operating a power amplifier, the method comprising:receiving a first carrier signal and a first peaking signal;generating a first predistorted carrier signal by applying a first predistortion to the first carrier signal;generating a first predistorted peaking signal by applying a second predistortion to the first peaking signal;providing the first predistorted carrier signal to a first type amplifier of the power amplifier and the first predistorted peaking signal to a second type amplifier of the power amplifier;generating an amplified carrier signal using the first type amplifier;generating an amplified peaking signal using the second type amplifier; andcombining the amplified carrier signal and the amplified peaking signal into an output signal.2.The method of Claim 1, further comprising:splitting the output signal into a second carrier signal and a second peaking signal;generating a second predistorted carrier signal by adding a third predistortion to the second carrier signal;generating, a second predistorted peaking signal by applying a fourth predistortion to the second peaking signal; anddetermining a first difference between the first predistorted carrier signal and the second predistorted carrier signal and a second difference between the first predistorted peaking signal and the second predistorted peaking signal.3.The method of Claim 2, further comprising updating the first predistortion based on determining that the first difference is greater than a threshold value and updating the second predistortion based on determining that the second difference is greater than the threshold value.4.The method of Claim 2, further comprising updating the first predistortion based on determining that the first difference is greater than a threshold value.5.The method of Claim 2, further comprising updating the second predistortion based on determining that the second difference is greater than a threshold value.6.The method of Claim 1, wherein the first predistorted carrier signal and the first predistorted peaking signal are generated concurrently.7.The method of Claim 1, wherein the first predistorted carrier signal and the first predistorted peaking signal are generated in parallel.8.A base station (BS) comprising:at least one transceiver including a power amplifier;at least one processor communicatively coupled to the at least one transceiver; andat least one memory, communicatively coupled to the at least one processor, storing instructions executable by the at least one processor individually or in any combination to cause the BS to:receive, by a first digital predistortion (DPD) circuitry of the power amplifier, a first carrier signal and a first peaking signal;generate, by the first DPD circuitry of the power amplifier, a first predistorted carrier signal by applying a first predistortion to the first carrier signal;generate, by the first DPD circuitry of the power amplifier, a first predistorted peaking signal by applying a second predistortion to the first peaking signal, wherein the first predistortion and second predistortion are generated by at least one artificial intelligence (AI) model;receive the first predistorted carrier signal and generate an amplified carrier signal, by a first type amplifier of the power amplifier;receive the first predistorted peaking signal and generate an amplified peaking signal, by a second type amplifier of the power amplifier; andcombine, by an output combiner circuitry of the power amplifier, the amplified carrier signal and the amplified peaking signal into an output signal.9.The BS of Claim 8, wherein the instructions further cause the BS to:receive, by a split circuitry of the power amplifier, the output signal and split the output signal into a second carrier signal and a second peaking signal;generate, by a second DPD circuitry of the power amplifier, a second predistorted carrier signal by adding a third predistortion to the second carrier signal, andgenerate, by the second DPD circuitry of the power amplifier, a second predistorted peaking signal by applying a fourth predistortion to the second peaking signal, wherein the third predistortion and fourth predistortion are generated by at least one artificial intelligence (AI) model,receive the first predistorted carrier signal and the second predistorted carrier signal and determine a first difference between the first predistorted carrier signal and the second predistorted carrier signal, by a first combinational circuitry of the power amplifier; andreceive the first predistorted peaking signal and the second predistorted peaking signal and determine a second difference between the first predistorted peaking signal and the second predistorted peaking signal, by a second combinational circuitry of the power amplifier.10.The BS of Claim 9, wherein the instructions further cause the BS to:update the first predistortion and the second predistortion based on the first difference being greater than a threshold value and update the second predistortion based on the second difference being greater than the threshold value, by a loss model of the power amplifier.11.The BS of Claim 9, wherein the instructions further cause the BS to:update, by the power amplifier, the first predistortion based on determining that the first difference is greater than a threshold value.12.The BS of Claim 9, wherein the instructions further cause the BS to:update, by the power amplifier, the second predistortion based on determining that the second difference is greater than a threshold value.13.The BS of Claim 8, wherein the first predistorted carrier signal and the first predistorted peaking signal are generated by a single AI model or by different AI models.14.A user equipment (UE) comprising:at least one transceiver including a power amplifier;at least one processor communicatively coupled to the at least one transceiver; andat least one memory, communicatively coupled to the at least one processor, storing instructions executable by the at least one processor individually or in any combination to cause the UE to:receive, by a first digital predistortion (DPD) circuitry of the power amplifier, a first carrier signal and a first peaking signal;generate, by the first DPD circuitry of the power amplifier, a first predistorted carrier signal by applying a first predistortion to the first carrier signal;generate, by the first DPD circuitry of the power amplifier, a first predistorted peaking signal by applying a second predistortion to the first peaking signal, wherein the first predistortion and second predistortion are generated by at least one artificial intelligence (AI) model;receive the first predistorted carrier signal and generate an amplified carrier signal, by a first type amplifier of the power amplifier;receive the first predistorted peaking signal and generate an amplified peaking signal, by a second type amplifier of the power amplifier; andcombine, by an output combiner circuitry of the power amplifier, the amplified carrier signal and the amplified peaking signal into an output signal.15.The UE of Claim 14, wherein the instructions further cause the UE to:receive, by a split circuitry of the power amplifier, the output signal and split the output signal into a second carrier signal and a second peaking signal;generate, by a second DPD circuitry of the power amplifier, a second predistorted carrier signal by adding a third predistortion to the second carrier signal, andgenerate, by the second DPD circuitry of the power amplifier, a second predistorted peaking signal by applying a fourth predistortion to the second peaking signal, wherein the third predistortion and fourth predistortion are generated by at least one artificial intelligence (AI) model,receive the first predistorted carrier signal and the second predistorted carrier signal and determine a first difference between the first predistorted carrier signal and the second predistorted carrier signal, by a first combinational circuitry of the power amplifier; andreceive the first predistorted peaking signal and the second predistorted peaking signal and determine a second difference between the first predistorted peaking signal and the second predistorted peaking signal, by a second combinational circuitry of the power amplifier.

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