Communication methods and related products

Abstract

The disclosure provides a communication method, including: obtaining a code length and a bit sequence including a plurality of information bits; obtaining cyclic redundancy check (CRC) bits based on the plurality of information bits and an upper bound of quantity of CRC bits, where the upper bound is determined based on the code length, a basic code rate, an error rate, and a noise condition; obtaining an encoded bit sequence by performing polar encoding, on the plurality of information bits and the CRC bits; and outputting the encoded bit sequence.

Description

COMMUNICATION METHODS AND RELATED PRODUCTS TECHNICAL FIELD

[0001] The present disclosure relates generally to the field of communication technologies, and more particularly to communication methods and related products.BACKGROUND

[0002] Channel coding techniques are used in communication systems, playing a role in enhancing bandwidth spectral efficiency and ensuring robustness of information transmission. As the demand for faster and more reliable communication escalates, especially with the advent of new wireless technologies, the importance of efficient coding techniques has grown exponentially.

[0003] Polar codes can be used for channel coding. The innovation behind polar codes lies in their ability to achieve channel capacity with low encoding and decoding complexities, making polar codes suitable for high-performance communication systems.SUMMARY

[0004] The present disclosure provides communication methods and apparatuses to improve communication performance of a communication system.

[0005] According to a first aspect, a communication method is described. The method may be applied at an encoding device, for example, a first device, a component (for example, a circuit, a chip, or a chip system) in a first device, or a logical module or software that can implement all or some functions of a encoding device.

[0006] For example, the method is performed at the encoding device, and the method includes: obtaining a code length and a bit sequence including a plurality of information bits; obtaining cyclic redundancy check (CRC) bits based on the plurality of information bits and an upper bound of quantity of CRC bits, where the upper bound is determined based on the code length, a basic code rate, an error rate, and a noise condition; obtaining an encoded bit sequence by performing polar encoding, on the plurality of information bits and the CRC bits; and outputting the encoded bit sequence.

[0007] Since adding inappropriate quantity of CRC bits may degrade the decoding performance such as increase the error rate, in these embodiments, the quantity of CRC bits is limited, and the upper bound of quantity of CRC bits is determined based on factors including the error rate which is a target error rate. As such, the error rate of decoding result may be guaranteed when CRC encoding is performed.

[0008] In some embodiments, the upper bound is determined based on the code length, the basiccode rate, the error rate, and the noise condition by actions of: obtaining a first code rate based on the error rate and the noise condition, where the error rate is satisfied in a case where the first code rate is used to perform polar encoding under the noise condition; obtaining a difference between the basic code rate and the first code rate; and determining the upper bound based on the difference and the code length.

[0009] A code rate of the polar encoding may increase from the basic code rate to the first code rate beyond which the actual error rate may exceed the target error rate. In other words, when the first code rate is applied for polar encoding, the actual error rate is not greater than the target error rate, while when a code rate greater than the first code rate is applied for polar encoding, the actual error rate will be greater than the target error rate.

[0010] In some embodiments, the upper bound is determined based on the code length, the basic code rate, the error rate, and the noise condition by actions of: obtaining a ratio by searching for a table based on the code length, the basic code rate, the error rate, and the noise condition; and determining the upper bound based on the ratio and the code length.

[0011] First, a corresponding table may be obtained based on the code length, the error rate, and the noise condition. That is, some tables may be precalculated based on different code lengths, error rates, and noise conditions. When the code length, the error rate, and the noise condition are determined, the corresponding table may be obtained. The corresponding table includes relationships between basic code rates and proportions of CRC bits. Second, the proportion of CRC bits, i.e., the ratio, may be found in the corresponding table based on the basic code rate.

[0012] In some embodiments, the bit sequence is further divided into a plurality of segments, and quantity of CRC bits for each of the plurality of segments is determined based on a proportion of CRC bits in each of the plurality of segments.

[0013] In some embodiments, the proportion of CRC bits in each of the plurality of segments is determined based on a proportion of information bits between each of the plurality of segments.

[0014] In some embodiments, the proportion of information bits between each of the plurality of segments is obtained based on a structure of a polar code, the code length, the basic code rate, and quantity of the plurality of segments, where the polar code is used to perform the polar encoding.

[0015] In some embodiments, a lower bound of the quantity of CRC bits in the last segment is obtained based on the error rate and a list size of a decoder for decoding using the polar code. In this way, the target error rate may be guaranteed.

[0016] In some embodiments, the plurality of segments includes 2lsegments, and l is a positive integer.

[0017] In some embodiments, the code length is greater than or equal to a threshold. In someembodiments, the threshold is 4096.

[0018] In some embodiments, the error rate includes one or more of: a target block error rate or a target false alarm rate.

[0019] According to a second aspect, a communication method is described. The method may be applied at a decoding device, for example, a decoding device, a component (for example, a circuit, a chip, or a chip system) in a decoding device, or a logical module or software that can implement all or some functions of a decoding device.

[0020] For example, the method is performed at the decoding device, and the method includes: obtaining a bit sequence including a plurality of encoded information bits and encoded CRC bits, where the encoded CRC bits are obtained based on an upper bound of quantity of CRC bits and the upper bound of quantity of CRC bits is determined based on a code length, a basic code rate, an error rate, and a noise condition, and the code length is a length of the to-be-decoded bit sequence; obtaining a decoded bit sequence including a plurality of decoded information bits and decoded CRC bits by performing polar decoding on the bit sequence; performing CRC verification on the plurality of decoded information bits based on the decoded CRC bits; and obtaining a result based on the CRC verification.

[0021] In some embodiments, the obtaining a result based on the CRC verification, includes: determining that the plurality of decoded information bits pass CRC verification based on the decoded CRC bits; and obtaining a decoding result including the decoded bit sequence, where the decoded bit sequence includes the plurality of decoded information bits.

[0022] In some embodiments, the decoded bit sequence includes a plurality of decoded segments, each decoded segment includes one or more decoded information bits and one or more decoded CRC bits, and performing CRC verification on the plurality of decoded information bits based on the decoded CRC bits, includes: performing CRC verification on one or more decoded information bits in each of the plurality of decoded segments based on respective one or more decoded CRC bits.

[0023] In some embodiments, the plurality of segments includes 2lsegments, and l is a positive integer.

[0024] In some embodiments, the code length is greater than or equal to a threshold. In some embodiments, the threshold is 4096.

[0025] In some embodiments, the error rate includes one or more of: a target block error rate or a target false alarm rate.

[0026] According to a third aspect, a communication apparatus is described. The communication apparatus has a function of implementing the first aspect. For example, the communicationapparatus includes a corresponding module, unit, or means (means) for performing operations in the first aspect. The module, unit, or means may be specifically implemented by using software, may be implemented by using hardware, or may be implemented by using software in combination with hardware.

[0027] According to a fourth aspect, a communication apparatus is described. The communication apparatus has a function of implementing the second aspect. For example, the communication apparatus includes a corresponding module, unit, or means (means) for performing operations in the second aspect. The module, unit, or means may be specifically implemented by using software, may be implemented by using hardware, or may be implemented by using software in combination with hardware.

[0028] According to a fifth aspect, another communication apparatus is described. The communication apparatus includes a memory and one or more processors. The memory is configured to store a part or all of a necessary computer program or instructions for implementing a function in the first aspect. The one or more processors may execute the computer program or the instructions, and when the computer program or the instructions is / are executed, the communication apparatus is enabled to implement the method in any possible design or implementation of the first aspect.

[0029] In some embodiments, the communication apparatus may further include an interface circuit, and the processor is configured to communicate with another apparatus or component through the interface circuit.

[0030] The communication apparatus may be an initiator, a module in an initiator or a chip responsible for a communication function in an initiator, for example, a modem chip (also referred to as a baseband chip) or an SoC chip or an SIP chip that includes a modem module.

[0031] According to a sixth aspect, another communication apparatus is described. The communication apparatus includes a memory and one or more processors. The memory is configured to store a part or all of a necessary computer program or instructions for implementing a function in the second aspect. The one or more processors may execute the computer program or the instructions, and when the computer program or the instructions is / are executed, the communication apparatus is enabled to implement the method in any possible design or implementation of the second aspect.

[0032] In some embodiments, the communication apparatus may further include an interface circuit, and the processor is configured to communicate with another apparatus or component through the interface circuit.

[0033] The communication apparatus may be a responder, a module in a responder or a chip responsible for a communication function in a responder, for example, a modem chip (also referred to as a baseband chip) or an SoC chip or an SIP chip that includes a modem module.

[0034] According to a seventh aspect, a communication system is described, the communication system including a first communication apparatus configured to implement the method in any possible design or implementation of the first aspect and a second communication apparatus configured to implement the method in any possible design or implementation of the second aspect.

[0035] According to an eighth aspect, a computer-readable storage medium is described. The computer-readable storage medium stores computer-readable instructions, and when a computer reads and executes the computer-readable instructions, the computer is enabled to perform the method in any one of the possible designs of the first aspect to the second aspect.

[0036] According to a ninth aspect, this application provides a computer program product. When a computer reads and executes the computer program product, the computer is enabled to perform the method in any one of the possible designs of the first aspect to the second aspect.

[0037] This application encompasses various embodiments, including not only method embodiments, but also other embodiments such as apparatus embodiments and embodiments related to non-transitory computer readable storage media. Embodiments may incorporate, individually or in combinations, the features disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS

[0038] For a better understanding of the present disclosure, as well as other aspects and further features thereof, reference is made to the following description which is to be used in conjunction with the accompanying drawings.

[0039] FIG. 1 is a schematic illustration of an example communication system according to one or more implementations of the present disclosure.

[0040] FIG. 2 is a schematic illustration of another example communication system according to one or more implementations of the present disclosure.

[0041] FIG. 3 is a schematic illustration showing an apparatus wirelessly communicating with another apparatus within a communication system according to one or more implementations of the present disclosure.

[0042] FIG. 4 is a schematic illustration of an example apparatus according to one or more implementations of the present disclosure.

[0043] FIG. 5 is a schematic illustration of another example apparatus according to one or more implementations of the present disclosure.

[0044] FIG. 6 is a schematic illustration showing a procedure involving coding and modulationdemodulation in communication systems according to one or more implementations of the present disclosure.

[0045] FIG. 7 illustrates an example scheme of successive cancellation (SC) decoding.

[0046] FIG. 8 illustrates an example scheme of code segmentation.

[0047] FIG. 9 illustrates an example segmented CRC encoding.

[0048] FIG. 10 illustrates another example encoding and decoding process.

[0049] FIG. 11 illustrates an example flowchart of an encoding method according to one or more implementations of the present disclosure.

[0050] FIG. 12 illustrates simulation results of BLER of polar decoding under a fixed noise variance or a fixed SNR according to one or more implementations of the present disclosure.

[0051] FIG. 13 illustrates simulation results of BLER of polar decoding under different SNRs according to one or more implementations of the present disclosure.

[0052] FIG. 14 illustrates functions for proportions of CRC bits when different basic code rates are applied according to one or more implementations of the present disclosure.

[0053] FIG. 15 illustrates an example where the original information bits are divided into four segments according to one or more implementations of the present disclosure.

[0054] FIG. 16 illustrates another example where the original information bits are divided into four segments according to one or more implementations of the present disclosure.

[0055] FIG. 17 illustrates an example flowchart of a decoding method according to one or more implementations of the present disclosure.DETAILED DESCRIPTION

[0056] The following describes embodiments of the present disclosure with reference to the accompanying drawings in embodiments of the present disclosure. In the following description, specific aspects of embodiments of the present disclosure or specific aspects in which embodiments of the present disclosure may be used are shown by the accompanying drawings.

[0057] First, communication systems in which embodiments of the present disclosure may be applied are described below.

[0058] FIG. 1 is a schematic illustration of an example communication system according to one or more implementations of the present disclosure. There is shown a communication system 100 that includes a radio access network (RAN) 120, one or more communication electronic devices (EDs) 110a, 110b, 110c, 110d, 110e, 110f, 110g, 110h, 110i, 110j (collectively referred to as 110), a core network 130, a public switched telephone network (PSTN) 140, the Internet 150, and othernetworks 160. The RAN 120 may include, but is not limited to, a future generation RAN, or a legacy RAN such as, but not limited to, 5th generation (5G), 4th generation (4G), 3rd generation (3G), or 2nd generation (2G) RAN. The RAN 120 may be, for example, an evolved universal mobile telecommunications system (UMTS) terrestrial radio access network (E-UTRAN), a next generation RAN (NG RAN), or some other type of RAN. Examples of RAN 120 based on the evolution of telecommunications standards include, but is not limited to, global system for mobile communications (GSM) and code division multiple access (CDMA) for 2G, universal mobile telecommunications system (UMTS) based on wideband code division multiple access (WCDMA) and CDMA2000 for 3G, long-term evolution (LTE) and worldwide interoperability for microwave access (WiMAX) for 4G, and new radio (NR) for 5G. In some implementations, The RAN 120 may use any radio access technology (RAT) in the wireless interface between the one or more EDs 110 and the RAN 120. In some implementations, the term “radio access” may refer to the future generation air interface standards which may include both terrestrial networks (TNs) and nonterrestrial networks (NTNs). These networks will be described in greater detail below in conjunction with various implementations. The one or more communication EDs 110 (also referred to as “user equipment (UE)”) are configured to connect (e.g., communicatively couple) with each other or to one or more network nodes 170a, 170b (collectively referred to as 170) in the RAN 120. The CN 130 is apart of the communication system 100 and includes network nodes (e.g., 170a, 170b) which provide support for the network features and telecommunication services. In some implementations, the CN 130 may be dependent on the RAT used in the communication system 100. In other implementations, the CN 130 may be access-agnostic, i.e., the CN 130 may be independent of the RAT used in the communication system 100. There are different types of CN 130, for different the 3rd generation partnership project (3GPP) system generations. For example, the CN 130 is the evolved packet core (EPC) in 4G, also known as the evolved packet system (EPS). In another example, the CN 130 is the 5G core (5GC) which was developed as part of the 5G system (5GS). The CN 130 also enables integration of different 3GPP and non-3GPP access types. In some implementations and referring to FIG. 1, the CN 130 also provides the interface towards external networks that may include the PSTN 140, the Internet 150, and other networks 160 in the communication system 100.

[0059] In general, the communication system 100 facilitates interaction between multiple wireless or wired elements. The communication system 100 may transmit different types of content, such as voice, data, video, and / or text, through different transmission methods such as, but not limited to, broadcast, multicast, groupcast, and unicast. Additionally, the communication system 100operates by allocating and / or sharing resources, such as carrier spectrum bandwidth, among its constituent elements.

[0060] The communication system 100 may provide a wide range of communication services and applications including, but not limited to, enhanced mobile broadband (eMBB) services, ultrareliable low-latency communication (URLLC) services, massive machine type communication (mMTC) services, integrated sensing and communication (ISAC), immersive communication, ultra-massive machine-type communication (uMTC), hyper reliable and low-latency communication, ubiquitous connectivity, integrated artificial intelligence (Al) and communication, and other services that can be provided by a future generation communication system. The communication system 100 may provide other services and applications such as, but not limited to, earth monitoring, remote sensing, passive sensing and positioning, navigation and tracking, autonomous delivery and mobility, and the like.

[0061] The communication system 100 may include a terrestrial communication system (or network) and / or a non-terrestrial communication system (or network). The communication system 100 may provide a high degree of availability and robustness through a joint operation of the terrestrial communication system and the non-terrestrial communication system. For example, integrating a non-terrestrial communication system (or components thereof) into a terrestrial communication system can result in a heterogeneous network including multiple layers. The heterogeneous network may achieve better overall performance through efficient multi-link joint operation, more flexible functionality sharing, and faster physical layer link switching between terrestrial networks and non-terrestrial networks. The terrestrial communication system and the non-terrestrial communication system may be considered as sub-systems of the communication system 100.

[0062] FIG. 2 is a schematic illustration of another example communication system 100 according to one or more implementations of the present disclosure. There is shown the communication system 100 includes EDs 110a, 110b, 110c, 110d (collectively referred to as ED 110), RANs 120a, 120b, one or more CNs 130, a PSTN 140, the Internet 150, and other networks 160. Additionally, the communication system 100 may also include a non-terrestrial network (NTN) 120c. The RANs 120a and 120b may include network nodes 170a and 170b respectively. Examples of network nodes 170a, 170b include base stations, which can be generally referred to as terrestrial network (TN) devices or terrestrial transmit and receive points (T-TRPs) 170a and 170b (collectively referred to as 170). In this context, the terms “TRP” and “base station” are used interchangeably unless otherwise specified. For simplicity, this disclosure refers to network nodes as base stations; however, unless explicitly stated otherwise, references to TRP are considered non-limiting andinterchangeable. The T-TRPs 170a, 170b may be base stations mounted on a building or tower. In one implementation, the NTN 120c includes a RAN node such as a base station 172, which may be generally referred to as an NTN device, a non-terrestrial node, a non-terrestrial network device, a non-terrestrial base station, or a non-terrestrial transmit and receive point (NT-TRP) 172.

[0063] In some implementations, the NT-TRP 172 is not attached to the ground, for example, as in the case of an airborne base station. An airborne base station may be implemented using communication equipment supported or carried by a flying device. For example, a flying device may include, but is not limited to, an airborne platform (such as a blimp or an airship), balloon, drone (such as quadcopter), and other types of aerial vehicles. In some implementations, an airborne base station may be supported or carried by an unmanned aerial system (UAS) or an unmanned aerial vehicle (UAV), such as a drone. An airborne base station may be a moveable or mobile base station that can be flexibly deployed in different locations to meet network demand. A satellite base station is another example of a non-terrestrial base station. A satellite base station may be implemented using communication equipment supported or carried by a satellite. A satellite base station may also be referred to as an orbiting base station. High altitude platforms are yet another example of non-terrestrial base stations, including international mobile telecommunication base stations.

[0064] As referred to herein, and unless specified otherwise, a “TRP” may also refer to a T-TRP or an NT-TRP, a “T-TRP” may also refer to a “TN TRP”, and an “NT-TRP” may also refer to an “NTN TRP”. The NTN 120c may be considered a RAN, sharing operational aspects with RANs 120a, 120b. The NTN 120c may include at least one NTN device and at least one corresponding terrestrial network device. The at least one NTN device may function as a transport layer device and the at least one corresponding terrestrial network device may function as a RAN node, communicating with the ED 110 via the NTN device. Additionally, there may be an NTN gateway on the ground (referred to as a terrestrial network device) that also functions as a transport layer device facilitating communication with both the NTN device and the RAN node. The RAN node may communicate with the ED 110 via the NTN device and the NTN gateway. In some implementations, the NTN gateway and the RAN node may be located within the same device.

[0065] A base station 170 (also referred to as a TRP as stated above) is a network element within a radio access network responsible for radio transmission and reception in one or more cells to or from the ED (such as a user equipment). In different implementations, the base station 170 may also be known as a base transceiver station (BTS), a radio base station, a network node, a network device, a device on the network side, a transmit / receive node, a Node B, an evolved NodeB (eNodeB or eNB), a home eNodeB, a next generation NodeB (gNB), a transmission point (TP), asite controller, an access point (AP), a wireless router, a relay station, a terrestrial node, a terrestrial network device, a terrestrial base station, a non-terrestrial node, a non-terrestrial network device, a non-terrestrial base station, and a positioning node, among other possibilities. The base station 170 may be a macro base station (BS), a pico BS, a relay node, a donor node, or combinations thereof. When the base station 170 performs (or is configured to perform) a method described herein, it may be interpreted as the base station itself, one or more modules (or units) in the base station, a circuit or chip, or a combination thereof, performing the method. For example, the circuit or chip may include a modem chip, also referred to as a baseband chip, a system on chip (SoC) including a modem core, system in package (SIP), and the like, and may be responsible for one or more communication functions within the base station.

[0066] The EDs 110a- 110d and TRPs 170a- 170b, 172 are examples of communication equipment configured to implement some or all of the operations and / or implementations described herein. The T-TRP 170a forms part of the RAN 120a, which may include other TRPs, and / or other devices. Also, the TRP 170b forms part of the RAN 120b, which may include other TRPs, and / or devices. Each TRP 170a, 170b may transmit and / or receive wireless signals within a particular geographic region or area, sometimes referred to as a “cell” or a “coverage area”. The TRPs 170a- 170b may be responsible for allocating and / or configuring resources and transmission and / or reception in a set of cell(s). A cell is a radio network object that can be uniquely identified by a cell identification that is broadcasted over a geographical region or area from base stations associated with the cell. A cell can work in either frequency division duplex (FDD) or time division duplex (TDD) mode. A cell may be further divided into cell sectors, and a base station 170a-170b may, for example, employ one or more transceivers to provide services to one or more sectors. Some implementations, may include pico or femto cells if supported by the radio access technology. In some implementations, one or more transceivers may be used for each cell, such as with multiple-input multiple-output (MIMO) technology. The number of RANs 120a- 120b shown is merely an example. Any number of RANs may be contemplated when designing the communication system 100.

[0067] A base station may be a single element, as shown in the figures, or multiple elements distributed throughout the corresponding RAN, or otherwise configured. In some implementations, a plurality of RAN nodes coordinate to assist the ED 110 in implementing radio access, and different RAN nodes separately implement and handle different functions of the base station. For example, the RAN node may be a central unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU) etc. The CU and the DU may be separately deployed, or included within the same element (i.e., a baseband unit (BBU)). The RU may beincluded in a radio frequency device or a radio frequency unit (i.e., a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). In different systems, the CU (or the CU-CP and the CU-UP), the DU, or the RU may be known by different names, but their functions are understood by a person skilled in the art. For example, in an open radio access network (ORAN) system, a CU may be referred to as an open CU (O-CU), a DU may be referred to as an open DU (O-DU), and a CU-CP may be referred to as an open CU-CP (O-CU-CP). The CU-UP may also be referred to as an open CU-UP (O-CU-UP), and the RU may also be referred to as an open RU (O-RU). Any one of the CU (or the CU-CP, the CU-UP), the DU, and the RU may be implemented using a software module, a hardware module, or a combination of a software module and a hardware module.

[0068] Furthermore, communication between different devices / apparatuses in various implementations of this disclosure may refer to direct communication (that is, without the need of forwarding by another device / apparatus), or may refer to communication(s) between different devices / apparatuses via another device / apparatus (that is, requiring forwarding by another device / apparatus). Alternatively, such communication(s) may involve one functional unit inside a device / apparatus using another functional unit within the device / apparatus to communicate with another device / apparatus. In other words, phrases such as “sending (or transmitting) information to... (an ED or a base station)” in this disclosure may be understood as a destination endpoint of the information being an ED or a base station, including, sending / transmitting information directly or indirectly to an ED or a base station. Similarly, phrases like “receiving information from... (an ED or a base station)” may be understood as a source endpoint of the information being an ED or a base station, including directly or indirectly receiving information from an ED or a base station. Between the source endpoint that sends the information and the destination endpoint, necessary processing such as, but not limited to, format conversion, digital-to-analog conversion, amplification, and filtering may be performed on the information. However, the destination endpoint may understand valid information from the source endpoint. A similar understanding applies to other descriptions in this disclosure without reiterating details already described. In the present disclosure, the terms “send” and “transmit” may be used interchangeably in different implementations of this disclosure.

[0069] The ED 110 is used to connect people, objects, machines, and other entities. The ED 110 may be widely used in various scenarios including, but not limited to, cellular communications, device-to-device (D2D), vehicle to everything (V2X), peer-to-peer (P2P), machine-to-machine (M2M), MTC, internet of things (loT), virtual reality (VR), augmented reality (AR), mixed reality (MR), metaverse, digital twin, industrial control, self-driving, remote medical, smart grid, smartfurniture, smart office, smart wearable, smart transportation, smart city, drones, robots, remote sensing, passive sensing, positioning, navigation and tracking, and autonomous delivery and mobility.

[0070] Each ED 110 represents any suitable end user device for wireless operation and may include such devices (or may be referred to as, but not limited to) a user equipment (UE) or a user device or a terminal device, a wireless transmit / receive unit (WTRU), a mobile station, a fixed or mobile subscriber unit, a cellular telephone, a station (STA), an MTC device, a personal digital assistant (PDA), a smartphone, a laptop, a computer, a tablet, a wireless sensor, a consumer electronics device, a smart book, a vehicle, a car, a truck, a bus, a train, or an loT device, wearable devices (such as a watch, a pair of glasses, head mounted equipment, etc.), an industrial device, or an apparatus (such as a module, modem, or chip) in the forgoing devices, among other possibilities. Future generation EDs 110 may be referred to by other terms. When an ED 110 performs (or is configured to perform) a method described herein, it may be interpreted as the ED itself, one or more modules (or units) in the ED, a circuit or chip, or a combination thereof, performing the method. For example, the circuit or chip may include a modem chip, also referred to as a baseband chip, an SoC including a modem core, or an SIP, and the like, and may be responsible for one or more communication functions in the ED.

[0071] Each ED 110 connected to TRPs 170a- 170b, and / or TRPs 172 can be dynamically or semi-statically tumed-on (i.e., established, activated, or enabled), turned-off (i.e., released, deactivated, or disabled) and / or configured in response to one of more of: connection availability and connection necessity.

[0072] Any ED 110 may be alternatively or additionally configured to interface, access, or communicate with any of the TRPs 170a, 170b and 172, the Internet 150, the CN 130, the PSTN 140, the other networks 160, or any combination thereof. In some examples, the ED 110a may communicate an uplink (UL) and / or downlink (DL) transmission over a terrestrial air interface 190a with station-TRP 170a. In some examples, the EDs 110a, 110b, 110c, and HOd may also communicate directly with one another via one or more sidelink (SL) air interfaces 190b. In some examples, the EDs 110a, 110d may communicate using an UL and / or DL transmission over a nonterrestrial air interface 190c withNT-TRP 172.

[0073] An air interface (such as, for example, 190a, 190b, 190c) generally includes a number of components and associated parameters that collectively specify how a transmission is to be sent and / or received over a wireless communications link between two or more communicating devices such as EDs and base station(s). For example, an air interface may include one or more components defining the waveform(s), frame structure(s), multiple access scheme(s), protocol(s), codingscheme(s) and / or modulation scheme(s) for conveying information (such as, data) over a wireless communications link. The air interfaces 190a and 190b may use similar communication technology, that may include any suitable radio access technology.

[0074] The non-terrestrial air interface 190c can enable communication between the EDs 110a, 110d and one or more NT-TRPs 172 via a wireless link or simply a link. For some examples, the link is a dedicated connection for unicast transmission, a connection for broadcast transmission, or a connection between a group of EDs 110 and one or more NT-TRPs 172 for multicast transmission.

[0075] The TRPs 170a- 170b, 172 may communicate with one another over one or more air interfaces 190e, 190f using wireless communication links (such as radio frequency (RF), microwave, infrared (IR), etc.) or wired communication links. The air interfaces 190e, 190f may utilize any suitable radio access technology, and may be substantially similar to the air interfaces 190a, 190c over which the EDs 110a-110d communicate with one or more of the TRP 170a- 170b, 172 or they may be substantially different. For example, the communication system 100 may implement one or more channel access methods, such as time division multiple access (TDMA), frequency division multiple access (FDMA), code division multiple access (CDMA), single carrier frequency division multiple access (SC-FDMA), low density signature multicarrier code division multiple access (LDS-MC-CDMA), non-orthogonal multiple access (NOMA), pattern division multiple access (PDMA), lattice partition multiple access (LPMA), resource spread multiple access (RSMA), and sparse code multiple access (SCMA).

[0076] The RANs 120a and 120b are in communication with the CN 130 to provide the EDs 110a 110b, and 110c with various services such as voice, data, multimedia, and other services. The RANs 120a and 120b and / or the CN 130 may be in direct or indirect communication with one or more other RANs (not shown), which may or may not be directly served by the CN 130, and may employ different radio access technologies from RAN 120a and / or RAN 120b. The CN 130 may also serve as a gateway access between (i) the RANs 120a and 120b and / or the EDs 110a 110b, and 110c, and (ii) other networks (such as the PSTN 140, the Internet 150, and the other networks 160). In addition, some or all of the EDs 110a 110b, and 110c may include functionality for communicating with different wireless networks over different wireless links using different wireless technologies and / or protocols. For example, the EDs 110a 110b, and 110c communicate using different cellular communications protocols, such as, but not limited to, a global system for mobile communications (GSM) protocol, a code-division multiple access (CDMA) network protocol, a push-to-talk (PTT) protocol, a PTT over cellular (POC) protocol, a universal mobile telecommunications system (UMTS) protocol, a 3 GPP long term evolution (LTE) protocol, a fifthgeneration (5G) protocol, a new radio (NR) protocol, and the like. Instead of wireless communication (or in addition thereto), the EDs 110a, 110b, and 110c may communicate using wired communication channels to a service provider or switch (not shown), and / or to the Internet 150. The PSTN 140 may include circuit switched telephone networks for providing plain old telephone service (POTS). The Internet 150 may include a network of computers and subnets (intranets) or both, and incorporate protocols, such as internet protocol (IP), transmission control protocol (TCP), user datagram protocol (UDP). EDs 110a 110b, and 110c may be multimode devices capable of operation according to multiple radio access technologies, and may incorporate one or multiple transceivers necessary to support such.

[0077] In addition, the communication system 100 may include a sensing agent (not shown) to manage the sensed data from ED 110 and / or any one of TRPs 170a, 170b, 172. In one implementation, the sensing agent may be part of any one of TRPs 170a, 170b, 172. In another implementation, the sensing agent is a separate node that can communicate with the CN 130 and / or the RAN 120 (such as any one of TRPs 170a, 170b, 172).

[0078] FIG. 3 is a schematic illustration showing an apparatus 310 wirelessly communicating with another apparatus 320 within a communication system (e.g., the communication system 100) according to one or more implementations of the present disclosure. The apparatus 310 may be an electronic device (such as ED 110). The apparatus 320 may be a network node (e.g., the network node 170) such as T-TRP 170 or an NT-TRP 172. Although only one apparatus 310, and one apparatus 320 are shown in the figure, the number of apparatuses 310 and / or number of apparatuses 320 can vary, potentially including one or more of each. For example, a single ED 110 may be served by a single T-TRP 170 (or a single NT-TRP 172), or by multiple T-TRPs 170 (or multiple NT-TRPs 172). Similarly, a single ED 110 may be served by one or more T-TRPs 170 and one or more NT-TRPs 172. Similarly, a single T-TRP 170 (or a single NT-TRP 172) may serve one or more EDs 110.

[0079] The apparatus 310 may include one or more processors 210. For clarity and to avoid overcrowding the illustration, only a single processor 210 is illustrated. The apparatus 310 may further include a transmitter 201 and a receiver 203 coupled to one or more antennas 204. For clarity, only a single antenna 204 is illustrated. One, some, or all of the antennas 204 may alternatively be panels. In some implementations, the transmitter 201 and the receiver 203 are separate from each other. In other implementations, the transmitter 201 and the receiver 203 may be integrated into a single unit, for example, as a transceiver. The transceiver is configured to modulate data or other content for transmission by the one or more antennas 204 or a network interface controller (NIC). The transceiver may also be configured to demodulate data or othercontent received by the one or more antennas 204. A transceiver may include any suitable structure for generating signals for wireless or wired transmission and / or for processing signals received through wireless or wired communication. Each antenna 204 includes any suitable structure for transmitting and / or receiving wireless or wired signals. The apparatus 310 may include a memory 208. In some implementations, the apparatus 310 may include multiple memories 208. Only a single transmitter 201, receiver 203, processor 210, memory 208, and antenna 204 is illustrated for simplicity, but the apparatus 310 may include one or more other components. In some implementations of the present disclosure, the transceiver (or transmitter 201 and / or receiver 203) may be viewed as an interface circuit.

[0080] The memory 208 is configured to store instructions used to perform operations described herein. The memory 208 may also be configured to store data that are used, generated, or collected by the apparatus 310. For example, the memory 208 can store software instructions or modules configured to implement some or all of the functionalities and / or operations described herein and that which are executed by the one or more processors 210.

[0081] The apparatus 310 may further include one or more input / output devices (not shown) or interfaces. The input / output devices or interfaces facilitate interaction with a user or other devices in the network. Each input / output device or interface includes suitable components for facilitating transmission of information to a user and reception of information from a user, and for various network interface communications. Such components may include, but are not limited to, a speaker, microphone, keypad, keyboard, display, touch screen, and the like.

[0082] The processor 210 may be configured to perform (or control the apparatus 310 to perform) operations (or methods) described herein as being performed by the apparatus 310. For example, the processor 210 performs or controls the apparatus 310 to perform the operations of: (a) receiving one or more transport blocks (TBs), (b) using a resource for decoding at least one of the received TBs, (c) releasing the resource for decoding another of the received TBs, and / or (d) receiving configuration information configuring a resource. Specifically, the operations may include tasks related to: preparing a transmission for UL transmission to the apparatus 320, processing DL transmissions received from the apparatus 320, and handling SL transmission to and from another apparatus 310. Processing operations related to preparing a transmission for UL transmission may include operations such as, but not limited to, encoding, modulating, transmit beamforming, and generating symbols for transmission. Processing operations related to processing DL transmissions may include operations such as, but not limited to, receive beamforming, demodulating and decoding received symbols. Processing operations related to processing SL transmissions may include operations such as, but not limited to, transmit / receive beamforming,modulating / demodulating and encoding / decoding symbols. Depending upon the implementation, a DL transmission may be received by the receiver 203, possibly using receive beamforming, and the processor 210 may extract signaling from the DL transmission (such as by detecting and / or decoding the signaling). An example of signaling may be a reference signal transmitted by the apparatus 320. In some implementations, the processor 210 implements the transmit beamforming and / or the receive beamforming based on the indication of beam direction, such as beam angle information (BAI), received from the apparatus 320. In some implementations, the processor 210 may be configured to perform operations relating to network access (such as initial access) and / or downlink synchronization, which includes operations for detecting a synchronization sequence, decoding and obtaining the system information, and the like. In some implementations, the processor 210 may perform channel estimation, such as using a reference signal received from the apparatus 320.

[0083] Although not illustrated, in some implementations, the processor 210 may either be a part of the transmitter 201 or a part of the receiver 203 or a part of both the transmitter 201 and the receiver 203. Although not illustrated, in some implementations, the memory 208 may be a part of the processor 210.

[0084] The processor 210, along with the processing components of the transmitter 201 and the receiver 203 may each be implemented by one or more processors that may the same or different. These processors are configured to execute instructions stored in a memory (such as in the memory 208).

[0085] The apparatus 320 includes one or more processors 260 (only one processor 260 is illustrated). The apparatus 320 may further include one or more transmitters 252 and one or more receivers 254 coupled to one or more antennas 256. Only a single antenna 256 is illustrated to avoid clutter in the illustration. One, some, or all of the antennas 256 may alternatively be panels. In some implementations, the transmitter 252 and the receiver 254 are separate from each other. In other implementations, the transmitter 252 and the receiver 254 may be integrated into a single unit such as, for example, as a transceiver. The apparatus 320 may further include a memory 258. In some implementations, the apparatus 320 may include multiple memories 258. The apparatus 320 may further include a scheduler 253. Only a single transmitter 252, receiver 254, processor 260, memory 258, antenna 256, and scheduler 253 are illustrated for simplicity, however the apparatus 320 may include one or more other components. In the present disclosure, in some implementations, the transceiver (or transmitter 252 and / or receiver254) may be viewed as an interface circuit.

[0086] In some implementations, various components of the apparatus 320 may be distributed. For example, some of the modules of the apparatus 320 may be located remotely from the equipment housing the antennas 256 for the apparatus 320 (and therefore also can be viewed as one or more nodes). These modules, which can be considered as one or more nodes, may be coupled to the equipment that houses the antennas 256 over a communication link (not shown), sometimes referred to as front haul, such as the common public radio interface (CPRI). Therefore, in some implementations, the term apparatus 320 may also refer to network-side nodes that perform processing operations such as, but not limited to, determining the location of the apparatus 310, resource allocation (scheduling), message generation, and encoding / decoding, and that which are not necessarily part of the equipment that houses the antennas 256 of the apparatus 320. The nodes may also be coupled to other apparatuses 320. In some implementations, the apparatus 320 may actually be a plurality of nodes that are operating together to serve the apparatus 310, such as through the use of coordinated multipoint transmissions, or through the use of ORAN system as described above in the disclosure.

[0087] The processor 260 is configured to perform operations including those related to: preparing a transmission for DL transmission to the apparatus 310, processing an UL transmission received from the apparatus 310, preparing a transmission for backhaul transmission to another apparatus 320, and processing a transmission received over backhaul from another apparatus 320. Processing operations related to preparing a transmission for DL or backhaul transmission may include operations such as, but not limited to, encoding, modulating, precoding (such as MIMO precoding), transmit beamforming, and generating symbols for transmission. Processing operations related to processing received transmissions in the UL or over backhaul may include operations such as, but not limited to, receive beamforming, demodulating received symbols, and decoding received symbols. The processor 260 may also be configured to perform operations relating to network access (such as initial access) and / or DL synchronization, such as generating the content of synchronization signal blocks (SSBs), generating the system information, and the like. In some implementations, the processor 260 is further configured to generate an indication of beam direction, such as BAI, which may be scheduled for transmission by the scheduler 253 which will be described below. In some implementations, the processor 260 implements the transmit beamforming and / or receive beamforming based on beam direction information (such as BAI) received from another apparatus 320. The processor 260 is configured to perform other network side processing operations described herein, such as, but not limited to, determining the location of the apparatus 310, determining where to deploy another apparatus 320, and the like. In some implementations, the processor 260 may generate signaling data, to configure one or moreparameters of the apparatus 310 and / or one or more parameters of another apparatus 320. Any signaling data generated by the processor 260 are sent by the transmitter 252. In some implementations, the apparatus 320 implements physical layer processing. In some implementations, the apparatus 320 may perform higher layer functions such as those at the medium access control (MAC) or radio link control (RLC) layers in addition to physical layer processing. In the apparatus 320, the scheduler 253 may be coupled to the processor 260 or integrated within the processor 260. In some implementations, the scheduler 253 may be integrated within the apparatus 320 or may be operated separately from the apparatus 320. The scheduler 253 may schedule UL, DL, SL, and / or backhaul transmissions, including issuing scheduling grants and / or configuring scheduling-free (such as “configured grant”) resources.

[0088] The apparatus 320 may further include a memory 258 that is configured to store instructions for performing the operations described herein. The memory 258 may also store data that are used, generated, or collected by the apparatus 320. For example, the memory 258 can store software instructions or modules configured to implement some or all of the functionalities and / or implementations described herein and that which are executed by the processor 260.

[0089] Although not illustrated, the processor 260 may be implemented as part of the transmitter 252 and / or a part of the receiver 254. Although not illustrated, in some implementations, the processor 260 may implement the scheduler 253 and the memory 258 may be implemented as part of the processor 260.

[0090] The processor 260, the scheduler 253, the processing components of the transmitter 252, and the processing components of the receiver 254 may each be implemented by the same or different processors that are configured to execute instructions stored in a memory, such as in the memory 258.

[0091] The apparatus 320 and / or the apparatus 310 may include other components, not shown or described herein for the sake of clarity.

[0092] Note that the term “signaling”, as used herein, may alternatively be referred to as control signaling, control message, control information, or message for simplicity. Signaling between a base station (such as the TRP 170a. 170b, 172) and a UE or sensing device (such as ED 110), or signaling between a different UE or sensing device (such as between ED 110a and ED 110b) may be carried in physical layer signaling (also called as dynamic signaling), which is transmitted in a physical layer control channel. For DL, the physical layer signaling may be known as downlink control information (DCI) which is transmitted in a physical downlink control channel (PDCCH). For UL, the physical layer signaling may be known as uplink control information (UCI) which is transmitted in a physical uplink control channel (PUCCH). For SL, signaling between differentUEs or sensing devices (such as between ED 110a and ED 110b) may be known as SL control information (SCI) which is transmitted in a physical sidelink control channel (PSCCH). Signaling may be carried in a higher layer (such as higher than physical layer) signaling, which is transmitted in a physical layer data channel, such as in a physical downlink shared channel (PDSCH) for downlink signaling, in a physical uplink shared channel (PUSCH) for uplink signaling, and in a physical sidelink shared channel (PSSCH) for SL signaling. Higher layer signaling may also be called static signaling, or semi-static signaling. The higher layer signaling may include radio resource control (RRC) protocol signaling or media access control - control element (MAC-CE) signaling. Signaling may be included in a combination of physical layer signaling and higher layer signaling.

[0093] It is noted that in the present disclosure, “information”, when different from “message”, may be carried within a single message, or may be carried in multiple separate messages.

[0094] FIG. 4 is a schematic illustration of an example apparatus 410 according to one or more implementations of the present disclosure. The apparatus 410 may be a communication device or an apparatus implemented in a communication device such as the ED 110 or the TRPs 170a, 170b, 172. For example, the apparatus 410 implemented in an ED may be an integrated circuit, which in some instances may be referred to as a chip, a modem, a modem chip, a baseband chip, or a baseband processor. In some implementations, one or more integrated circuits can be packaged into an SoC, an SIP, or a multi-chip module. The apparatus 410 can include one or more integrated circuits and other discrete components. In some implementations, the apparatus 410 may be a module within the ED 110, or within the apparatus 310. In some implementations, the apparatus 410 may be a module within one of the TRPs 170a, 170b, 172, or the apparatus 320.

[0095] In an example, the apparatus 410 may include one or more processors 411, and an interface circuit 412. The apparatus 410 may further include a memory 413. The one or more processors 411 are configured to process signals and execute one or more communication protocols. The memory 413 is configured to store at least a part of corresponding computer program instructions and / or data. In an example, the one or more processors 411 execute the computer program instructions stored in the memory 413 to implement related operations (for example, inputting, outputting, receiving, and transmitting) in the method embodiments disclosed herein. In some implementations, the memory 413 being configured to store the corresponding computer program instructions and / or data may mean that the memory 413 is configured to store all of the corresponding computer program instructions and / or data for execution by the one or more processors 411. In some implementations, the memory 413 being configured to store the corresponding computer program instructions and / or data may mean that the memory 413 isconfigured to store a part of the corresponding computer program instructions and / or data. For example, the part of the corresponding computer program instructions and / or data may include computer program instructions and / or data that need to be currently executed by the one or more processors 411. Thus, the memory 413 may store different parts of computer program instructions and / or data for a plurality of times for the one or more processors 411 to perform related operations in the method embodiments disclosed herein. As a communication interface, the interface circuit 412 is configured to implement communication with another component. For example, the interface circuit 412 may communicate a signal with another apparatus or system, such as a radio frequency processing apparatus or another processor. The signal may include or carry information intended as a payload, such as user data, control information, etc. The signal may also include or carry information useful to a receiver, but not necessarily as a payload, such as a pilot signal or reference signal. Communicating the signal may include transmitting the signal to another component or device. Communicating the signal may additionally or alternatively include receiving the signal from another component or device. Transmitting the signal may include outputting the signal to a component or device that is directly or indirectly coupled to the interface circuit 412. Receiving the signal may include inputting or obtaining the signal from a component or device that is directly or indirectly coupled to the interface circuit 412. For example, to reduce a load of the one or more processors, a baseband signal processing circuit 414 may be also disposed to implement processing of at least a part of baseband signals, including signal demodulation, modulation, encoding, decoding, or the like.

[0096] The apparatus 410 may be the processor 210 (or 260) within the apparatus 310 (or 320), in some scenarios, or may be included within the processor 210 (or 260) within the apparatus 310 (or 320) in some scenarios. The apparatus 410 may be a baseband chip or may include a baseband chip. In some implementations, the apparatus 410 may be independently packaged into a chip. In some implementations, the apparatus 310 (or 320) includes different types of chips. The apparatus 410 may be packaged into a processor chip (for example, an SoC chip or an SIP chip) with the different types of chips. In some implementations, the apparatus 410 may be packaged into a chip with some or all of circuits of a radio frequency processing system that may further be included in the apparatus 310 (or 320).

[0097] FIG. 5 is a schematic illustration of an example apparatus 510 according to one or more implementations of the present disclosure. The apparatus 510 may include corresponding modules or units configured to implement methods and / or implementations described herein. In some implementations, the apparatus 510 includes a processing unit 512 and a communication unit 513.For example, the apparatus 510 may further include a storage unit 511 configured to store apparatus program code (or instructions) and / or data.

[0098] The apparatus 510 may be an ED side apparatus, for example, an ED or a module in an ED, or a circuit or a chip responsible for a communication function in an ED. In some implementations, apparatus 510 may be the apparatus 310. The processing unit 512 may be the processor 210. The communication unit 513 may include a receiving unit and / or a transmitting unit. The receiving unit and / or the transmitting unit may be the transmitter 201 and / or the receiver 203 respectively. The storage unit 511 may be the memory 208.

[0099] The apparatus 510 may be a base station side apparatus, for example, a base station or a module in a base station, or a circuit or a chip responsible for a communication function in a base station. In some implementations, the apparatus 510 may be the apparatus 320. The processing unit 512 may be the processor 260 (the scheduler 253 may also be included). The communication unit 513 may include a receiving unit and / or a transmitting unit. The receiving unit and / or the transmitting unit may be the transmitter 252 and / or the receiver 254 respectively. The storage unit 511 may be the memory 258.

[0100] In some implementations, when the apparatus 510 is an ED 110 or a module in an ED 110, a function of the apparatus 510 may be implemented by one or more processors. Specifically, the processor may include a modem chip, or an SoC chip or an SIP chip that includes a modem core. A function of the communication unit 513 may be implemented by a transceiver circuit.

[0101] In some implementations, when the apparatus 510 is a circuit or a chip that is responsible for a communication function in an ED 110, such as, for example, a modem chip, an SoC chip or an SIP chip that includes a modem core - a function of the processing unit 512 may be implemented by a circuit system within the chip which includes one or more processors. A function of the communication unit 513 may be implemented by an interface circuit or a data transceiver circuit on the chip.

[0102] It may be understood that the units in the apparatus 510 may be logical or functional. Each function may correspond to one functional unit, or two or more functions may be integrated into a single functional unit. In actual implementation, all or some of the units may be integrated into a single physical entity, or may be distributed across different physical entities. In addition, the functional units may be implemented in the form of hardware, software, or a combination of hardware and software. Whether a function is implemented in the form of hardware or software depends on particular applications and design constraint conditions of the technical solutions. A person skilled in the art may use different methods to implement the described functions forspecific applications, but it may not be considered that the implementation goes beyond the scope of this disclosure.

[0103] In an example, a functional unit in any one of the apparatuses may be configured as one or more integrated circuits for implementing the methods disclosed herein, for example, as one or more application-specific integrated circuits (ASICs), one or more central processing units (CPUs), one or more microprocessors or microprocessor units (MPUs), one or more microcontrollers or microcontroller units (MCUs), one or more digital signal processors (DSPs), one or more field programmable gate arrays (FPGAs), or a combination of these.

[0104] In an example, the storage unit 511 may include a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, and / or a register.

[0105] A processor may be referred to as a processor system, an application processor, a baseband processor, a processor circuit, or a processor core. The processor may include one or a combination of one or more CPUs, one or more DSPs, one or more MPUs, one or more MCUs, one or more graphics processing units (GPUs), one or more field programmable gate arrays (FPGAs), one or more artificial intelligence processors (Al processors), or one or more neural network processing units (NPUs).

[0106] Memory or a storage unit may include one or more of the following storage media: a random access memory (RAM), a static random access memory (static RAM, SRAM), a dynamic random access memory (dynamic RAM, DRAM), a phase-change memory (PCM), a resistive random access memory (resistive RAM, ReRAM), a magnetoresistive random access memory (magnetoresistive RAM, MRAM), a ferroelectric random access memory (ferroelectric RAM, FRAM), a cache, a register, a read-only memory (ROM), a flash memory (flash memory), an erasable programmable read-only memory (erasable programmable ROM, EPROM), a hard disk, and the like. In an example, computer program instructions used to execute embodiments may be stored in a non-volatile memory, for example, at least a part of a memory or storage unit (for example, one or more of a ROM, a flash memory, an EPROM, or a hard disk). When a terminal runs, a part or all of corresponding computer program instructions may be loaded to a memory that has a higher transmission speed with the processor, for example, at least a part of a memory or a storage unit (for example, one or more of a RAM, an SRAM, a DRAM, a PCM, a RERAM, an MRAM, a FRAM, a cache, or a register), so that the processor executes the computer program instructions to perform the steps in the method embodiments disclosed herein.

[0107] The above describes communication systems in which embodiments of the present disclosure may be applied and elements in the communication systems. The following describes acoding and modulation-demodulation procedure in the communication systems. The coding and modulation-demodulation procedure ensures that information is transmitted and received correctly in the communication systems.

[0108] FIG. 6 is a schematic illustration showing a procedure involving coding and modulationdemodulation in communication systems according to one or more implementations of the present disclosure. For a transmitting end in the communication systems, original information that is to be transmitted is generated or obtained. The original information undergoes sequentially source encoding, channel encoding, and modulation, to obtain a modulation symbol. The transmitting end outputs or transmits the modulation symbol. Accordingly, for a receiving end in the communication systems, the modulation symbol is received. The modulation symbol undergoes sequentially demodulation, channel decoding, and source recovery, to obtain recovered original information. The recovered original information may be used, displayed, or stored as needed. The transmitting end may be the above ED 110 and the receiving end may be the above base station 170; the transmitting end may be the above base station 170 and the receiving end may be the above ED 110; the transmitting end and the receiving end may be two different EDs 110; or the transmitting end and the receiving end may be two different base stations 170.

[0109] Channel encoding and channel decoding are two aspects of channel coding. The channel encoding involves a process of adding redundancy to the original information before transmission, which allows the receiving end to detect and correct errors that may occur during the transmission process. The channel decoding is an inverse operation of the channel encoding. There are several types of codes applied in the channel coding such as polar codes, low-density parity-check (LDPC) codes, or Turbo codes. The following will describe several decoding methods for polar codes.

[0110] 1. Successive Cancellation (SC) Decoding

[0111] The SC decoding offers a simple approach to decode received information. The received information may refer to demodulated information by demodulating the received modulation symbol(s). During the SC decoding, bits in the received information are decoded sequentially, with one bit being decoded at a time. The SC decoding may be viewed as a depth-first binary tree search with preference to a left branch.

[0112] FIG. 7 illustrates an example scheme of the SC decoding. During the SC decoding, soft information is passed from a non-leaf node to leaf node(s), traversing a tree from left-to-right nodes. The soft information refers to reliability or confidence information about the received information. The soft information may be represented in the form of real numbers, such as the loglikelihood ratio (LLR). The LLR is used to measure whether the received information is more likely to be 0 or 1.

[0113] In FIG. 7, v represents a current node being processed and the current node may be an internal (i.e., non-leaf) node.and vrrepresent left and right child nodes of node v, respectively. pvrepresents a parent node of node v. avrepresents soft reliability values such as LLR passed from the parent node pvto the current node v.represents hard decision bit estimates passed back from the current node v to the parent node pv. aVland aVrrepresent soft reliability values passed from node v to its left child node vland right child node vr, respectively. βVland βVrrepresent hard decision bit estimates passed back from the left child node vland right child node vrto node v, respectively.

[0114] The SC decoder that performs the SC decoding may be described by the following recursive algorithm. When an internal (i.e., non-leaf) node v is activated, the SC decoder calculates aVlby a formula of:

[0115] where S is an operator which combines two extended real numbers x and y to form xffly = 2atanh(tanh(x / 2)tanh(y / 2)). aVlis then passed to vt, where dvis the depth of the current constituent code, n = log2(N), N is code length, i is the index of node at depth dv.

[0116] The node v then waits until it receives codeword fVlfrom vt. It then calculates aVrby a formula of:where aVris then passed to vr.

[0117] The node v then waits until it receives codeword ftVrfrom vr. It then calculates by a formula of:βv[2i + 1] = βVr[i] and βv[2i] = βVl[i] ⊕ βVr[i],then passed to pv.

[0118] However, when an incorrect decision is made regarding a bit in the received information, this error affects the decoding of all subsequent bits in the received information. Therefore, the error correction performance of the SC decoding degrades under challenging channel conditions. In addition, the sequential execution of the SC decoding leads to a delay.

[0119] 2. Successive Cancellation List (SCL) Decoding

[0120] The SCL decoding is designed to address limitations of the SC decoding in determining bits in the received information. In the SCL decoding, instead of making an unambiguous decision for each bit, whether it is 0 or 1, the decoding path is split into two: one path assumes that the bit is 0 and the other path assumes that the bit is 1. In this way, the decoder that performs the SCL decoding considers both possibilities simultaneously. Since the number of candidate paths for thereceived information doubles with each bit, a parameter may be needed to limit the number of candidate paths for the received information to avoid exponential growth in decoding complexity. To reduce the number of candidate paths for the received information, a criterion is required to determine which paths may be pruned (i.e., removed from the candidate list). In some solutions, the most probable path(s) may be kept.

[0121] The SCL decoding works by maintaining a list of potential codeword candidates, thereby improving the likelihood of accurately recovering the received information. While the error correction performance of the SCL decoding is better than that of the SC decoding, the SCL decoding also comes with a trade-off of higher computational complexity and increased delay, which may be detrimental in real-time communication scenarios where the low latency is needed.

[0122] 3. Cyclic Redundancy Check Aided Successive Cancellation List (CA-SCL) Decoding

[0123] The CA-SCL decoding is a combination of SCL decoding and cyclic redundancy check (CRC) detecting. The CA-SCL decoding achieves a lower bit error rate compared with using only the SCL decoding.

[0124] To solve the problem of selecting the final decoding path from multiple candidate paths at the SCL output, the use of CRC as a verification method was proposed. By adding CRC bits during the encoding process, it is possible to verify correctness of the received information during the decoding process. In the CA-SCL decoding, all candidate paths generated by the SCL decoding undergo CRC verification. Paths that pass the CRC verification are retained. The path with the smallest metric value (such as path metric or likelihood ratio) is selected from the candidate paths that have passed the CRC verification as the final decoding result.

[0125] However, the CA-SCL decoder that performs the CA-SCL decoding still suffers from its own disadvantage. For example, the decoding complexity of an JV-bit CA-SCL decoder with list size L is 풪(LN log N), where N is the code length, and L is the list size of the decoder. For highly noisy scenarios, which are common for wireless communications, large values of both L and N are always necessary to achieve the required performance. For these applications, how to properly balance the complexity and performance becomes crucial. Another problem is weak path management. The incorrect paths may be disregarded only at the last step of the decoding. Thus, the CA-SCL decoding is not able to check whether the decoded bits are correct or not until the last step. This disadvantage results in unnecessary decoding complexity and worse performance, especially in a low signal-to-noise ratio (SNR) region.

[0126] 4. Segmented CA-SCL (SCA-SCL) Decoding

[0127] The SCA-SCL decoding is proposed to reduce the decoding complexity and improve the decoding performance of the CA-SCL decoding. For the SCA-SCL encoding, the vector of thewhole bits is divided into subvectors and a CRC is attached to each subvector. Therefore, for the SCA-SCL decoding, each subvector is decoded and verified sequentially. When a subvector does not pass the CRC verification, the decoding process may end. This modification allows for preliminary stopping of the decoding and intermediate CRC verification, thereby improving the decoding performance.

[0128] The SCA-SCL decoding is suitable for highly noisy scenarios, such as in wireless communications, where large values of both list size and code length are essential for optimal performance. The SCA-SCL decoding helps balance complexity and delay by allowing for intermediate CRC verification through subdivision of the vector into smaller subvectors, enabling early stopping of decoding and decreasing complexity and memory requirements. This addresses the drawback of CA-SCL decoders that perform the CA-SCL decoding. The CA-SCL decoding requires the decoding of the whole received vector of length N, which results in high complexity and memory consumption, while the SCA-SCL decoding allows to use for smaller length codes, e.g., two N / 2 codes, thus reducing unnecessary complexity and memory.

[0129] FIG. 8 illustrates an example scheme of code segmentation.

[0130] In the upper part of FIG. 8, m represents the original information that is to be transmitted, and m may be a vector, crc represents CRC bits, and crc may also be a vector. The upper part of FIG. 8 shows a scheme of a single CRC where the bits labeled as m (i.e., vector m) are followed by a CRC block including the CRC bits, labeled as crc. In this scenario, the entire vector m may be fully received and processed before the CRC verification can be performed. This leads to higher latency as it requires waiting for the complete information to be transmitted.

[0131] The bottom part of FIG. 8 shows a scheme of segmented CRCs where the bits m are divided into several segments (i.e., vector m is divided into subvectors), labeled as mi, m2,..., mm. Each subvector r is accompanied by its own CRC. The corresponding CRC blocks are labeled as crci, crci,..., crcm. This method allows for immediate CRC verification upon receiving each segment, thereby reducing the overall decoding delay.

[0132] In this example, crc in the upper part is the same as crcmin the bottom part, while other CRCs (i.e., crci, crci, crcm-i) are not connected to crc in the upper part, and the number of other CRCs is chosen arbitrarily.

[0133] Some solutions have been proposed for determining positions and / or length of CRC bits (i.e., CRC parity) in segmented CRC encoding.

[0134] In solution 1, positions and / or length of CRC bits are determined based on previous information bits and previous CRC bits. FIG. 9 illustrates an example segmented CRC encoding in solution 1. As shown in FIG.9, the original information m that is to be transmitted is dividedinto j information blocks mi, m2,..., mj. Each information block includes some information bits in the original information m. The length of each information block is represented by ki, ki,..., kj, and the sum of lengths of all information blocks equals the length of the original information K, i.e., kj = K.

[0135] CRC parity is generated based on previous information block and / or previous CRC parity. For example, CRC parity n is generated based on information bits mi. CRC parity n is generated based on information bits mi, CRC parity n, and information bits m2. CRC parity rj is generated based on information bits mi, CRC parity n, information bits m2, CRC parity n,..., and information bits mj. In this example, since CRC parity is generated based on previous information block and / or previous CRC parity, the length of CRC parity is determined based on previous information block and / or previous CRC parity. The length of each CRC parity is represented by pi, p2,. and the sum of lengths of all CRC parities equals the total CRC length P, i.e., ^pj = P.

[0136] The optimization task k* for determining lengths of information blocks is given by a formula of:where j presents a serial number of the information block, the above formula aims to find a set of ki, k2,..., kj under a condition.kj=K, i presents the i-th SC decoding, is a number of check and variable node operations at the i-th SC decoding step, is a temporary number of decoding paths of the i-th decoding step, Sj is a number of comparison operations at the i-th decoding step.

[0137] However, in solution 1, the optimization task for determining lengths of information blocks is based on many parameters. Therefore, determining lengths of information blocks and lengths of CRC parities are complex. Moreover, a false alarm rate (FAR) preservation is not guaranteed.

[0138] In solution 2, CRC detectors that perform CRC verification are not only employed at the end of the decoding process, but also at other breaking points during the decoding. In solution 2, CRC bits are designed at fixed positions.

[0139] FIG. 10 illustrates encoding and decoding process in solution 2. In FIG. 10, “De-CRC” represents the breaking point. As shown in FIG. 10, CRC encoding is applied to k information bits, generating m CRC bits, resulting in a total of K bits, where K = k + m, with m being the number of CRC bits. These K bits are fed into the polar encoder to produce an encoded sequence W of length N. The encoded sequence W is passed to the SCA-SCL decoder that performs the SCA- SCL decoding.

[0140] The SCA-SCL decoder first performs a “half SCL” decoding, which is an improved version of the SCL decoding method that maintains multiple candidate paths during decoding.

[0141] After the half SCL decoding, CRC verification (De-CRC) is conducted to check if the decoding results pass the CRC verification. If at least one candidate path passes the CRC verification, that path is considered the correct decoding result, and the decoding process ends. If none of the candidate paths pass the CRC verification, the decoder marks it as a failure and may request retransmission or take other error handling measures. If decoding is successful, the decoded bits are output. If decoding fails, a failure signal is output.

[0142] This flowchart demonstrates how the SCA-SCL decoder uses CRC verification to improve decoding reliability and accuracy. By performing CRC verification during decoding, errors can be effectively detected and corrected, thereby enhancing the performance of the communication system.

[0143] However, solution 2 is only applicable to polar code with moderate length and is not applicable to long polar codes. Moreover, the FAR preservation is not guaranteed.

[0144] 5. Partitioned SCL (PSCL) Decoding

[0145] The PSCL decoding is an advanced decoding designed for polar codes, aiming to reduce the complexity and latency associated with the SCL decoding. The PSCL decoding includes the following steps.

[0146] -Tree Partitioning: The decoding tree is divided into multiple segments or partitions. Each partition represents a subset of the decoding process, allowing for parallel processing and reduced complexity.

[0147] -Metric Definition: Two metrics are defined at each level of the decoding tree. One metric assesses the reliability of each decoding path. Another metric estimates the probability that the correct path is included in the list of candidate paths.

[0148] -Dual Threshold Strategy: A dual threshold strategy is employed where: the first threshold prunes unreliable paths; and the second threshold selects the most reliable paths from the remaining candidates to continue the decoding process.

[0149] -Path Pruning: At each decoding step, ineffective paths and some unreliable paths are pruned to narrow down the list of candidate paths.

[0150] -Path Selection: After pruning, a small but reliable subset of paths is selected for further decoding.

[0151] -CRC Verification: CRC is used at each stage to verify the correctness of the paths.

[0152] -Output: If at least one candidate path passes the CRC verification, it is considered the correct decoding output, concluding the decoding process.

[0153] PSCL decoding is applicable to moderate length polar codes (polar codes with code length N = 1024 and code rate R=0.5), but not applicable to long length polar codes such as polar codes with length greater than or equal to 4096.

[0154] In various aspects and / or implementations of the present disclosure, solutions are disclosed to solve at least one of the above problems. In some implementations of the present disclosure, solutions are disclosed for determining an upper bound of quantity of CRC bits, to guarantee FAR preservation.

[0155] Reference is now made to FIG. 11, which illustrates an example flowchart of an encoding method in accordance with some implementations. The method 1100 may be performed by an encoding device or a module, a circuit or a chip in the encoding device, or a logical module or software that can implement all or some functions of the encoding device. The encoding device may be the transmitting end described in FIG. 6. For example, the method 1100 is performed by the encoding device and includes the following steps.

[0156] Step 1101, the encoding device obtains a code length and a bit sequence including a plurality of information bits.

[0157] The bit sequence is original information that is to be transmitted. The bit sequence is to be encoded into a codeword before transmission. The plurality of information bits included in the bit sequence may be generated by the encoding device, or may be generated by another device and provided to the encoding device. The plurality of information bits may also be referred to as original information bits.

[0158] The code length may be a length of the codeword, which also refers to a total number of bits in a transmission block when the codeword is transmitted. The code length may be a power of two. Further, the code length is preset or set by a user.

[0159] Step 1102, the encoding device obtains CRC bits based on the plurality of information bits and an upper bound of quantity of CRC bits.

[0160] The encoding device may attach the CRC bits to the plurality of information bits when encoding the plurality of information bits. The CRC bits may be used to verify correctness of the plurality of information bits during the decoding process. The encoding device may use CRC code to generate the CRC bits, and the CRC code may be a random systematic linear block code. When the quantity of CRC bits is smaller, the CRC verification effect is poor. When the quantity of CRC bits is larger, the decoding process may slow down, and the false alarm rate (FAR) or the block error rate (BLER) may increase. Therefore, a suitable quantity of CRC bits is needed. The quantity of CRC bits is associated with the plurality of information bits, and also associated with the upper bound of the quantity of CRC bits.

[0161] The upper bound of quantity of CRC bits refers to a maximum total number of CRC bits. The upper bound of quantity of CRC bits is determined based on the code length, a basic code rate, an error rate, and a noise condition. In an example, the encoding device determines the upper bound of quantity of CRC bits based on the code length, the basic code rate, the error rate, and the noise condition.

[0162] The basic code rate refers to the ratio of the number of original information bits to the total number of bits after encoding. For example, the basic code rate refers to the ratio of the number of original information bits to the code length. That is, when the code length and the bit sequence are obtained, the basic code rate is determined.

[0163] The error rate refers to a target error rate of a decoding result of the bit sequence. In an example, the target error rate is a target block error rate (BLER) which is defined as the ratio of the number of incorrectly decoded blocks to the total number of transmission blocks. In another example, the target error rate is a target false alarm rate (FAR) which is defined as the ratio of number of false alarms to total alarms. The false alarms event refers to the situation where the decoding device incorrectly identifies an incorrect decoding as a correct decoding. For example, false alarm occurs when the decoding result does pass the CRC verification, but this is a CRC collision error. Total alarms refer to total alarms generated by the decoding device, including both correct and false alarms. The FAR measures the probability that the decoding device incorrectly marks an error-free data block as erroneous. In yet another example, the target error rate is a target frame error rate (FER).

[0164] In an example, the error rate is predefined. In another example, since the error rate varies with the channel noise condition, the encoding device may simulate different channel noise conditions to obtain different error rates and determine the error rate for the current channel noise condition from the different error rates.

[0165] The noise condition refers to the channel noise condition between the encoding device and the decoding device. In an example, the noise condition includes a noise variance. In another example, the noise condition includes a signal-to-noise ratio (SNR). The noise variance or the SNR may be obtained by the channel measurement.

[0166] It is noted that “the quantity of...bits” and “the number of...bits” may be exchangeable.

[0167] Step 1103, the encoding device obtains an encoded bit sequence by performing polar encoding, on the plurality of information bits and the CRC bits.

[0168] By performing polar encoding, the information bits and the CRC bits may be mapped to a vector having a length of the code length. For example, a sequence including the information bitsand the CRC bits is multiplied by a polar-coding generator matrix such that a polar-coded bit sequence is obtained by the encoding device, which is the encoded bit sequence.

[0169] Step 1104, the encoding device outputs the encoded bit sequence. The encoding device may further modulate the encoded bit sequence and transmit the modulated encoded bit sequence.

[0170] For example, the bit sequence includes (k - r) original information bits. The encoding device obtains r-bit CRC (i.e., r CRC bits) by encoding the (k - r) original information bits using the CRC code. The encoding device appends the r-bit CRC to the k - r) original information bits, forming k total bits which are also referred to as resulting CRC encoded bits. The encoding device obtains the encoded bit sequence by performing polar encoding on k total bits. Subsequently, the encoded bit sequence is modulated and transmitted.

[0171] Since adding inappropriate quantity of CRC bits may degrade the decoding performance such as increase the error rate, in these embodiments, the quantity of CRC bits is limited, and the upper bound of quantity of CRC bits is determined based on factors including the error rate which is a target error rate. As such, the error rate of decoding result may be guaranteed when CRC encoding is performed.

[0172] In some embodiments, the code length is greater than or equal to a threshold. For example, the threshold is 4096. In this case, the solution may be applied to long polar codes.

[0173] In some embodiments, the encoding device determines the upper bound of quantity of CRC bits based on the code length, the basic code rate, the error rate, and the noise condition by actions of: obtaining a first code rate based on the error rate and the noise condition, where the error rate is satisfied in a case where the first code rate is used to perform polar encoding under the noise condition; obtaining a difference between the basic code rate and the first code rate; and determining the upper bound based on the difference and the code length. The error rate is satisfied, which means that an actual error rate will not be greater than a target error rate.

[0174] A code rate of the polar encoding may increase from the basic code rate to the first code rate beyond which the actual error rate may exceed the target error rate. In other words, when the first code rate is applied for polar encoding, the actual error rate is not greater than the target error rate, while when a code rate greater than the first code rate is applied for polar encoding, the actual error rate will be greater than the target error rate.

[0175] The target error rate may be predefined or may be calculated based on factors such as the code length, the basic code rate, and a basic noise variance. The target error rate may be calculated by the encoding device or calculated by other device and provided to the encoding device. In an example, the target error rate is calculated using successive cancellation (SC) bound which is a method for estimating the BLER performance of polar decoding. The target error rate may becalculated when CRC encoding is not performed (i.e., there are not any CRC bits appending to the bits). For example, for a given code length N, a given basic code rate R1and a given basic noise variance the encoding device calculates the target error rate BLER1using the SC bound by a formula of:BLER1= SC(N, R1,σ1).

[0176] For the same code length N and a given basic noise variance a2, the code rate of the polar encoding increases from the basic code rate R step by step. The step may be predefined. For example, the step equals 0.01. After the code rate increases at each step, the encoding device calculates BLER correspondingly using SC bound, where BLERn= SC(N, Rn, σ2), where Rnrepresents the increased code rate.

[0177] The encoding device further determines whether BLERnis equal to or less than BLER1. When BLERnis less than BLER, the encoding device continues increasing the code rate of the polar encoding step by step, until BLERnis greater than BLER1. When BLERnis greater than BLER1, Rnis used as the first code rate R2, that is, the first code rate R2is obtained. In this example, BLER will be not greater than BLER when the code rate is not greater than R2, while BLER will be greater than BLER1when the code rate is greater than R2. In the case of R2, BLER becomes BLER2, and BLER2= SC(N, R2, σ2).

[0178] The encoding device then calculates the difference r between the basic code rate R and the first code rate R2as r = R2— R. The encoding device calculates the upper bound T of total number of CRC bits as T = Nxr.

[0179] It is noted that σ2may or may not be the same as σ1. In an example,σ2represents the current noise variance.

[0180] FIG. 12 illustrates simulation results of BLER of polar decoding under a fixed noise variance or a fixed SNR. The upper curve represents results for SC decoding and the lower curve represents results for SCL decoding with list size 2. The number of original information bits is 125. The x-axis represents the number of information bits and the y-axis represents BLER. As shown in FIG. 12, BLER increases as the number of information bits increases, but there is a region with an acceptable BLER degradation. For example, the target BLER is 0.01, for SC decoding, BLER degrades as the number of information bits increases from 125, and BLER degradation is acceptable when the number of information bits is not greater than 135. In this example, the upper bound of the number of CRC bits is 10, where 135-125=10.

[0181] FIG. 13 illustrates simulation results of BLER of polar decoding under different SNRs. The x-axis represents the code rate and the y-axis represents BLER. The basic code rate is 0.5. As SNR increases, the code rate can be improved while BLER is not greater than the target BLER. Inan example, the target BLER = 10-5, as SNR increases from 0.75dB to l. OdB, the code rate can be improved to 0.52. In this example, 0.52 is the upper bound of the code rate. The difference between the basic code rate 0.5 and the first code rate 0.52 is calculated as 0.52-5 = 0.02. The upper bound of the CRC bits can be calculated as a product of the difference (i.e. 0.02) and the code length.

[0182] In some embodiments, the upper bound is determined based on the code length, the basic code rate, the error rate, and the noise condition by actions of: obtaining a ratio by searching for a table based on the code length, the basic code rate, the error rate, and the noise condition; and determining the upper bound based on the ratio and the code length.

[0183] In some implementations, the ratio means the proportion of CRC bits, which equals the difference between the basic code rate and the first code rate. In these implementations, the proportion of CRC bits may be precalculated by the solution described above, and the table may be obtained based on the precalculated proportions of CRC bits.

[0184] First, a corresponding table may be obtained based on the code length, the error rate, and the noise condition. That is, some tables may be precalculated based on different code lengths, error rates, and noise conditions. When the code length, the error rate, and the noise condition are determined, the corresponding table may be obtained. The corresponding table includes relationships between basic code rates and proportions of CRC bits. Second, the proportion of CRC bits, i.e., the ratio, may be found in the corresponding table based on the basic code rate.

[0185] Table 1 illustrates proportions of CRC bits for codes with code length greater than or equal to 4096 at BLER = 0.01 under different basic code rates. ASNR repress the difference between a basic SNR and a current SNR. The basic SNR is the SNR at which the target BLER is satisfied and there are no CRC bits in the encoded codeword. During simulation, the SNR is increased from the basic SNR to the current SNR, and the increment is S NR. The basic CNR may also be referred to as a reference SNR.

[0186] It is noted that the encoding device may apply the proportion of CRC bits that is around the value shown in Table 1. For example, as shown in Table 1, for code rate = 0.25, the proportion of CRC bits is 0.225 x SNR. The encoding device may apply the proportion of CRC bits that is around 0.225 according to actual need.Table 1

[0187] FIG. 14 illustrates functions for proportions of CRC bits when different basic code ratesare applied. In the example shown in FIG. 14, the code length is N = 8192, and R means the basic code rate. The x-axis is SNR, and the y-axis is the proportion of CRC bits.

[0188] In some embodiments, the bit sequence is further divided into a plurality of segments, and quantity of CRC bits for each of the plurality of segments is determined based on a proportion of CRC bits between each of the plurality of segments.

[0189] The number of the plurality of segments may be equal to a power of two. For example, the plurality of segments may include 2lsegments, and l is a positive integer. During simulation, the encoder may increase the number of the plurality of segments gradually until the number of the CRC bits in the last segments does not satisfy the lower bound of the number of the CRC bits.

[0190] The proportion of CRC bits in each of the plurality of segments may be determined based on a proportion of information bits between each of the plurality of segments. The proportion of CRC bits in each of the plurality of segments is directly proportional to the proportion of information bits between each of the plurality of segments. In an example, the proportion of CRC bits in each of the plurality of segments is the same as the proportion of information bits between each of the plurality of segments. The proportion of information bits between each of the plurality of segments is obtained based on a structure of a polar code, the code length, the basic code rate, and quantity of the plurality of segments. The polar code is used to perform the polar encoding. The structure of a polar code may also be referred to as the construction of the polar code.

[0191] In some embodiments, a lower bound of the quantity of CRC bits in the last segment may satisfy a condition. A lower bound of the quantity of CRC bits in the last segment may be obtained based on the error rate and a list size of a decoder for decoding using the polar code. For example, the error rate is the target FAR, and the relationship between the target FAR and the list size of the decoder satisfies a formula of:_ List sizer / iKtarget2CRCend ’where FARtargetis the target FAR, List size is the list size of the decoder, and CRCendis the number of CRC bits in the last segment. Therefore, the encoding device calculates the number of CRC bits in the last segment by a formula of:

[0192] The following describes how to determine the quantity of CRC bits for each of the plurality of segments.

[0193] For example, the encoding device divides the original information bits into 2lsegments. Once the encoding device obtains the total quantity of CRC bits which is represented as CRCTotabthe encoding device determines the quantity of CRC bits in each segment.

[0194] The quantity of information bits in segment i is Kt, where i is the index of an i-th segment, and i E {1,2,..., 21}. The quantity of CRC bits in the i-th segment is calculated by a formula of:where CRC is the quantity of CRC bits in the i-th segments, K is the total quantity of the original information bits. Since CRC obtained by the above formula may not be an integer, CRC may be rounded up, rounded down, rounded off, or truncated to CRC which is an integer.

[0195] It is noted that for different values of i, CRC may or may not rounded to CRC'i using the same manner. For example, for some values of i, CRCtmay be rounded up to CRC't, while for other values of i, CRCi may be rounded down to CRC'i. Moreover, some segments may not include CRC bits since CRC'i may equal 0 due to the rounding operation.

[0196] FIG. 15 illustrates an example where the original information bits are divided into four segments. In this example, the upper bound of total quantity of CRC bits CRCTotai= CRC + CRC2+ CRC3+ CRC4= 43, and the proportion of information bits between each of the plurality of segments is K2‘. K3:4which equal 1:3:4: 11. In this case, the proportion of CRC bits in each of the plurality of segments is calculated as CRC^. CRC^. CRC3CRC4= K^. K^. K^.4=l:3:4: 11.

[0197] In this example, the list size of the decoder is 8, the target FAR is 5e-7, and the encoding device calculates the lower bound of the quantity of CRC bits in the last segment by a formula of:

[0198] where CRCend criticaiis the lower bound of the quantity of CRC bits in the last segment.

[0199] The encoding device then calculates the quantity of CRC bits in each segment by a formula of:CRC, = *CRCTMIwhere:;

[0200] CRC is rounded up to CRC = 3, CRC2is rounded up to CRC'2= 7, and CRC3is rounded down to CRC'3= 9, and CRC4is rounded down to CRC'424.

[0201] FIG. 16 illustrates another example where the original information bits are divided into four segments. In this example, the code length of the polar code is 2V=4096, the quantity of theoriginal information bits is X=2048. In this case, the basic code rate is 0.5, list size of the decoder is List size = 1, and the target FAR is FAR = — The lower bound of CRC bits in the last segment is 11 bits. The target BLER is 1 O’2. The reference SNR is 1.63 dB, and the reference SNR refers to the SNR at which BLER=10-2is achieved. In an example, according to Table 1, when the target BLER is 1 O’2and the basic code rate is 0.5, the proportion of CRC bits is 0.162. The encoding device takes (0.162* ASNR) as the proportion of CRC bits. In an example, ASNR = 0.067 and the upper bound of total quantity of the CRC bits is calculated as 4096* (0.162*0.067)= 44.45. The encoding device then calculates the quantity of CRC bits in each segment according to the number of information bits in each segment by a formula of CRC[ =CRCTotai.

[0202] In another example, the encoding device computes reference SNR at which BLER= 0.01 is achieved, and SNR = 1.63 dB. CRCTotaiis computed using Table 5 (which is described later) or equation y = (0.162* ASNR (i.e. CRCTotai= (0.162) x ASNRxN) from Table 1. As a start, ASNR=0.067 is fixed. The resultant number of bits is CRCTotai= 45.

[0203] The CRC bits are than distributed to each segment, according to the information bits in Ieach segment as y X CRCTotai.

[0204] Table 2 illustrates the number of information bits and the number of CRC bits in each segment in the case of different number of segments. As seen from Table 2, the number of CRC bits in the last segments decreases as the number of segments increases.Table 2

[0205] As seen from the third column of Tabl2 A, the total quantity of CRC bits in segmentscomputed based on the x CRCadditionaiand rounding may be lower than CRCTotai. In this case, one or more bits may be appended to the CRC bits in the last segment. CRC distribution with appended bits is shown in the fourth column.

[0206] It is noted that if the quantity of CRC bits does not reach the lower bound of the number of CRC bits in the last segment, ASNR may be increased such that the target BLER may be satisfied.

[0207] In some embodiments, the encoding device may determine a noise variance such that the target BLER can be satisfied. Table 3 illustrates the ratio of σ2andin case of different BLERs and different basic code rates R, where a2is the noise variance that is determined by the encoding device, and ^0-2 represents the noise variance at which the code reaches BLER = 10’2. Table 3 may be applicable to the polar coder with code length greater or equal to 4096. As seen from Table 3, Given fixed R, the smaller BLER, the smaller σ2.Table 3

[0208] In some embodiments, the quantity of CRC bits increases with the increase of SNR. In this case, given a basic SNR at which the target BLER is achieved and the are no CRC bits in the codes, as the SNR increases from the basic SNR, the encoding device may add more CRC bits to the codes. For example, the SNR increases from the SNRi to SNR2, where SNRi is the basic SNR, SNR2 is the current SNR, and increment of SNR is represented as ASNR= SNR2 - SNRi.

[0209] Table 4 illustrates examples of the quantity of CRC bits for codes with different code lengths (i.e. code length N = 4096 or 8192) with the basic code rate R= 1 / 2 and different A SNR. CRCTotairepresents the upper bound of the quantity of CRC bits. It is noted that ASNR may betransformed or recalculated into Δσ2. In an example, Δσ2= Es / (2×R×10ΔSNR / 10), where R is the basic 2XRX10-io-code rate, and Esis symbol energy. The initial SNR is computed for target BLER = 10’2.Table 4

[0210] It can be seen from Table 4 that the upper bound of the quantity of CRC bits increases with the increase of A SNR. In some embodiments, the target BLER may influence the number of resultant CRC bits. Table 5 illustrates examples of the upper bound of the quantity of CRC bits for codes with a fixed code length N = 4096 and different quantity of the original information bits (i.e. K - 3072, 2048, or 1024) at different target BLERs.Table 5

[0211] It can be seen from Table 5 that the quantity of CRC bits almost does not change with the decrease in BLER for codes of rate 3 / 4 and 1 / 2. For lower code rate the quantity of CRC bits decreases with the reduction of BLER. It is noted that ΔSNR may be recalculated into Δσ2.

[0212] The above describes operations at the encoding device side and the following describes operations at the decoding device side.

[0213] Reference is now made to FIG. 17, which illustrates an example flowchart of a decoding method in accordance with some implementations. The method 1700 may be performed by a decoding device or a module, a circuit or a chip in the decoding device, or a logical module or software that can implement all or some functions of the decoding device. The decoding device may be the receiving end described in FIG. 6. For example, the method 1700 is performed by the decoding device and includes the following steps.

[0214] Step 1701, the decoding device obtains a bit sequence including a plurality of encoded information bits and encoded CRC bits, where the encoded CRC bits are obtained based on anupper bound of quantity of CRC bits and the upper bound of quantity of CRC bits is determined based on a code length, a basic code rate, an error rate, and a noise condition, and the code length is a length of the to-be-decoded bit sequence.

[0215] The bit sequence may be the encoded bit sequence that is generated at step 1103 by the encoding device. The error rate includes one or more of: a target block error rate or a target false alarm rate. It is noted that the details of the code length, the basic code rate, the error rate, the noise condition, the quantity of CRC bits, and the upper bound of the quantity of the CRC bits may refer to the related description at the encoding device side.

[0216] Step 1702, the decoding device obtains a decoded bit sequence including a plurality of decoded information bits and decoded CRC bits by performing polar decoding on the bit sequence.

[0217] Step 1703, the decoding device performs CRC verification on the plurality of decoded information bits based on the decoded CRC bits.

[0218] Step 1704, the decoding device obtains a result based on the CRC verification.

[0219] The result may be whether the decoded information bits pass the CRC verification.

[0220] In some implementations, in step 1704, the decoding device may determine whether the plurality of decoded information bits pass CRC verification. If the decoding device determines that the plurality of decoded information bits pass CRC verification based on the decoded CRC bits, the decoding device may obtain a decoding result including the decoded bit sequence, and the decoded bit sequence includes the plurality of decoded information bits.

[0221] In an example, polar decoding is CA-SCL decoding. During the CA-SCL decoding process, the SCL decoding is performed first, followed by the CRC. In the final stage of the SCL decoding, paths that pass the CRC are selected from the candidate paths to be the final output. If there are multiple paths among the candidates that pass the CRC verification, the path with the lowest metric is chosen as the final decoding path. The metric may be a path metric which is computed in loglikelihood or probability domain.

[0222] In some embodiments, the decoded bit sequence includes a plurality of decoded segments, each decoded segment includes one or more decoded information bits and one or more decoded CRC bits, and the deciding device performs CRC verification on the plurality of decoded information bits based on the decoded CRC bits includes that the decoding device performs CRC verification on one or more decoded information bits in each of the plurality of decoded segments based on respective one or more decoded CRC bits. The higher number of information segments may lead to smaller delay and complexity, due to the ability to perform early termination as soon as the information segment CRC is checked.

[0223] In some embodiments, the plurality of segments includes 2lsegments, and Z is a positiveinteger.

[0224] For example, in a case where the original information bits are divided into 2 segments, the decoding device may perform the CRC check as soon as N / 2 bits are reached. In a case where the original information bits are divided into 4 segments, the decoding device may perform the CRC check as soon as N / 4 bits are reached. In a case where the original information bits are divided into S segments, the decoding device may perform the CRC check as soon as N / S bits are reached.

[0225] It is noted that some segments may not include CRC bits. For example, the first one of the segments does not include CRC bits if the number of information bits in the first one of the segments is negligible. In this case, the decoding device may not perform CRC on the decoded information bits in the first one of the decoded segments since there are no CRC bits in this segment.

[0226] In some embodiments, the code length is greater than or equal to a threshold. For example, the threshold is 4096.

[0227] The above describes the encoding and decoding methods according to one or more implementations of the present disclosure. The following describes the apparatuses according to one or more implementations of the present disclosure.

[0228] Referring back to FIG. 5, in a first implementation manner, the apparatus 510 may be applied to the encoding device described above and realize the above method implementations performed by the encoding device.

[0229] In some implementations, the processing unit 512 may be configured to obtain a code length and a bit sequence including a plurality of information bits; obtain cyclic redundancy check (CRC) bits based on the plurality of information bits and an upper bound of quantity of CRC bits, where the upper bound is determined based on the code length, a basic code rate, an error rate, and a noise condition; obtain an encoded bit sequence by performing polar encoding, on the plurality of information bits and the CRC bits; and the communication unit may be configured to output the encoded bit sequence.

[0230] In some implementations, the upper bound is determined based on the code length, the basic code rate, the error rate, and the noise condition by actions of: obtaining a first code rate based on the error rate and the noise condition, where the error rate is satisfied in a case where the first code rate is used to perform polar encoding under the noise condition; obtaining a difference between the basic code rate and the first code rate; and determining the upper bound based on the difference and the code length.

[0231] In some implementations, the upper bound is determined based on the code length, the basic code rate, the error rate, and the noise condition by actions of: obtaining a ratio by searchingfor a table based on the code length, the basic code rate, the error rate, and the noise condition; and determining the upper bound based on the ratio and the code length.

[0232] In some implementations, the bit sequence is further divided into a plurality of segments, and quantity of CRC bits for each of the plurality of segments is determined based on a proportion of CRC bits in each of the plurality of segments.

[0233] In some implementations, the proportion of CRC bits in each of the plurality of segments is determined based on a proportion of information bits between each of the plurality of segments.

[0234] In some implementations, the proportion of information bits between each of the plurality of segments is obtained based on a structure of a polar code, the code length, the basic code rate, and quantity of the plurality of segments, where the polar code is used to perform the polar encoding.

[0235] In some implementations, a lower bound of the quantity of CRC bits in the last segment is obtained based on the error rate and a list size of a decoder for decoding using the polar code.

[0236] In some implementations, the plurality of segments includes 2lsegments, and l is a positive integer.

[0237] In some implementations, the code length is greater than or equal to a threshold.

[0238] In some implementations, the threshold is 4096.

[0239] In some implementations, the error rate includes one or more of: a target block error rate or a target false alarm rate.

[0240] Referring back to FIG. 5 again, in a second implementation manner, the apparatus 510 may be applied to the decoding device described above and realize the above method implementations performed by the decoding device.

[0241] In some implementations, the processing unit may be configured to obtain a bit sequence including a plurality of encoded information bits and encoded CRC bits, where the encoded CRC bits are obtained based on an upper bound of quantity of CRC bits and the upper bound of quantity of CRC bits is determined based on a code length, a basic code rate, an error rate, and a noise condition, and the code length is a length of the to-be-decoded bit sequence; obtain a decoded bit sequence including a plurality of decoded information bits and decoded CRC bits by performing polar decoding on the bit sequence; perform CRC verification on the plurality of decoded information bits based on the decoded CRC bits; and obtain a result based on the CRC verification.

[0242] In some implementations, the obtaining a result based on the CRC verification, includes: determining that the plurality of decoded information bits pass CRC verification based on the decoded CRC bits; and obtaining a decoding result including the decoded bit sequence, where the decoded bit sequence includes the plurality of decoded information bits.

[0243] In some implementations, the decoded bit sequence includes a plurality of decoded segments, each decoded segment includes one or more decoded information bits and one or more decoded CRC bits, and performing CRC verification on the plurality of decoded information bits based on the decoded CRC bits, includes: performing CRC verification on one or more decoded information bits in each of the plurality of decoded segments based on respective one or more decoded CRC bits.

[0244] In some implementations, the plurality of segments includes 2lsegments, and l is a positive integer.

[0245] In some implementations, the code length is greater than or equal to a threshold.

[0246] In some implementations, the threshold is 4096.

[0247] In some implementations, the error rate includes one or more of: a target block error rate or a target false alarm rate.

[0248] Referring back to FIG. 4, in a third implementation manner, the apparatus 410 may be applied to a encoding device and realize the above method implementations performed by the encoding device. The processor 411 executes computer executable instructions stored in the memory 413 for executing the above methods implemented by the encoding device.

[0249] Referring back to FIG. 4 again, in a fourth implementation manner, the apparatus 410 may be applied to a decoding device and realize the above method implementations performed by the decoding device. The processor 411 executes computer executable instructions stored in the memory 413 for executing the above methods implemented by the decoding device.

[0250] The present disclosure encompasses various embodiments, including not only method embodiments, but also other embodiments such as apparatus embodiments and embodiments related to non-transitory computer readable storage media. Embodiments may incorporate, individually or in combinations, the features disclosed herein.

[0251] Although this disclosure refers to illustrative embodiments, this is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the disclosure, will be apparent to persons skilled in the art upon reference to the description.

[0252] Features disclosed herein in the context of any particular embodiments may also or instead be implemented in other embodiments. Method embodiments, for example, may also or instead be implemented in apparatus, system, and / or computer program product embodiments. In addition, although embodiments are described primarily in the context of methods and apparatus, other implementations are also contemplated, as instructions stored on one or more non-transitorycomputer-readable media, for example. Such media may store programming or instructions to perform any of various methods consistent with the present disclosure.

[0253] Some embodiments of the present disclosure provide a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium). The computer-readable storage medium has stored thereon program instructions that, when run on a first device / second device, cause the first device / second device to execute one or more steps of the method for beam management as described in any one of the above embodiments.

[0254] For example, the computer-readable storage medium includes, but is not limited to, a magnetic storage device (e.g., a hard disk, a floppy disk or a magnetic tape), an optical disk (e.g., a compact disk (CD), or a DVD), a smart card, and a flash memory device (e.g., an erasable programmable read-only memory (EPROM), a card, a stick or a key driver). Various computer-readable storage media described in the embodiments of the present disclosure may represent one or more devices and / or other machine-readable storage media, which are used for storing information. The term “computer-readable storage medium” may include, but is not limited to, wireless channels and various other media capable of storing, containing and / or carrying instructions and / or data.

[0255] Some embodiments of the present disclosure further provide a computer program product. The computer program product includes program instructions carried on a non-transitory computer-readable storage medium. When executed on a first device / second device, the computer program instructions cause the first device / second device to perform one or more steps of the method for data transmission as described in the above embodiments.

[0256] Beneficial effects of the computer-readable storage medium and the computer program product are the same as the beneficial effects of the method for data transmission as described in some of the above embodiments, and details will not be repeated here.

[0257] The foregoing descriptions are merely specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or replacements within the technical scope of the present disclosure shall be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

[0258] In some aspects of the present disclosure, there is provided a computer program comprising instructions. The instructions, when executed by a processor, may cause the processor to implement a method of the present disclosure.

[0259] In some aspects of the present disclosure, there is provided an integrated circuit. The integrated circuit includes one or more logic circuits for executing the steps of the method for data transmission of the present disclosure.

[0260] In some aspects of the present disclosure, there is provided an apparatus comprising means (e.g., at least one processor) to implement a method of the present disclosure. The apparatus may be device (that is, a first device or a second device) or a module or component in the device. The at least one processor may execute instructions stored in a computer-readable medium to implement the method.

[0261] The apparatus may be a communication device or an apparatus implemented in a communication device. For example, the apparatus implemented in a communication device may be an integrated circuit, which in some contexts may be known by other colloquial names, such as chip, modem, modem chip, baseband chip, or baseband processor. In some implementations, one or more integrated circuits can be packaged into a system-on-chip, a system-in-package, or a multichip module. The apparatus may comprise one or more integrated circuits or comprise one or more integrated circuits and other discrete components.

[0262] It will be appreciated that any module, component, or device disclosed herein that executes instructions may include, or otherwise have access to, a non-transitory computer / processor readable storage medium or media for storage of information, such as computer / processor readable instructions, data structures, program modules and / or other data. A non-exhaustive list of examples of non-transitory computer / processor readable storage media includes magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, optical disks such as compact disc read-only memory (CD-ROM), digital video discs or digital versatile discs (i.e., DVDs), Blu-ray Disc™, or other optical storage, volatile and non-volatile, removable and nonremovable media implemented in any method or technology, random-access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology. Any such non-transitory computer / processor storage media may be part of a device / apparatus or accessible or connectable thereto. Computer / processor readable / executable instructions to implement a method, an application or a module described herein may be stored or otherwise held by such non-transitory computer / processor readable storage media.

[0263] It may be noted that the message in the disclosure may be replaced with information, which may be carried in one single message, or be carried in more than one separate message.

[0264] The terms “apparatus” and “device” are used exchangeable.

[0265] The terms “first”, “second”, and “third” are used for descriptive purposes only, and are not to be construed as indicating or implying the relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined with “first”, “second” or “third” may explicitly or implicitly include one or more of the features.

[0266] In the present disclosure, the terms “a” or “an” are defined to mean “at least one”, that is, these terms do not exclude a plural number of items, unless stated otherwise.

[0267] In the present disclosure, terms such as “substantially”, “generally” and “about”, which modify a value, condition or characteristic of a feature of an example embodiment, is understood to mean that the value, condition or characteristic is defined within tolerances that are acceptable for the proper operation of the example embodiment for its intended application.

[0268] In the present disclosure, unless stated otherwise, the terms “connected” and “coupled”, and derivatives and variants thereof, refer herein to any structural or functional connection or coupling, either direct or indirect, between two or more elements. For example, the connection or coupling between the elements can be acoustical, mechanical, optical, electrical, thermal, logical, or any combinations thereof.

[0269] In the present disclosure, expressions such as “match”, “matching” and “matched”, including variants and derivatives thereof, are intended to refer herein to a condition in which two or more elements are either the same or within some predetermined tolerance of each other. That is, these terms are meant to encompass not only “exactly” or “identically” matching the two elements but also “substantially”, “approximately” or “subjectively” matching the two or more elements, as well as providing a higher or best match among a plurality of matching possibilities.

[0270] In the present disclosure, the expression “based on” is intended to mean “based at least partly on”, that is, this expression can mean “based solely on” or “based partially on”, and so should not be interpreted in a limited manner. More particularly, the expression “based on” may also be understood as meaning “depending on”, “representative of’, “indicative of’, “associated with” or similar expressions.

[0271] In the present disclosure, the terms “system” and “network” may be used interchangeably in different embodiments of this application. “At least one” means one or more, and “a plurality of’ means two or more. The term “and / or” describes an association relationship of associated objects, and indicates that three relationships may exist. For example, A and / or B may indicate the following three cases: Only A exists, both A and B exist, and only B exists, where A and B may be singular or plural. The character “ / ” indicates an “or” relationship between associated objects. “At least one of the following items (pieces)” or a similar expression thereof indicates any combination of these items, including a single item (piece) or any combination of a plurality ofitems (pieces). For example, “at least one of A, B, or C” includes: only A; only B; only C; A and B; A and C; B and C; or A, B, and C, and “at least one of A, B, and C” may also be understood as including: only A; only B; only C; A and B; A and C; B and C; or A, B, and C. In addition, unless otherwise specified, ordinal numbers such as “first” and “second” in embodiments of this application are used to distinguish between a plurality of objects, and are not used to limit a sequence, a time sequence, priorities, or importance of the plurality of objects.

[0272] A person skilled in the art should understand that embodiments of this application may be provided as a method, an apparatus (or system), computer-readable storage medium, or a computer program product. Therefore, this application may use a form of a hardware-only embodiment, a software-only embodiment, or an embodiment with a combination of software and hardware. Moreover, this application may use a form of a computer program product that is implemented on one or more computer-usable storage media (including but not limited to a disk memory, an optical memory, and the like) that include computer-usable program code.

[0273] This application is described with reference to the flowcharts and / or block diagrams of the method, the device (system), and the computer program product according to this application. It is understood that computer program instructions may be used to implement each process and / or each block in the flowcharts and / or the block diagrams and a combination of a process and / or a block in the flowcharts and / or the block diagrams. The computer program instructions may be provided for a general-purpose computer, a dedicated computer, an embedded processor, or a processor of another programmable data processing device and enable a machine to execute the instructions. When executed by any computer or the processor of a programmable data processing device, the instructions cause the apparatus to implement specific functions as described in one or more procedures in the flowcharts and / or one or more blocks in the block diagrams. The computer program instructions may alternatively be stored in a computer-readable memory that can indicate a computer or another programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate an artifact that includes an instruction apparatus. The instruction apparatus implements a specific function in one or more procedures in the flowcharts and / or one or more blocks in the block diagrams.

[0274] The computer program instructions may alternatively be loaded onto a computer or another programmable data processing device, so that a series of operations and steps are performed on the computer or the another programmable device, so that computer-implemented processing is generated. Therefore, the instructions executed on the computer or on another programmable device provide steps for implementing specific functions as described in one or more procedures in the flowcharts and / or one or more blocks in the block diagrams.

[0275] It is clear that a person skilled in the art can make various modifications and variations to this application without departing from the scope of this disclosure. This disclosure is intended to cover these modifications and variations of this application provided that they fall within the scope of protection defined by the following claims and their equivalent technologies.

Claims

CLAIMS1. An encoding method, comprising:obtaining a code length and a bit sequence comprising a plurality of information bits; obtaining cyclic redundancy check (CRC) bits based on the plurality of information bits and an upper bound of quantity of CRC bits, wherein the upper bound is determined based on the code length, a basic code rate, an error rate, and a noise condition;obtaining an encoded bit sequence by performing polar encoding, on the plurality of information bits and the CRC bits; andoutputting the encoded bit sequence.

2. The method of claim 1, wherein the upper bound is determined based on the code length, the basic code rate, the error rate, and the noise condition by actions of:obtaining a first code rate based on the error rate and the noise condition, wherein the error rate is satisfied in a case where the first code rate is used to perform polar encoding under the noise condition;obtaining a difference between the basic code rate and the first code rate; and determining the upper bound based on the difference and the code length.

3. The method of claim 1, wherein the upper bound is determined based on the code length, the basic code rate, the error rate, and the noise condition by actions of:obtaining a ratio by searching for a table based on the code length, the basic code rate, the error rate, and the noise condition; anddetermining the upper bound based on the ratio and the code length.

4. The method of any one of claims 1 to 3, wherein the bit sequence is further divided into a plurality of segments, and quantity of CRC bits for each of the plurality of segments is determined based on a proportion of CRC bits in each of the plurality of segments.

5. The method of claim 4, wherein the proportion of CRC bits in each of the plurality of segments is determined based on a proportion of information bits between each of the plurality of segments.

6. The method of claim 5, wherein the proportion of information bits between each of the plurality of segments is obtained based on a structure of a polar code, the code length, the basic code rate, and quantity of the plurality of segments, wherein the polar code is used to perform the polar encoding.

7. The method of any one of claims 4 to 6, wherein a lower bound of the quantity of CRC bits in a last segment is obtained based on the error rate and a list size of a decoder for decoding using the polar code.

8. The method of any one of claims 4 to 7, wherein the plurality of segments comprises 2lsegments, and l is a positive integer.

9. The method of any one of claims 1 to 8, wherein the code length is greater than or equal to a threshold.

10. The method of claim 9, wherein the threshold is 4096.

11. The method of any one of claims 1 to 10, wherein the error rate comprises one or more of: a target block error rate or a target false alarm rate.

12. A decoding method, comprising:obtaining a bit sequence comprising a plurality of encoded information bits and encoded CRC bits, wherein the encoded CRC bits are obtained based on an upper bound of quantity of CRC bits and the upper bound of quantity of CRC bits is determined based on a code length, a basic code rate, an error rate, and a noise condition, and the code length is a length of the to-be-decoded bit sequence;obtaining a decoded bit sequence comprising a plurality of decoded information bits and decoded CRC bits by performing polar decoding on the bit sequence;performing CRC verification on the plurality of decoded information bits based on the decoded CRC bits; andobtaining a result based on the CRC verification.

13. The method of claim 12, wherein the obtaining a result based on the CRC verification, comprises:determining that the plurality of decoded information bits pass CRC verification based on the decoded CRC bits; andobtaining a decoding result comprising the decoded bit sequence, wherein the decoded bit sequence comprises the plurality of decoded information bits.

14. The method of claim 12 or 13, wherein the decoded bit sequence comprises a plurality of decoded segments, each decoded segment comprises one or more decoded information bits and one or more decoded CRC bits, and performing CRC verification on the plurality of decoded information bits based on the decoded CRC bits, comprises:performing CRC verification on one or more decoded information bits in each of the plurality of decoded segments based on respective one or more decoded CRC bits.

15. The method of claim 14, wherein the plurality of segments comprises 2lsegments, and l is a positive integer.

16. The method of any one of claims 12 to 15, wherein the code length is greater than or equal to a threshold.

17. The method of claim 16, wherein the threshold is 4096.

18. The method of any one of claims 12 to 17, wherein the error rate comprises one or more of: a target block error rate or a target false alarm rate.

19. A communication apparatus, comprising units for performing the method according to any one of claims 1 to 18.

20. A device comprising processing circuitry for performing the method according to any one of claims 1 to 18.

21. A chip, comprising an input / output (I / O) interface and at least one processor, wherein the at least one processor is configured to call and run a computer program stored in a memory, to enable a device installed with the chip to perform the method according to any one of claims 1 to 18.

22. A communication device, comprising:one or more processors; anda computer-readable storage medium coupled to the one or more processors and storing instructions for execution by the processors, wherein the instructions, when executed by the one or more processors, configure the communication device to perform the method according to any one of claims 1 to 18.

23. A communication system, comprising a first communication apparatus and a second communication apparatus, wherein the first communication apparatus is configured to perform the method of any one of claims 1 to 11, and the second communication apparatus is configured to perform the method of any one of claims 12 to 18.

24. A computer-readable medium carrying a program code which, when executed by a computer device, causes the computer device to perform the method according to any one of claims 1 to 18.

25. A computer program product comprising program code for performing the method according to any one of claims 1 to 18, when executed on a computer or a processor.

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