Delay predictor for ethernet frame timestamp

Abstract

Systems and methods for predicting delay through a device include a chip pin communicating an ethernet frame having an SOF bit, a parallel bus coupled between the chip pin and an internal reference point, a parallel bus clock enable signal, a memory containing table data corresponding to a pattern of the clock enable signal, and a delay prediction circuit for: (a) calculating, based on the data table, a parallel delay for the SOF bit communicating through the parallel bus; and (2) calculating a total delay for the SOF bit communicating between the chip pin and the internal reference point, the total delay based at least on the parallel delay. The systems and methods may include a timestamp circuit to update a frame timestamp in the ethernet frame based on the total delay for communication of the start of frame bit between the first chip pin and the internal reference point.

Description

[0001] PCT Application

[0002] 68354.234173 / 25056W001

[0003] 1

[0004] DELAY PREDICTOR FOR ETHERNET FRAME TIMESTAMP

[0005] PRIORITY

[0006] This application claims priority to commonly owned Indian Patent Application No.

[0007] 202511036131 filed April 14, 2025, the entire contents of which are hereby incorporated by reference for all purposes.

[0008] FIELD OF THE INVENTION

[0009] The present disclosure relates to systems and methods for predicting delay through a device with sub-nanosecond accuracy, and more specifically for predicting delay that is used in the precision time protocol (PTP) for ethernet communication.

[0010] BACKGROUND

[0011] The Precision Time Protocol (PTP) is a protocol used to synchronize clocks across a network with high precision. It is defined in the IEEE 1588 standard and is commonly used in applications where accurate time synchronization is critical, such as in telecommunications, industrial automation, power grids, and financial systems.

[0012] PTP works by exchanging timing messages between a master clock (the reference clock) and slave clocks (synchronized devices) on the network. The protocol allows the slave clocks to adjust their time based on the master clock, minimizing the time offset and maintaining precise synchronization.

[0013] PTP uses timestamps embedded in the PTP frame to synchronize the slave clock with the master clock and to calculate the network delay, allowing it to compensate for any network latency and achieve high precision. Typically, PTP can achieve clock synchronization with accuracy in the range of nanoseconds. With multiple nodes between master and slave, inaccuracies accumulated at each node over time can lead to the slave clock being out of sync with the master clock.

[0014] Existing PTP systems and methods may be unable to achieve sub-nanosecond accuracy, only attaining sub-microsecond accuracy.

[0015] Existing PTP systems and methods may not precisely account for delays across multiple internal buses within a device because they may rely on lump-sum or high-level calculations to predict the delay between the internal reference point and the chip pin, leading to potential prediction errors exceeding the sub-nanosecond range.PCT Application

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[0018] Existing PTP systems and methods may be difficult to adapt to different protocol code sublayers (PCS) or serializers / de-serializers (SERDES) due to their hardcoded logic design.

[0019] Existing PTP systems and methods may also be unable to accurately account for bus-by-bus delays within PCS or SERDES.

[0020] Existing PTP systems and methods may not precisely account for the impact of codeword marker (CWM) insertion and deletion on the delay through rate adapter FIFOs.

[0021] Existing PTP systems and methods may not precisely account for the exact start-of-frame (SOF) byte lane position on a parallel bus before the gearbox, which may affect the accurate prediction of the SOF first bit position on a serial bus after the gearbox outputs the frame to SERDES. (The gearbox may adapt the PCS bus width to the SERDES bus width, among other functions.)

[0022] Existing PTP systems and methods may not perform closed-loop compensation for accuracy loss caused by representing the actual clock cycle time or bit time as a digital value with a limited number of digits.

[0023] Accordingly, more accurate systems and methods are needed to predict delay through an ethernet device with sub-nanosecond accuracy. An accurate timestamp with subnanosecond accuracy may achieve precise synchronization, ensure system reliability and optimal performance, and have other advantages, as discussed herein.

[0024] SUMMARY

[0025] The examples herein enable systems and methods for predicting delay through a networking device with sub-nanosecond accuracy.

[0026] According to one aspect, a device is provided that may include a first chip pin to communicate an ethernet frame with a first network medium, the ethernet frame having a start of frame bit; a parallel bus communicatively coupled between the first chip pin and an internal reference point; a memory containing a parallel clock enable data table including data corresponding to a parallel bus clock enable pattern; a delay prediction circuit configured to: calculate, based on the parallel clock enable data table, a parallel delay for communication of the start of frame bit through the parallel bus; and calculate a total delay for communication of the start of frame bit between the first chip pin and the internal reference point, the total delay based at least on the parallel delay; and a timestamp circuit to update a frame timestamp in the ethernet frame based on the total delay for communication of the start of frame bit between the first chip pin and the internal reference point.PCT Application

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[0029] Aspects as in the previous paragraph provide a device wherein the total delay may be an egress delay for communication of the start of frame bit from the internal reference point to the first chip pin.

[0030] Aspects as in at least one of the two preceding paragraphs provide a device wherein the parallel delay may comprise a first number of clock cycles; and the delay prediction circuit may be configured to: calculate a compensated parallel delay by multiplying the first number of clock cycles by a first difference between an actual clock cycle time and a digital design clock cycle time; and calculate the total delay based on the parallel delay and the compensated parallel delay.

[0031] Aspects as in at least one of the three preceding paragraphs provide a device wherein the parallel bus clock enable pattern may comprise a periodic and non-consecutive clock enable pattern.

[0032] Aspects as in at least one of the four preceding paragraphs provide a device which may comprise a serial bus communicatively coupled between the first chip pin and the parallel bus; and wherein the delay prediction circuit may be configured to: calculate a serial delay comprising a first number of bit times for communication of the start of frame bit through the serial bus; and calculate the total delay for communication of the start of frame bit between the first chip pin and the internal reference point based at least on the parallel delay and the serial delay.

[0033] Aspects as in at least the preceding paragraph provide a device which may comprise a converter circuit to communicate the ethemet frame between the parallel bus and the serial bus, the converter circuit having a multi-bit data interface; and wherein the delay prediction circuit configured to calculate the serial delay comprises adjusting the first number of bit times when the start of frame bit is in an internal bit position within the converter circuit muti-bit data interface.

[0034] Aspects as in at least one of the two preceding paragraphs provide a device wherein the parallel delay may comprise a first number of clock cycles; and the delay prediction circuit may be configured to: calculate a compensated parallel delay by multiplying the first number of clock cycles by a first difference between an actual clock cycle time and a digital design clock cycle time; calculate a compensated serial delay by multiplying the first number of bit times by a second difference between an actual bit time and a digital design bit time; andPCT Application

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[0037] calculate the total delay based on the parallel delay, the compensated parallel delay, the serial delay, and the compensated serial delay.

[0038] Aspects as in at least one of the seven preceding paragraphs provide a device wherein the parallel delay may comprise a first number of clock cycles; and the delay prediction circuit configured to calculate the parallel delay for communication of the start of frame bit through the parallel bus may comprise adjusting the first number of clock cycles based on inserting or removing a codeword marker from the ethemet frame.

[0039] Aspects as in at least one of the eight preceding paragraphs provide a device which may comprise a memory element configured to store a first number of clock enable cycles for data traversal through the parallel bus; and wherein the delay prediction circuit may be configured to calculate the parallel delay based on the parallel clock enable data table and the first number of clock enable cycles.

[0040] According to another aspect, a method is provided that includes storing, in a memory of a networking device configured to communicate an ethernet frame having a start of frame bit, a first clock enable pattern table for an internal parallel bus of the networking device, the first clock enable pattern being periodic and non-consecutive and reflecting a functionality of the internal parallel bus; storing in a first register a first number of clock enable cycles for data traversal through the internal parallel bus; storing in a second register a second number of clock enable cycles for data traversal through an internal serial bus of the networking device; using the first clock enable pattern table and the first register to calculate a parallel delay for the internal parallel bus, wherein the parallel delay comprising a number of clock cycles; using the second register to calculate a serial delay for the internal serial bus, wherein the serial delay comprising a number of bit times; calculate a compensated parallel delay by multiplying the parallel delay by a first difference between an actual clock cycle time and a digital design clock cycle time; calculate a compensated serial delay by multiplying the serial delay by a second difference between an actual bit time and a digital design bit time; calculate a total delay for communication of the start of frame bit between a first chip pin of the networking device and an internal reference point in the networking device, the total delay based at least on the compensated parallel delay and the compensated serial delay; and update a frame timestamp in the ethernet frame based on the total delay for communication of the start of frame bit between the first chip pin and the internal reference point.PCT Application

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[0043] Aspects as in at least the preceding paragraph provide a method wherein the total delay may be an egress delay for communication of the start of frame bit from the internal reference point to the first chip pin.

[0044] Aspects as in at least one of the two preceding paragraphs provide a method which may include adjusting the number of bit times based on determining whether the start of frame bit is in an internal bit position of a multi-bit output of a converter circuit between the internal parallel bus and the internal serial bus.

[0045] Aspects as in at least one of the three preceding paragraphs provide a method which may include inserting or removing a codeword marker from the ethernet frame; and adjusting the number of clock cycles based on the inserting or the removing the codeword marker from the ethernet frame.

[0046] Aspects as in at least one of the four preceding paragraphs provide a method which may include storing, in the memory, a second clock enable pattern table for the internal parallel bus, wherein: the first clock enable pattern table comprises data indicating a plurality of cycles in which a clock is enabled for a period of the internal parallel bus; the second clock enable pattern table comprises data indicating an accumulated enabled clock count for respective cycles in the plurality of cycles for the period of the internal parallel bus; and the using the first clock enable pattern table and the first register to calculate the parallel delay for the internal parallel bus comprises using the first clock enable pattern table, the second clock enable pattern table, and the first register to calculate the parallel delay for the internal parallel bus.

[0047] According to another aspect, a device is provided that may include a first chip pin to communicate an ethernet frame with a first network medium, the ethernet frame having a start of frame bit; a second chip pin to communicate the ethernet frame with a second network medium; a first serial bus communicatively coupled to the first chip pin; a first parallel bus communicatively coupled to the first serial bus and an internal reference point; a second serial bus communicatively coupled to the second chip pin; a second parallel bus communicatively coupled to the second serial bus and the internal reference point; a memory containing: first modeling data corresponding to the first serial bus; second modeling data corresponding to the first parallel bus; third modeling data corresponding to the second serial bus; and fourth modeling data corresponding to the second parallel bus; a delay prediction circuit to: calculate a first serial bus residual time to communicate the start of frame bit through the first serial bus based on the first modeling data; calculate a first parallel bus residual time to communicate thePCT Application

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[0050] start of frame bit through the first parallel bus based on the second modeling data; calculate a second serial bus residual time to communicate the start of frame bit through the second serial bus based on the third modeling data; and calculate a second parallel bus residual time to communicate the start of frame bit through the second parallel bus based on the second modeling data; and a timestamp circuit to: determine a total residence time of the start of frame bit from the first chip pin to the second chip pin based on the first serial bus residual time, the first parallel bus residual time, the second serial bus residual time, and the second parallel bus residual time; and update a frame timestamp in the ethernet frame based on the total residence time of the start of frame bit from the first chip pin to the second chip pin.

[0051] Aspects as in at least the preceding paragraph provide a device which may include a compensation circuit to: calculate a parallel delay compensation based on a cycle time difference between an actual clock cycle time in the device and a digital design clock cycle time; and calculate a serial delay compensation based on a serial bit difference between an actual bit time in the device and a digital design bit time; and wherein the timestamp circuit to account for the parallel delay compensation and the serial delay compensation when determining the total residence time of the start of frame bit from the first chip pin to the second chip pin.

[0052] Aspects as in at least one of the two preceding paragraphs provide a device wherein the first modeling data may comprise a table corresponding to a periodic clock enable pattern.

[0053] Aspects as in at least one of the three preceding paragraphs provide a device which may include a conversion circuit to communicate the ethernet frame between the first serial bus and the first parallel bus, the conversion circuit having a multi-bit data interface; and wherein the delay prediction circuit to calculate the first serial bus residual time to communicate the start of frame bit through the first serial bus may comprise adjusting the first serial bus residual time when the start of frame bit is in an internal bit position within the multibit data interface.

[0054] Aspects as in at least one of the four preceding paragraphs provide a device wherein the delay prediction circuit to calculate the first parallel bus residual time to communicate the start of frame bit through the first parallel bus may comprise adjusting the first parallel bus residual time when a codeword marker is inserted or removed from the ethernet frame.

[0055] Aspects as in at least one of the five preceding paragraphs provide a device wherein the first modeling data may include a first number of bit times for data traversal through thePCT Application

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[0058] first serial bus and the second modeling data may include a first number of clock enable cycles for data traversal through the first parallel bus.

[0059] BREIF DESCRIPTION OF THE DRAWINGS

[0060] The figures illustrate example systems and methods for predicting delay through a networking device with sub-nanosecond accuracy.

[0061] FIGURE 1 illustrates a block diagram of an example apparatus for predicting delay through a networking device with sub-nanosecond accuracy.

[0062] FIGURE 2 illustrates a block diagram of an example apparatus for predicting delay through a networking device with sub-nanosecond accuracy.

[0063] FIGURE 3 illustrates a block diagram of an example apparatus for predicting delay through a networking device with sub-nanosecond accuracy.

[0064] FIGURE 4 illustrates a block diagram of an example apparatus for predicting delay through a networking device with sub-nanosecond accuracy.

[0065] FIGURE 5 illustrates a block diagram of an example apparatus for predicting delay through a networking device with sub-nanosecond accuracy.

[0066] FIGURE 6 illustrates a flow chart of an example method for predicting delay through a networking device with sub-nanosecond accuracy.

[0067] FIGURE 7 illustrates a flow chart of an example method for predicting delay through a networking device with sub-nanosecond accuracy.

[0068] FIGURE 8 illustrates a flow chart of an example method for predicting delay through a networking device with sub-nanosecond accuracy.

[0069] FIGURE 9 illustrates a flow chart of an example method for predicting delay through a networking device with sub-nanosecond accuracy.

[0070] FIGURE 10 illustrates a block diagram of an example apparatus for predicting delay through a networking device with sub-nanosecond accuracy.

[0071] FIGURE 11 illustrates a block diagram of an example apparatus for predicting delay through a networking device with sub-nanosecond accuracy.

[0072] FIGURE 12 illustrates an example parallel clock enable data table.

[0073] FIGURE 13 illustrates an example egress delay.

[0074] FIGURE 14 illustrates an example ingress delay.

[0075] FIGURE 15 illustrates various example delays through a parallel bus on an example networking device.PCT Application

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[0078] FIGURE 16 illustrates an example egress residual bit data table.

[0079] FIGURE 17 illustrates an example table and gearbox circuit for gearbox ingress. The reference number for any illustrated element that appears in multiple different figures has the same meaning across the multiple figures, and the mention or discussion herein of any illustrated element in the context of any particular figure also applies to each other figure, if any, in which that same illustrated element is shown.

[0080] DETAILED DESCRIPTION

[0081] The following description sets forth examples of the present disclosure. It should be recognized, however, that such description is not intended as a limitation on the scope of the present disclosure. Rather, the description also encompasses combinations and modifications to the examples described herein.

[0082] The teachings of the present disclosure may be employed to provide systems and / or methods for predicting delay through a networking device with sub-nanosecond accuracy, and more specifically for predicting delay that is used in the precision time protocol (PTP) for ethemet communication. The teachings of the present disclosure may enhance performance, reliability, and efficiency in time-critical applications, including:

[0083] • Higher quality of service for audio / video synchronization in Broadcasting

[0084] • Improved precision in machine coordination for Industrial Automation

[0085] • Superior transaction timestamping for Finance

[0086] • Enhanced synchronization for high-speed data transmission in Telecommunications According to various examples of the present disclosure, systems and methods are provided that may predict delay with sub-nanosecond accuracy and compensate the difference between the actual clock cycle / bit time (in real numbers) and the design clock cycle / bit time (in digital numbers with a limited number of digits).

[0087] In a PTP network, one clock may be designated as the master clock, which may provide the time reference, while the other clocks may act as slaves, adjusting their time based on the master. The master clock may be provided by a network device and may serve as the time reference for all the other clocks (slave) in the network (e.g., in other network devices). The master clock may be a dedicated piece of hardware or a network device that includes a built-in clock source. Common devices that may act as the master clock in a PTP network include networks routers and switches, dedicated clock devices specifically designed to act as thePCT Application

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[0090] master clock for PTP networks, servers, and GPS receivers, among others. The master clock may generally be part of a network device, which may vary depending on the setup and the level of precision required for the application.

[0091] Various delays may exist between the master clock and a slave clock including propagation delays through the network (network delays) and residence time within network elements such as a network switch. In PTP, timestamping may be used when attempting to achieve accurate time synchronization between clocks in a network. The purpose of timestamping is to measure the exact time when PTP messages are sent and received, allowing the protocol to account for network delays and calculate the time offset between the master clock and the slave clocks. In PTP, ingress and egress timestamping refer to the points at which timestamps are captured for packets entering and leaving a network device (like a switch or router), respectively. These timestamps may be used when attempting to achieve accurate time synchronization by recording the exact times when PTP messages are received (ingress) or transmitted (egress) at different devices in the network. Ingress timestamping may capture the time when a PTP message arrives at a device (incoming message). Egress timestamping may capture the time when a PTP message leaves a device (outgoing message).

[0092] In PTP, residence time may refer to the amount of time a PTP message spends within a network device (such as a switch or router) before it is forwarded to the next device or to its final destination. In other words, residence time may be the delay introduced by the device while processing the PTP message. When a PTP message passes through a network device, the residence time may contribute to the overall delay between the master and slave clocks. If the residence time is not compensated for, it may distort the accuracy of the synchronization between clocks. In PTP, accurate timestamping of ingress and egress events at each network device may help to calculate the network delay, including the residence time. However, for many PTP devices, like switches, it may be advantageous to account for residence time explicitly by either compensating for it in the protocol or by measuring and communicating the residence time to the slave device for adjustment.

[0093] The present disclosure may provide for sub-nanosecond accuracy by precisely accounting for (1) delays in data traversal across parallel buses within a network device per clock cycle, as well as (2) delays in bit data traversal on the serial bus per bit time. Examples of the present disclosure may predict the receive time (ingress timestamp), residence time, and transmit time (egress timestamp) with sub-nanosecond accuracy as a PTP frame traverses aPCT Application

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[0096] chip. In some examples of the present disclosure, closed-loop compensation may be employed to correct truncation errors and mitigate accuracy loss when representing a real-number delay of one bit time or clock cycle as a digital value. In the same or different examples, the present disclosure may consider other dynamic factors that affect prediction accuracy, such as the clock enable pattern of parallel buses, compensation for SOF start of frame being at byte 0 (sof-O) or byte 4 (sof-4) (which may affect when the SOF first bit is shifted serially to the wire), and codeword marker insertion / deletion (CWM) in RSFEC mode (or similar modes).

[0097] FIGURE 1 illustrates an example apparatus 100 for predicting delay through a networking device with sub-nanosecond accuracy. In an example, apparatus 100 may include chip pin 115. In an example, chip pin 115 may comprise a communication interface pin configured to transmit and / or receive data signals between an integrated circuit and an external network medium 120. In certain examples, chip pin 115 may be operable to support data communication in accordance with one or more networking protocols, including but not limited to Ethernet, SONET / SDH, MoCA, TSN, or any other suitable data communication standards. In an example, network medium 120 may support the Ethernet protocol which may include communication of ethernet frame 121 having first SOF bit 122. Chip pin 115 may be electrically coupled to circuitry within apparatus 100 that may be configured to serialize, deserialize, encode, decode, buffer, or otherwise process data for communication over the network medium. In some examples, chip pin 115 may be configured as a bidirectional input / output (VO) pin, while in other examples, it may be dedicated to either transmission (TX) or reception (RX) of data signals. The electrical characteristics and operational parameters of chip pin 115 may be programmable or adaptable based on the selected communication protocol or external interface requirements. In various examples, chip pin 115 may be coupled to external transceiver circuitry, magnetics, or other physical layer components to facilitate communication with remote devices over wired or wireless media.

[0098] In the same or different examples, apparatus 100 may include parallel bus 130 which may be configured to facilitate communication between internal components of apparatus 100 (e.g., between a central processing unit (CPU), memory subsystem, network processor, media access control (MAC) unit, timestamp unit (TSU), protocol code sublayer (PCS), media access control security (MACSEC) layer, and / or physical layer (PHY) interface, among others (not shown)). In the same or different examples, parallel bus 130 may be a parallel data path within internal components of apparatus 100 (e.g., CPU, MAC unit, TSU, PCS, MACSEC, amongPCT Application

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[0101] others). Examples of parallel bus architectures may include, but are not limited to, Media Independent Interface (Mil), Gigabit Media Independent Interface (GMII), and 10-Gigabit Media Independent Interface (XGMII), which may provide standardized signal paths between MAC and PHY layers for Ethernet communications. In the same or different examples, parallel bus 130 may comprise a unidirectional or bidirectional set of data lines and associated control signals, such as clock and enable signals, and may support data widths ranging from 4 bits to 64 bits or more, depending on protocol and system requirements. In the same or different examples, parallel bus 130 may operate synchronously with a reference clock provided by either the MAC or PHY side, and may support data rates appropriate for the respective communication protocol (e.g., 10 Mbps, 100 Mbps, or 1 Gbps Ethernet communication, among others).

[0102] In the same or different examples, parallel bus 130 may be implemented within an integrated Ethernet switch or controller, such as a multi-port managed switch integrated circuit, and may support additional signaling modes including Turbo Mil or proprietary enhanced timing configurations. In the same or different examples, parallel bus 130 may also be used in conjunction with a host processor interface, such as an 8-bit or 16-bit non-PCI CPU bus, to enable memory-mapped or register-based access to networking functions. These types of bus architectures are exemplified by networking products such as the KSZ-series Ethernet switches, LAN935x-series controllers, and embedded Ethernet MAC peripherals within PIC32 or SAM-series microcontrollers offered by Microchip Technology Inc. In the same or different examples, parallel bus 130 may be used to carry timestamp information or synchronization data in support of time-sensitive protocols such as PTP.

[0103] Parallel bus 130 may include parallel bus clock enable signal 131. In an example, parallel bus clock enable signal 131 may be a wire or other physical structure in apparatus 100 that may be used to enable data flow through circuit components (e.g., sequential circuit elements) of parallel bus 130. In the same or different examples, parallel bus clock enable signal 131 may be used in conjunction with a clock signal that may govern the timing of data sampling and transmission on parallel bus 130. For example, when parallel bus clock enable signal 131 is asserted, one or more components on the bus may be permitted to latch input data, drive output data, or perform other synchronized operations in accordance with the active clock edges. When parallel bus clock enable signal 131 is de-asserted, data movement across the busPCT Application

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[0106] may be suspended or held in a static state, thereby conserving power or preventing unintended data transitions.

[0107] In the same or different examples, parallel bus clock enable signal 131 may enable data traversal through parallel bus 130 on a per-cycle or per-transaction basis, and may be driven by a bus controller, state machine, or other control logic associated with a master or initiator device. In the same or different examples, parallel bus clock enable signal 131 may be asserted in a pattern associated with parallel bus 130. In the same or different examples, the pattern of clock enabled cycles (i.e., parallel bus clock enable signal 131 is asserted) may be periodic such that the pattern is repeated after a given number of clock cycles. In one example, parallel bus clock enable signal 131 may be asserted for 20 clock cycles out of 33 clock cycles in parallel bus 130, and this pattern may repeat every 33 clock cycles in parallel bus 130. Other examples may include a different pattern, including a different number of clock cycles in which parallel bus clock enable signal 131 is asserted and a different number of clock cycles in which the pattern repeats.

[0108] In an example, parallel bus 130 may be implemented such that the number of enabled clock cycles for data to travel through parallel bus 130 is known before runtime. In this example, this number of enabled clock cycles (ECC) may be different depending on various runtime states or parameters (e.g., protocol mode, ingress vs. egress, among others). Apparatus 100 may include memory for storing information about the number of ECC for data to travel through parallel bus 130. FIGURE 15 includes various example ECC delays through example parallel bus 130 implemented within an integrated Ethernet switch or controller. In this example, row 1503 (case 22) may indicate a latency of 26 ECCs for egress data (e.g., SOF bit) to travel from internal reference point 140 through parallel bus 130 when apparatus 100 is configured with 25G, RSFEC, and MAC retiming mode. In the same or different examples, timing information such as that depicted in FIGURE 15 may be stored in registers in apparatus 100 and updated when apparatus 100 is configured to be in one of the supported modes. These registers may then be accessed by other circuits (e.g., delay prediction circuit 160, timestamp circuit 170, among others) to predict the ingress / egress delay of a data communication.

[0109] In the same or different examples, apparatus 100 may include internal reference point 140. Internal reference point 140 may be a location (e.g., module, register(s), port(s), among others) internal to apparatus 100 that may be used as a start point or end point for delay prediction. In an example, internal reference point 140 may be located in a circuit in apparatusPCT Application

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[0112] 100 where the start of a data communication may be detected (e.g., located in a circuit where the SOF rising edge for an Ethernet packet may be detected). In an example, an egress delay prediction may be forward looking and may start from detection of SOF rising edge at internal reference point 140 and may include the time predicted for the first bit of SOF to communicate through parallel bus 130 and chip pin 115 to network medium 120. In the same or different examples, an ingress delay prediction may be backward looking and end with detection of SOF rising edge at internal reference point 140 and may include the time it takes the first bit of SOF to communicate through chip pin 115 and parallel bus 130 from network medium 120.

[0113] In the same or different examples, apparatus 100 may include memory 150. Memory 150 may include one or more storage modules configured to retain data and executable instructions for controlling network operations. Memory 150 may include non-volatile memory (e.g., flash, ROM, among others) for persistent storage, and volatile memory (e.g., RAM, DRAM, SRAM, among others) for temporary storage of runtime data and program execution. Memory 150 may be operatively coupled to one or more circuits (e.g., processors, delay prediction circuit 160, time stamp circuit 170, among others) and may be accessible via an internal bus or communication interface (not shown).

[0114] In the same or different examples, memory 150 may include parallel clock enable data table 151. In an example, parallel clock enable data table 151 may include data corresponding to a periodic pattern of parallel bus clock enable signal 131 in parallel bus 130. FIGURE 12 depicts an example parallel clock enable data table 1251. In the example, parallel clock enable data table 1251 may have 33 columns corresponding to a periodic pattern of parallel bus clock enable signal 131 that repeats every 33 clock cycles. This periodic pattern of 33 clock cycles may be specific to the design of parallel bus 130 and may differ (i.e., be less than or more than 33 clock cycles) for alternative designs or buses.

[0115] In the FIGURE 12 example, row 1204 may correspond to a clock cycle index (i.e., from 0 to 32, representing 33 clock cycles) of the periodic pattern. In the example, row 1203 may represent a clock enable pattern for parallel bus clock enable signal 131, where a ‘1’ may indicate a clock cycle in which parallel bus clock enable signal 131 is asserted, thus allowing data movement through parallel bus 130; a ‘0’ may indicate a clock cycle in which parallel bus clock enable signal 131 is not asserted. For example, during the first clock cycle of the periodic pattern (row 1204 index=0), parallel bus clock enable signal 131 is asserted; and during the second clock cycle of the periodic pattern (row 1204 index=l), parallel bus clock enable signalPCT Application

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[0118] 131 is not asserted. In the example, row 1205 may represent a count of the number of cycles (in the current period) in which parallel bus clock enable signal 131 is or has been asserted. While FIGURE 12 example depicts a single table, the same information may be stored in any number of tables. For example, rows 1203 and 1204 may be stored as a first table, and rows 1204 and 1205 may be stored as a second table. In another example, row 1203 may be stored as a first table, and row 1205 may be stored as a second table. In this example, the index (i.e., information in row 1204) may be implicit and need not be separately stored.

[0119] Returning to FIGURE 1, in the same or different examples, apparatus 100 may include delay prediction circuit 160. Delay prediction circuit 160 may include logic configured to predict portions or all of an ingress / egress delay of data communicated between chip pin 115 and internal reference point 140. In some examples, delay prediction circuit 160 may predict portions of an ingress / egress delay and not all of the ingress / egress delay. In these examples, another circuit, for example, timestamp circuit 170, may be configured to use delay(s) from delay prediction circuit 160 to determine a total ingress / egress delay of data communicated between chip pin 115 and internal reference point 140. The logic in delay prediction circuit 160 may be combinational, sequential, a state machine, a processor, or any other circuit sufficient to predict an ingress / egress delay (or portion thereof) according to the present disclosure. Delay prediction circuit 160 may be operatively coupled to one or more circuits (e.g., processors, memory 150, time stamp circuit 170, internal reference point 140, parallel bus 130, among others) and may be accessible via an internal bus or communication interface (not shown).

[0120] In the same or different examples, apparatus 100 may include timestamp circuit 170. In an example, timestamp circuit 170 may include logic configured to update a timestamp in communicated data (e.g., a frame timestamp for PTP) based on the total delay for communication between chip pin 115 and internal reference point 140. In the same or different examples, timestamp circuit 170 may include logic may determine a total residence time of a first bit of data (e.g., start of frame bit) from chip pin 115 through internal reference point 140 and to an output chip pin (e.g., second chip pin 480 of FIGURE 4, discussed below). In the same or different examples, timestamp circuit 170 may update a timestamp in communicated data (e.g., a frame timestamp for PTP) based on the total residence time of the first bit of data from the chip pin 115 to the output chip pin. The logic in timestamp circuit 170 may be combinational, sequential, a state machine, a processor, or any other circuit sufficient to determine a total residence time, update a timestamp, or perform any of the other operationsPCT Application

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[0123] described in the present disclosure. Timestamp circuit 170 may be operatively coupled to one or more circuits (e.g., processors, memory 150, time delay prediction circuit 160, internal reference point 140, parallel bus 130, among others) and may be accessible via an internal bus or communication interface (not shown).

[0124] Although parallel bus 130, internal reference point 140, memory 150, delay prediction circuit 160, and timestamp circuit 170 are depicted as separate blocks in FIGURE 1, they may be implemented in any configuration, for example, as separate circuits, modules, or blocks; in the same circuit, module, or block; or any other variation where some of the depicted blocks are implemented in the same circuit, module, or block and other(s) of the depicted blocks are implemented in other circuit(s), module(s), or block(s).

[0125] In operation, delay prediction circuit 160 may predict a delay of data communicated through apparatus 100 with sub-nanosecond accuracy. In an example, this predicted delay may be a delay between (1) detection of the start of communication, e.g., detecting first SOF bit 122 at internal reference point 140, and (2) the time the start of communication is transmitted or received on network medium 120 at chip pin 115. In the same or different examples, timestamp circuit 170 may adjust the original timestamp (e.g., a PTP timestamp) with the delay predicted by delay prediction circuit 160. In the same or different examples, delay prediction circuit 160 may consider one or more factors in the delay prediction such as transmission speeds (e.g., 1G, 10G, 25G, among others), encoding schemes (e.g., RSFEC with three modes (Full, SFB, Ignore), Non-RSFEC, among others), traffic directions (egress, ingress), retiming modes (e.g., MAC, PCS, among others), and functional modes (e.g., normal, bypass, MCH, among others).

[0126] In an example, delay prediction circuit 160 may predict an egress delay starting from internal reference point 140 and adding up delays incurred as the data communication travels through data paths inside apparatus 100 until the data communication reaches network medium 120. FIGURE 13 illustrates an example egress delay related to FIGURE 1 which may include delays incurred as the data travels between internal reference point 140 and parallel bus 130 (tl), through parallel bus 130 (t2), between parallel bus 130 and chip pin 115 (t3), and through chip pin 115 (t4). In the same or different examples, delay prediction circuit 160 may predict an ingress delay starting from network medium 120 and adding up delays incurred as the data communication travels through data paths inside apparatus 100 until the data communication reaches internal reference point 140. FIGURE 14 illustrates an example ingress delay related to FIGURE 1 which may include delays incurred as the data travels through chip pin 115 (t5),PCT Application

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[0129] between chip pin 115 and parallel bus 130 (t6), through parallel bus 130 (t7), and between parallel bus 130 and internal reference point 140 (t8).

[0130] In the examples illustrated in FIGURES 13-14 (and others discussed in this disclosure), certain delays related to the egress / ingress delay may be static (e.g., may be a delay known at design time or any other time prior to runtime). For example, delay tl in FIGURE 13 may be a static delay in various examples of apparatus 100 (although it might not be a static delay in other examples).

[0131] In the examples illustrated in FIGURES 13-14 (and others discussed in this disclosure), certain delays related to the egress / ingress delay may be dynamic (e.g., may not be known prior to runtime, may be based on runtime properties of apparatus 100, may be based on runtime properties of the communicated data, among others). In an example, certain modes in Ethernet communications may result in codeword marker (CWM) insertion or deletion, which may dynamically affect delays through apparatus 100. In the same or different examples, buses (e.g., parallel bus 130) may have non-consecutive clock enable patterns, which may dynamically affect delays through apparatus 100. For example, if a beginning of a data communication (e.g., first SOF bit 122) arrives at the input to parallel bus 130 in a clock cycle where parallel bus clock enable signal 131 is not asserted, it may take more time for the data communication to travel through parallel bus 130 compared to a data communication that arrives at the input to parallel bus 130 in a clock cycle where parallel bus clock enable signal 131 is asserted. The latter may have less delay because the data communication may begin moving through parallel bus 130 immediately upon arrival because parallel bus clock enable signal 131 is enabled. In the same or different examples, conversion between parallel and serial modules may dynamically affect delays through apparatus 100 (e.g., see discussion of converter circuit 390, FIGURE 3).

[0132] In examples, delay prediction circuit 160 may predict egress / ingress delays using both static delay information, dynamic delay information, or a combination of both static and dynamic delay information.

[0133] In an example, delay prediction circuit 160 may predict an egress delay (i.e., from internal reference point 140 to network medium 120) through parallel bus 130 based on state information when the beginning of the data communication is detected (e.g., first SOF bit 122 is detected at internal reference point 140). In an example, parallel bus 130 may have a non-consecutive periodic clock enable pattern such as that shown in FIGURE 12, which mayPCT Application

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[0136] include 20 clock enable cycles in a 33-cycle period. In this example, delay prediction circuit 160 may determine a cycle count within the example 33-cycle period when the beginning of the data communication is detected. In an example, the cycle count of a 33-cycle period may correspond to row 1204 in FIGURE 12, where the first cycle count of the period may be cycle 0 and the last cycle count of the period may be cycle 32. In an example, the cycle count information for parallel bus 130 may be stored in a register (e.g., counter) within apparatus 100. Delay prediction circuit 160 may latch the value of the parallel bus 130 cycle count register when detecting the beginning of a data communication at internal reference point 140 and may use that information and other information about the timing through parallel bus 130 (e.g., FIGURE 15) to predict an egress delay.

[0137] For this example, apparatus 100 may be an Ethernet switch configured according to example row 1503 (case 22) of FIGURE 15. Delay prediction circuit 160 may determine (based on the latched value) that parallel bus 130 is in cycle 7 (row 1204 index=6, FIGURE 12) when first SOF bit 122 is detected at internal reference point 140. Delay prediction circuit 160 may determine (based on row 1503, FIGURE 15) that an egress latency through parallel bus 130 is 26 ECCs. Because example parallel bus 130 (FIGURE 12) has 20 ECCs per period, delay prediction circuit 160 may determine a latency through parallel bus 130 of one period (33 clocks) plus the number of clocks required to accumulate an additional 6 ECCs, starting at cycle 7 (row 1204 index=6). Delay prediction circuit 160 may determine from row 1205 (FIGURE 12), that 4 ECCs have already accumulated at cycle 7 and that six additional ECCs will accumulate in cycle 16 (row 1204 index=15). Thus, delay prediction circuit 160 may predict an egress delay through parallel bus 130 of one full period (33 clock cycles) plus nine additional clock cycles (i.e., cycle 16 is nine additional clock cycles from cycle 7), for a total of 42 clock cycles (33+9=42).

[0138] Although delay prediction circuit 160 may predict a 42-clock-cycle egress delay through parallel bus 130 in this example, other examples may result in different delays. For example, where delay prediction circuit 160 determines that parallel bus 130 is in cycle 8 (row 1204 index=7, FIGURE 12) when first SOF bit 122 is detected at internal reference point 140, an egress delay through parallel bus 130 may be 43 clock cycles. Thus, egress delays through a module such as parallel bus 130 may differ depending at least on (1) when the beginning of the data communication is detected and (2) the specific periodic clock enable pattern associated with the module (e.g., parallel bus clock enable pattern 131).PCT Application

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[0141] In the same or different example, delay prediction circuit 160 may predict an ingress delay (i.e., from network medium 120 to internal reference point 140) through parallel bus 130 in a similar fashion to the above-described egress delay prediction, except that an ingress delay may be backward looking whereas an egress delay may be forward looking (from the standpoint of internal reference point 140). For example, delay prediction circuit 160 may latch the value of the parallel bus 130 cycle count register when detecting the beginning of a data communication at internal reference point 140 and may use that information and other information about the timing through parallel bus 130 (e.g., FIGURES 12 & 15) to determine what happened in the past and predict an ingress delay.

[0142] In an example, apparatus 100 may be an Ethernet switch configured according to example row 1505 (case 17) of FIGURE 15. Delay prediction circuit 160 may determine (based on the latched value of the parallel bus 130 cycle count register) that parallel bus 130 is in cycle 19 (row 1204 index=18, FIGURE 12) when first SOF bit 122 is detected at internal reference point 140. Delay prediction circuit 160 may determine (based on row 1505, FIGURE 15) that an ingress latency through parallel bus 130 is 1205 ECCs. Because example parallel bus 130 (FIGURE 12) has 20 ECCs per period, delay prediction circuit 160 may determine a latency through parallel bus 130 of sixty (60) periods (33 clocks * 60 = 1980) plus the number of clocks required to accumulate an additional 5 ECCs, ending at cycle 19 (row 1204 index=18). Delay prediction circuit 160 may determine from row 1205 (FIGURE 12), that 12 ECCs have already accumulated at cycle 19 and that five fewer ECCs would have accumulated in cycle 11 (row 1204 index=10). Thus, delay prediction circuit 160 may predict an ingress delay through parallel bus 130 of sixty full periods (1980 clock cycles) plus eight additional clock cycles (i.e., cycle 19 is eight additional clock cycles from cycle 11), for a total of 1988 clock cycles (1980+8=1988).

[0143] Like the egress delay prediction, ingress delays through a module such as parallel bus 130 may differ depending at least on (1) when the beginning of the data communication is detected and (2) the specific periodic clock enable pattern associated with the module (e.g., parallel bus clock enable pattern 131). For example, if delay prediction circuit 160 determined (based on the latched value of the parallel bus 130 cycle count register) that parallel bus 130 is in cycle 18 (row 1204 index=17, FIGURE 12) when first SOF bit 122 is detected at internal reference point 140, the total ingress delay may be sixty full periods (1980 clock cycles) plus nine additional clock cycles, or 1989 clock cycles.PCT Application

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[0146] FIGURE 2 illustrates an example apparatus 200 for predicting delay through a networking device with sub-nanosecond accuracy. In an example, apparatus 200 may include the same blocks as in FIGURE 1 with the addition of serial bus 280. Serial bus 280 may be configured to facilitate communication between internal components of apparatus 200 (e.g., between a CPU, memory subsystem, network processor, MAC unit, TSU, PCS, MACSEC, parallel bus 130, among others) and chip pin 115. In an example, serial bus 280 may be a serializer / deserializer (SERDES) module which may be configured to provide high-speed data communication between functional blocks of apparatus 200 and external interfaces (e.g., chip pin 115) by converting parallel data into serial data for transmission and reconverting received serial data into parallel form for processing. In the example, serial bus 280 may include a transmit path that serializes outgoing data, a receive path that deserializes incoming data, and associated control circuitry (e.g., a shifting register, among others) that manages timing, alignment, and signal conditioning, thereby enabling operation across a range of communication speeds and protocols.

[0147] In operation, serial bus 280 may include a serial delay for data communication through the bus. In an example, a serial delay through serial bus 280 implemented as a SERDES may be measured from a SERDES shifting register to chip pin 115. In an example, the serial delay through serial bus 280 may be known, as the number of clocks needed for each bit to travel through the SERDES may be the same. In the same or different examples, the known serial delay through serial bus 280 may be adjusted depending on the bit position of the first bit of the data communication (e.g., first SOF bit 122) within the SERDES shifting register. In an example where serial bus 280 is a 40-bit SERDES, the serial delay for an egress (TX) communication may include (1) the known bit delay for communicating through the SERDES and (2) an additional bit delay for every bit before or on the right of first SOF bit 122 within the SERDES shifting register. The additional bit delay(s) may be incurred because the SERDES may transmit all 40 bits in the shifting register, and the bits to the right of first SOF bit 122 may be communicated on network medium 120 before first SOF bit 122, adding delay before SOF bit 122 hits the wire. In the same or different examples, the serial delay for an ingress (RX) communication may reduce the delay for every bit after or on the left of first SOF bit 122 within the 40-bit SERDES shifting register.

[0148] In the previous example, whether to increase or decrease the serial delay based on bits that are before or after first SOF bit 122 assumes implementation details of the bit order in thePCT Application

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[0151] SERDES shifting register. Other examples may use different bit orders such that different adjustments may be appropriate to accurately predict the delays through serial bus 280.

[0152] In operation, delay prediction circuit 160 may predict a total egress or ingress delay for apparatus 200 by (1) determining a serial delay for communication through serial bus 280, determining a parallel delay for communication through parallel bus 130, and (2) adding the serial delay and parallel delay and any other delays between the busses and other components along the path between network medium 120 and internal reference point 140 (e.g., rate adapter FIFO(s), gearbox, I / O, among others). Timestamp circuit 170 may update a timestamp in communicated data (e.g., a frame timestamp for PTP) based on the total egress / ingress delay for communication between chip pin 115 and internal reference point 140.

[0153] As discussed, a serial delay may be based on the number of bits in the SERDES shifting register that are to the left or to the right of first SOF bit 122. In an example, delay prediction circuit 160 may determine the position of first SOF bit 122 in the SERDES shifting register based on cycle count information for parallel bus 130 and the number residual bits when communication data is converted between parallel bus 130 and serial bus 280. For example, an Ethernet device may convert between a 66-bit PCS parallel bus and a 40-bit SERDES serial bus. Since the PCS encoding boundaries (66 bits) may not align cleanly with the 40-bit SERDES width, a converter circuit (FIGURE 3) may align and repack the bits. The residual bits are the leftover bits that do not fit in the current 40-bit SERDES shifting register. The residual bits may be carried over into the next cycle and combined with bits from the next 66-bit PCS encoding boundary to maintain continuity (see discussion of FIGURE 16).

[0154] FIGURE 3 illustrates an example apparatus 300 for predicting delay through a networking device with sub-nanosecond accuracy. In an example, apparatus 300 may include the same blocks as in FIGURE 2 with the addition of converter circuit 390 having multi-bit data interface 391. Converter circuit 390 may be any circuit capable of facilitating data communication by converting data signals between different lane configurations and data rates. In an example, converter circuit 390 may be a gearbox in an Ethernet device and may convert between parallel bus 130 having a 66-bit interface (e.g., PCS), and serial bus 280 having a 40-bit interface (e.g., 40-bit SERDES) in non-RSFEC mode. In a different example, converter circuit 390 may be a gearbox in an Ethernet device and may convert between parallel bus 130 having a 257-bit interface (e.g., PCS), and serial bus 280 having a 160-bit interface (e.g., 160-bit SERDES) in RSFEC mode. In still other examples, converter circuit 390 may be a gearboxPCT Application

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[0157] in an Ethernet device and may convert between other parallel bus sizes and other SERDES sizes, depending on the specific implementation.

[0158] In operation, converter circuit 390 may include a parallel delay. In an example, a parallel delay through converter circuit 390 implemented as a gearbox in an Ethernet device may generally be known prior to runtime based on the gearbox implementation and, although known, may differ based on runtime information such as (1) the state of parallel bus 130 (i.e., cycle count within a period of a repeating clock enable pattern) when the beginning of the data communication is detected (e.g., first SOF bit 122 is detected), and (2) the location of first SOF bit 122 within the packet (e.g., bit 2 for sof-0 or bit 34 for sof-4). In an example, the cycle count within parallel bus 130 (e.g., row 1204, FIGURE 12) may affect a parallel delay through converter circuit 390 implemented as a gearbox when there are residual bits due to mismatch between the gearbox output and the Ethernet block size. For example, a gearbox converting between a 66-bit PCS parallel bus (e.g., Non-RSFEC Ethernet mode) and a 40-bit SERDES may include a 33 -clock-cycle PCS parallel bus period with residual bits illustrated in FIGURE 16.

[0159] FIGURE 16 depicts an example egress residual bit data table 1601. In the example, egress residual bit data table 1601 may have 33 rows corresponding to a 33-clock period of parallel bus 130 for egress data. In the example, egress residual bit data table 1601 may include the cycle count in column 1604 and the residual bits corresponding to the cycle count in column 1605. (Different architectures, implementations, or protocols may have different egress residual bit counts associated with converter circuit 390.). In the FIGURE 16 example, converter circuit 390 may transmit egress data received at its input (66-bits) to its output (40-bits) every clock cycle. Thus, if the packet containing first SOF bit 122 arrives at converter circuit 390 input in clock cycle 0, the delay through converter circuit 390 may be one clock cycle. This may be the case where first SOF bit 122 is in in bit 2 (sof-O) or in bit 34 (sof-4) because the first 40 bits of the packet may be transmitted to converter circuit 390 output in one clock cycle.

[0160] In other egress examples, first SOF bit 122 may take two clock cycles to move through converter circuit 390, e.g., where the packet containing first SOF bit 122 arrives at converter circuit 390 input in a clock cycle where there are residual bits from the previous 66-bit block that may prevent first SOF bit 122 from being transmitted to converter circuit 390 output in the first clock cycle. Using the FIGURE 16 example, if first SOF bit 122 is in bit 34 (sof-4) andPCT Application

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[0163] arrives at converter circuit 390 input in clock cycle 2, it will take two clock cycles before first SOF bit 122 is transmitted to converter circuit 390 output because there are 26 residual bits in clock cycle 2 and the first 14 bits of the new 66-bit block will be transmitted to converter circuit 390 output. Thus, bit 34 (sof-4) will be transmitted to converter circuit 390 output in the next clock cycle (cycle 3), resulting in a two clock cycle delay through converter circuit 390. In the FIGURE 16 example, the egress delay through converter circuit 390 may be generalized as ((bit index of first sof bit + residual bits from table 1601) / 40 + 1) clock cycles. In other words, there may be a one clock cycle delay through converter circuit 390 when (1) first SOF bit 122 is in bit 2 (sof-0), or (2) residual bits from table 1601 is less than seven (7) for the cycle when SOF bit 122 shows up at the converter circuit 390 input; otherwise, there may be two clock cycles of delay through converter circuit 390.

[0164] In an example, the FIGURE 16 residual bit data may also be used to predict the serial delay through serial bus 280 (FIGURE 2). For example, delay prediction circuit 160 may use the residual bits combined with the bit location of first SOF bit 122 (bit 2 (sof-O) or bit 34 (sof-4)) to determine the bit location of first SOF bit 122 within multi-bit data interface 391 (FIGURE 3). In an example, multi-bit data interface 391 may be a 40-bit data interface that is latched for egress communication by a 40-bit shifting register in serial bus 280. Using the FIGURE 16 example, if first SOF bit 122 is in bit 2 (sof-O) and arrives at converter circuit 390 input in clock cycle 17 (20 residual bits), delay prediction circuit 160 may determine that first SOF bit 122 will be in bit position 22. In this example, delay prediction circuit 160 may add 21 clock cycles of egress serial delay from the time first SOF bit 122 is latched into the shifting register. In the FIGURE 16 example, the additional serial delay based on first SOF bit 122 position within multi-bit data interface 391 may be generalized as ((bit index of first sof bit + residual_bits_from_table_1601) % 40) clock cycles.

[0165] In the same or different examples, an ingress parallel delay through converter circuit 390 may be determined based on a cycle count of a repeating clock enable pattern. For example, a gearbox converting between a 40-bit SERDES and 66-bit PCS parallel bus (e.g., Non-RSFEC Ethernet mode) may include a 33 -clock-cycle period as illustrated in FIGURE 17.

[0166] FIGURE 17 depicts an example table 1701 and gearbox circuit 1703 illustrating an example gearbox ingress conversion. In the example, table 1701 may have 33 rows corresponding to a 33-clock period for ingress data. In the example, table 1701 may include:PCT Application

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[0168] 23

[0169] • First column: the cycle count

[0170] • Second column: the number of bits from dO that will be transmitted to the output (dO is the 40-bit SERDES output)

[0171] • Third column: the number of bits from dl that will be transmitted to the output (dl is dO delayed by one clock cycle, as illustrated in gearbox circuit 1703)

[0172] • Fourth column: the number of bits from d2 that will be transmitted to the output (d2 is dl delayed by one clock cycle)

[0173] • Fifth column: ‘X’ indicates cycles where 66-bits are ready at the output (Different architectures, implementations, or protocols may have different ingress characteristics from those shown in example table 1701 and circuit 1703.) In the FIGURE 17 example, a parallel delay may be (1) zero clock cycles (first SOF bit 122 is in dO when the 66-bit block is ready), (2) one clock cycle (first SOF bit 122 is in dl when the 66-bit block is ready), or (3) two clock cycles (first SOF bit 122 is in d2 when the 66-bit block is ready). In operation, delay prediction circuit 160 may predict an ingress delay through converter circuit 390 based on (1) the cycle count when first SOF bit 122 appeared at the output of converter circuit 390 and (2) the origin of first SOF bit 122 (dO, dl, or d2). For example, if first SOF bit 122 is detected at the output of converter circuit 390 in cycle 22 and first SOF bit 122 is at bit position 30 within the 66-bit output, delay prediction circuit 160 may determine a delay of one cycle through converter circuit 390 (i.e., bit 30 is in dl, indicating a one clock cycle delay).

[0174] Turning back to FIGURE 3, in operation, delay prediction circuit 160 may predict a total egress or ingress delay for apparatus 300 by (1) determining a serial delay for communication through serial bus 280, determining a parallel delay through converter circuit 390, determining a parallel delay for communication through parallel bus 130, and (2) adding the serial delay and parallel delays and any other delays between the busses and other components along the path between network medium 120 and internal reference point 140 (e.g., rate adapter FIFO(s), I / O, among others). Timestamp circuit 170 may update a timestamp in communicated data (e.g., a frame timestamp for PTP) based on the total egress / ingress delay for communication between chip pin 115 and internal reference point 140.

[0175] Although FIGURES 1-3 depict a specific number of serial and parallel buses (and converter circuits) on the communication path between first chip pin 115 and internal reference point 140, other examples may include more or fewer serial and parallel buses (and converterPCT Application

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[0178] circuits) on that path. In those alternative examples, delay prediction circuit 160 may predict a total ingress / egress delay by calculating the delay through all serial and parallel buses (and any other delays between the busses and other components) on the communication path between first chip pin 115 and internal reference point 140.

[0179] FIGURE 4 illustrates an example apparatus 400 for predicting delay through a networking device with sub-nanosecond accuracy. In an example, apparatus 400 may include the same blocks as in FIGURE 1 (i.e., first chip pin 115, first serial bus 280, first parallel bus 130, internal reference point 140, delay prediction circuit 160, timestamp circuit 170).

[0180] Apparatus 400 may additionally include second chip pin 418 which, like first chip pin 115, may comprise a communication interface pin configured to transmit and / or receive data signals between an integrated circuit and second network medium 420. The previous description of first chip pin 115 (FIGURE 1) applies equally to second chip pin 418. (Likewise, the previous description of first network medium 120 (FIGURE 1) applies equally to second network medium 420.)

[0181] Apparatus 400 may additionally include second parallel bus 435 which, like first parallel bus 130, may be configured to facilitate communication between internal components of apparatus 400. The previous description of first parallel bus 130 (FIGURE 1) applies equally to second parallel bus 435. In an example, first parallel bus 130 and second parallel bus 435 may have a similar architecture (e.g., both PCS blocks). In the same or different examples, first parallel bus 130 and second parallel bus 435 may be separate ingress and egress paths in the same module (e.g., in a PCS block). In another example, first parallel bus 130 and second parallel bus 435 may have different architectures (e.g., one MAC block, one PCS block).

[0182] Apparatus 400 may additionally include second serial bus 495 which, like first serial bus 280, may be configured to facilitate communication between internal components of apparatus 400. The previous description of first serial bus 280 (FIGURE 2) applies equally to second serial bus 495. In an example, first serial bus 280 and second serial bus 495 may have a similar architecture (e.g., both SERDES blocks). In the same or different examples, first serial bus 280 and second serial bus 495 may be separate ingress and egress paths in the same module (e.g., in a single SERDES block). In another example, first serial bus 280 and second serial bus 495 may have different architectures (e.g., one SERDES block, one non-SERDES serial block).

[0183] Apparatus 400 may additionally include memory 450 which, like memory 150 (FIGURE 1), may include one or more storage modules configured to retain data andPCT Application

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[0186] executable instructions for controlling network operations. Memory 450 may include first modeling data 452, second modeling data 453, third modeling data 454, and fourth modeling data 455. First modeling data 452 may include data corresponding to first serial bus 280 and may be used to calculate a first serial bus residual time to communicate a start of frame bit through first serial bus 280. Second modeling data 453 may include data corresponding to first parallel bus 130 and may be used to calculate a first parallel bus residual time to communicate a start of frame bit through first parallel bus 130. Third modeling data 454 may include data corresponding to second serial bus 495 and may be used to calculate a second serial bus residual time to communicate a start of frame bit through second serial bus 495. Fourth modeling data 455 may include data corresponding to second parallel bus 435 and may be used to calculate a second parallel bus residual time to communicate a start of frame bit through second parallel bus 495. In an example, modeling data 452-455 may be similar to data illustrated in FIGURE 12. In the same or different examples, modeling data 452-455 may be similar to data illustrated in FIGURE 15. In the same or different examples, modeling data 452-455 may be any other data useful in calculating delays through first parallel bus 130, second parallel bus 435, first serial bus 280, or second serial bus 495.

[0187] In operation, delay prediction circuit 160 may predict a total residence delay for apparatus 400 by (1) determining a first serial delay for communication through first serial bus 280, determining a second serial delay for communication through second serial bus 495, determining a first parallel delay for communication through first parallel bus 130, determining a second parallel delay for communication through second parallel bus 435; and (2) adding the serial delays and parallel delays and any other delays between the busses and other components along the path between first network medium 120 and second network medium 420 (e.g., rate adapter FIFO(s), I / O, among others). Timestamp circuit 170 may update a timestamp in communicated data (e.g., a frame timestamp for PTP) based on the total residence delay for communication between first chip pin 115 and second chip pin 418.

[0188] FIGURE 5 illustrates an example apparatus 500 for predicting delay through a networking device with sub-nanosecond accuracy. Apparatus 500 may include the same blocks as in FIGURE 4 with the addition of converter circuit 590 having multi -bit data interface 591.

[0189] Like converter circuit 390 (FIGURE 3), converter circuit 590 may be any circuit capable of facilitating data communication by converting data signals between different lane configurations and data rates. The previous description of converter circuit 390 and multi-bitPCT Application

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[0192] data interface 391 (FIGURE 3) applies equally to converter circuit 590 and multi-bit data interface 591. In an example (not illustrated), apparatus 500 may include a second converter circuit for converting data between second parallel bus 435 and second serial bus 495.

[0193] In operation, delay prediction circuit 160 may predict a total residence delay for apparatus 500 by (1) determining a first serial delay for communication through first serial bus 280, determining a second serial delay for communication through second serial bus 495, determining a first parallel delay for communication through first parallel bus 130, determining a second parallel delay for communication through second parallel bus 435, determining a third parallel delay for communication through converter circuit 590; and (2) adding the serial delays and parallel delays and any other delays between the busses and other components along the path between first network medium 120 and second network medium 420 (e.g., rate adapter FIFO(s), I / O, among others). Timestamp circuit 170 may update a timestamp in communicated data (e.g., a frame timestamp for PTP) based on the total residence delay for communication between first chip pin 115 and second chip pin 418.

[0194] Although FIGURES 4-5 depict a specific number of serial and parallel buses (and converter circuits) on the communication path between first chip pin 115 and second chip pin 418, other examples may include more or fewer serial and parallel buses (and converter circuits) on that path. In those alternative examples, delay prediction circuit 160 may predict a total residence delay by calculating the delay through all serial and parallel buses (and any other delays between the busses and other components) on the communication path between first chip pin 115 and second chip pin 418.

[0195] FIGURE 6 illustrates a flow chart of an example method 600 for predicting delay through a networking device with sub-nanosecond accuracy. According to one example, method 600 may begin at block 610. The initialization point for method 600 and the order of blocks 610 through 690 may vary depending on implementation.

[0196] At block 610, a first clock enable pattern table for an internal parallel bus of the networking device may be stored in a memory of a networking device configured to communicate an Ethernet frame having a start of frame bit, where the first clock enable pattern may be periodic and non-consecutive and may reflect a functionality of the internal parallel bus. At block 620, a first number of clock enable cycles for data traversal through the internal parallel bus may be stored in a first register. At block 630, a second number of clock enablePCT Application

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[0199] cycles for data traversal through an internal serial bus of the networking device may be stored in a second register.

[0200] At block 640, a parallel delay for the internal parallel bus may be calculated using the first clock enable pattern table and the first register, where the parallel delay comprises a number of clock cycles. At block 650, a serial delay for the internal serial bus may be calculated using the second register, where the serial delay comprises a number of bit times.

[0201] At block 660, a compensated parallel delay may be calculated by multiplying the parallel delay by a first difference between an actual clock cycle time and a digital design clock cycle time. At block 670, a compensated serial delay may be calculated by multiplying the serial delay by a second difference between an actual bit time and a digital design bit time.

[0202] At block 680, a total delay may be calculated for communication of the start of frame bit between a first chip pin of the networking device and an internal reference point in the networking device, where the total delay is based at least on the compensated parallel delay and the compensated serial delay. At block 690, a frame timestamp in the Ethernet frame may be updated based on the total delay for communication of the start of frame bit between the first chip pin and the internal reference point.

[0203] Although FIGURE 6 discloses a particular number of operations related to method 600, method 600 may be executed with greater or fewer operations than those depicted in FIGURE 6. For example, storing the first number of clock enable cycles in a first register in block 620 may not be required if that information is available elsewhere (e.g., from a specific table in memory). Similarly, storing the second number of clock enable cycles in a second register in block 630 may not be required if that information is available elsewhere. FIGURES 7-9 provide examples of additional operations that may be performed. In addition, although FIGURE 6 discloses a certain order of operations to be taken with respect to method 600, the operations comprising method 600 may be completed in any suitable order.

[0204] FIGURE 7 illustrates a flow chart of an example method 700 for predicting delay through a networking device with sub-nanosecond accuracy. According to one example, method 700 may begin with blocks 610-650 (FIGURE 6) and then proceed to block 755. At block 755, the number of bit times may be adjusted based on determining whether the start of frame bit is in an internal bit position of a multi-bit output of a converter circuit between the internal parallel bus and the internal serial bus. Method 700 may then proceed to blocks 660-690 (FIGURE 6).PCT Application

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[0207] FIGURE 8 illustrates a flow chart of an example method 800 for predicting delay through a networking device with sub-nanosecond accuracy. According to one example, method 800 may begin with blocks 610-640 (FIGURE 6) and then proceed to block 845. At block 845, a codeword marker may be inserted or removed from the Ethernet frame. At block 846, the number of clock cycles may be adjusted based on the inserting or the removing the codeword marker from the Ethernet frame. Method 800 may then proceed to blocks 650-690 (FIGURE 6).

[0208] FIGURE 9 illustrates a flow chart of an example method 900 for predicting delay through a networking device with sub-nanosecond accuracy. According to one example, method 900 may begin with blocks 610-630 (FIGURE 6) and then proceed to block 935. At block 935, a second clock enable pattern table for the internal parallel bus may be stored in the memory. Method 700 may then proceed to blocks 640-690 (FIGURE 6).

[0209] Methods 600-900 may be implemented using apparatus 100-500, apparatus 1000-1100, or any other system operable to implement methods 600-900. Although examples have been described above, other variations and examples may be made from this disclosure without departing from the spirit and scope of these disclosed examples.

[0210] FIGURE 10 illustrates an example apparatus 1000 for predicting delay through a networking device with sub-nanosecond accuracy. Apparatus 1000 may include the same blocks as in FIGURE 1 and may additionally include memory element 1061 within delay prediction circuit 160. Memory element 1061 may include one or more storage modules configured to retain data for controlling network operations. In an example, memory element 1061 may be configured to store a first number of clock enable cycles for data traversal through parallel bus 130. In the same or different examples, memory element 1061 may store latency values from FIGURE 15 and may be updated when the mode / configuration of apparatus 1000 changes. In the same or different examples, memory element 1061 may store other latency values related to parallel bus 130 (e.g., stall delay, among others).

[0211] In operation, delay prediction circuit 160 may predict a total egress or ingress delay for apparatus 1000 by (1) determining a parallel delay for communication through parallel bus 130, and (2) adding the parallel delay and any other delays along the path between network medium 120 and internal reference point 140 (e.g., serial delay, rate adapter FIFO(s), gearbox, I / O, stall, among others). In an example, delay prediction circuit 160 may be configured to calculate the parallel delay based on (1) parallel clock enable data table 151 and (2) the firstPCT Application

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[0214] number of clock enable cycles stored in memory element 1061. Because latency information may be stored in memory element 1061, delay prediction circuit 160 may save time compared to obtaining the FIGURE 15 data from a table in memory. Timestamp circuit 170 may update a timestamp in communicated data (e.g., a frame timestamp for PTP) based on the total egress / ingress delay for communication between chip pin 115 and internal reference point 140.

[0215] TRUNCATION ERROR COMPENSATION FIGURE 11 illustrates an example apparatus 1100 for predicting delay through a networking device with sub-nanosecond accuracy. Apparatus 1100 may include the same blocks as in FIGURE 4 and may additionally include compensation circuit 1175. In an example, compensation circuit 1175 may include logic configured to adjust a predicted delay based on a cycle time difference between an actual clock cycle time in apparatus 1100 and a digital design clock cycle time. In the same or different examples, compensation circuit 1175 may include logic configured to adjust a predicted delay based on a serial bit difference between an actual bit time in the device and a digital design bit time. Although exemplary compensation circuit 1175 is depicted as a separate block in apparatus 1100, compensation circuit 1175 may be implemented within or as part of another block such as delay prediction circuit 160, timestamp circuit 170, among others.

[0216] In operation, compensation circuit 1175 may adjust the delay that is predicted by delay prediction circuit 160 in order to compensate for truncation errors. In the examples discussed herein (FIGURES 1-11), delay prediction circuit 160 may predict delays based on (1) clock cycles (e.g., parallel delay(s)) and (2) bit times (e.g., serial delay(s)). In the same example, after determining a number of clock cycles or bit times of delay, delay prediction circuit 160 may multiply those numbers by a clock period or bit time specified at design time. In an example, truncation errors (TE) may occur because the 16-bit number in 1 / 65536 ns unit represents the sub-nanosecond of a real number. Thus, TE may occur in the calculation of parallel delay and serial delay based on a difference between a digitized number (e.g., design clock period or design bit time specified at design time) and a real number (e.g., the actual clock period or bit time on the manufactured device). In some scenarios, the TE from each clock cycle and from each bit time may degrade the sub-nanosecond accuracy of prediction.

[0217] In an example, compensation circuit 1175 may obtain the cycle time of the real clock (CTRC) in ns (i.e., based on the runtime clock frequency of apparatus 1100) from a status register in apparatus 1100 (not illustrated). Compensation circuit 1175 may then calculate thePCT Application

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[0220] cycle time difference (CTD) between CTRC and a hard-coded cycle time of the design clock and multiply that difference by 65536 to convert the time to 1 / 65536 ns time unit (CTD 65536). Compensation circuit 1175 may then divide CTRC by 40 (40-bits per cycle) and multiply the division result by 65536 to convert the bit time of the real clock to 1 / 65536 ns time unit (BTRC 65536). Compensation circuit 1175 may calculate the bit time difference (BTD 65536) between BTRC 65536 and the bit time of the design clock (in 1 / 65536 ns time unit).

[0221] Once the CTD 65536 is calculated, compensation circuit 1175 may multiple this number by the number of clock cycles of parallel delay (e.g., determined by delay prediction circuit 160) and convert the result back to 1 / 256 ns time unit by shifting the result to the right by 8 (i.e., » 8) (TE PARALLEL ADJUST). Where the parallel delay prediction determined by delay prediction circuit 160 is less than the delay expected with the real clock cycle time, the result (TE PARALLEL ADJUST) may be added to the prediction. Where the parallel delay prediction determined by delay prediction circuit 160 is more than the delay expected with the real clock cycle time, the result (TE PARALLEL ADJUST) may be subtracted from the prediction.

[0222] Similarly, once the BTD 65536 is calculated, compensation circuit 1175 may multiple this number by the number of bit times of serial delay (e.g., determined by delay prediction circuit 160) and convert the result back to 1 / 256 ns time unit by shifting the result to the right by 8 (i.e., » 8) (TE SERIAL ADJUST). Where the serial delay prediction determined by delay prediction circuit 160 is less than the delay expected with the real clock bit time, the result (TE SERIAL ADJUST) may be added to the prediction. Where the serial delay prediction determined by delay prediction circuit 160 is more than the delay expected with the real clock bit time, the result (TE SERIAL ADJUST) may be subtracted from the prediction.

[0223] Timestamp circuit 170 may update a timestamp in communicated data (e.g., a frame timestamp for PTP) based on the total egress / ingress delay for communication between chip pin 115 and internal reference point 140, as adjusted by compensation circuit 1175.

[0224] CODEWORD MARKER INSERTION / DELETION

[0225] In an example, apparatus 100-500, 1000-1100 may support codeword marker (CWM) insertion / deletion in 25G RSFEC, and delay prediction circuit 160 may account for the effects of those operations. For example, CWM insertion in 25G RSFEC egress may result in additional delay as first SOF bit 122 is stalled (e.g., inside a rate adapter FIFO) while the CWMPCT Application

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[0228] is inserted. In this example, delay prediction circuit 160 may add a known CWM insertion delay to the predicted delay. In an example, 140 parity bits may be added to the end of RSFEC codeword, and if first SOF bit 122 is at the beginning of the next RSFEC codeword, the egress delay may be increased by the 140-bit parity. In the same or different examples, delay prediction circuit 160 may determine that the prediction may be inaccurate due to CWM insertion (e.g., if the prediction happens in the window right after CWM insertion) and force the CF field of the PTP frame to a maximum value so that an overflow condition may cause the link partner to discard the timestamp.

[0229] In the same or different examples, a CWM in 25G RSFEC ingress may be deleted (e.g., not written to a rate adapter FIFO by suppressing a FIFO write enable signal when the CWM is at the FIFO input). In this example, delay prediction circuit 160 may account for the CWM deletion by decreasing the index of the enabled clock cycle (ECC) when the SOF is received (e.g., with 4 ECC for the CWM before SOF, the index of ECC receiving SOF following the CWM deletion will be decreased by 4).

[0230] Thus, systems and / or methods for predicting delay through a device with subnanosecond accuracy, and more specifically for predicting delay that is used in the precision time protocol (PTP) for ethernet communication are provided. Changes may be made to the present disclosure without departing from the spirit and scope of the disclosure.

Claims

PCT Application68354.234173 / 25056W00132CLAIMS1. A device, comprising:a first chip pin to communicate an ethernet frame with a first network medium, the ethemet frame having a start of frame bit;a parallel bus communicatively coupled between the first chip pin and an internal reference point;a memory containing a parallel clock enable data table including data corresponding to a parallel bus clock enable pattern;a delay prediction circuit configured to:calculate, based on the parallel clock enable data table, a parallel delay for communication of the start of frame bit through the parallel bus;calculate a total delay for communication of the start of frame bit between the first chip pin and the internal reference point, the total delay based at least on the parallel delay; anda timestamp circuit to update a frame timestamp in the ethemet frame based on the total delay for communication of the start of frame bit between the first chip pin and the internal reference point.

2. The device of claim 1, wherein the total delay is an egress delay for communication of the start of frame bit from the internal reference point to the first chip pin.

3. The device as claimed in any of claims 1-2, wherein:the parallel delay comprises a first number of clock cycles; andthe delay prediction circuit configured to:calculate a compensated parallel delay by multiplying the first number of clock cycles by a first difference between an actual clock cycle time and a digital design clock cycle time; andcalculate the total delay based on the parallel delay and the compensated parallel delay.PCT Application68354.234173 / 25056W001334. The device as claimed in any of claims 1-3, wherein the parallel bus clock enable pattern comprises a periodic and non-consecutive clock enable pattern.

5. The device as claimed in any of claims 1-4, comprising a serial bus communicatively coupled between the first chip pin and the parallel bus; andwherein the delay prediction circuit configured to:calculate a serial delay comprising a first number of bit times for communication of the start of frame bit through the serial bus; andcalculate the total delay for communication of the start of frame bit between the first chip pin and the internal reference point based at least on the parallel delay and the serial delay.

6. The device of claim 5, comprising:a converter circuit to communicate the ethernet frame between the parallel bus and the serial bus, the converter circuit having a multi-bit data interface; andwherein the delay prediction circuit configured to calculate the serial delay comprises adjusting the first number of bit times when the start of frame bit is in an internal bit position within the converter circuit muti-bit data interface.

7. The device as claimed in any of claims 5-6, wherein:the parallel delay comprises a first number of clock cycles; andthe delay prediction circuit configured to:calculate a compensated parallel delay by multiplying the first number of clock cycles by a first difference between an actual clock cycle time and a digital design clock cycle time;calculate a compensated serial delay by multiplying the first number of bit times by a second difference between an actual bit time and a digital design bit time; and calculate the total delay based on the parallel delay, the compensated parallel delay, the serial delay, and the compensated serial delay.

8. The device as claimed in any of claims 1-7, wherein:the parallel delay comprises a first number of clock cycles; andPCT Application68354.234173 / 25056W00134the delay prediction circuit configured to calculate the parallel delay for communication of the start of frame bit through the parallel bus comprises adjusting the first number of clock cycles based on inserting or removing a codeword marker from the ethernet frame.

9. The device as claimed in any of claims 1-8, comprising:a memory element configured to store a first number of clock enable cycles for data traversal through the parallel bus; andwherein the delay prediction circuit configured to calculate the parallel delay based on the parallel clock enable data table and the first number of clock enable cycles.

10. A method, comprising:storing, in a memory of a networking device configured to communicate an ethernet frame having a start of frame bit, a first clock enable pattern table for an internal parallel bus of the networking device, the first clock enable pattern being periodic and non-consecutive and reflecting a functionality of the internal parallel bus;storing in a first register a first number of clock enable cycles for data traversal through the internal parallel bus;storing in a second register a second number of clock enable cycles for data traversal through an internal serial bus of the networking device;using the first clock enable pattern table and the first register to calculate a parallel delay for the internal parallel bus, wherein the parallel delay comprising a number of clock cycles;using the second register to calculate a serial delay for the internal serial bus, wherein the serial delay comprising a number of bit times;calculate a compensated parallel delay by multiplying the parallel delay by a first difference between an actual clock cycle time and a digital design clock cycle time;calculate a compensated serial delay by multiplying the serial delay by a second difference between an actual bit time and a digital design bit time;calculate a total delay for communication of the start of frame bit between a first chip pin of the networking device and an internal reference point in the networking device, the total delay based at least on the compensated parallel delay and the compensated serial delay; andPCT Application68354.234173 / 25056W00135update a frame timestamp in the ethemet frame based on the total delay for communication of the start of frame bit between the first chip pin and the internal reference point.

11. The method of claim 10, wherein the total delay is an egress delay for communication of the start of frame bit from the internal reference point to the first chip pin.

12. The method as claimed in any of claims 10-11, comprising:adjusting the number of bit times based on determining whether the start of frame bit is in an internal bit position of a multi -bit output of a converter circuit between the internal parallel bus and the internal serial bus.

13. The method as claimed in any of claims 10-12, comprising:inserting or removing a codeword marker from the ethemet frame; andadjusting the number of clock cycles based on the inserting or the removing the codeword marker from the ethernet frame.

14. The method as claimed in any of claims 10-13, comprising:storing, in the memory, a second clock enable pattern table for the internal parallel bus, wherein:the first clock enable pattern table comprises data indicating a plurality of cycles in which a clock is enabled for a period of the internal parallel bus;the second clock enable pattern table comprises data indicating an accumulated enabled clock count for respective cycles in the plurality of cycles for the period of the internal parallel bus; andthe using the first clock enable pattern table and the first register to calculate the parallel delay for the internal parallel bus comprises using the first clock enable pattern table, the second clock enable pattern table, and the first register to calculate the parallel delay for the internal parallel bus.

15. A device, comprising:PCT Application68354.234173 / 25056W00136a first chip pin to communicate an ethernet frame with a first network medium, the ethemet frame having a start of frame bit;a second chip pin to communicate the ethernet frame with a second network medium; a first serial bus communicatively coupled to the first chip pin;a first parallel bus communicatively coupled to the first serial bus and an internal reference point;a second serial bus communicatively coupled to the second chip pin;a second parallel bus communicatively coupled to the second serial bus and the internal reference point;a memory containing:first modeling data corresponding to the first serial bus;second modeling data corresponding to the first parallel bus;third modeling data corresponding to the second serial bus; and fourth modeling data corresponding to the second parallel bus;a delay prediction circuit to:calculate a first serial bus residual time to communicate the start of frame bit through the first serial bus based on the first modeling data;calculate a first parallel bus residual time to communicate the start of frame bit through the first parallel bus based on the second modeling data; calculate a second serial bus residual time to communicate the start of frame bit through the second serial bus based on the third modeling data; and calculate a second parallel bus residual time to communicate the start of frame bit through the second parallel bus based on the second modeling data; anda timestamp circuit to:determine a total residence time of the start of frame bit from the first chip pin to the second chip pin based on the first serial bus residual time, the first parallel bus residual time, the second serial bus residual time, and the second parallel bus residual time; andupdate a frame timestamp in the ethernet frame based on the total residence time of the start of frame bit from the first chip pin to the second chip pin.PCT Application68354.234173 / 25056W0013716. The device of claim 15, comprising:a compensation circuit to:calculate a parallel delay compensation based on a cycle time difference between an actual clock cycle time in the device and a digital design clock cycle time; andcalculate a serial delay compensation based on a serial bit difference between an actual bit time in the device and a digital design bit time; and wherein the timestamp circuit to account for the parallel delay compensation and the serial delay compensation when determining the total residence time of the start of frame bit from the first chip pin to the second chip pin.

17. The device as claimed in any of claims 15-16, wherein the first modeling data comprises a table corresponding to a periodic clock enable pattern.

18. The device as claimed in any of claims 15-17, comprising a conversion circuit to communicate the ethernet frame between the first serial bus and the first parallel bus, the conversion circuit having a multi-bit data interface; andwherein the delay prediction circuit to calculate the first serial bus residual time to communicate the start of frame bit through the first serial bus comprises adjusting the first serial bus residual time when the start of frame bit is in an internal bit position within the multibit data interface.

19. The device as claimed in any of claims 15-18, wherein the delay prediction circuit to calculate the first parallel bus residual time to communicate the start of frame bit through the first parallel bus comprises adjusting the first parallel bus residual time when a codeword marker is inserted or removed from the ethernet frame.

20. The device as claimed in any of claims 15-19, wherein the first modeling data includes a first number of bit times for data traversal through the first serial bus and the second modeling data includes a first number of clock enable cycles for data traversal through the first parallel bus.

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