Dry edge bead removal and backside clean for metal-containing resist

Abstract

Methods and systems for processing a semiconductor substrate are provided. The method comprises (a) providing, in a process chamber, a semiconductor substrate with a metal-containing photoresist film disposed on the semiconductor substrate; (b) exposing the semiconductor substrate to etch conditions comprising a hydrogen-containing species activated by a remote plasma source to remove a portion of the metal-containing photoresist film; and (c) exposing the semiconductor substrate to an oxygen-containing species activated by the remote plasma source.

Description

Attorney Docket No. LAM1P113WO / 12101-1WODRY EDGE BEAD REMOVAL AND BACKSIDE CLEAN FOR METAL-CONTAINING RESISTRELATED APPLICATION(S)

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in its entirety and for all purposes.BACKGROUND

[0002] The fabrication of semiconductor devices, such as integrated circuits, is a multi-step process involving photolithography. In general, the process includes the deposition of material on a wafer, and patterning the material through lithographic techniques to form structural features (e.g., transistors and circuitry) of the semiconductor device. The steps of a typical photolithography process known in the art include: preparing the substrate; applying a photoresist, such as by spin coating; exposing the photoresist to light in a desired pattern, causing the exposed areas of the photoresist to become more or less soluble in a developer solution; developing by applying a developer solution to remove either the exposed or the unexposed areas of the photoresist; and subsequent processing to create features on the areas of the substrate from which the photoresist has been removed, such as by etching or material deposition.

[0003] Specifically, wafer edge bead removal (EBR) refers to a process where excess photoresist material that builds up at the edges of a wafer during the spin coating process is selectively removed using a specialized solvent or cleaning solution, typically applied while the wafer is still spinning, to prevent defects and ensure proper patterning in subsequent lithography steps. This process is crucial for metal-oxide photoresists as their edge bead can cause issues with adhesion and patterning accuracy. However, wet EBR processes have several drawbacks.

[0004] The background description provided herein is for the purpose of generally presenting the context of the present technology. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present technology.Attorney Docket No. LAM1P113WO / 12101-1WOSUMMARY

[0005] Disclosed herein are methods and systems for processing a semiconductor substrate are provided. One aspect of the disclosure provides a method of processing the semiconductor substrate. In some embodiments, the method comprises (a) providing, in a process chamber, the semiconductor substrate with a metal-containing photoresist film disposed on the semiconductor substrate, (b) exposing the semiconductor substrate to etch conditions comprising a hydrogen-containing species activated by a remote plasma source to remove a portion of the metal-containing photoresist film, and (c) exposing the semiconductor substrate to an oxygen-containing species activated by the remote plasma source.

[0006] In some embodiments, the metal-containing photoresist film is an organo-metal oxide film. In some embodiments, the metal-containing photoresist film is an organo-metal-containing thin film. In some embodiments, the metal-containing photoresist film comprises an organotin oxide. In some embodiments, the metal-containing photoresist film comprises an element, such as tin, hafnium, tellurium, bismuth, indium, antimony, iodine, or germanium.

[0007] In some embodiments, (b) removes the portion of the metal-containing photoresist film on an edge, a bevel, and a backside of the semiconductor substrate.

[0008] In some embodiments, the etch conditions of (b) comprise a carrier gas. In some embodiments, the carrier gas comprises helium (He), neon (Ne), argon (Ar), xenon (Xe), nitrogen (N2), or methane (CH4).

[0009] In some embodiments, the carrier gas comprises Ar and a flow rate of Ar ranges from about 2000 seem to about 7000 seem. In some embodiments, the carrier gas comprises N2 and a flow rate of N2 ranging from about 2000 seem to about 7000 seem.

[0010] In some embodiments, the hydrogen-containing species of (b) comprises molecular hydrogen (H2) or a hydrogen halide (HX), where X is a halogen.

[0011] In some embodiments, a flow rate of the hydrogen-containing species is between about 2000 seem and about 7000 seem.

[0012] In some embodiments, the hydrogen-containing species comprises H2 and the etch conditions of (b) comprise molecular oxygen (O2). In some embodiments, a flow rate of O2 is about 100 ppm.

[0013] In some embodiments, the etch conditions of (b) causes deposition of an etch byproduct on the semiconductor substrate. In some embodiments, the oxygen-containing species in (c) removes the etch byproduct.Attorney Docket No. LAM1P113WO / 12101-1WO

[0014] In some embodiments, subsequent (b), an amount of a metal from the metalcontaining photoresist film present on a surface of the semiconductor substrate is about 5 E10 / cm2.

[0015] In some embodiments, the etch conditions of (b) comprise a pressure ranging from about 100 mT to about 500 mT.

[0016] In some embodiments, the etch conditions of (b) comprise a temperature ranging from about 20°C to about 120°C.

[0017] In some embodiments, in (c), the oxygen-containing species comprises O2, ozone (O3), carbon monoxide (CO), carbon dioxide (CO2), nitric oxide (NO), and / or nitrogen dioxide (NO2).

[0018] In some embodiments, the method further comprises (d) exposing the semiconductor substrate to a hydrogen-containing plasma to remove a trace metal from a surface of the semiconductor substrate and (e) repeating operations (c) and (d) in a multi-cycle etch process.

[0019] In some embodiments, the multi-cycle etch process of (e) is repeated for a frequency of at least two cycles.

[0020] In some embodiments, subsequent (e), an amount of a metal from the metalcontaining photoresist film present on the surface of the semiconductor substrate is about less than 1 E10 / cm2.

[0021] In some embodiments, subsequent (d), the method further comprises performing a purge operation using a purge gas. In some embodiments, the purge gas comprises argon (Ar), hydrogen (H2), or nitrogen (N2).

[0022] Another aspect of the disclosure provides an apparatus for processing the semiconductor substrate. In some embodiments, the apparatus comprises one or more process chambers. In some embodiments, each process chamber of the one or more process chambers comprises a substrate support. In some embodiments, the apparatus further comprises a vacuum line coupled to the one or more process chambers, a remote plasma source, one or more gas inlets into the one or more process chambers and associated flow-control hardware, and a controller having at least one processor and a memory. In some embodiments, the at least one processor and the memory are communicatively connected with one another. In some embodiments, the at least one processor is at least operatively connected with the flowcontrol hardware. In some embodiments, the memory stores computer-executable instructions for controlling the at least one processor to perform a method comprising: (a) receiving, on the substrate support, the semiconductor substrate with the metal-containing photoresist film disposed on the semiconductor substrate, (b) exposing the semiconductorAttorney Docket No. LAM1P113WO / 12101-1WOsubstrate to the etch conditions comprising the hydrogen-containing species activated by the remote plasma source to remove the portion of the metal-containing photoresist film, and (c) exposing the semiconductor substrate to the oxygen-containing species activated by the remote plasma source

[0023] In some embodiments, the apparatus further comprises a vacuum loadlock. In some embodiments, the vacuum loadlock comprises the remote plasma source.

[0024] In some embodiments, in (b), the hydrogen-containing species activated by the remote plasma source is delivered to an edge of the semiconductor substrate.

[0025] In some embodiments, the apparatus further comprises a deflector disposed between the remote plasma source and the semiconductor substrate.

[0026] In some embodiments, the deflector is configured to deliver a purge gas to a location between the deflector and the semiconductor substrate.

[0027] In some embodiments, at least one of a top surface of the deflector and a surface of walls of each process chamber comprise a coating material configured to reduce hydrogen radical recombination. In some embodiments, the coating material comprises polytetrafluoroethylene (PTFE), quartz, quartz oxide, or silicon dioxide (SiCh).

[0028] In some embodiments, a first process chamber of the one or more process chambers is a deposition chamber. In some embodiments, the method is executed in a second process chamber of the one or more process chambers. In some embodiments, the first process chamber differs from the second process chamber. In some embodiments, the first process chamber and the second process chamber are located on a same platform.

[0029] In some embodiments, the first process chamber of the one or more process chambers is the deposition chamber and the method is executed in the first process chamber.

[0030] In some embodiments, the apparatus further comprises a showerhead. In some embodiments, the showerhead is configured to deliver the hydrogen-containing species to a location on the semiconductor substrate.

[0031] In some embodiments, the apparatus further comprises a nozzle. In some embodiments, the nozzle is configured to deliver the hydrogen-containing species to a location on the semiconductor substrate. In some embodiments, the nozzle is movable. In some embodiments, the nozzle is fixed and the substrate support is rotatable.

[0032] In some embodiments, (b) removes the portion of the metal-containing photoresist film on the edge, the bevel, and the backside of the semiconductor substrate.

[0033] Another aspect of the disclosure is directed to a method of processing the semiconductor substrate. In some embodiments, the method comprises (a) providing, in aAttorney Docket No. LAM1P113WO / 12101-1WOprocess chamber, the semiconductor substrate with the metal-containing photoresist film disposed on the semiconductor substrate, (b) exposing the semiconductor substrate to the etch conditions comprising the hydrogen-containing species activated by the remote plasma source to remove the portion of the metal-containing photoresist film, (c) exposing the semiconductor substrate to the oxygen-containing species activated by the remote plasma source, (d) exposing the semiconductor substrate to the hydrogen-containing plasma to remove the trace metal from the surface of the semiconductor substrate, (e) performing the purge operation using the purge gas, and (f) repeating operations (c)-(e) in the multi-cycle etch process.

[0034] These and other features of the disclosed embodiments will be described in detail below with reference to the associated drawings.BRIEF DESCRIPTION OF DRAWINGS

[0035] Figures 1A-1D depict schematic diagrams of a method of processing a semiconductor substrate comprising a combined dry EBR and backside clean (BSC) (such as the method of Figure 3).

[0036] Figures 2A-2B depict the schematic diagrams of Figures 1C-1D, respectfully, for a multi-cycle etch process of the method of Figure 3.

[0037] Figure 3 depicts a flow chart of a method of processing a semiconductor substrate.

[0038] Figure 4 depicts a configuration of an apparatus for processing a semiconductor substrate.

[0039] Figure 5 depicts another configuration of an apparatus for processing a semiconductor substrate.

[0040] Figure 6 A depicts a schematic diagram of a configuration an apparatus for processing a semiconductor substrate including a deflector, an annular ring, and a pedestal ring.

[0041] Figure 6B depicts a schematic diagram of an exploded view of various components of an apparatus for processing a semiconductor substrate.

[0042] Figure 6C depicts a schematic diagram of the annular ring, the pedestal ring, and an arm baffle of an apparatus for processing a semiconductor substrate.

[0043] Figure 7A-7C depict schematic diagrams of system configurations.

[0044] Figure 8 depicts a schematic diagram of wafer placement sequences of a system.

[0045] Figure 9 depicts a schematic diagram depicting the wafer clamping ring of Figure 7C.

[0046] Figure 10 depicts a schematic illustration of an example process station for maintaining a low-pressure environment that is suitable for performing development, clean, rework, descum, and smoothing operations.Attorney Docket No. LAM1P113WO / 12101-1WO

[0047] Figure 11 depicts a schematic illustration of an example multi-station processing tool suitable for implementation of various development, clean, rework, descum, and smoothing operations.

[0048] Figure 12 shows a cross-sectional schematic view of an example inductively-coupled plasma apparatus for implementing certain embodiments and operations described herein.

[0049] Figure 13 depicts a semiconductor process cluster tool architecture with vacuum-integrated deposition and patterning modules that interface with a vacuum transfer module, suitable for implementations of processes described herein.DETAILED DESCRIPTION

[0050] Reference is made herein in detail to specific embodiments of the disclosure. Examples of the specific embodiments are illustrated in the accompanying drawings. While the disclosure will be described in conjunction with these specific embodiments, it will be understood that it is not intended to limit the disclosure to such specific embodiments. On the contrary, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail so as to not unnecessarily obscure the present disclosure.

[0051] Patterning of thin films in semiconductor processing is often an important step in the fabrication of semiconductors. Patterning involves lithography. In conventional photolithography, such as 193 nm photolithography, patterns are printed by emitting photons from a photon source onto a mask and printing the pattern onto a photosensitive photoresist, thereby causing a chemical reaction in the photoresist that, after development, removes certain portions of the photoresist to form the pattern.

[0052] Advanced technology nodes (as defined by the International Technology Roadmap for Semiconductors) include nodes 22 nm, 16 nm, and beyond. In the 16 nm node, for example, the width of a typical via or line in a Damascene structure is typically no greater than about 30 nm. Scaling of features on advanced semiconductor integrated circuits (ICs) and other devices is driving lithography to improve resolution.

[0053] Extreme ultraviolet (EUV) lithography can extend lithography technology by moving to smaller imaging source wavelengths than would be achievable with conventional photolithography methods. EUV light sources at approximately 10-20 nm, or 11-14 nm wavelength, for example 13.5 nm wavelength, can be used for leading-edge lithography tools,Attorney Docket No. LAM1P113WO / 12101-1WOalso referred to as scanners. The EUV radiation is strongly absorbed in a wide range of solid and fluid materials including quartz and water vapor.

[0054] EUV lithography makes use of EUV resists that are patterned to form masks for use in etching underlying layers. EUV resists may be polymer-based chemically amplified resists (CARs) produced by liquid-based spin-on techniques. An alternative to CARs are directly photopattemable metal oxide-containing films, such as those available from Inpria, Corvallis, OR, and described, for example, in US Patent Publications US 2017 / 0102612, US 2016 / 021660 and US 2016 / 0116839, incorporated by reference herein at least for their disclosure of photopattemable metal oxide-containing films. Such films may be produced by spin-on techniques or dry vapor-deposited. The metal oxide-containing film can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum ambient providing sub-30 nm patterning resolution, for example as described in U.S. Pat. No.9,996,004, issued Jun. 12, 2018 and titled EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS, and / or in Application PCT / US19 / 31618, filed May 9, 2019, and titled METHODS FOR MAKING EUV PATTERNABLE HARD MASKS, the disclosures of which at least relating to the composition, deposition, and patterning of directly photopattemable metal oxide films to form EUV resist masks is incorporated by reference herein. Generally, the patterning involves exposure of the EUV resist with EUV radiation to form a photo pattern in the resist, followed by development to remove a portion of the resist according to the photo pattern to form the mask.

[0055] It should also be understood that the while present disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, it is also applicable to other next generation lithographic techniques. In addition to EUV, which includes the standard 13.5 nm EUV wavelength currently in use and development, the radiation sources most relevant to such lithography are DUV (deep-UV), which generally refers to use of 248 nm or 193 nm excimer laser sources, X-ray, which formally includes EUV at the lower energy range of the X-ray range, as well as e-beam, which can cover a wide energy range. The specific methods may depend on the particular materials and applications used in the semiconductor substrate and ultimate semiconducting device. Thus, the methods described in this application are merely exemplary of the methods and materials that may be used in present technology.

[0056] Directly photopattemable EUV resists may be composed of or contain metals and / or metal oxides mixed within organic components. The metals / metal oxides are highlyAttorney Docket No. LAM1P113WO / 12101-1WOpromising in that they can enhance the EUV photon adsorption and generate secondary electrons and / or show increased etch selectivity to an underlying film stack and device layers. To date, these resists have been developed using a wet (solvent) approach, which requires the wafer to move to the track, where it is exposed to developing solvent, dried and baked. Wet development does not only limit productivity but can also lead to line collapse due to surface tension effects during the evaporation of solvent between fine features.

[0057] Specifically, in photolithography, EBR and edge exclusion width (EEW) refer to the process of removing excess photoresist or anti-reflective coating material from the edges of a wafer, preventing defects and improving yield. EBR refers to a process where excess photoresist material that builds up at the edges of a wafer during the spin coating process is selectively removed using a specialized solvent or cleaning solution, typically applied while the wafer is still spinning, to prevent defects and ensure proper patterning in subsequent lithography steps. This process is crucial for metal-oxide photoresists as their edge bead can cause issues with adhesion and patterning accuracy.

[0058] Typical wafer EBR utilizes an organic solvent or hydrofluoric acid solution to dissolve the metal-oxide photoresists. In some instances, a backside scrub of the wafer may be performed. However, wet EBR processes are expensive. Moreover, for dry metal-oxide photoresist deposition, the wet EBR is an additional process step that utilizes another process tool on a separate platform.

[0059] Backside and / or bevel edge clean of a semiconductor substrate may be non-selectively applied to the metal-containing photoresist film to equally remove film with various levels of oxidation or crosslinking on the substrate backside and bevel edge. During application of the metal-containing photoresist film, either by wet deposition processing or dry deposition processing, there may be some unintended deposition of resist material on the substrate bevel edge and / or backside. The unintended deposition may lead to undesirable particles later moving to a top surface of the semiconductor substrate and becoming particle defects. Moreover, this bevel edge and backside deposition can cause downstream processing problems, including contamination of the patterning (scanner) and development tools. Conventionally, removal of this bevel edge and backside deposition is done by wet cleaning techniques. For spin-coated photoresist material, this process is called edge bead removal (EBR) and is performed by directing a stream of solvent from above and below the bevel edge while the substrate is spinning. The same process can be applied to soluble organotin oxide-based resists deposited by vapor deposition techniques. The substrate bevel edge and / or backside clean may also be a dry clean process.Attorney Docket No. LAM1P113WO / 12101-1WO

[0060] Due to the drawbacks of wet EBR techniques, the instant disclosure provides a method of processing a semiconductor substrate that is a combined dry EBR and backside clean (BSC) process. The dry EBR and backside clean involves exposing a substrate with a metalcontaining photoresist film disposed thereon to a first remote hydrogen plasma. Exposure to the remote hydrogen plasma may be followed by exposure to a remote oxygen plasma. In some implementations, exposure to the remote oxygen plasma may be followed by an overetch step, where the over-etch step includes exposure to a second remote hydrogen plasma.

[0061] The method disclosed herein comprises (a) providing, in the process chamber, the semiconductor substrate with the metal-containing photoresist film disposed on the semiconductor substrate; (b) exposing the semiconductor substrate to the etch conditions comprising the hydrogen-containing species activated by the remote plasma source to remove the portion of the metal-containing photoresist film; (c) exposing the semiconductor substrate to the oxygen-containing species activated by the remote plasma source; (d) exposing the semiconductor substrate to the hydrogen-containing plasma to remove the trace metal from the surface of the semiconductor substrate; (e) performing the purge operation using the purge gas; and (f) repeating the operations (c)-(e) in the multi-cycle etch process. In some implementations, the portion of the metal-containing photoresist film that is removed is on an edge, a bevel, and a backside of the semiconductor substrate.

[0062] The method described herein provides several benefits over conventional processes. For example, in some embodiments, the method disclosed herein can be performed in a vacuum loadlock, a transfer module, or a separate process chamber. In some embodiments, the method disclosed herein can be integrated on the same platform as the metal-oxide photoresist deposition chamber. The method disclosed herein provides an integrated EBR / BSC process that occurs subsequent to deposition of the metal-oxide photoresist on the same platform to simplify the process flow and tool set, instead of performing a wet EBR process on a separated platform. The method disclosed herein provides a cost effective process as compared to wet EBR. Moreover, the method disclosed herein utilizes non-halogen-based chemistry to remove the metal-containing photoresist film, which prevents potential halogen contamination on the metal-containing photoresist film after dry EBR. Additionally, the method disclosed herein utilizes remote plasma without plasma UV, which prevents UV damage to the metal-oxide photoresist film. In some embodiments, the method disclosed herein minimizes hydrogen radical recombination by utilizing a penning ionization method or by incorporating a deflector into the process chamber. In some embodiments where the deflector is incorporated, at least one of a top surface of the deflector and a surface ofAttorney Docket No. LAM1P113WO / 12101-1WOwalls of the process chamber comprise a coating material configured to reduce hydrogen radical recombination. These and other benefits over conventional processes are described herein.

[0063] Figures 1A-1D depict schematic diagrams of a method of processing a semiconductor substrate comprising a combined dry EBR and backside clean (such as the method of Figure 3). The semiconductor substrate comprises a metal-containing photoresist film disposed on the semiconductor substrate. Specifically, Figure 1A depicts a schematic diagram 100 of a semiconductor substrate 110 with a metal-containing photoresist film 120 disposed on the semiconductor substrate 110. In some embodiments, the semiconductor substrate 110 is received in a process chamber, as discussed herein. In some embodiments, the metalcontaining photoresist film 120 is an organo-metal oxide film. In some embodiments, the metal-containing photoresist film 120 is an organo-metal-containing thin film. In some embodiments, the metal-containing photoresist film 120 comprises an organotin oxide. In some embodiments, the metal-containing photoresist film 120 comprises an element, such as tin, hafnium, tellurium, bismuth, indium, antimony, iodine, or germanium.

[0064] In some embodiments, the semiconductor substrate 110 is exposed to the etch conditions 130, resulting in a schematic diagram 140 of Figure IB. In some embodiments, the etch conditions 130 comprise the hydrogen-containing species activated by the remote plasma source, which removes a portion of the metal-containing photoresist film 120. In some embodiments, the etch conditions 130 remove the portion of the metal-containing photoresist film 120 on the edge and the bevel of the semiconductor substrate 110. In some embodiments, the etch conditions 130 remove the portion of the metal-containing photoresist film 120 on the backside of the semiconductor substrate 110. In some embodiments, the etch conditions 130 remove the portion of the metal-containing photoresist film 120 on the edge, the bevel, and the backside of the semiconductor substrate 110.

[0065] In some embodiments, the etch conditions 130 comprise a pressure ranging from about 100 mT to about 500 mT. In some embodiments, the etch conditions 130 comprise a temperature ranging from about 20°C to about 120°C.

[0066] In some embodiments, the etch conditions 130 comprise a carrier gas. In some embodiments, the carrier gas comprises He, Ne, Ar, Xe, N2, and / or CH4. In some embodiments, the carrier gas comprises Ar and a flow rate of Ar ranges from about 2000 seem to about 7000 seem. In some embodiments, the carrier gas comprises N2 and a flow rate of N2 ranging from about 2000 seem to about 7000 seem.Attorney Docket No. LAM1P113WO / 12101-1WO

[0067] In some embodiments, the hydrogen-containing species of the etch conditions 130 comprises H2 or HX, where X is a halogen. In some embodiments, a flow rate of the hydrogen-containing species is between about 2000 seem and about 7000 seem.

[0068] In some embodiments, the hydrogen-containing species of the etch conditions 130 comprises H2 and the etch conditions 130 further comprise an oxygen-containing species such as O2. A concentration of the oxygen-containing species is less than a concentration of the hydrogen-containing species. In some embodiments, a flow rate of Chis between about 1 ppm and about 500 ppm, such as about 100 ppm.

[0069] In some embodiments, and as shown in Figure IB, the etch conditions 130 may leave some residual amount of the metal-containing photoresist film 120 present on the substrate edge, bevel, and backside of the semiconductor substrate 110. In some embodiments, and as shown in Figure IB, the etch conditions 130 may cause deposition of an etch byproduct (not shown) on the semiconductor substrate 110. In some embodiments, subsequent exposure to the etch conditions 130, an amount of a metal from the metal-containing photoresist film 120 present on a surface of the semiconductor substrate 110 is about 5 E10 / cm2.

[0070] In some embodiments, the method may conclude after exposure to the etch conditions 130 at Figure IB to prevent redeposition of etch byproducts, such as tin hydride (SnFE), on the surface of the of the semiconductor substrate 110.

[0071] In some embodiments, the method continues to a schematic diagram 180 of Figure 1C. Specifically, the semiconductor substrate 110 of Figure IB is exposed to an oxygencontaining species 160 activated by the remote plasma source. In some embodiments, the oxygen-containing species 160 comprises O2, O3, CO, CO2, NO, and / or NO2. In some embodiments, the oxygen-containing species 160 removes the etch byproduct located on the surface of the semiconductor substrate 110. In some embodiments, the oxygen-containing species 160 oxidizes at least some of the metal from the metal-containing photoresist film 120 present on the surface of the semiconductor substrate 110.

[0072] As shown in Figure 1C, trace metal or metal oxide 150 may be located on surface of the semiconductor substrate 110. In some embodiments, the semiconductor substrate 110 of Figure 1C is exposed to hydrogen-containing plasma 170 to remove the trace metal or metal oxide 150 from the surface of the semiconductor substrate 110, resulting in a schematic diagram 190 of Figure ID. In some embodiments, the hydrogen-containing plasma 170 is a remote hydrogen-containing plasma. In the schematic diagram 190 of Figure ID, the metalcontaining photoresist film 120, and any trace metal or metal oxide 150, is removed from the substrate edge, bevel, and backside of the semiconductor substrate 110. In someAttorney Docket No. LAM1P113WO / 12101-1WOembodiments, the semiconductor substrate 110 of Figure ID may be exposed to the purge gas, such as Ar, H2, and / or N2.

[0073] Figures 2A-2B depict the schematic diagrams of Figures 1C-1D, respectfully, for a multi-cycle etch process of the method of Figure 3. In some embodiments, the semiconductor substrate 110 is exposed to the oxygen-containing species 160 activated by the remote plasma source (Figure 2A), the hydrogen-containing plasma 170 (Figure 2B), and the purge gas in a multi-cycle etch process such that exposure to the oxygen-containing species 160 activated by the remote plasma source (Figure 2A), the hydrogen-containing plasma 170 (Figure 2B), and the purge gas is repeated for a frequency of at least “X” cycles. In some embodiments, the semiconductor substrate 110 is exposed to the oxygen-containing species 160 activated by the remote plasma source (Figure 2A), the hydrogen-containing plasma 170 (Figure 2B), and the purge gas in the multi-cycle etch process, which is repeated for a frequency of at least two cycles. In some embodiments, the semiconductor substrate 110 is exposed to the oxygencontaining species 160 activated by the remote plasma source (Figure 2A), the hydrogencontaining plasma 170 (Figure 2B), and the purge gas in the multi-cycle etch process, which is repeated for the frequency of three cycles. In some embodiments, subsequent the multicycle etch process, an amount of the metal from the metal-containing photoresist film 120 present on the surface of the semiconductor substrate 110 is about less than 1 E10 / cm2. Method

[0074] Figure 3 depicts a flow chart 300 of a method of processing a semiconductor substrate.

[0075] The method of Figure 3 begins with an operation 310 that comprises providing, in the process chamber, the semiconductor substrate with the metal-containing photoresist film disposed on the semiconductor substrate. In some embodiments, the metal-containing photoresist film is an organo-metal oxide film. In some embodiments, the metal-containing photoresist film is an organo-metal-containing thin film. In some embodiments, the metalcontaining photoresist film comprises an organotin oxide. In some embodiments, the metalcontaining photoresist film comprises an element, such as tin, hafnium, tellurium, bismuth, indium, antimony, iodine, or germanium. In addition to being deposited on a frontside of the semiconductor substrate, the metal-containing photoresist film may be deposited on an edge, bevel, and backside of semiconductor substrate.

[0076] In some embodiments in the method of Figure 3, an operation 320 follows the operation 310. In some embodiments, the operation 320 comprises exposing the semiconductor substrate to the etch conditions comprising the hydrogen-containing species activated by the remote plasma source to remove the portion of the metal-containingAttorney Docket No. LAM1P113WO / 12101-1WOphotoresist film. In some embodiments, the operation 320 removes the portion of the metalcontaining photoresist film on the edge, the bevel, and the backside of the semiconductor substrate. The exposure to the hydrogen-containing species activated by the remote plasma source to remove the portion of the metal-containing photoresist film provides a dry EBR process that avoids the use of any aqueous solution, organic solvents, or other corrosive chemistries like hydrogen fluoride which would necessitate a post-EBR deionized water clean. Use of non-halogen-based chemistry to remove the metal-containing photoresist film prevents potential halogen contamination on the metal-containing photoresist film after dry EBR. Additionally, the method disclosed herein utilizes remote plasma without plasma UV, which prevents UV damage to the metal-containing photoresist film.

[0077] In some embodiments, the etch conditions of the operation 320 comprise a pressure ranging from about 100 mT to about 500 mT. In some embodiments, the etch conditions of the operation 320 comprise a temperature ranging from about 20°C to about 120°C.

[0078] In some embodiments, the etch conditions of the operation 320 comprise a carrier gas. In some embodiments, the carrier gas comprises He, Ne, Ar, Xe, N2, and / or CH4. In some embodiments, the carrier gas comprises Ar and a flow rate of Ar ranges from about 2000 seem to about 7000 seem. In some embodiments, the carrier gas comprises N2 and wherein a flow rate of N2 ranging from about 2000 seem to about 7000 seem.

[0079] In some embodiments, the hydrogen-containing species of the operation 320 comprises H2 or HX, where X is a halogen. In some embodiments, the hydrogen-containing species of the operation 320 comprises H2. In some embodiments, a flow rate of the hydrogencontaining species is between about 2000 seem and about 7000 seem.

[0080] In some embodiments, the hydrogen-containing species of the operation 320 comprises H2 and the etch conditions of the operation 320 comprise an oxygen-containing species such as O2. Here, the oxygen-containing species may be co-flowed simultaneously with the hydrogen-containing species. The flow rate of the oxygen-containing species may be less than the flow rate of the hydrogen-containing species. In some embodiments, the oxygen-containing species is also activated by the remote plasma source. In some embodiments, a flow rate of O2 is between about 1 ppm and about 500 ppm, such as about 100 ppm.

[0081] In some embodiments, the etch conditions of the operation 320 cause deposition of an etch byproduct on the semiconductor substrate. For example, the etch byproduct may be a polymer etch byproduct. In some embodiments, subsequent the operation 320, an amount ofAttorney Docket No. LAM1P113WO / 12101-1WOa metal from the metal-containing photoresist film present on a surface of the semiconductor substrate is about 5 E10 / cm2.

[0082] In some embodiments in the method of Figure 3, an operation 330 follows the operation 320. In some embodiments, the operation 330 comprises exposing the semiconductor substrate to the oxygen-containing species activated by the remote plasma source. In some embodiments, the oxygen-containing species comprises O2, O3, CO, CO2, NO, and / or NO2. In some embodiments, the oxygen-containing species in the operation 330 removes the etch byproduct deposited in the operation 320. In some embodiments, the oxygen-containing species in the operation 330 oxidizes the trace metal from the metalcontaining photoresist film present on the surface of the semiconductor substrate.

[0083] In some embodiments, the operation 330 concludes the method of Figure 3.

[0084] In some embodiments, the method of Figure 3 further comprises an optional operation 340, which follows the operation 330. In some embodiments, the optional operation 340 comprises exposing the semiconductor substrate to the hydrogen-containing plasma to remove the trace metal or metal oxide from the surface of the semiconductor substrate. In some embodiments, the hydrogen-containing plasma may be a remote hydrogen-containing plasma. The hydrogen-containing plasma may remove any residual metal-containing photoresist film on the edge, bevel, and backside of the semiconductor substrate as well as the trace metal or metal oxide from the edge, bevel, and backside of the semiconductor substrate.

[0085] In some embodiments, an optional operation 350 follows the optional operation 340. In some embodiments, the optional operation 350 comprises performing a purge operation using the purge gas. In some embodiments, the purge gas comprises Ar, H2, and / or N2.

[0086] In some embodiments, an optional operation 360 follows the optional operation 350. In some embodiments, the optional operation 360 comprises repeating the operation 330, the optional operation 340, and the optional operation 350 in a multi-cycle etch process. In some embodiments, the optional operation 360 comprises repeating the operation 330 and the optional operation 340 in a multi-cycle etch process. In some embodiments, the multi-cycle etch process of the optional operation 360 is repeated for a frequency of at least two cycles. In some embodiments, subsequent the multi-cycle etch process, the amount of the metal from the metal-containing photoresist film present on the surface of the semiconductor substrate is about less than 1 E10 / cm2. In some embodiments, subsequent the optional operation 360, the method of Figure 3 concludes.Attorney Docket No. LAM1P113WO / 12101-1WO

[0087] It should be appreciated that in one or more systems disclosed herein, the method of Figure 3 may be performed in a vacuum load lock, a transfer module, or a separate process chamber. In some embodiments, the method of Figure 3 disclosed herein can be integrated on the same platform as the metal-oxide photoresist deposition chamber. In some embodiments, the method disclosed herein provides an integrated EBR / BSC process that occurs subsequent deposition of the metal-oxide photoresist on the same platform to simplify the process flow and tool set, instead of performing a wet EBR process on a separated platform or tool.

[0088] It some embodiments, a first process chamber of the one or more process chambers is a deposition chamber and the method of Figure 3 is executed in a second process chamber of the one or more process chambers. In some embodiments, the first process chamber differs from the second process chamber. In some embodiments, the first process chamber and the second process chamber are located on a same platform.

[0089] In some embodiments, the first process chamber of the one or more process chambers is a deposition chamber, and the method of Figure 3 is executed in the first process chamber.Apparatus and System

[0090] Figure 4 depicts a configuration of an apparatus 400 for processing a semiconductor substrate. In some embodiments, the apparatus 400 of Figure 4 may comprise one or more process chambers, such as two, three, four, or six proves chambers. A single process chamber 480 is shown in Figure 4. The process chamber 480 comprises a substrate support or a pedestal 460 configured to receive a wafer or a semiconductor substrate 450 thereon. The apparatus 400 of Figure 4 may comprise a vacuum line coupled to the process chamber 480 and a remote plasma source 420. The apparatus 400 of Figure 4 may comprise one or more gas inlets 410, 470 into the process chamber 480 and associated flow-control hardware. The gas inlet 410 may provide remote plasma source gases 430 into the process chamber 480. In some embodiments, the remote plasma source gases 430 comprise Ar, FE, O2, CH4, and / or He. In one example, the remote plasma source gases 430 comprise at least H2. In another example, the remote plasma source gases 430 comprise at least H2 and He. In yet another example, the remote plasma source gases 430 comprise at least H2 and Ar. In still yet another example, the remote plasma source gases 430 comprise at least He. The gas inlet 470 may provide inert purge gases (such as Ar and / or N2) into the process chamber 480. In some embodiments, the remote plasma source gases 430 comprise Ar, H2, CH4, and / or O2 and the purge gases comprise Ar and / or N2. In some embodiments, the remote plasma source gases 430 comprise Ar, H2, He, and / or O2 and the purge gases comprise Ar and / or N2. In someAttorney Docket No. LAM1P113WO / 12101-1WOembodiments, the remote plasma source gases 430 comprise He and the purge gases comprise H2, CH4, and / or O2.

[0091] The apparatus 400 may also comprise a deflector 440. As depicted, in some embodiments, the deflector 440 may be disposed between the remote plasma source 420 and the wafer or the semiconductor substrate 450. In some embodiments, the deflector 440 is configured to distribute the purge gas (from the gas inlet 470) to a location between the deflector 440 and the wafer or the semiconductor substrate 450.

[0092] The apparatus 400 of Figure 4 also comprises a controller (not shown) having at least one processor (not shown) and a memory (not shown). In some embodiments, the at least one processor and the memory are communicatively connected with one another. In some embodiments, the at least one processor is at least operatively connected with the flow-control hardware. In some embodiments, the memory stores computer-executable instructions for controlling the at least one processor to perform the method of Figure 3.

[0093] Plasma-based strip technologies typically use radical species to remove a photoresist layer. Substrate processing systems may use capacitively coupled plasma (CCP) or inductively coupled plasma (ICP) to generate radicals directly above the substrate. CCP and ICP processes are typically used for in-situ photoresist strip after performing a plasma etch process. Advantages of these processes include stripping without a vacuum break and a relatively high removal rate. However, ions or vacuum ultraviolet (VUV) photons generated by the direct plasma may damage underlying layers and cause measurable substrate loss in areas exposed to the direct plasma.

[0094] It should be appreciated that hydrogen-containing radicals are generated in the remote plasma source 420 and are delivered to only the edge of the wafer or the semiconductor substrate 450 where the frontside of the wafer or the semiconductor substrate 450 is protected by the deflector 440 above the wafer or the semiconductor substrate 450 while the inert purge gases are delivered through the center of the deflector 440 to a location between the deflector 440 and the wafer or the semiconductor substrate 450.

[0095] In some embodiments, the hydrogen-containing radicals are generated by using a penning ionization method. Penning ionization refers to the ionization of an atom through the transfer of excitation energy from a metastable atom with higher excitation energy than the ionization energy of the atom being ionized. Specifically, penning ionization refers to the interaction between: an electronically excited gas-phase atom G* and a target molecule M. The collision results in the ionization of the molecule yielding a cation M+, an electron e“,Attorney Docket No. LAM1P113WO / 12101-1WOand a neutral gas molecule, G, in the ground state, as shown:G* + M MT* + e“ + G

[0096] In some embodiments, metastable atoms that are produced exit the remote plasma source 420 through showerhead(s) (not shown). The showerhead(s) filter most if not all energetic damage-producing ions and VUV and / or UV light. The metastable atoms are then mixed with a secondary gas (such as O2) injected under or between the showerhead(s) and the pedestal 460. The gas species can be excited through penning ionization. It is beneficial for certain process to generate molecular radical species to increase strip or etch selectivity.

[0097] In some embodiments, the apparatus 400 of Figure 4 may comprise a nozzle to deliver the hydrogen-containing species to a location on the wafer or the semiconductor substrate 450. In some embodiments, the nozzle is movable. In some embodiments, the nozzle is fixed and the substrate support is rotatable.

[0098] In some embodiments, helium metastable is generated in the remote plasma source 420 and is delivered to the edge of the wafer or the semiconductor substrate 450 where hydrogen (and optionally methane) gas is delivered from the deflector 440 on the frontside of the center of the wafer or the semiconductor substrate 450. In some embodiments, hydrogen radicals are generated only around the bevel regime of the wafer or the semiconductor substrate 450 by the penning ionization method, which hydrogen dissociation is formed due to excitation energy transferred from the helium metastable to hydrogen. In some embodiments, the EBR rate is improved because the efficiency of the hydrogen radical transport is more effective than when the hydrogen radical is delivered from the remote plasma source 420.

[0099] It should be appreciated that use of the deflector 440 or penning ionization are used to minimize or reduce hydrogen radical recombination.

[0100] Figure 5 depicts another configuration of an apparatus 500 for processing a semiconductor substrate. Similar to Figure 4, in some embodiments, the apparatus 500 of Figure 5 may comprise one or more process chambers. A single process chamber 580 is shown in Figure 5. The process chamber 580 comprises a substrate support or a pedestal configured to receive a wafer or a semiconductor substrate 540 thereon. The apparatus 500 may comprise a vacuum line coupled to the process chamber 580 and a remote plasma source 510. As noted in Figure 4, the hydrogen-containing radicals 520 are generated in the remote plasma source 510. In some embodiments, the hydrogen-containing radicals may be accompanied by other gases, such as CH4, He, Ar, and / or O2.Attorney Docket No. LAM1P113WO / 12101-1WO

[0101] The apparatus 500 may comprise one or more gas inlets into the process chamber 580 and associated flow-control hardware. The one or more gas inlets may provide remote plasma source gases and the inert purge gases into the process chamber 580. Gas inlet 585 provides the inert purge gases into the process chamber 580. The apparatus 500 may also comprise a deflector 550. As depicted, in some embodiments, the deflector 550 may be disposed between the remote plasma source 510 and the wafer or the semiconductor substrate 540. In some embodiments, the deflector 550 is configured to distribute the purge gas to a location between the deflector 550 and the wafer or the semiconductor substrate 540.

[0102] In some embodiments, the deflector 550 may be heated for etch rate enhancement. In some embodiments, the deflector 550 may be heated to a temperature of about 120°C or higher. In some embodiments where the process is run at a temperature ranging from about 30°C to about 50°C, the deflector 550 is not heated. In some embodiments, at least one of a top surface of the deflector 550 and a surface of walls of the process chamber 580 comprises a coating material 570 configured to reduce hydrogen radical recombination. In some embodiments, the coating material is polytetrafluoroethylene (PTFE), quartz, quartz oxide, and / or silicon dioxide (SiCh). The apparatus 500 also comprises a controller (not shown) having at least one processor (not shown) and a memory (not shown). In some embodiments, the at least one processor and the memory are communicatively connected with one another. In some embodiments, the at least one processor is at least operatively connected with the flow-control hardware. In some embodiments, the memory stores computer-executable instructions for controlling the at least one processor to perform the method of Figure 3. The apparatus 500 also depicts a pumping port 560 that may be used to pump gases out of the process chamber 580.

[0103] It should be appreciated that EBR edge exclusion is tunable by adjusting hardware settings and / or process conditions. In some embodiments, the EBR edge exclusion is tunable by adjusting the hardware settings, such as a size of the deflector 550, a size of a radical gap 530 (where a width of the radical gap 530 and flow rates of the gases affects intrusion), and a width of the gap between the deflector 550 and a frontside of the wafer or the semiconductor substrate 540. In some embodiments, the EBR edge exclusion is tunable by adjusting one or more process conditions, such as pressure, radical / purge gas flow, etc.

[0104] Figure 6A depicts a schematic diagram of a configuration an apparatus 600 for processing a semiconductor substrate including a deflector 620, an annular ring 650, and a pedestal ring 630, according to some embodiments disclosed herein. As shown in Figure 6A, the apparatus 600 further comprises a top lid 610 and a bottom shelf 640. Remote plasmaAttorney Docket No. LAM1P113WO / 12101-1WOsource gases are received at 670. Figure 6A also depicts a location of frontside purge gases 660.

[0105] Figure 6B depicts a schematic diagram of an exploded view of various components of an apparatus for processing the semiconductor substrate. Specifically, Figure 6B depicts a loadlock chamber that is configured to receive a pedestal 615. An end effector 635 may be received by the pedestal 615. A wafer position 680 is also depicted. Figure 6B also depicts a heated deflector 625, which comprises a heater AC power 675 and a purge gas supply 685. Figure 6B also depicts a shield 665 (such as a quartz shield). A loadlock lid 655 is configured to engage the loadlock chamber. In some embodiments, the loadlock lid 655 may receive a wafer cooled adapter plate 645, which may comprise a spool piece 690 disposed thereon. In some embodiments, the spool piece 690 may comprise a quartz spool piece.

[0106] Figure 6C depicts a schematic diagram of an annular ring 650, a pedestal ring 630, and an arm baffle 695 of the apparatus for processing the semiconductor substrate. Since the processing chamber of the apparatus includes dead volume, to isolate the wafer or the semiconductor substrate from an outer chamber area, the annular ring 650, the pedestal ring 630, and the arm baffle 695 may be used. Hydrogen radicals want to recombine to molecular hydrogen. Since hydrogen is diffusive, if hydrogen radicals move to the outer part of the processing chamber and recombine, they want to diffuse back to the wafer or the semiconductor substrate and dilute the hydrogen radicals that are being used for etching. Using the annular ring 650, the pedestal ring 630, and the arm baffle 695 to create an isolation between the wafer area and the outer chamber mitigates or reduces the diffusion of molecular hydrogen back to the wafer or the semiconductor substrate.

[0107] Figure 7A-7C depict schematic diagrams of system configurations. As shown in Figure 7A, a system 700 comprises a wafer or a substrate 750 disposed on a pedestal 740. In some embodiments, the pedestal 740 is heated. As shown in Figure 7A, process gases 730 are directed in the top slit around the bevel edge of the wafer or the substrate 750. Plasma 710 may be directed towards the wafer or the substrate 750, as shown, e.g., around the bevel edge of the wafer or the substrate 750. Purge gases 720, such as N2, may be directed towards the wafer or the substrate 750 from a top showerhead 790.

[0108] As shown in Figure 7B, a system 705 comprises a showerhead 770 and a heater 760. The heater 760 is located proximate the showerhead 770. The wafer or the substrate 750 is disposed on a wafer ring, such as the wafer rings disclosed herein. As shown, the process gases 730 are received from the showerhead 770. As shown, the plasma 710 is directed onAttorney Docket No. LAM1P113WO / 12101-1WOthe wafer or the substrate 750 backside and bevel. In some embodiments, the purge gases 720 are directed towards the wafer or the substrate 750 from a top showerhead.

[0109] As shown in Figure 7C, a system 715 depicts the heater 760, the top showerhead 790, and a bottom showerhead 770. The heater 760 is located proximate the top showerhead 790. The wafer or the substrate 750 is disposed on a wafer ring 780, such as the wafer rings disclosed herein. In some embodiments, the process gases 730 are directed towards the wafer or the substrate 750 from the bottom showerhead 770. As shown, the plasma 710 is directed towards the wafer or the substrate 750 backside and bevel. In some embodiments, the purge gases 720 are directed from the top showerhead 790 towards the wafer or the substrate 750. In some embodiments, the top showerhead 790 may be configured to deliver the hydrogencontaining species to a location on the wafer or the substrate 750. In some embodiments, the bottom showerhead 770 may be configured to deliver the hydrogen-containing species to a location on the wafer or the substrate 750.

[0110] Figures 8A-8J depict schematic diagrams of a wafer placement sequence of a system. In each of Figures 8 A- 8 J, a chamber top and a chamber bottom are depicted. The wafer placement sequence occurs sequentially from Figures 8 A- 8 J. As shown in Figure 8 A, the arm paddle is extended. As shown in Figure 8B, the lift pin is up. As shown in Figure 8C, the arm paddle is retracted. As shown in Figure 8D, the lift pin is down. Figure 8E depicts the process position. Figure 8F shows the wafer placement sequency of Figure 7B. As shown in Figure 8G, the lift pin is up. As shown in Figure 8H, the arm paddle is extended. As shown in Figure 81, the lift pin is down. As shown in Figure 8J, the arm paddle is retracted.

[0111] Figure 9 depicts a schematic diagram 900 depicting the wafer clamping ring or the wafer ring 780 of Figure 7C. As shown in Figure 9, the assembly comprises a wafer clamp ring (WCR) 905 configured to receive a wafer 945. The assembly further comprises bearing housing and facilities plate 935, WCR air cylinder 920, actuation shafts and bearings 930, WCR bellows 940, an upper plate and WCR support rods 950, an upper electrode (ground) 960, a showerhead / lower electrode assembly 970, a pin lifter assembly 980, a gap drive assembly 910, a chamber and pumping system 990, and upper plate and support rods 925. A gap 915 between the wafer backside to the showerhead is between about 5 mm to about 30 mm. The gap 915 between the wafer backside to the showerhead is between about 10 mm to about 20 mm.

[0112] Figure 10 depicts a schematic illustration of an example process station 1000 for maintaining a low-pressure environment that is suitable for performing development, clean, rework, descum, and smoothing operations according to some embodiments. The exampleAttorney Docket No. LAM1P113WO / 12101-1WOprocess station 1000 of Figure 10 includes a process chamber body 1002 for maintaining a low-pressure environment that is suitable for embodiment of described dry development, clean, rework, descum and smoothing embodiments. A plurality of process stations 1000 may be included in a common low-pressure process tool environment. For example, Figure 11 depicts an embodiment of a multi-station processing tool 1100, such as a VECTOR® processing tool available from Lam Research Corporation, Fremont, CA. In some embodiments, one or more hardware parameters of the example process station 1000 including those discussed in detail below may be adjusted programmatically by one or more computer controllers 1150.

[0113] The example process station 1000 may be configured as a module in a cluster tool. Figure 13 depicts a semiconductor process cluster tool architecture with vacuum-integrated deposition and patterning modules that interface with a vacuum transfer module, suitable for implementations of processes described herein. Such a cluster process tool architecture can include resist deposition, resist exposure (EUV scanner), resist development and etch modules, as described above and further below with reference to Figures 12 and 13.

[0114] In some embodiments, certain of the processing functions can be performed consecutively in the same module, for example dry development and etch. Embodiments of this disclosure are directed to methods and apparatus for (a) providing, in a process chamber, a semiconductor substrate with a metal-containing photoresist film disposed on a substrate layer of the semiconductor substrate; (b) exposing the semiconductor substrate to etch conditions comprising a hydrogen-containing species activated by a remote plasma source to remove a portion of the metal-containing photoresist film; and (c) exposing the semiconductor substrate to an oxygen-containing species activated by the remote plasma source.

[0115] Returning to Figure 10, the example process station 1000 fluidly communicates with a reactant delivery system 1001 for delivering process gases to a distribution showerhead 1006. The reactant delivery system 1001 optionally includes a mixing vessel 1004 for blending and / or conditioning process gases, for delivery to showerhead 1006. One or more mixing vessel inlet valves 1020 may control introduction of process gases to the mixing vessel 1004. One or more valves 1005 may control introduction of the process gases to the process chamber body 1002. Where plasma exposure is used, plasma 1007 may also be delivered to the showerhead 1006 or may be generated in the example process station 1000. As noted above, in at least some embodiments, non-plasma thermal exposure is favored.Attorney Docket No. LAM1P113WO / 12101-1WO

[0116] Figure 10 also includes an optional vaporization point 1003 for vaporizing liquid reactant to be supplied to the mixing vessel 1004. In some embodiments, a liquid flow controller (LFC) upstream of the optional vaporization point 1003 may be provided for controlling a mass flow of liquid for vaporization and delivery to the example process station 1000. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. A plunger valve of the LFC may then be adjusted responsive to feedback control signals provided by a proportional-integral-derivative (FED) controller in electrical communication with the MFM.

[0117] The showerhead 1006 distributes process gases toward a substrate 1012. In the embodiment shown in Figure 10, the substrate 1012 is located beneath showerhead 1006 and is shown resting on a pedestal 1008. The showerhead 1006 may have any suitable shape, and may have any suitable number and arrangement of ports for distributing process gases to the substrate 1012.

[0118] In some embodiments, the pedestal 1008 may be raised or lowered to expose the substrate 1012 to a volume between the substrate 1012 and the showerhead 1006. It will be appreciated that, in some embodiments, pedestal height may be adjusted programmatically by a suitable computer controller (e.g., a computer controller 1150 of Figure 11). In some embodiments, the showerhead 1006 may have multiple plenum volumes with multiple temperature controls.

[0119] In some embodiments, the pedestal 1008 may be temperature controlled via a heater 1010. In some embodiments, the pedestal 1008 may be heated to a temperature of greater than 0°C and up to 300°C or more, for example 50°C to 120°C, such as about 65°C to 80°C, during non-plasma thermal exposure of a photopattemed resist to hydrogen halide dry development chemistry, such as HBr or HC1, as described in disclosed embodiments. In some embodiments, the heater 1010 of the pedestal 1008 may include a plurality of independently controllable temperature control zones.

[0120] Further, in some embodiments, pressure control for the example process station 1000 may be provided by a butterfly valve 1018. As shown in the embodiment of Figure 10, the butterfly valve 1018 throttles a vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, pressure control of the example process station 1000 may also be adjusted by varying a flow rate of one or more gases introduced to the example process station 1000.

[0121] In some embodiments, a position of showerhead 1006 may be adjusted relative to the pedestal 1008 to vary a volume between the substrate 1012 and the showerhead 1006. Further,Attorney Docket No. LAM1P113WO / 12101-1WOit will be appreciated that a vertical position of pedestal 1008 and / or the showerhead 1006 may be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 1008 may include a rotational axis for rotating an orientation of the substrate 1012. It will be appreciated that, in some embodiments, one or more of these example adjustments may be performed programmatically by one or more suitable computer controllers (e.g., the computer controller 1150 of Figure 11).

[0122] Where the plasma 1007 may be used, for example in gentle plasma-based dry development embodiments and / or etch operations conducted in the same chamber, the showerhead 1006 and the pedestal 1008 electrically communicate with a radio frequency (RF) power supply 1014 and matching network 1016 for powering the plasma 1007. In some embodiments, the plasma energy may be controlled by controlling one or more of a process station pressure, a gas concentration, an RF source power, an RF source frequency, and a plasma power pulse timing. For example, the RF power supply 1014 and the matching network 1016 may be operated at any suitable power to form the plasma having a desired composition of radical species. Examples of suitable powers are up to about 500W.

[0123] In some embodiments, instructions for the computer controller 1150 may be provided via input / output control (IOC) sequencing instructions. In one example, the instructions for setting conditions for a process phase may be included in a corresponding recipe phase of a process recipe. In some cases, process recipe phases may be sequentially arranged, so that all instructions for a process phase are executed concurrently with that process phase. In some embodiments, instructions for setting one or more reactor parameters may be included in a recipe phase. For example, a recipe phase may include instructions for setting a flow rate of a dry development chemistry reactant gas, such as HBr or HC1, and time delay instructions for the recipe phase. In some embodiments, the computer controller 1150 may include any of the features described below with reference to Figure 11.

[0124] Figure 11 depicts a schematic illustration of an example multi-station processing tool 1100 suitable for implementation of various development, clean, rework, descum, and smoothing operations described herein. As shown in Figure 11, the multi-station processing tool 1100 comprises an inbound loadlock 1102 and an outbound loadlock 1104, either or both of which may include a remote plasma source. A robot 1106 at atmospheric pressure is configured to move wafers from a cassette loaded through a pod 1108 into the inbound loadlock 1102 via an atmospheric port 1110. A wafer is placed by the robot 1106 on a pedestal 1112 in the inbound loadlock 1102, the atmospheric port 1110 is closed, and the loadlock is pumped down. Where the inbound loadlock 1102 includes a remote plasma source, the waferAttorney Docket No. LAM1P113WO / 12101-1WOmay be exposed to a remote plasma treatment to treat the silicon nitride surface in the loadlock prior to being introduced into a processing chamber 1114. Further, the wafer also may be heated in the inbound loadlock 1102 as well, for example, to remove moisture and adsorbed gases. Next, a chamber transport port 1116 to processing chamber 1114 is opened, and another robot (not shown) places the wafer into the reactor on a pedestal of a first station shown in the reactor for processing. While the embodiment depicted in Figure 11 includes loadlocks, it will be appreciated that, in some embodiments, direct entry of the wafer into a process station may be provided. In some embodiments, the loadlocks may comprise the remote plasma source.

[0125] The depicted processing chamber 1114 includes four process stations, numbered from 1 to 4 in the embodiment shown in Figure 11. Each station has a heated pedestal (shown at 1118 for station 1), and gas line inlets. It will be appreciated that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, a process station may be switchable between dry development and etch process modes. Additionally or alternatively, in some embodiments, the processing chamber 1114 may include one or more matched pairs of dry development and etch process stations. While the depicted processing chamber 1114 includes four stations, it will be understood that a processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, a processing chamber may have five or more stations, while in other embodiments a processing chamber may have three or fewer stations.

[0126] Figure 11 depicts an embodiment of a wafer handling system 1190 for transferring wafers within processing chamber 1114. In some embodiments, wafer handling system 1190 may transfer wafers between various process stations and / or between a process station and a loadlock. It will be appreciated that any suitable wafer handling system may be employed. Non-limiting examples include wafer carousels and wafer handling robots. Figure 11 also depicts an embodiment of a system controller 1150 employed to control process conditions and hardware states of the multi-station processing tool 1100. The system controller 1150 may include one or more memory devices 1156, one or more mass storage devices 1154, and one or more processors 1152. Each of the one or more processors 1352 may include a CPU or computer, analog, and / or digital input / output connections, stepper motor controller boards, etc.

[0127] In some embodiments, the system controller 1150 controls all of the activities of the multi-station processing tool 1100. The system controller 1350 executes system control software 1158 stored in mass storage device 1154, loaded into memory device 1156, andAttorney Docket No. LAM1P113WO / 12101-1WOexecuted on the one or more processors 1152. Alternatively, the control logic may be hard coded in the controller 1350. Applications Specific Integrated Circuits, Programmable Logic Devices (e.g., field-programmable gate arrays, or FPGAs) and the like may be used for these purposes. In the following discussion, wherever “software” or “code” is used, functionally comparable hard coded logic may be used in its place. The system control software 1158 may include instructions for controlling the timing, mixture of gases, gas flow rates, chamber and / or station pressure, chamber and / or station temperature, wafer temperature, target power levels, RF power levels, substrate pedestal, chuck and / or susceptor position, and other parameters of a particular process performed by the multi-station processing tool 1100. The system control software 1158 may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operation of the process tool components used to carry out various process tool processes. The system control software 1258 may be coded in any suitable computer readable programming language.

[0128] In some embodiments, the system control software 1158 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored on the mass storage device 1154 and / or the memory device 1156 associated with the system controller 1150 may be employed in some embodiments. Examples of programs or sections of programs for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0129] A substrate positioning program may include program code for process tool components that are used to load the substrate onto the pedestal 1118 and to control the spacing between the substrate and other parts of the multi-station processing tool 1100.

[0130] A process gas control program may include code for controlling gas composition and flow rates and optionally for flowing gas into one or more process stations prior to deposition in order to stabilize the pressure in the process station. A pressure control program may include code for controlling the pressure in the process station by regulating, for example, a throttle valve in the exhaust system of the process station, a gas flow into the process station, etc.

[0131] A heater control program may include code for controlling the current to a heating unit that is used to heat the substrate. Alternatively, the heater control program may control delivery of a heat transfer gas (such as helium) to the substrate.Attorney Docket No. LAM1P113WO / 12101-1WO

[0132] A plasma control program may include code for setting RF power levels applied to the process electrodes in one or more process stations in accordance with the embodiments herein.

[0133] A pressure control program may include code for maintaining the pressure in the reaction chamber in accordance with the embodiments herein.

[0134] In some embodiments, there may be a user interface associated with the system controller 1150. The user interface may include a display screen, graphical software displays of the apparatus and / or process conditions, and user input devices such as pointing devices, keyboards, touch screens, microphones, etc.

[0135] In some embodiments, parameters adjusted by the system controller 1150 may relate to process conditions. Non-limiting examples include process gas composition and flow rates, temperature, pressure, plasma conditions (such as RF bias power levels), etc. These parameters may be provided to the user in the form of a recipe, which may be entered utilizing the user interface.

[0136] Signals for monitoring the process may be provided by analog and / or digital input connections of the system controller 1150 from various process tool sensors. The signals for controlling the process may be output on the analog and digital output connections of the multi-station processing tool 1100. Non-limiting examples of process tool sensors that may be monitored include mass flow controllers, pressure sensors (such as manometers), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with data from these sensors to maintain process conditions.

[0137] The system controller 1150 may provide program instructions for implementing the above-described deposition processes. The program instructions may control a variety of process parameters, such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate development and / or etch processes according to various embodiments described herein

[0138] The system controller 1150 will typically include one or more memory devices and one or more processors configured to execute the instructions so that the apparatus will perform a method in accordance with disclosed embodiments. Machine -readable media containing instructions for controlling process operations in accordance with disclosed embodiments may be coupled to the system controller 1150.

[0139] In some embodiments, the system controller 1150 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platformsAttorney Docket No. LAM1P113WO / 12101-1WOfor processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be referred to as the “controller,” winch may control various components or subparts of the system or systems. The system controller 1150, depending on the processing conditions and / or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow' rate settings, fluid delivery' settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or loadlocks connected to or interfaced with a specific system.

[0140] Broadly speaking, the system controller 1150 may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the system controller 1150 in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0141] The system controller 1150, in some embodiments, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the system controller 1150 may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remoteAttorney Docket No. LAM1P113WO / 12101-1WOcomputer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 1150 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the system controller 1150 is configured to interface with or control. Thus as described above, the system controller 1150 may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber

[0142] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a development chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0143] As noted above, depending on the process step or steps to be performed by the tool, the system controller 1150 might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0144] Inductively coupled plasma (ICP) reactors which, in certain embodiments, may be suitable for etch operations suitable for implementation of some embodiments, are now described. Although ICP reactors are described herein, in some embodiments, it should be understood that capacitively coupled plasma reactors may also be used.

[0145] Figure 12 shows a cross-sectional schematic view of an example inductively-coupled plasma apparatus 1200 for implementing certain embodiments and operations describedAttorney Docket No. LAM1P113WO / 12101-1WOherein, such as dry development and / or etch, an example of which is a Kiyo® reactor, produced by Lam Research Corp, of Fremont, CA. In other embodiments, other tools or tool types having the functionality to conduct the dry development and / or etch processes described herein may be used for implementation.

[0146] The inductively coupled plasma apparatus 1200 includes an overall process chamber structurally defined by chamber walls 1201 and a window 1211. The chamber walls 1201 may be fabricated from stainless steel, aluminum, or plastic. The window 1211 may be fabricated from quartz or another dielectric material. An optional internal plasma grid 1250 divides the overall process chamber into an upper sub-chamber 1202 and a lower subchamber 1203. In some embodiments, the optional internal plasma grid 1250 may be removed, thereby utilizing a chamber space made of the sub-chambers 1202 and 1203. A chuck 1217 is positioned within the lower sub-chamber 1203 near the bottom inner surface. The chuck 1217 is configured to receive and hold a semiconductor wafer 1219 upon which the etching and deposition processes are performed. The chuck 1217 can be an electrostatic chuck for supporting the semiconductor wafer 1219 when present. In some embodiments, an edge ring (not shown) surrounds the chuck 1217, and has an upper surface that is approximately planar with a top surface of the semiconductor wafer 1219, when present over chuck 1217. The chuck 1217 also includes electrostatic electrodes for chucking and dechucking the semiconductor wafer 1219. A filter and DC clamp power supply (not shown) may be provided for this purpose. Other control systems for lifting the semiconductor wafer 1219 off the chuck 1217 can also be provided. The chuck 1217 can be electrically charged using an RF power supply 1223. The RF power supply 1223 is connected to matching circuitry 1221 through a connection 1227. The matching circuitry 1221 is connected to the chuck 1217 through a connection 1225. In this manner, the RF power supply 1223 is connected to the chuck 1217. In various embodiments, a bias power of the electrostatic chuck may be set at about 50 V or may be set at a different bias power depending on the process performed in accordance with disclosed embodiments. For example, the bias power may be between about 20 V and about 100 V, or between about 30 V and about 150 V.

[0147] Elements for plasma generation include a coil 1233 that is positioned above the window 1211. In some embodiments, a coil is not used in disclosed embodiments. The coil 1233 is fabricated from an electrically conductive material and includes at least one complete turn. The example of the coil 1233, as shown in Figure 12, includes three turns. The cross sections of the coil 1233 are shown with symbols, and coils having an “X” extending rotationally into the page, while coils having a circle extend rotationally out of the page.Attorney Docket No. LAM1P113WO / 12101-1WO

[0148] Elements for plasma generation also include an RF power supply 1241 configured to supply RF power to the coil 1233. In general, the RF power supply 1241 is connected to matching circuitry 1239 through a connection 1245. The matching circuitry' 1239 is connected to the coil 1233 through a connection 1243. In this manner, the RF power supply 1241 is connected to the coil 1233.

[0149] An optional Faraday shield 1249 is positioned between the coil 1233 and the window 1211. The Faraday shield 1249 may be maintained in a spaced apart relationship relative to the coil 1233. In some embodiments, the Faraday shield 1249 is disposed immediately above the window 1211. In some embodiments, the Faraday shield 1249 is between the window 1211 and the chuck 1217. In some embodiments, the Faraday shield 1249 is not maintained in a spaced apart relationship relative to the coil 1233. For example, the Faraday shield 1249 may be directly below the window 1211 without a gap. The coil 1233, the Faraday shield 1249, and the window 1211 are each configured to be substantially parallel to one another. The Faraday shield 1249 may prevent metal or other species from depositing on the window 1211 of the process chamber.

[0150] Process gases may be flowed into the process chamber through one or more main gas flow inlets 1260 positioned in the upper sub-chamber 1202 and / or through one or more side gas flow inlets 1270. Eikewise, though not explicitly shown, similar gas flow inlets may be used to supply process gases to a capacitively coupled plasma processing chamber. A vacuum pump, e.g., a one or two stage mechanical dry pump and / or turbomolecular pump 1240, may be used to draw process gases out of the process chamber and to maintain a pressure within the process chamber. For example, the vacuum pump may be used to evacuate the lower subchamber 1203 during a purge operation of AED. A valve-controlled conduit may be used to fluidically connect the vacuum pump to the process chamber so as to selectively control application of the vacuum environment provided by the vacuum pump. This may be done employing a closed loop-controlled flow restriction device, such as a throttle valve (not shown) or a pendulum valve (not shown), during operational plasma processing. Likewise, a vacuum pump and valve controlled fluidic connection to the capacitively coupled plasma processing chamber may also be employed.

[0151] During operation of the inductively-coupled plasma apparatus 1200, one or more process gases may be supplied through the gas flow inlets 1260 and / or 1270. In certain embodiments, process gas may be supplied only through the main gas flow inlet 1260, or only through the side gas flow inlet 1270 In some cases, the gas flow inlets shown in Figure 12 may be replaced by more complex gas flow inlets, one or more showerheads, for example.Attorney Docket No. LAM1P113WO / 12101-1WOThe Faraday shield 1249 and / or the optional internal plasma grid 1250 may include internal channels and holes that allow delivery of process gases to the process chamber. Either or both of Faraday shield 1249 and optional internal plasma grid 1250 may serve as a showerhead for delivery of process gases. In some embodiments, a liquid vaporization and delivery system may be situated upstream of the process chamber, such that once a liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process chamber via a gas flow inlet 1260 and / or 1270.

[0152] Radio frequency power is supplied from the RF power supply 1241 to the coil 1233 to cause an RF current to flow through the coil 1233. The RF current flowing through the coil 1233 generates an electromagnetic field about the coil 1233. The electromagnetic field generates an inductive current within the upper sub-chamber 1202. The physical and chemical interactions of various generated ions and radicals with the semiconductor wafer 1219 etch features of and selectively deposit layers on the semiconductor wafer 1219.

[0153] If the optional internal plasma grid 1250 is used such that there is both an upper subchamber 1202 and a lower sub-chamber 1203, the inductive current acts on the gas present in the upper sub-chamber 1202 to generate an electron-ion plasma in the upper sub-chamber 1202. The optional internal plasma grid 1250 limits the amount of hot electrons in the lower sub-chamber 1203. In some embodiments, the inductively-coupled plasma apparatus 1200 is designed and operated such that the plasma present in the lower sub-chamber 1203 is an ionion plasma.

[0154] Both the upper electron-ion plasma and the lower ion-ion plasma may contain positive and negative ions, though the ion-ion plasma will have a greater ratio of negative ions to positive ions. Volatile etching and / or deposition byproducts may be removed from the lower sub-chamber 1203 through port 1222. The chuck 1217 disclosed herein may operate at elevated temperatures ranging between about 10°C and about 250°C. The temperature will depend on the process operation and specific recipe.

[0155] The inductively-coupled plasma apparatus 1200 may be coupled to facilities (not shown) when installed in a clean room or a fabrication facility. Facilities include plumbing that provide processing gases, vacuum, temperature control, and environmental particle control. These facilities are coupled to the inductively-coupled plasma apparatus 1200, when installed in the target fabrication facility. Additionally, the inductively-coupled plasma apparatus 1200 may be coupled to a transfer chamber that allows robotics to transfer semiconductor wafers into and out of the inductively-coupled plasma apparatus 1200 using typical automation.Attorney Docket No. LAM1P113WO / 12101-1WO

[0156] In some embodiments, a system controller 1230 (which may include one or more physical or logical controllers) controls some or all of the operations of the process chamber. The system controller 1230 may include one or more memory devices and one or more processors. In some embodiments, the inductively-coupled plasma apparatus 1200 includes a switching system for controlling flow rates and durations when disclosed embodiments are performed. In some embodiments, the inductively-coupled plasma apparatus 1200 may have a switching time of up to about 500 ms, or up to about 750 ms. Switching time may depend on the flow chemistry, recipe chosen, reactor architecture, and other factors.

[0157] In some embodiments, the system controller 1230 is part of a system, which may be part of the above-described examples. Such systems can include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems may be integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics may be integrated into the system controller 1230, which may control various components or subparts of the system or systems. The system controller , depending on the processing parameters and / or the type of system, may be programmed to control any of the processes disclosed herein, including the delivery of processing gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or loadlocks connected to or interfaced with a specific system.

[0158] Broadly speaking, the system controller 1230 may be defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files), defining operational parameters for carrying out a particular process on or for a semiconductor wafer or to a system. The operational parameters may, in some embodiments, be part of a recipe defined by- process engineers to accomplish one or more processing stepsAttorney Docket No. LAM1P113WO / 12101-1WOduring the fabrication or removal of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0159] The system controller 1230, in some embodiments, may be a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or a part of a fab host computer system, which can allow for remote access of the wafer processing. The computer may enable remote access to the system to monitor current progress of fabrication operations, examine a history of past fabrication operations, examine trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process. In some examples, a remote computer (e.g. a server) can provide process recipes to a system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the system controller 1230 receives instructions in the form of data, which specify parameters for each of the processing steps to be performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus as described above, the system controller 1230 may be distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would be one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0160] Without limitation, example systems may include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVT)) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an ALE chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a dry development chamber or module, and any other semiconductor processing systems that may be associated or used in the fabrication and / or manufacturing of semiconductor wafersAttorney Docket No. LAM1P113WO / 12101-1WO

[0161] As noted above, depending on the process step or steps to be performed by the tool, the controller might communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0162] EUVL patterning may he conducted using any suitable tool, often referred to as a scanner, for example the TWIN SC AN NXE: 3300B© platform supplied by ASML of Vefdhoven, NL). The EUVL patterning tool may be a standalone device from which the substrate is moved into and out of for deposition and etching as described herein. Or, as described below, the EUVL patterning tool may be a module on a larger multi-component tool.

[0163] Figure 13 depicts a semiconductor process cluster tool architecture with vacuum-integrated deposition and patterning modules that interface with a vacuum transfer module, suitable for implementations of processes described herein. While the processes may be conducted without such vacuum integrated apparatus, such apparatus may be advantageous in some embodiments. The arrangement of transfer modules to “transfer” wafers among multiple storage facilities and processing modules may be referred to as a “cluster tool architecture” system. Deposition and patterning modules are vacuum-integrated, in accordance with the requirements of a particular process. Other modules, such as for etch, may also be included on the cluster.

[0164] A vacuum transport module (VTM) 1338 interfaces with four processing modules (e.g., a first processing module 1320a, a second processing module 1320b, a third processing module 1320c, and a fourth processing module 1320d), which may be individually optimized to perform various fabrication processes. By way of example, the four processing modules (e.g., the first processing module 1320a, the second processing module 1320b, the third processing module 1320c, and the fourth processing module 1320d) may be implemented to perform deposition, evaporation, ELD, dry development, etch, strip, and / or other semiconductor processes. For example, the first processing module 1320a may be an ALD reactor that may be operated to perform in a non-plasma, thermal atomic layer depositions as described herein, such as Vector tool, available from Lam Research Corporation, Fremont, CA and the second processing module 1320b may be a PECVD tool, such as the Lam Vector©. It should be understood that the figure is not necessarily drawn to scale.Attorney Docket No. LAM1P113WO / 12101-1WO

[0165] A first airlock 1342 and a second airlock 1346, also known as a loadlocks or transfer modules, interface with the VTM 1338 and a patterning module 1340. For example, as noted above, a suitable patterning module may be the TWINSCAN NXE: 330QB® platform supplied by ASML of Veldhoven, NL). This tool architecture allows for work pieces, such as semiconductor substrates or wafers, to be transferred under vacuum so as not to react before exposure. Integration of the deposition modules with the lithography tool is facilitated by the fact that EUVL also requires a greatly reduced pressure given the strong optical absorption of the incident photons by ambient gases.

[0166] As noted above, this integrated architecture is just one possible embodiment of a tool for implementation of the described processes. The processes may also be implemented with a more conventional stand-alone EUVL scanner and a deposition reactor, such as a Lam Vector tool, either stand alone or integrated in a cluster architecture with other tools, such as etch, strip etc. (e.g., Lam Kiyo or Gamma tools), as modules, for example as described with reference to Figure 15 but without the integrated patterning module.

[0167] The first airlock 1342 may be an “Outgoing” loadlocks referring to the transfer of a substrate out from the VTM 1338 serving the first processing module 1320a (e.g., a deposition module) to the patterning module 1340 and the second airlock 1346 may be an “ingoing” loadlock, referring to the transfer of a substrate from the patterning module 1340 back into the VTM 1338. The second airlock 1346 (or the ingoing loadlock) may also provide an interlace to the exterior of the tool for access and egress of substrates. Each process module has a facet that interfaces the module to the VTM 1338. For example, the first processing module 1320a (e.g., the deposition module) has a facet 1336. Inside each facet, sensors, for example, sensors 1-18 as shown, are used to detect the passing of the wafer 1326 when moved between respective stations. The patterning module 1340, the first airlock 1342, and the second airlock 1346 may be similarly equipped with additional facets and sensors, not shown.

[0168] A main VTM robot 1322 transfers the wafer 1326 between modules, including the first airlock 1342 and the second airlock 1346. In one embodiment, the main VTM robot 1322 has one arm, and in another embodiment, the main VTM robot 1322 has two arms, where each arm has an end effector 1324 to pick wafers, such as the wafer 1326 for transport. A front-end robot 1344 is used to transfer the wafer 1326 from the first airlock 1342 (e.g., the outgoing airlock) into the patterning module 1340 and from the patterning module 1340 into the second airlock 1346 (e.g., the ingoing airlock). The front-end robot 1344 may also transport the wafer 1326 between the ingoing loadlock and the exterior of the tool for access and egress of substrates. Because the second airlock 1346 (e.g., the ingoing airlock) has theAttorney Docket No. LAM1P113WO / 12101-1WOability to match the environment between atmospheric and vacuum, the wafer 1326 is able to move between the two pressure environments without being damaged.

[0169] It should be noted that a EUVL tool typically operates at a higher vacuum than a deposition tool. If this is the case, it is desirable to increase the vacuum environment of the substrate during the transfer between the deposition to the EUVL tool to allow the substrate to degas prior to entry' into the patterning tool. The first airlock 1342 (e.g., the outgoing airlock) may provide this function by holding the transferred wafers at a lower pressure, no higher than the pressure in the patterning module 1340, for a period of time and exhausting any off-gassing, so that the optics of the patterning module 1340 are not contaminated by-off-gassing from the substrate. A suitable pressure for the outgoing, off-gassing airlock is no more than IE- 8 Torr.

[0170] In some embodiments, a system controller 1350 (which may include one or more physical or logical controllers) controls some or all of the operations of the cluster tool and / or its separate modules. It should be noted that the controller can be local to the cluster architecture, or can be located external to the cluster architecture in the manufacturing floor, or in a remote location and connected to the cluster architecture via a network. The system controller 1350 may include one or more memory devices and one or more processors. The processor may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, stepper motor controller boards, and other like components. Instructions for implementing appropriate control operations are executed on the processor. These instructions may be stored on the memory devices associated with the controller or they may be provided over a network. In certain embodiments, the system controller executes system control software.

[0171] The system control software may include instructions for controlling the timing of application and / or magnitude of any aspect of tool or module operation. System control software may be configured in any suitable way. For example, various process tool component subroutines or control objects may be written to control operations of the process tool components necessary to carry' out various process tool processes. System control software may be coded in any suitable compute readable programming language. In some embodiments, system control software includes input / output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of a semiconductor fabrication process may include one or more instructions for execution by the system controller. The instructions for setting process conditions for condensation,Attorney Docket No. LAM1P113WO / 12101-1WOdeposition, evaporation, patterning and / or etching phase may be included in a corresponding recipe phase, for example.

[0172] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus may include a processing chamber for patterning, deposition and etch, and a controller including instructions for forming a negative pattern mask. The instructions may include code for, in the processing chamber, patterning a feature in a chemically amplified (CAR) resist on a semiconductor substrate by EUV exposure to expose a surface of the substrate, developing the photopattemed resist, and etching the underlying layer or layer stack using the patterned resist as a mask. Development may be performed using a halide-containing chemistry.

[0173] It should be noted that the computer controlling the wafer movement can be local to the cluster architecture, or can be located external to the cluster architecture in the manufacturing floor, or in a remote location and connected to the cluster architecture via a network. A controller as described above with respect to any of the figures.Clause Section

[0174] It is to be understood that the above disclosure, while focusing on a particular example implementation or implementations, is not limited to only the discussed example, but may also apply to similar variants and mechanisms as well, and such similar variants and mechanisms are also considered to be within the scope of this disclosure. For example, the above disclosure is directed to at least, but not exclusively, the following numbered implementations.

[0175] Implementation 1: A method of processing a semiconductor substrate, the method comprising: (a) providing, in a process chamber, a semiconductor substrate with a metalcontaining photoresist film disposed on the semiconductor substrate; (b) exposing the semiconductor substrate to etch conditions comprising a hydrogen-containing species activated by a remote plasma source to remove a portion of the metal-containing photoresist film; and (c) exposing the semiconductor substrate to an oxygen-containing species activated by the remote plasma source.

[0176] Implementation 2: The method of Implementation 1, wherein (b) removes the portion of the metal-containing photoresist film on an edge, a bevel, and a backside of the semiconductor substrate.

[0177] Implementation 3: The method of Implementation 1, wherein the metal-containing photoresist film is an organo-metal oxide or an organo-metal-containing thin film.Attorney Docket No. LAM1P113WO / 12101-1WO

[0178] Implementation 4: The method of Implementation 3, wherein the metal-containing photoresist film comprises an organotin oxide.

[0179] Implementation 5: The method of Implementation 1, wherein the metal-containing photoresist film comprises an element selected from the group consisting of: tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium.

[0180] Implementation 6: The method of Implementation 1, wherein the etch conditions of (b) comprise a carrier gas, and wherein the carrier gas is selected from the group consisting of helium (He), neon (Ne), argon (Ar), xenon (Xe), nitrogen (N2), and methane (CH4).

[0181] Implementation 7: The method of Implementation 6, wherein the carrier gas comprises Ar, and wherein a flow rate of Ar ranges from about 2000 seem to about 7000 seem.

[0182] Implementation 8: The method of Implementation 6, wherein the carrier gas comprises N2, and wherein a flow rate of N2 ranging from about 2000 seem to about 7000 seem.

[0183] Implementation 9: The method of Implementation 1, wherein the hydrogencontaining species of (b) comprises molecular hydrogen (H2) or a hydrogen halide (HX), wherein X is a halogen.

[0184] Implementation 10: The method of Implementation 9, wherein a flow rate of the hydrogen-containing species is between about 2000 seem and about 7000 seem.

[0185] Implementation 11: The method of Implementation 9, wherein the hydrogencontaining species comprises H2, and wherein the etch conditions of (b) comprise molecular oxygen (O2).

[0186] Implementation 12: The method of Implementation 11, wherein a flow rate of Chis about 100 ppm.

[0187] Implementation 13: The method of Implementation 1, wherein the etch conditions of (b) causes deposition of an etch byproduct on the semiconductor substrate, and wherein the oxygen-containing species in (c) removes the etch byproduct.

[0188] Implementation 14: The method of Implementation 1, wherein subsequent (b), an amount of a metal from the metal-containing photoresist film present on a surface of the semiconductor substrate is about 5 E10 / cm2.

[0189] Implementation 15: The method of Implementation 1, wherein the etch conditions of (b) comprise a pressure ranging from about 100 mT to about 500 mT.

[0190] Implementation 16: The method of Implementation 1, wherein the etch conditions of (b) comprise a temperature ranging from about 20°C to about 120°C.Attorney Docket No. LAM1P113WO / 12101-1WO

[0191] Implementation 17: The method of Implementation 1, further comprising: (d) exposing the semiconductor substrate to a hydrogen-containing plasma to remove a trace metal from a surface of the semiconductor substrate; and (e) repeating operations (c) and (d) in a multi-cycle etch process.

[0192] Implementation 18: The method of Implementation 17, wherein the multi-cycle etch process of (e) is repeated for a frequency of at least two cycles.

[0193] Implementation 19: The method of Implementation 17, wherein subsequent (e), an amount of a metal from the metal-containing photoresist film present on the surface of the semiconductor substrate is about less than 1 E10 / cm2.

[0194] Implementation 20: The method of Implementation 17, further comprising: subsequent (d), performing a purge operation using a purge gas, wherein the purge gas is selected from the group consisting of argon (Ar), hydrogen (H2), and nitrogen (N2).

[0195] Implementation 21: The method of Implementation 1, wherein in (c), the oxygencontaining species is selected from the group consisting of molecular oxygen (O2), ozone (O3), carbon monoxide (CO), carbon dioxide (CO2), nitric oxide (NO), and nitrogen dioxide (NO2).

[0196] Implementation 22: An apparatus for processing a semiconductor substrate, the apparatus comprising: one or more process chambers, wherein each process chamber of the one or more process chambers comprises a substrate support; a vacuum line coupled to the one or more process chambers; a remote plasma source; one or more gas inlets into the one or more process chambers and associated flow-control hardware; and a controller having at least one processor and a memory, wherein: the at least one processor and the memory are communicatively connected with one another, the at least one processor is at least operatively connected with the flow-control hardware, and the memory stores computer-executable instructions for controlling the at least one processor to perform a method comprising: (a) receiving, on the substrate support, a semiconductor substrate with a metal-containing photoresist film disposed on the semiconductor substrate; (b) exposing the semiconductor substrate to etch conditions comprising a hydrogen-containing species activated by a remote plasma source to remove a portion of the metal-containing photoresist film; and (c) exposing the semiconductor substrate to an oxygen-containing species activated by the remote plasma source

[0197] Implementation 23: The apparatus of Implementation 22, wherein the apparatus further comprises a vacuum loadlock, and wherein the vacuum loadlock comprises the remote plasma source.Attorney Docket No. LAM1P113WO / 12101-1WO

[0198] Implementation 24: The apparatus of Implementation 22, wherein in (b), the hydrogen-containing species activated by the remote plasma source is delivered to an edge of the semiconductor substrate.

[0199] Implementation 25: The apparatus of Implementation 24, further comprising a deflector disposed between the remote plasma source and the semiconductor substrate.

[0200] Implementation 26: The apparatus of Implementation 25, wherein the deflector is configured to deliver a purge gas to a location between the deflector and the semiconductor substrate.

[0201] Implementation 27: The apparatus of Implementation 25, wherein at least one of a top surface of the deflector and a surface of walls of each process chamber comprise a coating material configured to reduce hydrogen radical recombination.

[0202] Implementation 28: The apparatus of Implementation 27, wherein the coating material is selected from the group consisting of polytetrafluoroethylene (PTFE), quartz, quartz oxide, and silicon dioxide (SiCh).

[0203] Implementation 29: The apparatus of any one of Implementations 22-28, wherein a first process chamber of the one or more process chambers is a deposition chamber, wherein the method is executed in a second process chamber of the one or more process chambers, and wherein the first process chamber differs from the second process chamber.

[0204] Implementation 30: The apparatus of Implementation 29, wherein the first process chamber and the second process chamber are located on a same platform.

[0205] Implementation 31: The apparatus of any one of Implementations 22-28, wherein a first process chamber of the one or more process chambers is a deposition chamber, and wherein the method is executed in the first process chamber.

[0206] Implementation 32: The apparatus of Implementation 22, further comprising a showerhead to deliver the hydrogen-containing species to a location on the semiconductor substrate.

[0207] Implementation 33: The apparatus of Implementation 22, further comprising a nozzle configured to deliver the hydrogen-containing species to a location on the semiconductor substrate.

[0208] Implementation 34: The apparatus of Implementation 33, wherein the nozzle is movable.

[0209] Implementation 35: The apparatus of Implementation 33, wherein the nozzle is fixed and the substrate support is rotatable.Attorney Docket No. LAM1P113WO / 12101-1WO

[0210] Implementation 36: The apparatus of any one of Implementations 22-35, wherein (b) removes the portion of the metal-containing photoresist film on an edge, a bevel, and a backside of the semiconductor substrate.

[0211] Implementation 37: A method of processing a semiconductor substrate, the method comprising: (a) providing, in a process chamber, a semiconductor substrate with a metalcontaining photoresist film disposed on the semiconductor substrate; (b) exposing the semiconductor substrate to etch conditions comprising a hydrogen-containing species activated by a remote plasma source to remove a portion of the metal-containing photoresist film; (c) exposing the semiconductor substrate to an oxygen-containing species activated by the remote plasma source; (d) exposing the semiconductor substrate to a hydrogen-containing plasma to remove a trace metal from a surface of the semiconductor substrate; (e) performing a purge operation using a purge gas; and (f) repeating operations (c)-(e) in a multi-cycle etch process.Conclusion

[0212] It is understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art. Although various details have been omitted for clarity’s sake, various design alternatives may be implemented. Therefore, the present examples are to be considered as illustrative and not restrictive, and the disclosure is not to be limited to the details given herein, but may be modified within the scope of the disclosure.

Claims

Attorney Docket No. LAM1P113WO / 12101-1WOCLAIMSWhat is claimed is:

1. A method of processing a semiconductor substrate, the method comprising:(a) providing, in a process chamber, a semiconductor substrate with a metalcontaining photoresist film disposed on the semiconductor substrate;(b) exposing the semiconductor substrate to etch conditions comprising a hydrogencontaining species activated by a remote plasma source to remove a portion of the metalcontaining photoresist film; and(c) exposing the semiconductor substrate to an oxygen-containing species activated by the remote plasma source.

2. The method of claim 1, wherein (b) removes the portion of the metal-containing photoresist film on an edge, a bevel, and a backside of the semiconductor substrate.

3. The method of claim 1, wherein the metal-containing photoresist film is an organo-metal oxide or an organo-metal-containing thin film.

4. The method of claim 3, wherein the metal-containing photoresist film comprises an organotin oxide.

5. The method of claim 1, wherein the etch conditions of (b) causes deposition of an etch byproduct on the semiconductor substrate, and wherein the oxygen-containing species in (c) removes the etch byproduct.

6. The method of claim 1, wherein the etch conditions of (b) comprise at least one of a pressure ranging from about 100 mT to about 500 mT and a temperature ranging from about 20°C to about 120°C.

7. The method of claim 1, further comprising:(d) exposing the semiconductor substrate to a hydrogen-containing plasma to remove a trace metal from a surface of the semiconductor substrate; and(e) repeating operations (c) and (d) in a multi-cycle etch process.Attorney Docket No. LAM1P113WO / 12101-1WO8. The method of claim 7, wherein subsequent (e), an amount of a metal from the metal-containing photoresist film present on the surface of the semiconductor substrate is about less than 1 E10 / cm2.

9. An apparatus for processing a semiconductor substrate, the apparatus comprising:one or more process chambers, wherein each process chamber of the one or more process chambers comprises a substrate support;a vacuum line coupled to the one or more process chambers;a remote plasma source;one or more gas inlets into the one or more process chambers and associated flowcontrol hardware; anda controller having at least one processor and a memory, wherein:the at least one processor and the memory are communicatively connected with one another,the at least one processor is at least operatively connected with the flowcontrol hardware, andthe memory stores computer-executable instructions for controlling the at least one processor to perform a method comprising:(a) receiving, on the substrate support, a semiconductor substrate with a metal-containing photoresist film disposed on the semiconductor substrate;(b) exposing the semiconductor substrate to etch conditions comprising a hydrogen-containing species activated by a remote plasma source to remove a portion of the metal-containing photoresist film; and (c) exposing the semiconductor substrate to an oxygen-containing species activated by the remote plasma source10. The apparatus of claim 9, wherein the apparatus further comprises a vacuum loadlock, and wherein the vacuum loadlock comprises the remote plasma source.

11. The apparatus of claim 10, wherein the apparatus further comprises a deflector disposed between the remote plasma source and the semiconductor substrate.Attorney Docket No. LAM1P113WO / 12101-1WO12. The apparatus of claim 11, wherein at least one of a top surface of the deflector and a surface of walls of each process chamber comprise a coating material configured to reduce hydrogen radical recombination.

13. The apparatus of claim 9, wherein a first process chamber of the one or more process chambers is a deposition chamber, wherein the method is executed in a second process chamber of the one or more process chambers, and wherein the first process chamber differs from the second process chamber.

14. The apparatus of claim 13, wherein the first process chamber and the second process chamber are located on a same platform.

15. The apparatus of claim 9, wherein a first process chamber of the one or more process chambers is a deposition chamber, and wherein the method is executed in the first process chamber.

16. The apparatus of claim 9, wherein the apparatus further comprises a showerhead to deliver the hydrogen-containing species to a location on the semiconductor substrate.

17. The apparatus of claim 9, wherein the apparatus further comprises a nozzle configured to deliver the hydrogen-containing species to a location on the semiconductor substrate.

18. The apparatus of claim 17, wherein: (i) the nozzle is movable, or (ii) the nozzle is fixed and the substrate support is rotatable.

19. The apparatus of claim 9, wherein (b) removes the portion of the metal-containing photoresist film on an edge, a bevel, and a backside of the semiconductor substrate.

20. A method of processing a semiconductor substrate, the method comprising:(a) providing, in a process chamber, a semiconductor substrate with a metalcontaining photoresist film disposed on the semiconductor substrate;(b) exposing the semiconductor substrate to etch conditions comprising a hydrogencontaining species activated by a remote plasma source to remove a portion of the metalcontaining photoresist film;Attorney Docket No. LAM1P113WO / 12101-1WO(c) exposing the semiconductor substrate to an oxygen-containing species activated by the remote plasma source;(d) exposing the semiconductor substrate to a hydrogen-containing plasma to remove a trace metal from a surface of the semiconductor substrate;(e) performing a purge operation using a purge gas; and(f) repeating operations (c)-(e) in a multi-cycle etch process.

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