Plasma processing system modeling for sensor calibration

Abstract

Methods and apparatus for calibrating a sensor. One example plasma processing system circuit includes a first printed circuit board (PCB) that includes a pulser circuit coupled to a reference potential node and a first capacitive element coupled to the pulser circuit, and a second PCB that includes an inductive element, a second capacitive element coupled to the inductive element, and a load coupled to the second capacitive element and to the reference potential node. The processing system circuit also includes a sensor that includes an input for coupling to the first PCB and an output for coupling to the second PCB. By comparing information measured by the sensor with other measurements taken on the plasma processing system circuit, the sensor can be adjusted until the information measured by the sensor matches the corresponding measurements taken on the plasma processing system circuit.

Description

PATENTAtorney Docket No.: 44025569WO01PLASMA PROCESSING SYSTEM MODELING FOR SENSOR CALIBRATION BACKGROUNDField

[0001] Embodiments described herein generally relate to a system and methods used in semiconductor device fabrication. More specifically, embodiments of the present disclosure relate to plasma processing system modeling for calibrating a sensor and a waveform generating system.Description of the Related Art

[0002] Reliably producing high aspect ratio features is one of the key technology challenges for the next generation of semiconductor devices. One method of forming high aspect ratio features uses a plasma-assisted etching process to bombard a material formed on a surface of a substrate through openings formed in a patterned mask layer formed on the substrate surface.

[0003] With technology node advancing towards 2 nanometers (nms), the fabrication of smaller features with larger aspect ratios requires atomic precision for plasma processing. For etching processes where the plasma ions play a major role, ion energy control is always challenging the semiconductor equipment industry. In a typical plasma-assisted etching process, the substrate is positioned on an electrostatic chuck (ESC) disposed in a processing chamber, a plasma is formed over the substrate, and ions are accelerated from the plasma towards the substrate across a plasma sheath, i.e. , region depleted of electrons, formed between the plasma and the surface of the substrate. Traditional radio frequency (RF) substrate biasing methods, which use sinusoidal RF waveforms to excite the plasma and form the plasma sheath, have been unable to desirably form these smaller device feature sizes. Recently, it has been found that utilizing pulsed power sources to deliver high voltage direct current (DC) pulses to one or more electrodes within a processing chamber can be useful in desirably controlling the plasma sheath formed over the surface of the substrate.

[0004] In some cases, one or more sensors may be used in conjunction with a plasma processing system to measure parameters associated with voltage pulses and / or waveforms used during plasma processing. For example, the one or morePATENTAtorney Docket No.: 44025569WO01sensors may measure, for example, delivered power, reflected power, harmonics, and / or other parameters associated with the pulses and / or waveforms. However, it is frequently challenging for sensors to obtain accurate and meaningful parameter measurements in a plasma processing system, due to sensor-to-sensor variation, variations in plasma processing chamber components, and interactions between waveform (e.g., RF or voltage waveforms) power delivery components.

[0005] Accordingly, there is a need in the art for improved plasma processing systems and methods that solve the problems described above.SUMMARY

[0006] To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed.

[0007] Embodiments provided herein generally include apparatus, plasma processing system circuits, and methods for calibrating a sensor.

[0008] Embodiments of the present disclosure provide a plasma processing system circuit. The plasma processing system circuit generally includes a first printed circuit board (PCB) including a pulser circuit including an input coupled to a reference potential node and including an output, a first capacitive element including a first terminal coupled to the output of the pulser circuit and including a second terminal, and a first PCB output coupled to the second terminal of the first capacitive element; and a second PCB including a second PCB input node, an inductive element coupled to the second PCB input node, a second capacitive element coupled to the inductive element, and a load coupled to the second capacitive element and to the reference potential node, where first PCB output is configured to be coupled to an input of a sensor and the second PCB input node is configured to be coupled to an output of the sensor.

[0009] Embodiments of the present disclosure provide a plasma processing system circuit. The plasma processing system circuit generally includes ( / ') a pulser circuit that includes a first transistor, a second transistor coupled to the first transistor, a powerPATENTAtorney Docket No.: 44025569WO01supply including a first terminal coupled to a reference potential node, and a converter including a first terminal coupled to the reference potential node; ( / ' / ) a damping circuit including an input coupled to a second terminal of the power supply, a second terminal of the converter, and the first transistor; (7 / 7) a first capacitive element including a first terminal coupled to an output of the damping circuit and including a second terminal configured to be coupled to an input of a sensor; (7v) an inductive element including a first terminal configured to be coupled to an output of the sensor; (v) a second capacitive element including a first terminal coupled to a second terminal of the inductive element and including a second terminal coupled to the reference potential node; (v / ) a third capacitive element including a first terminal coupled to the second terminal of the inductive element; and (v / 7) a load coupled between a second terminal of the third capacitive element and the reference potential node.

[0010] Embodiments of the present disclosure provide a method of calibrating a sensor. The method generally includes ( / ') coupling an input of the sensor to a pulser circuit included in a plasma processing system circuit and an output of the sensor to a chamber circuit included in the plasma processing system circuit, (77) effectively modeling, using the plasma processing system circuit, a plasma processing system, (777) generating, using the pulser circuit, a pulsed voltage (PV) waveform, (7v) measuring, using the sensor, a voltage provided to the input of the sensor, (v) providing an output signal to a system controller using a first transfer function, (v7) measuring, using a probe, a voltage at one or more nodes of the chamber circuit, and (v / 7) adjusting, based on the voltage at the output of the sensor and the voltage at the one or more nodes of the chamber circuit, a calibration of the sensor used by the system controller by adjusting the first transfer function.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] So that the manner in which the above recited features of embodiments of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.PATENTAtorney Docket No.: 44025569WO01

[0012] Figure 1 is a schematic representation of an example plasma processing system, in which embodiments of the present disclosure may be implemented.

[0013] Figure 2 illustrates a graph of two separate asymmetric voltage waveforms that are established on a substrate due to a voltage waveform applied to an electrode of a processing chamber, in accordance with certain embodiments of the present disclosure.

[0014] Figure 3 is a block diagram of an example plasma processing system circuit for sensor calibration that includes a control side and a load side, in accordance with certain embodiments of the present disclosure.

[0015] Figure 4A is a schematic diagram of an example plasma processing system circuit for sensor calibration that includes a pulser circuit and a chamber circuit, in accordance with certain embodiments of the present disclosure.

[0016] Figure 4B is an example circuit diagram of the plasma processing system circuit for sensor calibration of Figure 4A, in accordance with certain embodiments of the present disclosure.

[0017] Figure 5 is a flow diagram illustrating example operations for sensor calibration, in accordance with certain embodiments of the present disclosure.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation.DETAILED DESCRIPTION

[0019] Certain embodiments of the present disclosure generally relate to an apparatus and methods for testing, adjusting and / or controlling sensing elements used in a plasma processing system. Aspect of the disclosure include a system that models (e.g., mimics) a plasma processing system to test, adjust, and qualify sensors used to detect aspects of the delivery of radio frequency (RF) signals and / or voltage waveforms to one or more electrodes disposed within a plasma processing chamber. The plasma processing system may be modeled (at a relatively small scale), for example, using a plasma processing system circuit that includes a control side and a load side. In some embodiments, the control side may include a pulser circuit andPATENTAtorney Docket No.: 44025569WO01additional circuitry (e.g., a damping circuit and / or one or more capacitive elements), and the load side may include a load (e.g., representing a plasma load) and additional circuitry (e.g., one or more inductive element and / or one or more capacitive elements). In some cases, the control side may be implemented on a first printed circuit board (PCB), and the load side may be implemented on a second PCB. The sensor may include an input for coupling to the control side and includes an output for coupling to the load side.

[0020] After being coupled between the control side and the load side of the plasma processing system circuit, the sensor may measure (e.g., during generation of a pulsed voltage (PV) waveform by the pulser circuit) a voltage (and / or a current) at the output of the sensor (or another part of the sensor), and a probe may be used to measure a voltage at the one or more nodes of the plasma processing system circuit. In this manner, the voltage (and / or a current) at the output of the sensor and the voltage measured by the probe may be compared, and the calibration of the sensor may be adjusted (e.g., by updating a transfer function-based algorithm of the sensor) in accordance with the comparison to properly calibrate the sensor. In some cases, the sensor may be calibrated for a wide frequency range (e.g., 200 kHz to 800 kHz) and a full range of duty cycles (0-100%). After being calibrated, the sensor may be used in conjunction with actual plasma processing systems and relied upon for accurate measurements (e.g., to enable improved control of the plasma processing system).Processing System Examples

[0021] Figure 1 is a schematic representation of an example plasma processing system 10, in which embodiments of the present disclosure may be implemented. The plasma processing system 10 is configured for plasma-assisted substrate processing process, such as a plasma-assisted etching process or deposition process. In some examples, a plasma-assisted process include a plasma-assisted etching process, such as a reactive ion etch (RIE) process. The plasma processing system 10 can also be used in other plasma-assisted processes, such as plasma-enhanced deposition processes (for example, plasma-enhanced chemical vapor deposition (PECVD) processes, plasma-enhanced physical vapor deposition (PEPVD) processes, plasma-enhanced atomic layer deposition (PEALD) processes, plasma treatment processing,PATENTAtorney Docket No.: 44025569WO01plasma-based ion implant processing, or plasma doping (PLAD) processing. In some embodiments, as shown in Figure 1, the plasma processing system 10 is configured to form a capacitively-coupled-plasma (CCP). In other embodiments, a plasma may alternately be generated by an inductively coupled plasma (ICP) source disposed over a processing region of the plasma processing system 10.

[0022] The plasma processing system 10 includes a processing chamber 100, a substrate support assembly 136, a gas delivery system 182, a high voltage direct current (DC) supply 173, a RF generator 171, and a RF match 172 (e.g., RF impedance matching networks). The processing chamber 100 includes a chamber lid 123 positioned in a processing volume 129 of the processing chamber 100. The chamber lid 123 includes one or more sidewalls and a chamber base that are configured to withstand the pressures and energy applied to them while a plasma 101 is generated within a vacuum environment maintained in the processing volume 129 of the processing chamber 100 during processing.

[0023] The gas delivery system 182, which is coupled to the processing volume 129 of the processing chamber 100, is configured to deliver at least one processing gas from at least one gas processing source 119 to the processing volume 129 of the processing chamber 100. The gas delivery system 182 includes the gas processing source 119 and one or more gas inlets 128 positioned through the chamber lid 123. The gas inlets 128 are configured to deliver one or more processing gasses to the processing volume 129 of the processing chamber 100.

[0024] The processing chamber 100 includes a chamber lid 123 and a substrate support assembly 136 positioned in the processing volume 129 of the processing chamber 100. In some embodiments, the chamber lid 123 is grounded and thus acts as an upper electrode during plasma processing. In some embodiments, the RF generator 171 is electrically coupled to a first lower electrode, such as the RF baseplate 137. The RF generator 171 is configured to deliver an RF signal to ignite and maintain the plasma 101 between the upper and lower electrodes. In one example, the RF generator 171 may deliver an RF source power to the RF baseplate 137 within the substrate support assembly 136 (e.g., a cathode assembly) for plasma production. However, in some alternative configurations, the RF generator 171 can be electrically coupled to the upper electrode. A center frequency of the RF sourcePATENTAtorney Docket No.: 44025569WO01power can be from 13.56 megahertz (MHz) to very high frequency band such as 40 MHz, 60 MHz, 120 MHz or 162 MHz. The RF source power can be operated in a continuous mode or a pulsed mode. A pulsing frequency of the RF power can be from 100 to 10 kHz, and duty cycles are ranging from 5% to 95%. The RF generator 171 has a frequency tuning capability and can adjust its RF power frequency within e.g., ±5% or ±10%. In some embodiments, the RF generator 171 switches the RF power frequency at a predefined speed (e.g., two nanoseconds, fifty nanoseconds, etc.).

[0025] The substrate support assembly 136 is coupled to the RF generator 171, and the RF generator 171 is configured to deliver an RF signal to the processing volume 129 of the processing chamber 100. The RF generator 171 is electronically coupled to the RF match 172 disposed between the RF generator 171 and the processing volume 129 of the processing chamber 100. For example, the RF match 172 is an electrical circuit used between the RF generator 171 and a plasma reactor (e.g., the processing volume 129 of the processing chamber 100) to optimize power delivery efficiency. One or more RF filters (e.g., within the RF match 172) are designed to only allow powers in a selected frequency range, and to isolate RF power supplies from each other. In some cases, a bandwidth of an RF filter has to be larger than a frequency tuning range of the RF generator 171.

[0026] During the plasma processing, the RF generator 171 delivers an RF signal to the RF baseplate 137 of the substrate support assembly 136 via the RF match 172. For example, the RF signal is applied to a load (e.g., gas) in the processing volume 129 of the processing chamber 100. If an impedance of the load is not properly matched to an impedance of a source (e.g., the RF generator 171), a portion of a waveform can reflect back in an opposite direction. Accordingly, to prevent a substantial portion of the waveform from reflecting back, it may be beneficial to find a match impedance (e.g., a matching point) by adjusting one or more components of the RF match 172 as the source and load impedances change. The RF match 172 is electrically coupled to the RF generator 171, the substrate support assembly 136, and a voltage waveform generator 175. The RF match 172 is configured to receive a synchronization signal from either or both of the RF generator 171 and the voltage waveform generator 175.PATENTAtorney Docket No.: 44025569WO01

[0027] The substrate support assembly 136 may be coupled to a high voltage DC supply 173 that supplies a chucking voltage thereto. The high voltage DC supply 173 may be coupled to a filter assembly 111 that is disposed between the high voltage DC supply 173 and the substrate support assembly 136. The filter assembly 111 is configured to electronically isolate the high voltage DC supply 173 during plasma processing. In one configuration, a static DC voltage is between about -5000V and about +5000V, and is delivered using an electrical conductor (such as a coaxial power delivery line). The filter assembly 111 may include multiple filtering components or a single common filter.

[0028] The substrate support assembly 136 is also coupled to a voltage waveform generator 175 configured to supply a voltage to a bias electrode 138 within the substrate support assembly 136 to bias a substrate disposed on the substrate support assembly 136. The voltage waveform generator 175 may alternately be coupled to the RF baseplate 137 or a second electrode disposed within the substrate support assembly 136. The voltage waveform generator 175 is coupled to the filter assembly 111, which is coupled to the electrode disposed within the substrate support assembly 136. The filter assembly 111 is disposed between the voltage waveform generator 175 and the substrate support assembly 136. The filter assembly 111 is configured to electronically isolate the voltage waveform generator 175 from at least the RF signal provided by the RF generator 171 during plasma processing.

[0029] Voltage and current sensors can be placed at an input and / or output of the RF match 172 to measure impedance and other electrical parameters. These sensors can be synchronized using an external transistor-transistor logic (TTL) synchronization signal from an advanced waveform generator and / or RF generators or using measured voltage and current data to determine timing internally. For example, an output sensor 117 is configured to measure the impedance of the processing chamber 100, and other characteristics such as the voltage, current, harmonics, phase, and / or the like. An input sensor 116 is configured to measure the impedance of the RF generator 171 and other characteristics such as the voltage, current, harmonics, phase, and / or the like. Based on either of the synchronization signals or the characteristics of the processing chamber 100, the RF match 172 is able to capture fast impedance changes and optimize impedance matching. In some embodiments, a sensor 118 may be coupled between the voltage waveform generator 175 and thePATENTAtorney Docket No.: 44025569WO01filter assembly 111 (as illustrated), coupled between the filter assembly 111 and the bias electrode 138, or coupled between the filter assembly 111 and the high voltage DC supply 173. Any combination of the input sensor 116, the output sensor 117, and the sensor 118 (as well as any other additional sensors not shown) may be configured to detect aspects of the delivery of RF signals and / or voltage waveforms within the processing chamber 100, and may be the sensors described herein.

[0030] The voltage waveform generator 175 is used to supply a voltage waveform and / or a tailored voltage waveform, which includes a series of voltage pulses that are provided to the bias electrode 138. The voltage waveform generator 175 may output a synchronization TTL signal to the RF match 172. The voltage waveform is coupled to the bias electrode 138 through the filter assembly 111. Typically, the bias electrode 138 is formed of one or more electrically conductive parts, such as one or more metal meshes, foils, plates, or combinations thereof. The high voltage DC supply 173 is applied to chuck a wafer (e.g., a substrate) during a process for a thermal control. In some cases, there can be a third electrode at an edge of the cathode assembly for edge uniformity control.

[0031] The RF generator 171 and the voltage waveform generator 175 are each directly coupled to a system controller 126. The system controller 126 synchronizes the respective generated RF signal and voltage waveform. The system controller 126, also referred to herein as a processing chamber controller, includes a central processing unit (CPU), memory, and support circuits. The system controller 126 is used to control the process sequence used to process the substrate, including substrate biasing. The CPU is a general-purpose computer processor configured for use in an industrial setting for controlling the processing chamber and sub-processors related thereto. The memory described herein, which is generally non-volatile memory, may include random access memory, read-only memory, floppy or hard disk drive, or other suitable forms of digital storage, local or remote. The support circuits are conventionally coupled to the CPU and comprise cache, clock circuits, input / output subsystems, power supplies, and the like, and combinations thereof. Software instructions (program) and data can be coded and stored within memory to instruct a processor within CPU. A software program (or computer instructions) readable by CPU in the system controller 126 determines which tasks are performable by the components in the plasma processing system 10.PATENTAtorney Docket No.: 44025569WO01

[0032] Typically, the program, which is readable by the CPU in the system controller 126, includes code, which, when executed by the CPU, performs tasks relating to the plasma processing schemes described herein. The program may include instructions that are used to control the various hardware and electrical components within the plasma processing system 10 to perform the various process tasks and various process sequences used to implement the methods described herein. In some embodiments, the program includes instructions that are used to perform one or more of the operations described below in relation to Figure 2.Voltage Waveform Examples

[0033] Figure 2 illustrates a graph 200 of two separate non-sinusoidal voltage waveforms established at a substrate disposed on the substrate support assembly 136 of the processing chamber 100 due to the delivery of a voltage waveform to the bias electrode 138 of the processing chamber 100, in accordance with certain embodiments of the present disclosure. A first waveform (e.g., a waveform 225) is an example of a non-com pensated voltage waveform established at the substrate during the plasma processing. A second waveform (e.g., a waveform 230) is an example of a compensated voltage waveform established at the substrate by applying a negative slope waveform to the bias electrode 138 of the processing chamber 100 during an “ion current stage” portion of the voltage waveform cycle by use of a current source. The compensated voltage waveform can alternatively be established by applying a negative voltage ramp during the ion current stage of the voltage waveform generated by the voltage waveform generator 175. The voltage waveform cycle of the waveforms 225 and 230 each have a period TP, which is, for example, typically between 2 microsecond (ps) and 10 ps, such as 2.5 ps. The ion current stage of the voltage waveform cycle will typically take up between about 50% and about 95% of the period TP, such as from about 80% to about 90% of the period TP.

[0034] The waveforms 225 and 230 include two main stages: an ion current stage and a sheath collapse stage. Both portions (e.g., the ion current stage and the sheath collapse stage) of the waveforms 225 and 230, can be alternately and / or separately established at the substrate during the plasma processing. At a beginning of the ion current stage, a drop in the voltage at the substrate is created, due to the delivery of a negative portion of the voltage waveform (e.g., the ion current portion) provided toPATENTAtorney Docket No.: 44025569WO01the bias electrode 138 by the voltage waveform generator 175, which creates a high voltage sheath above the substrate. The high voltage sheath allows the plasma generated positive ions to be accelerated towards the biased substrate during the ion current stage, and thus, for RIE processes, controls the amount and characteristics of the etching process that occurs on the surface of the substrate during the plasma processing. The sheath collapse stage includes a positive voltage swing 240 (e.g., as a result of the positive wafer voltage), and the ion current stage includes a negative voltage swing (e.g., as a result of the positive wafer voltage), as illustrated in Figure 2.

[0035] In some embodiments, it is desirable for the ion current stage to include a region of the voltage waveform that achieves the voltage at the substrate that is stable or minimally varying throughout the stage, as illustrated in Figure 2 by the waveform 230. One will note that significant variations in the voltage established at the substrate during the ion current stage, such as shown by the positive slope in the waveform 225, will undesirably cause a variation in the ion energy distribution (IED) and thus cause undesirable characteristics of the etched features to be formed in the substrate during the RIE process. Plasma sheath impedance varies with supplied voltage waveform voltages. The RF match 172 can use either or both of the synchronization signals and / or use its internal sensors to sample impedances in different processing phases. In one example, a synchronization signal or characteristics determined by the input sensor 116 or the output sensor 117 are used to trigger the RF match 172 to determine at least two different impendences at different processing stages. Then, the RF match 172 updates its matching point based on the at least two different impedances.Example Plasma Processing System Circuits for Sensor Calibration

[0036] In some embodiments, one or more sensors may be used in conjunction with a plasma processing system to measure some parameters associated with voltage pulses and / or radio frequency (RF) waveforms used during plasma processing. In some cases, a sensor may measure voltage and / or current information from a plasma processing system and produce, based on a transfer function-based algorithm used by a system controller (e.g., a system controller of the plasma processing system or a system controller included in the sensor itself). The transfer function-based algorithm may depend on the calibration of the sensor, measurements of various parameters of the plasma processing system. For example, the sensor may measure deliveredPATENTAtorney Docket No.: 44025569WO01power, reflected power, harmonics, and other parameters associated with the pulses and / or waveforms. However, without properly calibrated sensors that accurately measure, it is challenging to obtain measurements of meaningful parameters of a plasma processing system (e.g., to better control plasma-assisted processing), especially at the substrate level.

[0037] As discussed above, embodiments of the present disclosure generally relate to an apparatus and methods for testing, adjusting, and / or controlling sensing elements used in a plasma processing system. Aspect of the disclosure include a system that models (e.g., mimics) a plasma processing system to test, adjust and qualify sensors used to detect aspects of the delivery of radio frequency (RF) signals and / or voltage waveforms to one or more electrodes disposed within a plasma processing chamber. The plasma processing system may be modeled by a plasma processing system circuit. In some cases, the plasma processing system circuit may be relatively low-power (e.g., around 200 watts), and may be constructed using various circuit components coupled together and disposed on one or more printed circuit boards (PCBs).

[0038] Figure 3 is a block diagram of an example plasma processing system circuit 300 for sensor calibration that includes a control side 310 and a load side 330, in accordance with certain embodiments of the present disclosure. The plasma processing system circuit 300 may also include a sensor 320 for coupling between the control side 310 and the load side 330. The control side 310 may be configured to effectively model (e.g., represent) the control side (e.g., the voltage waveform generator 175 and related circuitry) of a plasma processing system (e.g., plasma processing system 10). The load side may be configured to effectively model the complex load (e.g., the plasma resistance, inductance, and / or capacitance) created by the generated plasma (e.g., plasma 101 in Figure 1) within the plasma processing system.

[0039] By comparing information measured by the sensor 320 with other measurements taken (e.g., using a probe) on the plasma processing system circuit 300, the sensor 320 can be adjusted until the information measured by the sensor 320 matches the corresponding measurements taken on the plasma processing system circuit 300. After a sensor 320 has been properly calibrated, the sensor 320 mayPATENTAtorney Docket No.: 44025569WO01measure voltage and / or current information from an actual plasma processing system and produce, based on a transfer function-based algorithm that depends on the calibration of the sensor, measurements of various parameters of the plasma processing system. For example, the sensor 320 may be relied upon in plasma processing systems to accurately measure voltage waveforms at the substrate level, the ion flux of a plasma (e.g., plasma 101) within a processing chamber (e.g., processing chamber 100) of the plasma processing system, and / or other important parameters for a wide range of voltages, frequencies, and / or duty cycles. In this manner, the calibrated sensor 320 may serve a key diagnostic role during plasma-assisted processing. In some embodiments, the transfer function-based algorithm used by the sensor may be stored in memory (e.g., memory included in a system controller 126 or memory included in the sensor itself) and may be used by the system controller to modify the measurements associated with the voltage pulses and / or RF waveforms taken using the calibrated sensor.

[0040] Figure 4A is a schematic diagram of an example plasma processing system circuit 400A for sensor calibration that includes a pulser circuit 410 and a chamber circuit 450, in accordance with certain embodiments of the present disclosure. The plasma processing system circuit 400A is an example implementation of the plasma processing system circuit 300 and may thus include the control side 310, the sensor 320, and the load side 330, as illustrated. In some cases, the sensor 320 may be implemented as a voltage-current (VI) sensor configured to measure voltage and current. It is to be understood that each of the components in the plasma processing system circuit 400A may model (e.g., mimic) parts of an actual plasma processing system to enable calibration of the sensor 320.

[0041] The control side 310 may include the pulser circuit 410, a damping circuit 420, and a direct current (DC) blocking capacitor circuit 430. The pulser circuit 410 may include a DC supply 412, a DC converter 414, a charging field-effect-transistor (FET) (or a metal-oxide-sem iconductor field-effect transistor (MOSFET)) 416 (which may be implemented, for example, by a switching network), and a discharging FET (or MOSFET) 418 (which may be implemented, for example, by another switching network), and may represent a waveform generator (e.g., voltage waveform generator 175). The DC supply 412 may be coupled to the DC converter 414, and the DC converter 414 may be coupled to the charging FET 416 and the discharging FET 418.PATENTAtorney Docket No.: 44025569WO01The DC supply 412, the DC converter 414, and the discharging FET 418 may be coupled to a reference potential node 350 (e.g., electrical ground, via port 472). The damping circuit 420 may be coupled to the charging FET 416, and the DC blocking capacitor circuit 430 may be coupled to the damping circuit 420. The pulser circuit 410 may include an input coupled to the reference potential node 350 and an output coupled to the damping circuit 420. The DC blocking capacitor circuit 430 may include a first terminal coupled to the output of the pulser circuit 410.

[0042] The load side 330 may include an inductive element 440, which may represent elements that form a connection to a cathode, such as elements coupling the power supply to the electrode within the substrate support assembly 136, and the chamber circuit 450. The chamber circuit 450 may include a capacitive element 452 (labeled “Parasitic Capacitance,” which may represent the parasitic capacitance in the processing chamber 100), electrostatic chuck (ESC) capacitance 454 (labeled “ESC Capacitance,” which may represent the substrate or wafer in the processing chamber 100), and the load 456 (labeled “Plasma,” which may represent the plasma 101 (e.g., complex impedance)). The inductive element 440 may be coupled to the capacitive element 452 and the ESC capacitance 454. The capacitive element 452 and the ESC capacitance 454 may be coupled to the load 456. The load 456 may be coupled to the reference potential node 350 (e.g., via port 474). In some cases, the pulser circuit 410 may be coupled to the chamber circuit 450 via ports 462 and 464. For example, a node coupled between the charging FET 416 and the discharging FET 418 may be coupled to the capacitive element 452 and the load 456, as illustrated.

[0043] In some cases, the charging FET 416 may be implemented as a first metal-oxide-sem iconductor field-effect transistor (MOSFET) (or a switching network) and may be configured to deliver a pulsed voltage waveform to the load side 330 during a pulse on period (e.g. , when the pulser circuit 410 is generating a pulse or pulses). The discharging FET 418 may be implemented as a second MOSFET (or a switching network) and may be configured to discharge stored electrical charge from the inductive element 440 and / or the capacitive element 452 during a pulse off period (e.g., when the pulser circuit 410 is not generating a pulse or pulses). The charging FET 416 and the discharging FET 418 may be coupled together. In some cases, there may be a delay between the pulse on period and the pulse off period (e.g., to avoid any damage, such as shoot through, a short-circuit scenario, and the like).PATENTAtorney Docket No.: 44025569WO01

[0044] The sensor 320 may include an input for coupling to an output of the DC blocking capacitor circuit 430 (e.g., via port 422). The sensor input may receive (e.g., measure) voltage and / or current information from output of the DC blocking capacitor circuit 430. Each of the circuit components on the control side 310 may be disposed on a PCB, and may be connected via wires 460 (or traces, or other electrically conductive material). The sensor 320 may include an output for coupling to a terminal of the inductive element 440 (e.g., via port 424). Each of the circuit components on the load side 330 may be disposed on a PCB, and may be connected via wires 461 (or traces, or other electrically conductive material. In some cases, the control side 310 (including the pulser circuit 410) may be disposed on a first PCB, and the load side 330 (including the chamber circuit 450) may be disposed on a second PCB, whereas in other cases, the control side 310 (including the pulser circuit 410) and the load side 330 (including the chamber circuit 450) may both be disposed on the same PCB.

[0045] In some cases, the DC supply 412 may include a first terminal coupled to the reference potential node 350, the DC converter 414 may include a first terminal coupled to the reference potential node 350, and the damping circuit 420 may include an input coupled to a second terminal of the DC supply 412, a second terminal of the DC converter 414, and the charging FET 416. In these cases, the DC blocking capacitor circuit 430 may include a first terminal coupled to an output of the damping circuit 420 and include a second terminal configured to be coupled to the input of the sensor 320 (at port 422), the inductive element 440 may include a first terminal configured to be coupled to the output of the sensor 320 (at port 424), and the capacitive element 452 may include a first terminal coupled to a second terminal of the inductive element 440 and include a second terminal coupled to the reference potential node 350. In addition, and in these cases, the ESC capacitance 454 may include a first terminal coupled to the second terminal of the inductive element 440, and the load 456 may be coupled between a second terminal of the ESC capacitance 454 and the reference potential node.

[0046] In some embodiments, the control side 310 may be implemented on a first PCB, the first PCB may have an output coupled to a second terminal of the DC blocking capacitor circuit 430, and the output of the first PCB may be configured to be coupled to the input of the sensor 320. In these embodiments, the load side 330 mayPATENTAtorney Docket No.: 44025569WO01be implemented on a second PCB, and the second PCB may include an input configured to be coupled to the output of the sensor 320.

[0047] Figure 4B is an example circuit diagram 400B of the plasma processing system circuit 400A for sensor calibration of Figure 4A, in accordance with certain embodiments of the present disclosure. The plasma processing system circuit 400A may be implemented with various circuit components. As illustrated in the circuit diagram 400B, the DC supply 412 may be implemented by DC supply P1 , the charging FET 416 may be implemented by a p-type (or n-type) MOSFET M1 with a driver 482, the discharging FET 418 may be implemented by a p-type (or n-type) MOSFET M2 with a driver 484, and the DC blocking capacitor circuit 430 may be implemented by capacitor C1. In addition, the inductive element 440 may be implemented by inductor L1, capacitive element 452 may be implemented by capacitor C2, and ESC capacitance 454 may be implemented by capacitor C3, and the load 456 may be implemented using diodes DSH and DWALL, capacitors CSH and CWALL, resistive element RPLASMA, and current sources IWALL and li. It is to be understood that that the circuit diagram 400B is merely an example of an implementation of the plasma processing system circuit 400A. Any number of other circuit configurations (with other combinations of circuit components) may be used. For example, each of DC blocking capacitor circuit 430, capacitive element 452, and ESC capacitance 454 may be implemented with any number of capacitive elements, charging FET 416 and discharging FET 418 may each be implemented with any number or type of transistors (or any type of switching networks), and the load may be implemented with any other suitable circuit configuration.

[0048] In some cases, after being coupled between the control side 310 and the load side 330, the sensor 320 may measure (e.g., during generation of a pulsed voltage (PV) waveform with the pulser circuit) a voltage (and / or a current) at the output of the sensor 320, and a probe (not shown) may be used to measure a voltage (and / or a current) at the one or more nodes of the plasma processing system circuit. The one or more nodes of the plasma processing system circuit may include, for example, the output of the sensor (e.g., the same node as measured by the sensor 320). In this manner, the voltage (and / or a current) at the output of the sensor 320 and the voltage (and / or a current) measured by the probe may be compared (e.g., using the known values associated with the circuit components in the plasma processing system circuitPATENTAtorney Docket No.: 44025569WO01400A or 400B), and the calibration of the sensor 320 may be adjusted in accordance with the comparison to properly calibrate the sensor.

[0049] After a sensor 320 has been properly calibrated, the sensor 320 may measure voltage and / or current information from a plasma processing system and produce measurements of various parameters of the plasma processing system. The produced measurements may be based on a transfer function-based algorithm that depends on the calibration of the sensor that is used by the controller to adjust the real-time sensor readings. For example, the sensor 320 may be relied upon in real plasma processing systems to accurately measure voltage waveforms at the substrate level, the ion flux of a plasma (e.g., plasma 101) within a processing chamber (e.g., processing chamber 100) of the plasma processing system, and / or other important parameters for a wide range of voltages, frequencies, and / or duty cycles. In this manner, the calibrated sensor 320 may serve a key diagnostic role during plasma-assisted processing.Example Operations for Sensor Calibration

[0050] Figure 5 is a flow diagram illustrating example operations 500 for sensor calibration, in accordance with certain embodiments of the present disclosure. The operations 500 may be performed using a plasma processing system circuit, such as the plasma processing system circuit 300, 400A, or 400B of Figures 3, 4A, and 4B respectively and with one or more sensors, such as the sensor 320 of Figures 3, 4A, and 4B. In some cases, the one or more sensors may be implemented by a voltagecurrent (VI) sensor.

[0051] In some embodiments, the operations 500 may optionally include removing (e.g., decoupling) the sensor from a first position within a power delivery circuit (e.g., RF generator 171 and / or voltage waveform generator 175) of a plasma processing system. In other embodiments, the operations 500 may optionally include providing the sensor that is to be positioned in the first position within the power delivery circuit of the plasma processing system. The removing or providing the sensor may be performed before block 510, which is described below. In some configurations, the first position within the plasma processing system can be, for example, a position in which a sensor is coupled between an (e.g., RF generator 171) and an electrode (e.g., bias electrode 138) within the plasma processing chamber or a position in which thePATENTAtorney Docket No.: 44025569WO01sensor is coupled between a voltage waveform generator (e.g., voltage waveform generator 175) and the electrode within the plasma processing chamber.

[0052] The operations 500 may include, at block 510, coupling an input of the sensor to a pulser circuit (e.g., pulser circuit 410) included in a plasma processing system circuit (e.g., plasma processing system circuit 300, 400A, or 400B) and an output of the sensor to a chamber circuit (e.g., chamber circuit 450) included in the plasma processing system circuit.

[0053] At block 520, the operations 500 may include effectively modeling (e.g., mimicking), using the plasma processing system circuit, a plasma processing system (e.g., plasma processing system 10), as described herein.

[0054] At block 530, the operations 500 may include generating, using the pulser circuit, a pulsed voltage (PV) waveform (e.g., waveform 225 or waveform 230).

[0055] At block 540, the operations 500 may include measuring, using the sensor, a voltage provided to the input of the sensor.

[0056] At block 550, the operations 500 may include providing an output signal to a system controller (e.g., system controller 126) using a first transfer function (e.g., a transfer function-based algorithm). In some cases, the first transfer function may be applied to the voltage (and / or other measurements taken using the sensor) at block 540 to produce the output signal. In this manner, the voltage (and / or other measurements taken using the sensor) at block 540 may be adjusted by the first transfer function (e.g., in accordance with the calibration of the sensor).

[0057] At block 560, the operations 500 may include measuring, using a probe, a voltage at one or more nodes of the chamber circuit. In some cases, the one or more nodes of the chamber circuit may include a node positioned at the output of the sensor. In this manner, the voltage measured by the sensor at the output of the sensor and the voltage measured by the probe at the output of the sensor may be compared, and the calibration of the sensor, controlled by the transfer function-based algorithm, may be adjusted until the sensor measurement matches the probe measurement.

[0058] At block 570, the operations 500 may include adjusting, based on the voltage at the output and the voltage at the one or more nodes of the chamber circuit, a calibration of the sensor used by the system controller by transferring the first transferPATENTAtorney Docket No.: 44025569WO01function to the system controller. The system controller may be included in the plasma processing system, or in the sensor itself.

[0059] According to certain embodiments, the operations 500 may include, ( / ') after adjusting the calibration of the sensor, decoupling the sensor from the pulser circuit and the chamber circuit, and ( / ' / ) after decoupling the sensor from the pulser circuit and the chamber circuit, coupling the sensor to the first position within the power delivery circuit (e.g., a power delivery system coupled to an electrode within a processing region of a processing chamber in the plasma processing system, such as voltage waveform generator 175 and / or high voltage DC supply 173). In this manner, the sensor may be used in conjunction with actual plasma processing systems and relied upon for accurate measurements (e.g., to enable improved control of the plasma processing system), as described herein.

[0060] According to certain embodiments, the operations 500 may include, before coupling the input of the sensor to the pulser circuit and the output of the sensor to the chamber circuit, decoupling the sensor from the power delivery circuit (e.g., from the plasma processing system).

[0061] In some cases, the pulser circuit may be disposed on a first printed circuit board (PCB) and the chamber circuit may be disposed on a second PCB, whereas in other cases, the pulser circuit and the chamber circuit may both be disposed on the same PCB.

[0062] The pulser circuit may include a power supply (e.g., DC supply 412) coupled to a damping circuit (e.g., damping circuit 420), a converter (e.g., converter 414) coupled to the power supply, a first transistor (e.g., charging FET 416) coupled to the damping circuit, and a second transistor (e.g., discharging FET 418) coupled to the first transistor. In these cases, the chamber circuit may include an inductive element (e.g., inductive element 440), a second capacitive element (e.g., capacitive element 452) coupled to the inductive element, a load (e.g., load 456) coupled to the second capacitive element and to a reference potential node (e.g., reference potential node 350), and a third capacitive element (e.g., ESC capacitance 454) coupled to the inductive element and to the load.

[0063] In some cases, the first transistor may include a first metal-oxide-sem iconductor field-effect transistor (MOSFET) and may be configured to deliver aPATENTAtorney Docket No.: 44025569WO01pulsed voltage waveform during a pulse on period, and the second transistor may include a second MOSFET and may be configured to discharge stored electrical charge from the inductive element and the second capacitive element during a pulse off period.Additional Considerations

[0064] In the above description, details are set forth by way of example to facilitate an understanding of the disclosed subject matter. It should be apparent to a person of ordinary skill in the field, however, that the disclosed implementations are exemplary and not exhaustive of all possible implementations. Thus, it should be understood that reference to the described examples is not intended to limit the scope of the disclosure. Any alterations and further modifications to the described devices, instruments, methods, and any further application of the principles of the present disclosure are fully contemplated as would normally occur to one skilled in the art to which the disclosure relates. In particular, it is fully contemplated that the features, components, and / or steps described with respect to one implementation may be combined with the features, components, and / or steps described with respect to other implementations of the present disclosure. As used herein, the term “about” may refer to a + / -10% variation from the nominal value. It is to be understood that such a variation can be included in any value provided herein.

[0065] As used herein, “a processor,” “at least one processor,” or “one or more processors” generally refers to a single processor configured to perform one or multiple operations or multiple processors configured to collectively perform one or more operations. In the case of multiple processors, performance of the one or more operations could be divided amongst different processors, though one processor may perform multiple operations, and multiple processors could collectively perform a single operation. Similarly, “a memory,” “at least one memory” or “one or more memories” generally refers to a single memory configured to store data and / or instructions, multiple memories configured to collectively store data and / or instructions.

[0066] As used herein, a phrase referring to “at least one of” or “one or more of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, andPATENTAtorney Docket No.: 44025569WO01a-b-c, as well as any combination with multiples of the same element (e.g., a-a, a-a-a, a-a-b, a-a-c, a-b-b, a-c-c, b-b, b-b-b, b-b-c, c-c, and c-c-c or any other ordering of a, b, and c).

[0067] The methods disclosed herein comprise one or more steps or actions for achieving the described method. The method steps and / or actions may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of specific steps and / or actions may be modified without departing from the scope of the claims.

[0068] The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B and object B touches object C, then objects A and C may still be considered coupled to one another — even if objects A and C do not directly physically touch each other. For instance, a first object may be coupled to a second object even though the first object is never directly physically in contact with the second object.

[0069] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

PATENTAtorney Docket No.: 44025569WO01We claim:

1. A plasma processing system circuit comprising:a first printed circuit board (PCB) comprising:a pulser circuit comprising an input coupled to a reference potential node and an output;a first capacitive element comprising a first terminal coupled to the output of the pulser circuit and a second terminal; and a first PCB output coupled to the second terminal of the first capacitive element; anda second PCB comprising:a second PCB input node;an inductive element coupled to the second PCB input node; a second capacitive element coupled to the inductive element; anda load coupled to the second capacitive element and to the reference potential node,wherein first PCB output is configured to be coupled to an input of a sensor and the second PCB input node is configured to be coupled to an output of the sensor.

2. The plasma processing system circuit of claim 1 , wherein the sensor is configured to measure voltage and current.

3. The plasma processing system circuit of claim 1 , wherein the load is coupled to the pulser circuit.

4. The plasma processing system circuit of claim 1 , wherein the first PCB further comprises a damping circuit coupled between the pulser circuit and the first terminal of the first capacitive element and wherein the second PCB further comprises a third capacitive element coupled to the inductive element and to the load.

5. The plasma processing system circuit of claim 4, wherein the pulser circuit comprises:PATENTAtorney Docket No.: 44025569WO01a power supply;a converter coupled to the power supply;a first transistor coupled to the damping circuit; anda second transistor coupled to the first transistor.

6. The plasma processing system circuit of claim 5, wherein:the first transistor comprises a first metal-oxide-sem iconductor field-effect transistor (MOSFET) and is configured to deliver a pulsed voltage waveform during a pulse on period; andthe second transistor comprises a second MOSFET and is configured to discharge stored electrical charge from the inductive element and the second capacitive element during a pulse off period.

7. The plasma processing system circuit of claim 1 , wherein the plasma processing system circuit is configured to model a plasma processing system.

8. A plasma processing system circuit comprising:a pulser circuit comprising:a first transistor;a second transistor coupled to the first transistor;a power supply including a first terminal coupled to a reference potential node; anda converter including a first terminal coupled to the reference potential node;a damping circuit including an input coupled to a second terminal of the power supply, a second terminal of the converter, and the first transistor;a first capacitive element including a first terminal coupled to an output of the damping circuit and including a second terminal configured to be coupled to an input of a sensor;an inductive element including a first terminal configured to be coupled to an output of the sensor;PATENTAtorney Docket No.: 44025569WO01a second capacitive element including a first terminal coupled to a second terminal of the inductive element and including a second terminal coupled to the reference potential node;a third capacitive element including a first terminal coupled to the second terminal of the inductive element; anda load coupled between a second terminal of the third capacitive element and the reference potential node.

9. The plasma processing system circuit of claim 8, wherein a node coupled between the first transistor and the second transistor is coupled to the second terminal of the second capacitive element and the load.

10. The plasma processing system circuit of claim 8, wherein the sensor is configured to measure voltage and current.

11. The plasma processing system circuit of claim 8, further comprising a first printed circuit board (PCB), wherein the pulser circuit, the damping circuit, and the first capacitive element are disposed on the first PCB.

12. The plasma processing system circuit of claim 10, further comprising a second PCB, wherein the load, the second capacitive element, the third capacitive element, and the inductive element are disposed on the second PCB.

13. The plasma processing system circuit of claim 12, wherein:the first transistor comprises a first metal-oxide-sem iconductor field-effect transistor (MOSFET) and is configured to deliver a pulsed voltage waveform during a pulse on period; andthe second transistor comprises a second MOSFET and is configured to discharge stored electrical charge from the inductive element and the second capacitive element during a pulse off period.

14. A method of calibrating a sensor, the method comprising:PATENTAtorney Docket No.: 44025569WO01coupling an input of the sensor to a pulser circuit included in a plasma processing system circuit and an output of the sensor to a chamber circuit included in the plasma processing system circuit;effectively modeling, using the plasma processing system circuit, a plasma processing system;generating, using the pulser circuit, a pulsed voltage (PV) waveform; measuring, using the sensor, a voltage provided to the input of the sensor; providing an output signal to a system controller using a first transfer function; measuring, using a probe, a voltage at one or more nodes of the chamber circuit; andadjusting, based on the voltage at the output of the sensor and the voltage at the one or more nodes of the chamber circuit, a calibration of the sensor used by the system controller by adjusting the first transfer function.

15. The method of claim 14, wherein the one or more nodes of the chamber circuit comprise the output of the sensor.

16. The method of claim 14, further comprising:after adjusting the calibration of the sensor, decoupling the sensor from the pulser circuit and the chamber circuit; andafter decoupling the sensor from the pulser circuit and the chamber circuit, coupling the sensor to a first position within a power delivery circuit.

17. The method of claim 16, further comprising:before coupling the input of the sensor to the pulser circuit and the output of the sensor to the chamber circuit, removing the sensor from the first position within the power delivery circuit of a plasma processing system.

18. The method of claim 14, wherein the pulser circuit is disposed on a first printed circuit board (PCB) and wherein the chamber circuit is disposed on a second PCB.

19. The method of claim 14, whereinPATENTAtorney Docket No.: 44025569WO01the pulser circuit comprises:a power supply coupled to a damping circuit;a converter coupled to the power supply;a first transistor coupled to the damping circuit; anda second transistor coupled to the first transistor; andthe chamber circuit comprises:an inductive element;a second capacitive element coupled to the inductive element;a load coupled to the second capacitive element and to a reference potential node; anda third capacitive element coupled to the inductive element and to the load.

20. The method of claim 19, wherein:the first transistor comprises a first metal-oxide-sem iconductor field-effect transistor (MOSFET) and is configured to deliver a pulsed voltage waveform during a pulse on period; andthe second transistor comprises a second MOSFET and is configured to discharge stored electrical charge from the inductive element and the second capacitive element during a pulse off period.

Images