Improving yield of semiconductor wafers

Abstract

Techniques disclosed herein relate to improving yield of semiconductor wafers. The techniques may involve receiving indications of a set of process parameters, a set of virtual metrology measurements and a set of physical metrology measurements. The techniques may further involve pairing physical metrology measurements of the set of physical metrology measurements with corresponding virtual metrology measurements of the set of virtual metrology measurements to form a set of paired metrology measurements. The techniques may further involve transmitting instructions for training a digital twin of a semiconductor fabrication apparatus based on the set of process parameters and the paired metrology measurements to generate a trained digital twin. The techniques may further involve receiving an indication of a change in at least one physical metrology measurement or at least one virtual metrology measurement to be achieved to increase a yield in semiconductor wafers, the change determined using the trained digital twin.

Description

Docket No. LAM1P136WOIMPROVING YIELD OF SEMICONDUCTOR WAFERSINCORPORATION BY REFERENCE

[0001] A PCT Request Form is filed concurrently with this specification as part of the present application. Each application that the present application claims benefit of or priority to as identified in the concurrently filed PCT Request Form is incorporated by reference herein in their entireties and for all purposes.BACKGROUND

[0002] When a new semiconductor technology is developed, e.g., to develop a new processed wafer or the like, the technology may take months or even years to develop in order to identify a process that yields a wafer having desired specifications. In particular, much time is spent to develop a process with a high yield, defined as a percentage of the wafers that undergo processing that meet target specifications. Improving process development and more generally improving yield more quickly is critical.

[0003] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.SUMMARY

[0004] Techniques disclosed herein relate to improving yield of semiconductor wafers. The techniques may be practiced with a processor-implemented method, a system comprising one or more processors and one or more processor-readable media, and / or one or more non-transitory processor- readable media.

[0005] In some embodiments, the techniques may involve (a) receiving indications of a set of process parameters, a set of virtual metrology measurements and a set of physical metrology measurements. The techniques may further involve (b) pairing physical metrology measurements of the set of physical metrology measurements with corresponding virtual metrology measurements of the set of virtual metrology measurements to form a set of paired metrology measurements. The techniques may further involve (c) transmitting instructions for training a digital twin of a semiconductor fabrication apparatus based on the set of processDocket No. LAM1P136WOparameters and the paired metrology measurements to generate a trained digital twin. The techniques may further involve (d) receiving an indication of a change in at least one physical metrology measurement or at least one virtual metrology measurement to be achieved to increase a yield in semiconductor wafers, wherein the change is determined using the trained digital twin, and wherein the yield is determined based on a percentage of processed wafers that meet a set of target wafer specifications.

[0006] In some examples, the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is identified using a Pareto analysis of at least a subset of the set of process parameters, a subset of the virtual metrology measurements, and / or a subset of the physical metrology measurements. In some examples, the subset of the set of process parameters, the subset of the virtual metrology measurements, and / or the subset of the physical metrology measurements are selected via a user interface. In some examples, the subset of the set of process parameters are ranked based on contribution to variability of the subset of the virtual metrology measurements, and / or the subset of the virtual metrology measurements are ranked by an effect of process parameter variation on variability of the virtual metrology measurements. In some examples, the techniques further involve presenting the rankings.

[0007] In some examples, the indication of the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is presented in a box plot depicting a current median and range of the at least one physical metrology measurement or the at least one virtual metrology measurement and a target median and range of the at least one physical metrology measurement or the at least one virtual metrology measurement to be achieved.

[0008] In some examples, the digital twin is configured to generate virtual metrology measurements that match a sensitivity and a variability of physical metrology measurements produced in a physical fabrication environment.

[0009] In some examples, the set of virtual metrology measurements comprises at least one virtual metrology measurement that does not have a corresponding physical metrology measurement.

[0010] In some examples, (a) occurs within a user interface, and wherein the indication of the at least one change to be achieved in (d) is presented within the same user interface.

[0011] In some examples, operations (a) - (d) occur in a period of time of less than two weeks. In some examples, (b) - (d) occur in an automated sequence. In some examples, (b) - (d) occur in a period of time of one week or less.Docket No. LAM1P136WO

[0012] In some examples, (b), (c), and (d) comprise transmitting and / or receiving information obtained via a user interface to a backend system via an application programming interface (API). In some examples, training the digital twin and identifying the change in the at least one physical metrology measurement or at the at least one virtual metrology measurement comprise utilizing compiled source code not accessible via the user interface.

[0013] In some examples, the change in the at least one physical metrology measurement or the at least one virtual metrology measurement comprise a plurality of changes.

[0014] In some examples, the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is determined using the trained digital twin and based on the set of target wafer specifications. In some examples, the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is determined based on at least one identified failure mode. In some examples, the at least one identified failure mode corresponds to a virtual metrology measurement that is not within a corresponding specification of the set of target wafer specifications.BRIEF DESCRIPTION OF THE DRAWINGS

[0015] FIG. 1 is an example graph illustrating yield as a function of time during process development in accordance with some embodiments.

[0016] FIG. 2 is a block diagram of an example system for improving yield in accordance with some embodiments.

[0017] FIG. 3 is an example user interface for configuring model variables in accordance with some embodiments.

[0018] FIG. 4 is an example user interface for pairing model metrology variables with physical metrology variables in accordance with some embodiments.

[0019] FIG. 5 is an example user interface for configuring target specifications for a fabrication process in accordance with some embodiments.

[0020] FIGS. 6 and 7 are user interfaces associated with training of a digital twin representing a fabrication process in accordance with some embodiments.

[0021] FIGS. 8 and 9 are user interface associated with ranking variables based on contribution to yield variability in accordance with some embodiments.

[0022] FIGS. 10 and 11 are user interfaces associated with a Pareto analysis of failures associated with a fabrication process in accordance with some embodiments.

[0023] FIGS. 12A and 12B illustrate contributions to failure of various factors before and after a metrology re-targeting process, respectively, in accordance with some embodiments.Docket No. LAM1P136WO

[0024] FIGS. 13A and 13B illustrate box plots of re-targeted metrology variables in accordance with some embodiments.

[0025] FIG. 14 is a flowchart of an example process for improving yield of semiconductor wafers in accordance with some embodiments.

[0026] FIG. 15 presents an example computer system that may be employed to implement certain embodiments described herein.DETAILED DESCRIPTION

[0027] In the following description, numerous specific details are set forth to provide a thorough understanding of the presented embodiments. The disclosed embodiments may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail to not unnecessarily obscure the disclosed embodiments. While the disclosed embodiments will be described in conjunction with the specific embodiments, it will be understood that it is not intended to limit the disclosed embodiments.

[0028] When a new semiconductor technology is developed, e.g., to develop a new processed wafer or the like, the technology may take months or even years to develop in order to identify a process that yields a wafer having desired specifications. In particular, much time is spent to develop a process with a high yield, defined as a percentage of the wafers that undergo processing that meet target specifications and are thus useful. Conventional techniques involve a highly manual process for increasing yield. In particular, over the course of months, wafers that have undergone processing are analyzed to determine wafer statistics, which may include metrology indicative of whether or not a wafer meets the target specifications. Based on the wafer statistics, process changes may be identified that are to be implemented. This process may repeat several times, with each cycle (e.g., of obtaining wafer metrology data, analyzing wafer statistics, and implementing a process change) lasting weeks or even months. Moreover, manual process changes are typically identified such that each process change or set of process changes are identified to improve one metrology measurement or outcome, or in other words, one possible failure mode. The manual nature of the process, and optimization based on one failure mode at a time, causes conventional techniques for improving yield to be extremely slow, such that the iterative process may take over a year to identify a robust process with high yield.

[0029] Disclosed herein are techniques for improving yield of semiconductor wafers. In particular a digital twin is trained that is configured to generate virtual metrology measurementsDocket No. LAM1P136WOthat are aligned with and match physical metrology measurements generated in a physical fabrication environment for a given process. Once the digital twin is trained, based on paired virtual metrology and physical metrology data, the digital twin may be used to identify one or more process parameters or metrology measurements that highly contribute to failure. Based on this analysis, sometimes referred to as a “Pareto analysis,” optimized metrology measurements that are to be targeted are provided to the end user. Note that these optimized metrology measurements are sometimes referred to herein as “re-targeted” metrology measurements, because they indicate a new target that is to be achieved. The optimized metrology measurements may be used to identify process changes in a next iteration, where the optimized metrology measurements are guaranteed to generate an improvement in yield. One iterative cycle of the techniques disclosed herein may be completed on the order of 1-2 weeks, substantially speeding up the time to develop a fabrication process with high yield. Note that the improvement in speed of determining parameters for a next iterative cycle are due to use of the digital twin which is trained to generate virtual metrology measurements that match the physical metrology measurements of a particular fabrication environment, thereby ensuring that the digital twin is simulating the physical fabrication process in the particular fabrication environment accurately. Moreover, the Pareto analysis based on such a trained digital twin enables the speed up in iterative cycles, because the Pareto analysis can be performed in an automated fashion based on the results of the digital twin.

[0030] As used herein, a “digital twin” is a virtual representation of a physical fabrication process, metrology measurements associated with a fabrication wafer, and failure detection. In other words, a digital twin, as described herein generally is comprised of three components: 1) a fabrication process simulation; 2) virtual metrology that simulates measurements of a virtually fabricated wafer (e.g., fabricated using the fabrication process simulation; and 3) virtual failure detection that simulates the physical testing of wafers in a fabrication environment to determine yield. A digital twin may represent a particular physical fabrication process (e.g., an etch process, a deposition process, a lithography process, etc.) in a particular fabrication environment. As will be described below in more detail, a digital twin may be trained and calibrated to mirror the characteristics of the particular fabrication process when performed in the particular fabrication environment. In particular, the digital twin may be trained and calibrated to generate virtual metrology measurements that match (e.g., are the same within an error threshold, such as + / - 1%, + / - 5%, etc.) physical metrology measurements generated in the particular fabrication environment. Note that, while the digital twin is comprised of three components as described above, training of the digital twin is with respectDocket No. LAM1P136WOto the metrology component. The virtual and physical metrology measurements of the trained digital twin may match in terms of median, variability, and / or sensitivity. Because the digital twin is trained to generate virtual metrology measurements that match the physical metrology measurements, the digital twin may be utilized to recommend optimized, or re-targeted metrology measurements that, if achieved in the physical fabrication environment, are likely to improve the yield of wafers processed in the physical fabrication environment. Additionally, the digital twins described herein may additionally be configured to generate virtual metrology measurements that cannot be physically measured in the fabrication environment, e.g., due to being destructive.Virtual Fabrication Engines

[0031] It should be noted that the techniques disclosed herein may utilize a virtual fabrication environment. For example, a digital twin may utilize a virtual fabrication environment to simulate a fabrication process and / or to perform virtual metrology. A virtual fabrication environment for semiconductor device structures offers a platform for performing semiconductor process development at a lower cost and higher speed than is possible with conventional trial-and-error physical experimentation. In contrast to conventional computer-aided design (CAD) and technology CAD (TCAD) environments, a virtual fabrication environment is capable of virtually modeling an integrated process flow and predicting the complete 3D structures of all devices and circuits that comprise a full technology suite. Virtual fabrication can be described in its most simple form as combining a description of an integrated process sequence with a subject design, in the form of 2D design data (masks or layout), and producing a 3D structural model that is predictive of the result expected from a real / physical fabrication run. A 3D structural model includes the geometrically accurate 3D shapes of multiple layers of materials, implants, diffusions, etc. that comprise a chip or a portion of a chip. Virtual fabrication is done in a way that is primarily geometric, however the geometry involved is instructed by the physics of the fabrication processes. By performing the modeling at the structural level of abstraction (rather than physics-based simulations), construction of the structural models can be dramatically accelerated, enabling full technology modeling, at a circuit-level area scale. The use of a virtual fabrication environment thus provides fast verification of process assumptions, and visualization of the complex interrelationship between the integrated process sequence and the 2D design data.

[0032] As discussed above, virtual metrology measurements may be made within a virtual fabrication environment. The virtual metrology measurements may be used to train the digital twin, predict yield, optimize yield, etc., as will be discussed below in more detail. Because ofDocket No. LAM1P136WOthe large number of structural dimensions that are critical to the success of an integrated technology such as semiconductor devices, finding the relationship between the many interrelated process steps used to fabricate a device structure and the created structure is critical. As structural modifications produced by a step in the process sequence may be affected by previous and subsequent steps in the sequence, a particular step may affect a structural dimension in ways that are not obvious. A virtual fabrication environment enables automatic extraction of structural measurements from the device being created. The automatic extraction of a measurement is accomplished by specifying a virtual metrology measurement step in the process sequence at a point in the process when the measurement is critical. A locator shape for this virtual metrology measurement can be added to a layer in the design data and specified by the virtual metrology measurement step. The output data from this virtual metrology measurement can be used to provide quantitative comparison to other modeling results or to physical metrology measurements. This virtual metrology measurement capability is provided by during the processing sequence to extract a critical physical dimension at the correct point in the integrated process flow.

[0033] As will be discussed below in more detail, in some cases, a virtual metrology measurement may have a paired physical metrology measurement that is measured in-fab. Additionally or alternatively, virtual metrology measurements without a physical metrology counterpart may be considered in the techniques disclosed herein. Typically, physical in-fab measurements are done on specific characterization structures fabricated in the scribe lines or saw kerfs, adjacent to the product dice. In most cases, these characterization structures need to be designed to accommodate limitations of the measurement technique, such as optical spot size. Therefore, the characterization structures are not entirely representative of the actual structures on the product dice. Because of these differences, users of in-fab measurements usually face the challenge of inferring the result on the product structure from a measurement on a characterization structure. In the virtual fabrication environment, measurements can be added to any design layout at specified points in the process sequence thus providing greater insight into the effect of the inter-related process steps on the virtual structural model being constructed. As such, the in-fab challenge of measuring a characterization structure and inferring the result on a product structure is eliminated.

[0034] Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) may be performed in the virtual fabrication environment. DRCs and ORCs have typically been performed by specialized software on 2D design data as part of the process of preparing 2D design data for conversion into photolithography masks. Such checks are performed for purposes ofDocket No. LAM1P136WOidentifying errors in the layout that would result in non-functional or poorly functioning chips. The checks are also performed after adding compensations for optical effects such as optical proximity correction (OPC). Typical design rules (as published in design manuals and coded in DRC decks) are simple 2D criteria intended to prevent problems that are fundamentally 3D in nature. However, with the growing complexity of semiconductor process technology, design manuals have blossomed into thousand-page documents with thousands of 2D design rules to codify and explain. In many cases, a single 3D failure mechanism / concem can drive hundreds of 2D design rules. The development of those 2D design rules requires significant assumptions about the 3D nature of the integrated process flow and resulting structures.

[0035] 2D DRCs are developed from relatively simple calculations that may result in overly conservative designs. For example, consider the 2D design rules required to assure a minimum contact area between a line on a metal interconnect layer and an underlying via. A via is a vertical, electrically conductive connector between two interconnect layers, also called metal layers, or a vertical connector between an interconnect layer and a device such as a transistor, resistor or capacitor.

[0036] Many additional 2D DRCs are required to satisfy a criterion that is very simple to state in 3D: that the contact area between metal lines and vias must exceed a specified threshold value. The 2D DRC situation becomes even more complex when one considers that multiple manufacturing variations can affect the contact area, including over or under-exposure during lithography steps, mis-registration of the masks, planarization (via chemical mechanical polishing (CMP)) of the via layer, and the sidewall tapers produced by plasma etching. It is infeasible to include all of these statistical variations in the simple formulae that drive 2D DRCs, so the DRCs are stricter than necessary to guard against manufacturing variations. These overly strict 2D DRCs may result in sub-optimal designs with wasted area on the die.

[0037] In contrast to a 2D DRC environment, a virtual fabrication environment may perform checks, such as minimum line width, minimum space between features, and minimum area of contacts, directly in 3D without making assumptions about the translation from 2D to 3D. Checks performed directly in 3D are referred to herein as "3D DRCs". One benefit of 3D DRC is that the required number of checks is significantly smaller than the number required in 2D environments. As a result, the checks are more robust and easier to develop than 2D checks. Furthermore, with a much smaller set of 3D rules, the virtual fabrication environment can perform the checks for a range of statistical variations in process parameters.

[0038] It should be appreciated that 3D-DRCs are distinct from virtual measurement / metrology operations that may also be performed in the virtual fabricationDocket No. LAM1P136WOenvironment. The virtual measurement metrology operations mimic actual measurement and metrology operations in the fab, whereby a measurement location is specified and a metric such as a distance value or area is output. For 3D DRCs, on the other hand, a geometric criterion is specified and the location and value of the criterion are desired. That is, the location is an output of the 3D DRC operation rather than an input. For example, a virtual metrology operation may specify an oxide film thickness measurement at a specific location indicated by a locator in the 2D design data, whereas a 3D DRC for minimum layer thickness may request the location(s) anywhere in the 3D model where the oxide film thickness is less than a specified threshold value. The 3D structural model may then be searched for locations where the specified minimum dimensional criteria are satisfied. Similarly, a 3D DRC may also cause the structural model to be searched to see if a maximum dimensional criteria is satisfied. 3D DRCs of this type thus provide benefits unavailable with virtual measurement / metrology operations for identifying unexpected causes of failures. Examples of 3D-DRCs may include: Electrical Net Isolation-, finds the shortest distance between selected conductors. A conductor is a lump that may be comprised of one or more conducting materials (a "lump" is a discrete volumetric region (technically, a 3-manifold) within a 3D structural model. A lump may be composed of a single material or multiple materials); Minimum Separation: finds the shortest distance between any pair in a group of selected lumps; Minimum Line Width, finds the shortest distance through any lump in a group of selected lumps; Minimum Layer Thickness, finds the shortest distance through any lump in the collection of lumps that comprise a layer of material; and Minimum Contact Area: finds the smallest contact area between all pairs of selected lumps. In some implementations, a DRC may be considered a “virtual proxy” for process-limited yield. In particular, while yield may generally be thought of as a percentage of physically fabricated wafers that are usable, a virtual proxy may be utilized in a virtual fabrication environment to serve as a “virtual yield.”Techniques for Improving Yield

[0039] Figure 1 depicts a graph representing yield as a function of time for development of a given fabrication process. Curve 102 represents yield as a function of time using conventional yield optimization techniques. Each stepwise jump in yield, such as jump 104, represents yield improvement as a result of one iteration of modifying process parameters for the fabrication process. For conventional techniques, as described above, one iteration of the process development and refinement cycle typically involves a large degree of manual involvement, for example, with a yield engineer identifying a single failure mode that is to be addressed in the next iterative cycle. Note that, from curve 102, it may take over a year (e.g., a year and aDocket No. LAM1P136WOhalf, two years, etc.) to reach an acceptable yield (e.g., above 90%, above 95%, etc.).

[0040] Curve 106 illustrates an example yield as a function of time utilizing the techniques disclosed herein. Note that, as shown in curve 106, the initial iterative cycles each yield a larger improvement in yield relative to conventional techniques. For example, the increase in yield (as shown by curve 102) using conventional techniques after the first 10 weeks is 10%, whereas, using the techniques disclosed herein, the initial increase in yield after the first iterative cycle is more than 35%. Similarly, using the techniques disclosed herein, and as shown by curve 106, far fewer iterative cycles may be needed to reach an acceptable yield. For example, a yield of 90% may be reached after only 30 weeks using the techniques disclosed herein, compared to 55 weeks using conventional techniques. The dramatic increase in rate of yield improvement may enable considerable savings in cost and manual resources, as a successful fabrication process that meets target specifications may be identified much faster and with fewer wasted wafers during the development process.

[0041] Figure 2 illustrates an example system 200 for improving yield in accordance with some embodiments. As illustrated, system 200 includes a user interface 202. User interface 202 is the primary mechanism by which an end user (e.g., a yield engineer, a process engineer, etc.) may interact with the yield optimization system. As shown in and described below in connection with Figures 3, 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 13A, and 13B, user interface 202 may allow the user to configure a digital twin of a fabrication process, initialize training of the digital twin, utilize the trained digital twin to identify process parameters and / or metrology variables that have a high contribution to yield variability, and perform a Pareto analysis on various metrology variables to identify optimized metrology targets for a subsequent fabrication process iteration. Example user interfaces that may be used in conjunction with each operation are shown in and described below in connection with Figures 3, 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 13 A, and 13B. It should be understood that because user interface 202 is the primary mechanism by which the end user interacts with the yield optimization system, the end user may be able to utilize the techniques disclosed herein for yield optimization without any understanding of the underlying algorithms, software, etc. underpinning the system.

[0042] User interface 202 may interact with a backend 206 via interface 204. In one example, interface 204 may be a client / server representational state transfer (REST) interface. For example, the REST client may be user interface 202 which utilizes one or more application programming interfaces (APIs) to access and / or utilize functions provided by backend 206. In this example, backend 206 may be the REST server.

[0043] Backend 206 may be implemented by one or more server devices. Backend 206 mayDocket No. LAM1P136WObe configured to implement various functions, which will be described below in more detail in connection with Figures 3, 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 13A, and 13B. For example, backend 206 may include a setup block 208, configured to set up a digital twin of a fabrication process. Setup may involve identifying one or more process parameters and / or one or more virtual metrology variables or measurements to be included in the digital twin.

[0044] After setup of the digital twin, backend 206 may utilize data pairing block 210 to pair virtual metrology variables and physical metrology variables corresponding to physical metrology measurements made in a physical fabrication environment. Pairing the virtual metrology variables with the physical metrology variables allows the digital twin to have a one-to-one mapping indicating that the digital twin is to be trained such that a virtual metrology measurement generated by a trained digital twin should match a corresponding (i.e., paired) physical metrology measurement in both sensitivity and variability. As used herein, “sensitivity” refers to the degree to which a given change in a process parameter value changes a given metrology value. As used herein, “variability” refers to the variance, or statistical spread, of a given metrology value. Accordingly, the digital twin is trained to generate virtual metrology measurements that match physical metrology measurements both in sensitivity and variability.

[0045] After pairing virtual metrology and physical metrology variables or measurements, data specifications block 212 is used to receive variable statistical specifications. The variable statistical specifications include user- specified standard deviation values for both process parameter variables as well as metrology variables. The variable statistical specification may also include a target for metrology variables. The target value for a given metrology variable may be obtained from physical fabrication environment (sometimes referred to herein as the “Fab”) data and correspond to ideal values coming from Fab design rules. Note that the target values can be different than the Fab nominal values, for example, in cases in which the Fab is not processing technology according to design targets.^ For some context, the target value is generally derived from initial design rules, which may be taken from earlier and / or related technologies, which set initial targets for one or more metrology measurements. When initial wafers are processed (e.g., in an initial or first iterative cycle for optimizing the current fabrication process of interest), each physical metrology measurement will have a distribution which includes a mean and a standard deviation (the distribution may include within wafer and / or wafer-to-wafer data). The mean and standard deviation for each metrology variable obtained at block 212 generally corresponds to the distribution values for the initial physical metrology measurements made for an initial batch of wafers. Note that, as described hereinDocket No. LAM1P136WO(e.g., in connection with Pareto analysis block 218), the techniques disclosed herein iteratively generate optimized distributions for each metrology variable in order to optimize yield.

[0046] After receiving the target specifications, model training block 214 may be used to initiate and perform training of the digital twin. As discussed above, a digital twin represents a particular fabrication process and, once trained, virtually replicates the physical happenings in a physical fab. The digital twin may be used to model a given fabrication process and obtain virtual metrology measurements, either during timepoints of the virtual fabrication run and / or after the virtual fabrication run. Note that training the digital twin generally involves calibrating the digital twin, e.g., to generate virtual metrology measurements that match physical metrology measurements from the fabrication environment.

[0047] Once a trained digital twin of a fabrication process is generated, variable ranking block 216 may be used to identify one or more metrology variables (whether virtual or physical) or one or more process parameters that have the most impact on or are most responsive to process variability. For example, the top N metrology variables may be identified. These identified metrology variables are the ones showing most significant response to variability induced in process parameters. As another example, the top M process parameter variables may be identified, which are the process parameter variables that have the most influence on metrology variables. In general, variable ranking involves ordering variables (both model parameter variables corresponding to process parameters) and metrology variables based on their contribution to sensitivity. For example, model parameter variables may be ranked (e.g., in descending order) based on their influence on virtual metrology measurements. Correspondingly, virtual metrology variables may be ranked based on how impacted each virtual metrology measurement is by changes in model parameter variables (e.g., by changes to process parameter values). By performing the variable ranking, the dimensionality of the variable space may be reduced prior to performing Pareto analysis. In other words, variable ranking may allow the Pareto analysis in the next step to focus on variables that have the highest likelihood of substantially impacting yield.

[0048] Once one or more metrology variables that are highly impacted by variability in process parameter variables are identified, Pareto analysis block 218 may be used to perform retargeting of one or more metrology variables. For example, Pareto analysis block 218 may determine optimal values for the one or more metrology variables that are to be targeted in a next iterative cycle, where the optimal values are ones that, if achieved, will improve yield (e.g., by causing a larger percentage of fabricated wafers to meet the target specifications). Note that, Pareto analysis block 218 may identify optimal values for multiple metrologyDocket No. LAM1P136WOvariables. Optimizing multiple metrology variables in one iterative cycle is an improvement over conventional techniques, which utilize a manual (i.e., human) identification of a single metrology variable corresponding to a single failure mode to be improved. The optimized metrology values may then be provided to the user, e.g., via user interface 202. Once provided, yield engineers and / or process engineers can identify process changes that will bring about the optimized metrology values. Pareto analysis block 218 may perform various Bayesian optimization techniques, to identify the optimized metrology values.

[0049] It should be understood that a “Pareto analysis” as used herein generally refers to an analysis of failure modes of the fabrication process, e.g., that are causing a lower than desired yield. The failure analysis may identify metrology variables that are correlated to the majority of failures.

[0050] Note that portions of model training block 214, variable ranking block 216, and Pareto analysis block 218 may be compiled. Functions performed by compiled modules are not accessible to a user of user interface 202. In this way, a user of user interface 202 can utilize the functions provided by backend 206 without any knowledge of algorithmic techniques, Bayesian optimization techniques, or the like. Moreover, by compiling computationally intensive functions such as model training and optimization to identify optimized metrology values, training of the digital twin, ranking of variables, and metrology value optimization may be performed quickly.

[0051] As discussed above in connection with Figure 2, a user may utilize the techniques disclosed herein for yield optimization via a user interface. The user interface may be used to configure (e.g., set up) a digital twin of a fabrication process, train the digital twin, and obtain an analysis that indicates optimized metrology measurements for a next iterative cycle. In some implementations, the user interface may include one or more menus. For example, a menu may be used to access different functions. For example, a first menu option (sometimes referred to herein as a “workflow component”) may be used to configure or set up a digital twin, a second menu option (or second workflow component) may be used to pair virtual metrology and physical metrology variables, etc. Selection of a given menu option (or workflow component) may cause one or more panels of the user interface to change, e.g., to perform various functions associated with the selected menu option. Note that, as described above, the user interface may be configured to interface with a backend system via one or more APIs such that a user of the user interface can utilize the techniques described herein for yield optimization entirely within the user interface (e.g., without accessing or modifying scripts or other computer software, within having to initiate running of compiled code, etc.). ExamplesDocket No. LAM1P136WOof such a user interface are shown in and described below in connection with Figures 3, 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 13A, and 13B.

[0052] Figure 3 illustrates an example user interface 300 for configuring a digital twin in accordance with some embodiments. As illustrated, user interface 300 includes a menu panel 302 that includes menu options (sometimes referred to herein as “workflow components”) for performing various functions associated with the yield optimization techniques herein. As illustrated, button 304 corresponding to set up, or configuration, of the digital twin is selected. Note that selection of other buttons within menu panel 302 causes the panels and information within user interface 300 to change, e.g., as shown in and described below in connection with Figures 4, 5, 6, 7, 8, 9, 10, 11, 12A, 12B, 13A, and 13B.

[0053] In general, configuring the digital twin involves selecting process parameter variables and metrology variables to be used by the digital twin. Process parameter panel 306 may be used to select various process parameter variables for inclusion as a variable in the digital twin model. As illustrated, process parameter panel 306 includes checkboxes next to each variable name, such that selection of a checkbox causes the corresponding process parameter variable to be included as a variable in the model. In general, “process parameters” refers to knobs or settings that are controlled during various parts of the fabrication process. Examples of process parameters include an etch rate, a deposition rate, a gas flow rate, a plasma power, pressure parameters, deposition time, temperature, etc. Panel 307 allows nominal values of each process parameter to be specified, where a nominal value corresponds to a baseline or reference value of the process parameter variable. The nominal value may be an initial value that is specified based on human expertise, which will subsequently be revised as discussed below.

[0054] Metrology variable panel 308 may be used to select various metrology variables for inclusion in the digital twin model. Examples of metrology variables include critical dimension (CD), film thickness, etc. As illustrated, metrology variable panel 308 includes checkboxes next to each variable name, such that selection of a checkbox causes the corresponding metrology variable to be included as a variable in the model.

[0055] User interface 300 includes a commit button 310. Selection of button 310 causes the selected variables from panels 306 and 308 to be utilized by the digital twin, along with any nominal values specified for process parameter variables (e.g., as shown in panel 307).

[0056] As discussed above in connection with Figure 2, virtual metrology variables (sometimes referred to herein as “model metrology variables”) are paired with physical metrology variables in training the digital twin. By pairing the virtual metrology variables with the physical metrology variables, the digital twin is trained to generate, for a given fabricationDocket No. LAM1P136WOprocess simulated with a set of process parameters having a set of process parameter values, virtual metrology measurements that match the sensitivity and variability of the corresponding (e.g., paired) physical metrology measurements. The pairing of virtual metrology variables with the physical metrology variables in training the digital twin is a critical aspect of generating a digital twin that mimics the fabrication environment (sometimes referred to herein as “the Fab”) and a fabrication process performed in the fabrication environment.

[0057] Figure 4 illustrates an example user interface 400 for pairing virtual and physical metrology variables in accordance with some embodiments. As illustrated in Figure 4, user interface 400 may be presented responsive to selection of button 404. User interface 400 includes a model metrology variable panel 406 that lists model (or virtual) metrology variables that have been selected (e.g., via user interface 300 of Figure 3) for inclusion in the digital twin, and physical metrology variables panel 408 that lists physical metrology variables. By selecting a model (or variable) metrology variable from panel 406 and a physical metrology variable from panel 408 (e.g., the highlighted two variables from panels 406 and 408), and subsequently selecting pairing button 410, the two selected variables may be paired with each other. Paired variables are listed in panel 412, with a model metrology variable listed next to (e.g., in the same row) as a corresponding physical metrology variable.

[0058] As discussed above in connection with Figure 2, variable statistical specifications may be obtained. These variable statistical specifications are the values of each parameter coming from technology design rules.

[0059] Figure 5 illustrates an example user interface 500 for obtaining variable statistical specifications in accordance with some embodiments. As illustrated in Figure 5, user interface 500 may be presented responsive to selection of button 504 in menu 302. User interface 500 includes a panel 506 that indicates model metrology variables and the corresponding (e.g., paired, as discussed above in connection with Figure 4) physical metrology variables. For each paired model (e.g., virtual) metrology variable and corresponding physical metrology variable, the mean, target, and standard deviations for the metrology measurement may be specified by the user via user interface 500. The mean and standard distribution correspond to the distribution of physical metrology measurements from the fabrication environment. As a particular example, a metrology variable of depth may have a mean of 125 nanometers, with a standard deviation of 5 nanometers, indicating that real Fab mean for this depth (i.e., the physical metrology measurement) is 125 nanometers, and the variation around the mean depth is a standard deviation of 5 nanometers, as measured by the physical metrology measurements from the Fab. These values are used for model training, in particular, to train the digital twinDocket No. LAM1P136WOto generate virtual metrology measurements that match the physical metrology measurements in statistical distribution. Note that “target” in panel 506 refers to the value obtain from the design rule as a reference.. The weight may be a user-specified value that indicates an importance to be assigned to the variable. The weight may be used in calibrating the digital twin, as well as in variable ranking.

[0060] User interface 500 additionally includes a panel 508 that may be used to set statistical distributions associated with model process parameter variables. For example, as shown in Figure 5, for each model process parameter variable (e.g., as selected using user interface 300 of Figure 3), a mean and standard deviation for the variable may be specified. The mean and standard distribution generally correspond to the distribution of process parameter variables to be used by the model. The mean is set to the nominal value. The standard deviation may be a user-specified value that defines the variation of model parameters when a Design of Experiments (DoE) procedure is run to perform model training. Note that the minimum and maximum model process variable values shown in panel 508 may be estimated from the standard deviations. The user may be able to adjust the minimum and maximum values prior to beginning model training.

[0061] As discussed above in connection with Figure 2, after configuring the digital twin (e.g., by pairing virtual and physical metrology variables and receiving target wafer specifications), the digital twin may be trained. Note that the digital twin may comprise one or more physicsbased models and / or one or more behavioral models. The digital twin may utilize a virtual fabrication engine configured to simulate a fabrication process utilizing various process parameter values. The digital twin may be configured to obtain virtual metrology measurements. Training the digital twin may involve performing a user- specified number of Design of Experiments (DoE) simulations and a user- specified number of iterations. After training the digital twin, the trained digital twin may be configured to, when simulating a fabrication process using a set of process parameter values, generate virtual metrology measurements that match physical metrology measurements in terms of value generated, sensitivity, and / or variability.

[0062] It should be noted that a DoE simulation generally refers to a structured approach to conducting simulations in order to optimize a system. In the simulation, parameters may be systematically varied and the effect is studied, where the parameters are varied in a way that gains the most amount of information. DoE simulation utilizes focused exploration of a parameter space in order to efficiently optimize a system using statistical methods and predesigned experiments.Docket No. LAM1P136WO

[0063] Figure 6 illustrates an example user interface 600 for initiating training of a digital twin in accordance with some embodiments. As illustrated in Figure 6, user interface 600 may be presented responsive to selection of button 604 in menu 302. User interface 600 includes a panel 606 for receiving user-specified training parameters, such as the number of DoEs, the number of iterations, and / or a stopping criteria (e.g., a root-mean-square (RMS) error threshold) for stopping training. Note that stopping of model training may occur if the number of specified iterations is reached or if the RMS error is below the specified threshold. Model training may begin responsive to detecting that start button 610 has been selected. Note that user interface 600 includes a panel 608 that indicates nominal values of model process parameters and minimum and maximum values for each process parameter. Panel 608 additionally includes model / virtual metrology variables that are to be measured virtually using the digital twin once trained.

[0064] After training of the model has been completed, user interface 700 of Figure 7 may be presented. Note that user interface 700 is generally similar to user interface 600, with the exception that new nominal values for the model process parameter variables have been filled in in panel 708 based on the digital twin, and calibrated values for each model / virtual metrology variable have been filled in in the table of panel 708. Note that the new nominal value is a value identified for the process parameter after calibration / training of the digital twin. The new nominal value(s), when used by the digital twin, are ones that will generate virtual metrology measurements that match the corresponding physical metrology measurements obtained in the physical fabrication environment.

[0065] As discussed above in connection with Figure 2, after the digital twin has been trained, outputs of the digital twin may be used to identify the process parameter variables and / or the metrology variables that contribute the most to variability. In other words, as discussed above in connection with block 216 of Figure 2, identified process parameter variables are variables that induce high amounts of variability in metrology variables, and identified metrology variables are variables that are highly impacted by changes in process parameter variables. In some implementations, the identified variables may be separated into input variables (e.g., process parameter variables) and output variables (virtual and physical metrology variables). A correlation matrix may be calculated among all output variables. The output variables may be filtered by discarding output variables that are highly correlated with at least one other output variable and that has a lower weight (e.g., a weight assigned by a user as described above in connection with FIG. 5). A feature importance matrix may then be determined that indicates an importance of each input variable (e.g., process parameter variable) to each of theDocket No. LAM1P136WOremaining output variables, where the feature importance is determined through DoE results. A normalized feature importance may then be calculated by normalizing based on the range of the output variable (i.e., the metrology variable) and the total of the importance scores.

[0066] A feature importance metric may be identified for each variable (whether a process parameter variable, a virtual metrology variable, or a physical metrology variable), which may indicate the importance of that variable to yield. For example, for a given metrology variable, if its feature importance metric is relatively high, the value of the metrology variable is easily changed by variation in a process parameter. In other words, given a target specification range for the metrology variable, for a metrology variable that is easily changed by changes in process parameters, the metrology variable will therefore be an important factor to yield, as it will easily become out of specification, and will accordingly be assigned a relatively high feature importance metric. As another example, a given process parameter variable may be assigned a relatively high feature importance metric if it is likely to induce large changes in at least one metrology variable. In other words, a process parameter variable that is capable of affecting large changes in at least one metrology variables should be well-controlled, as looser control of this process parameter variable will have a large effect on yield, and may accordingly be assigned a relatively high feature importance metric.

[0067] In some implementations, a user-specified threshold may be received (e.g., via a user interface, as shown in Figure 8), and variable with a feature importance metric that exceed the threshold may be identified in the user interface. This may allow the user (e.g., a yield engineer or a process engineer) to quickly identify the most important variable to optimize. Moreover, it should be understood that multiple variables may be identified, and their relative importance to improving yield may be determined and presented to the user, which may allow the engineer to optimize multiple variables concurrently.

[0068] Figure 8 illustrates an example user interface 800 for initiating a variable ranking procedure in accordance with some embodiments. As illustrated in Figure 8, user interface 800 may be presented responsive to selection of button 804 in menu 302. User interface 800 includes a panel 806 that includes various user interface controls (e.g., text input boxes) for receiving user- specified parameters for the variable ranking procedure. For example, panel 806 includes inputs for receiving a number of samples per input and a feature importance threshold. Additionally, user interface 800 includes a start button 808. Selection of start button 808 causes a DoE simulation procedure to begin from which the variables may be ranked in order of importance.

[0069] As illustrated in Figure 9, once the DoE simulation has completed, user interface 900Docket No. LAM1P136WOmay be presented, which indicates the model process parameter variables and the model / virtual metrology variables that are identified as most important to optimizing yield. For example, panel 906 indicates the model process parameter variables that have been identified the most important. Note that the process parameter variables are presented in order of importance, with the rank indicating their relative importance. The rank may additionally or alternatively be indicated via a graph (e.g., a bar graph as shown in Figure 9) for clear visualization of the relative importance. Note that, in the example shown in Figure 9, only the variables with a feature importance metric that exceeds the threshold specified in user interface 800 are presented.

[0070] Panel 908 indicates the virtual metrology variables that have been identified as the most important. Similar to what is shown in panel 906, the virtual metrology variables are presented in order of importance, with the rank indicating their relative importance. The rank may additionally or alternatively be indicated via a graph (e.g., a bar graph as shown in Figure 9).

[0071] As discussed above in connection with Figure 2, a Pareto analysis may be performed to identify the N most important failure modes of the fabrication process. The most important failure modes are correlated to metrology measurements that, if improved or optimized, will yield the biggest improvement in yield. Failure modes may be identified by virtual proxies, e.g., based on virtual structural failure detection measurements that are correlated with and / or paired with virtual metrology measurements. In particular, virtual failures may be detected on the model when they fail to meet target wafer specifications. The virtual metrology measurements that, if optimized, will yield the biggest yield improvement, can be identified based on a DoE simulation. Additionally or alternatively to presenting a Pareto analysis that indicates the degree of importance of various identified failure modes, an analysis indicating the degree of importance of the identified failure modes, if metrology measurements are optimized, may also be presented. Furthermore, optimized targets for metrology measurements may be presented. This may allow the user (e.g., a yield engineer or a process engineer) to determine a change to a current metrology measurement that, if achieved by one or more process changes, will optimally improve yield.

[0072] Figure 10 illustrates an example user interface 1000 for initiating and presenting a failure analysis in accordance with some embodiments. As illustrated in Figure 10, user interface 1000 may be presented responsive to selection of button 1004 in menu 302. User interface 1000 includes an input 1006 for receiving user- specified parameters, such as a number of failures to consider in a failure analysis. User interface 1000 additionally includes a start button 1008, which, when selected, causes the failure analysis to begin.Docket No. LAM1P136WO

[0073] Responsive to completion of the failure analysis, user interface 1100 of Figure 11 may be presented. Note that, a graph panel 1102 is presented which indicates the most common causes of failure of the current fabrication process. Note that the most common causes of failure are determined based on outputs of the digital twin, which has been trained such that virtual metrology measurements match physical metrology measurements. Graph panel 1102 includes a bar graph that indicates the contributions of different failure modes. In particular, each failure mode corresponds to a virtual specific detection measurement (e.g., a specific virtual metrology measurement) that was not within the corresponding target wafer specifications, thereby causing a failure. In some implementations, the graph may be a Pareto failure graph that ranks the failure modes in order of contribution.

[0074] Figures 12A and 12B illustrate failure analysis bar graphs for a current process of record (POR) and a failure analysis if optimized metrology targets are achieved, respectively. Note that the graph shown in Figure 12A is the same as the graph in graph panel 1102 of Figure 11. In some embodiments, graph panel 1102 may include the graphs of both Figures 12A and 12B, and the panel may be scrolled through to access both graphs. Note that the X-axes of the graphs in Figure 12A and Figure 12B include the same analyzed failure modes. However, the failure ratio for each failure mode in the graph of Figure 12B (as shown on the Y-axis of each bar graph) is lower in the graph of Figure 12B compared to the graph of Figure 12 A. This indicates that optimization of metrology measurements will reduce multiple failure modes concurrently if the optimized metrology measurements are achieved in the next iterative cycle.

[0075] In some implementations, changes in metrology measurement targets, whether virtual or physical, may be provided. In some implementations, the changes may be provided as plots. For example, a plot may indicate a current process of record (POR) metrology measurement, and may additionally indicate a target metrology measurement, corresponding to an optimized value. In some implementations, the changes may be provided in box plots that indicate the distribution of the metrology measurement (e.g., a median, first and third quartiles, whiskers, etc.) for the POR and for the optimized measurement.

[0076] Figures 13A and 13B illustrate example box plots for presenting changes in metrology measurements in accordance with some embodiments. As illustrated, each box plot includes a box and whiskers for the POR and for the optimized metrology measurements for a given metrology measurement. Note that each box plot (e.g., the plot shown in Figure 13A, and the plot shown in Figure 13B) corresponds to a single metrology measurement, with the change between the POR and the optimized value shown in the plot. Referring to Figure 13 A, for the metrology measurement considered, the optimized metrology value should have a lowerDocket No. LAM1P136WOmedian value to increase the yield, however, the distribution breadth can remain similar. In contrast, Figure 13B shows an example metrology measurement where the median value can remain similar, but the variability (e.g., across simulation runs or fabrication runs) must be substantially reduced to improve the yield.

[0077] Examples such as the box plots shown in Figures 13A and 13B may be presented within a user interface for various metrology measurements. For example, the plots may be accessed via a tab in user interface 1100. Multiple (e.g., two, five, ten, twenty, etc.) plots may be shown, each corresponding to a different metrology variable. In some cases, the plots may be ordered based on the degree of contribution to the yield such that more important variables are presented earlier or prior to less important variables.

[0078] Note that, the metrology variables may be virtual metrology variables that have been paired with a physical metrology variable (e.g., during the pairing step shown in and described above in connection with Figure 4). Additionally or alternatively, the metrology variables may be virtual metrology variables for which no corresponding physical metrology variable has been specified. In particular, in some cases, a virtual metrology measurement may be one that, if performed as a physical measurement, would be highly destructive, or even impossible to perform, but may be measured virtually in a simulation. Such virtual metrology measurements may be optimized or re-targeted, even if there is no pairing with a physical metrology measurement, which may allow a user (e.g., process engineer or a yield engineer) an additional metrology optimization target to consider in a next iterative cycle.

[0079] Figure 14 is a flowchart of an example process 1400 for improving yield of semiconductor wafers in accordance with some embodiments. Blocks of process 1400 may be executed by one or more computing devices. For example, the computing devices may include a user device (e.g., a laptop computer, a desktop computer, etc.) configured to present user interfaces, which may be used to receive information from a user and / or present information to the user. The user device may be communicatively coupled to a backend device (e.g., a server device). Example components of a computing device are shown in and described below in connection with Figure 15. In some implementations, blocks of process 1400 may be executed in an order other than what is shown in Figure 14. In some embodiments, two or more blocks of process 1400 may be executed substantially in parallel. In some embodiments, one or more blocks of process 1400 may be omitted.

[0080] Process 1400 can begin at 1402 by receiving indications of a set of process parameters, a set of virtual metrology measurements, a set of physical metrology measurements, and a set of target wafer specifications. The set of process parameters may be process parameterDocket No. LAM1P136WOvariables that are to be incorporated into a digital twin model of a given fabrication process. The set of virtual metrology measurements may be virtual metrology measurements that may be made in a virtual fabrication environment. The set of physical metrology measurements may be physical metrology measurements that can be measured in a physical fabrication environment. The set of target wafer specifications may include one or more specifications a processed wafer is to meet to be considered usable. The set of process parameters, the set of virtual metrology measurements, the set of physical metrology measurements, and statistical distributions associated with each parameter may be obtained via one or more user interfaces, e.g., as shown in and described above in connection with Figures 3-5.

[0081] At 1404, process 1400 can pair physical metrology measurements of the set of physical metrology measurements with corresponding virtual metrology measurements of the set of virtual metrology measurements to form a set of paired metrology measurements. Indications of pairs of physical metrology measurements and virtual metrology measurements may be received via a user interface, e.g., as shown in and described above in connection with Figure 4. Note that, in some implementations, there may not be a one-to-one mapping of physical metrology measurements and virtual metrology measurements. For example, in some implementations, there may be one or more virtual metrology measurements that do not have a corresponding physical metrology measurement. This may occur in cases where, e.g., it is possible to obtain a virtual metrology measurement in a virtual fabrication environment that is not possible to obtain in a physical fabrication environment, e.g., due to lack of equipment, destructiveness of the metrology measurement, or the like.

[0082] At 1406, process 1400 may transmit instructions to train a digital twin of a semiconductor fabrication apparatus based on the set of process parameters and the set of paired metrology measurements to generate a trained digital twin. For example, as shown in and described above in connection with FIG. 6, selection of a button in a user interface may initiate training of the digital twin by causing instructions to be transmitted to a backend server that hosts the digital twin. Note that the digital twin may be a model, or a set of models. The model, or the set of models, may comprise one or more physics-based models, one or more behavioral models, or any combination thereof. Note that the digital twin is trained such that, once trained, the digital twin generates virtual metrology measurements that match a sensitivity and / or a variability of physical metrology measurements produced in the physical fabrication environment modeled by the digital twin for the given fabrication process.

[0083] At 1408, process 1400 can, receive an indication of a change in at least one physical metrology measurement or at least one virtual metrology measurement to be achieved toDocket No. LAM1P136WOincrease a yield in semiconductor wafers. The change in the at least one physical metrology measurement or the at least one virtual metrology measurement may be identified using results of the digital twin. For example, as described above in connection with FIG. 2, the change may be determined based on a variable ranking and / or Pareto analysis utilizing virtual metrology measurements generated by the digital twin. The yield may be determined based on a percentage of processed wafers that meet the set of target wafer specifications. Note that the indication of the change may include a change in a median value of the metrology measurement, and / or a change in the variability (e.g., the statistical distribution) of the metrology measurement. This may allow a user (e.g., a process engineer, a yield engineer, etc.) to determine a magnitude of change in the metrology measurement to be achieved, as well as to what degree variability in the metrology measurement (e.g., across fabrication runs) is to be changed in order to most improve yield. In some embodiments, the change in the at least one physical metrology measurement or the at least one virtual metrology measurement may be presented in a user interface. For example, the user interface may include one or more plots each showing a target metrology value to be achieved. In some embodiments, the plot may include a POR value for the metrology measurement and an optimized metrology measurement to be achieved. The plot may be a box plot, e.g., as shown in and described above in connection with Figures 13A and 13B.

[0084] In some embodiments, process parameters, virtual metrology measurements, and / or physical metrology measurements may be ranked based on their contribution to the variability of the yield. In some implementations, the ranking may be presented, e.g., via a user interface (e.g., as shown in and described above in connection with Figures 10, 11, 12A, and 12B), which may allow the user to see which parameters / variables / metrology measurements contribute the most to failures, and accordingly, if optimized, would increase yield. In some embodiments, the ranking may be based on a subset of virtual metrology measurements or a subset of physical metrology measurements. The subset may be user- selected.CONTEXT FOR DISCLOSED COMPUTATIONAL EMBODIMENTS

[0085] Systems including computing devices (e.g., server devices, desktop or laptop computer devices, etc.) as described herein may include logic for improving yield.

[0086] The analysis logic may be designed and implemented in any of various ways. For example, the logic can be implemented in hardware and / or software. Examples are presented in the controller section herein. Hardware-implemented control logic may be provided in any of a variety of forms, including hard coded logic in digital signal processors, applicationspecific integrated circuits, and other devices that have algorithms implemented as hardware.Docket No. LAM1P136WOAnalysis logic may also be implemented as software or firmware instructions configured to be executed on a general-purpose processor. System control software may be provided by “programming” in a computer readable programming language.

[0087] The computer program code can be written in any conventional computer readable programming language: for example, assembly language, C, C++, Pascal, Fortran, Python, or others. Compiled object code or script is executed by the processor to perform the tasks identified in the program. Also as indicated, the program code may be hard coded.

[0088] Integrated circuits used in logic may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated in the form of various individual settings (or program files), defining operational parameters for carrying out a particular analysis or image analysis application.

[0089] Figure 15 is a block diagram of an example of the computing device 1500 suitable for use in implementing some embodiments of the present disclosure. For example, device 1500 may be suitable for implementing some or all functions for pairing virtual metrology and physical metrology, ranking variable factors, identifying changes in metrology targets, or the like.

[0090] Computing device 1500 may include a bus 1502 that directly or indirectly couples the following devices: memory 1504, one or more central processing units (CPUs) 1506, one or more graphics processing units (GPUs) 1508, a communication interface 1510, input / output (VO) ports 1512, input / output components 1514, a power supply 1516, and one or more presentation components 1518 (e.g., display(s)). In addition to CPU 1506 and GPU 1508, computing device 1500 may include additional logic devices that are not shown in Figure 15, such as but not limited to an image signal processor (ISP), a digital signal processor (DSP), an ASIC, an FPGA, or the like.

[0091] Although the various blocks of Figure 15 are shown as connected via the bus 1502 with lines, this is not intended to be limiting and is for clarity only. For example, in some embodiments, a presentation component 1518, such as a display device, may be considered an VO component 1514 (e.g., if the display is a touch screen). As another example, CPUs 1506 and / or GPUs 1508 may include memory (e.g., the memory 1504 may be representative of a storage device in addition to the memory of the GPUs 1508, the CPUs 1506, and / or other components). In other words, the computing device of Figure 15 is merely illustrative. Distinction is not made between such categories as “workstation,” “server,” “laptop,”Docket No. LAM1P136WO“desktop,” “tablet,” “client device,” “mobile device,” “hand-held device,” “electronic control unit (ECU),” “virtual reality system,” and / or other device or system types, as all are contemplated within the scope of the computing device of Figure 15.

[0092] Bus 1502 may represent one or more busses, such as an address bus, a data bus, a control bus, or a combination thereof. The bus 1502 may include one or more bus types, such as an industry standard architecture (ISA) bus, an extended industry standard architecture (EISA) bus, a video electronics standards association (VESA) bus, a peripheral component interconnect (PCI) bus, a peripheral component interconnect express (PCIe) bus, and / or another type of bus.

[0093] Memory 1504 may include any of a variety of computer- readable media. The computer-readable media may be any available media that can be accessed by the computing device 1500. The computer-readable media may include both volatile and nonvolatile media, and removable and non-removable media. By way of example, and not limitation, the computer-readable media may comprise computer- storage media and / or communication media.

[0094] The computer-storage media may include both volatile and nonvolatile media and / or removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules, and / or other data types. For example, memory 1504 may store computer-readable instructions (e.g., that represent a program(s) and / or a program element(s), such as an operating system. Computer-storage media may include, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by computing device 1500. As used herein, computer storage media does not comprise signals per se.

[0095] The communication media may embody computer-readable instructions, data structures, program modules, and / or other data types in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term “modulated data signal” may refer to a signal that has one or more of its characteristics set or changed in such a manner as to encode information in the signal. By way of example, and not limitation, the communication media may include wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media. Combinations of any of the above should also be included within the scope of computer-readable media.Docket No. LAM1P136WO

[0096] CPU(s) 1506 may be configured to execute the computer-readable instructions to control one or more components of the computing device 1500 to perform one or more of the methods and / or processes described herein. CPU(s) 1506 may each include one or more cores (e.g., one, two, four, eight, twenty-eight, seventy-two, etc.) that are capable of handling a multitude of software threads simultaneously. CPU(s) 1506 may include any type of processor and may include different types of processors depending on the type of computing device 1500 implemented (e.g., processors with fewer cores for mobile devices and processors with more cores for servers). For example, depending on the type of computing device 1500, the processor may be an ARM processor implemented using Reduced Instruction Set Computing (RISC) or an x86 processor implemented using Complex Instruction Set Computing (CISC). Computing device 1500 may include one or more CPUs 1506 in addition to one or more microprocessors or supplementary co-processors, such as math co-processors.

[0097] GPU(s) 1508 may be used by computing device 1500 to render graphics (e.g., 3D graphics). GPU(s) 1508 may include many (e.g., tens, hundreds, or thousands) of cores that are capable of handling many software threads simultaneously. GPU(s) 1508 may generate pixel data for output images in response to rendering commands (e.g., rendering commands from CPU(s) 1506 received via a host interface). GPU(s) 1508 may include graphics memory, such as display memory, for storing pixel data. The display memory may be included as part of memory 1504. GPU(s) 1508 may include two or more GPUs operating in parallel (e.g., via a link). When combined, each GPU 1508 can generate pixel data for different portions of an output image or for different output images (e.g., a first GPU for a first image and a second GPU for a second image). Each GPU can include its own memory or can share memory with other GPUs.

[0098] In examples where the computing device 1500 does not include the GPU(s) 1508, the CPU(s) 1506 may be used to render graphics.

[0099] Communication interface 1510 may include one or more receivers, transmitters, and / or transceivers that enable computing device 1500 to communicate with other computing devices via an electronic communication network, included wired and / or wireless communications. Communication interface 1510 may include components and functionality to enable communication over any of a number of different networks, such as wireless networks (e.g., Wi-Fi, Z-Wave, Bluetooth, Bluetooth LE, ZigBee, etc.), wired networks (e.g., communicating over Ethernet), low-power wide-area networks (e.g., LoRaWAN, SigFox, etc.), and / or the internet.

[0100] EG ports 1512 may enable the computing device 1500 to be logically coupled to otherDocket No. LAM1P136WOdevices including I / O components 1514, presentation component(s) 1518, and / or other components, some of which may be built in to (e.g., integrated in) computing device 1500. Illustrative I / O components 1514 include a microphone, mouse, keyboard, joystick, track pad, satellite dish, scanner, printer, wireless device, etc. I / O components 1514 may provide a natural user interface (NUI) that processes air gestures, voice, or other physiological inputs generated by a user. In some instances, inputs may be transmitted to an appropriate network element for further processing. An NUI may implement any combination of speech recognition, stylus recognition, facial recognition, biometric recognition, gesture recognition both on screen and adjacent to the screen, air gestures, head and eye tracking, and touch recognition (as described in more detail below) associated with a display of computing device 1500. Computing device 1500 may be include depth cameras, such as stereoscopic camera systems, infrared camera systems, RGB camera systems, touchscreen technology, and combinations of these, for gesture detection and recognition. Additionally, computing device 1500 may include accelerometers or gyroscopes (e.g., as part of an inertia measurement unit (IMU)) that enable detection of motion. In some examples, the output of the accelerometers or gyroscopes may be used by computing device 1500 to render immersive augmented reality or virtual reality.

[0101] Power supply 1516 may include a hard-wired power supply, a battery power supply, or a combination thereof. Power supply 1516 may provide power to computing device 1500 to enable the components of computing device 1500 to operate.

[0102] Presentation component(s) 1518 may include a display (e.g., a monitor, a touch screen, a television screen, a heads-up-display (HUD), other display types, or a combination thereof), speakers, and / or other presentation components. Presentation component(s) 1518 may receive data from other components (e.g., GPU(s) 1508, CPU(s) 1506, etc.), and output the data (e.g., as an image, video, sound, etc.).

[0103] The disclosure may be described in the general context of computer code or machine-useable instructions, including computer-executable instructions such as program modules, being executed by a computer or other machine, such as a personal data assistant or other handheld device. Generally, program modules including routines, programs, objects, components, data structures, etc., refer to code that perform particular tasks or implement particular abstract data types. The disclosure may be practiced in a variety of system configurations, including hand-held devices, consumer electronics, general-purpose computers, more specialty computing devices, etc. The disclosure may also be practiced in distributed computing environments where tasks are performed by remote-processing devices that are linked through a communications network.Docket No. LAM1P136WOAdditional Considerations

[0104] As used in this specification and appended claims, the singular forms “a”, “an”, and “the” include plural referents unless the content and context dictates otherwise. For example, reference to “a cell” includes a combination of two or more such cells. Unless indicated otherwise, an “or” conjunction is used in its correct sense as a Boolean logical operator, encompassing both the selection of features in the alternative (A or B, where the selection of A is mutually exclusive from B) and the selection of features in conjunction (A or B, where both A and B are selected).

[0105] It is to be understood that the phrases “for each <item> of the one or more <items>,” “each <item> of the one or more <items>,” or the like, if used herein, are inclusive of both a single-item group and multiple-item groups, i.e., the phrase “for ... each” is used in the sense that it is used in programming languages to refer to each item of whatever population of items is referenced. For example, if the population of items referenced is a single item, then “each” would refer to only that single item (despite the fact that dictionary definitions of “each” frequently define the term to refer to “every one of two or more things”) and would not imply that there must be at least two of those items. Similarly, the term “set” or “subset” should not be viewed, in itself, as necessarily encompassing a plurality of items — it will be understood that a set or a subset can encompass only one member or multiple members (unless the context indicates otherwise).

[0106] The use, if any, of ordinal indicators, e.g., (a), (b), (c)... or the like, in this disclosure and claims is to be understood as not conveying any particular order or sequence, except to the extent that such an order or sequence is explicitly indicated. For example, if there are three steps labeled (i), (ii), and (iii), it is to be understood that these steps may be performed in any order (or even concurrently, if not otherwise contraindicated) unless indicated otherwise. For example, if step (ii) involves the handling of an element that is created in step (i), then step (ii) may be viewed as happening at some point after step (i). Similarly, if step (i) involves the handling of an element that is created in step (ii), the reverse is to be understood. It is also to be understood that use of the ordinal indicator “first” herein, e.g., “a first item,” should not be read as suggesting, implicitly or inherently, that there is necessarily a “second” instance, e.g., “a second item.”

[0107] Various computational elements including processors, memory, instructions, routines, models, or other components may be described or claimed as “configured to” perform a task or tasks. In such contexts, the phrase “configured to” is used to connote structure by indicating that the component includes structure (e.g., stored instructions, circuitry, etc.) that performs theDocket No. LAM1P136WOtask or tasks during operation. As such, the unit / circuit / component can be said to be configured to perform the task even when the specified component is not necessarily currently operational (e.g., is not on).

[0108] The components used with the “configured to” language may refer to hardware — for example, circuits, memory storing program instructions executable to implement the operation, etc. Additionally, “configured to” can refer to generic structure (e.g., generic circuitry) that is manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in manner that is capable of performing the recited task(s). Additionally, “configured to” can refer to one or more memories or memory elements storing computer executable instructions for performing the recited task(s). Such memory elements may include memory on a computer chip having processing logic. In some contexts, “configured to” may also include adapting a manufacturing process (e.g., a semiconductor fabrication facility) to fabricate devices (e.g., integrated circuits) that are adapted to implement or perform one or more tasks.

[0109] Example Embodiments:

[0110] Embodiment 1: A method for improving yield of semiconductor wafers, the method comprising: (a) receiving indications of a set of process parameters, a set of virtual metrology measurements and a set of physical metrology measurements; (b) pairing physical metrology measurements of the set of physical metrology measurements with corresponding virtual metrology measurements of the set of virtual metrology measurements to form a set of paired metrology measurements; (c) transmitting instructions for training a digital twin of a semiconductor fabrication apparatus based on the set of process parameters and the paired metrology measurements to generate a trained digital twin; and (d) receiving an indication of a change in at least one physical metrology measurement or at least one virtual metrology measurement to be achieved to increase a yield in semiconductor wafers, wherein the change is determined using the trained digital twin, and wherein the yield is determined based on a percentage of processed wafers that meet a set of target wafer specifications.

[0111] Embodiment 2: The method of embodiment 1, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is identified using a Pareto analysis of at least a subset of the set of process parameters, a subset of the virtual metrology measurements, and / or a subset of the physical metrology measurements.

[0112] Embodiment 3: The method of embodiment 2, wherein the subset of the set of process parameters, the subset of the virtual metrology measurements, and / or the subset of the physicalDocket No. LAM1P136WOmetrology measurements are selected via a user interface.

[0113] Embodiment 4: The method of any one of embodiments 2 or 3, wherein the subset of the set of process parameters are ranked based on contribution to variability of the subset of the virtual metrology measurements, and / or the subset of the virtual metrology measurements are ranked by an effect of process parameter variation on variability of the virtual metrology measurements.

[0114] Embodiment 5: The method of embodiment 4, further comprising presenting the rankings.

[0115] Embodiment 6: The method of any one of embodiments 1-5, wherein the indication of the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is presented in a box plot depicting a current median and range of the at least one physical metrology measurement or the at least one virtual metrology measurement and a target median and range of the at least one physical metrology measurement or the at least one virtual metrology measurement to be achieved.

[0116] Embodiment 7: The method of any one of embodiments 1-6, wherein the digital twin is configured to generate virtual metrology measurements that match a sensitivity and a variability of physical metrology measurements produced in a physical fabrication environment.

[0117] Embodiment 8: The method of any one of embodiments 1-7, wherein the set of virtual metrology measurements comprises at least one virtual metrology measurement that does not have a corresponding physical metrology measurement.

[0118] Embodiment 9: The method of any one of embodiments 1-8, wherein (a) occurs within a user interface, and wherein the indication of the at least one change to be achieved in (d) is presented within the same user interface.

[0119] Embodiment 10: The method of any one of embodiments 1-9, wherein operations (a) -(d) occur in a period of time of less than two weeks.

[0120] Embodiment 11: The method of embodiment 10, wherein (b) - (d) occur in an automated sequence.

[0121] Embodiment 12: The method of embodiment 11, wherein (b) - (d) occur in a period of time of one week or less.

[0122] Embodiment 13: The method of any one of embodiments 1-12, wherein (b), (c), and (d) comprise transmitting and / or receiving information obtained via a user interface to a backend system via an application programming interface (API).

[0123] Embodiment 14: The method of embodiment 13, wherein training the digital twin andDocket No. LAM1P136WOidentifying the change in the at least one physical metrology measurement or at the at least one virtual metrology measurement comprise utilizing compiled source code not accessible via the user interface .

[0124] Embodiment 15: The method of any one of embodiments 1-14, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement comprise a plurality of changes.

[0125] Embodiment 16: The method of any one of embodiments 1-15, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is determined using the trained digital twin and based on the set of target wafer specifications.

[0126] Embodiment 17: The method of embodiment 16, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is determined based on at least one identified failure mode.

[0127] Embodiment 18: The method of embodiment 17, wherein the at least one identified failure mode corresponds to a virtual metrology measurement that is not within a corresponding specification of the set of target wafer specifications.

[0128] Embodiment 19: A non-transitory computer- readable media storing instructions which, when executed by one or more processors, cause performance of: (a) receiving indications of a set of process parameters, a set of virtual metrology measurements and a set of physical metrology measurements; (b) pairing physical metrology measurements of the set of physical metrology measurements with corresponding virtual metrology measurements of the set of virtual metrology measurements to form a set of paired metrology measurements; (c) transmitting instructions for training a digital twin of a semiconductor fabrication apparatus based on the set of process parameters and the paired metrology measurements to generate a trained digital twin; and (d) receiving an indication of a change in at least one physical metrology measurement or at least one virtual metrology measurement to be achieved to increase a yield in semiconductor wafers, wherein the change is determined using the trained digital twin, and wherein the yield is determined based on a percentage of processed wafers that meet a set of target wafer specifications.

[0129] Embodiment 20: The non-transitory computer-readable media of embodiment 19, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is identified using a Pareto analysis of at least a subset of the set of process parameters, a subset of the virtual metrology measurements, and / or a subset of the physical metrology measurements.Docket No. LAM1P136WO

[0130] Embodiment 21: The non-transitory computer-readable media of embodiment 20, wherein the subset of the set of process parameters, the subset of the virtual metrology measurements, and / or the subset of the physical metrology measurements are selected via a user interface.

[0131] Embodiment 22: The non-transitory computer- readable media of any one of embodiments 20 or 21, wherein the subset of the set of process parameters are ranked based on contribution to variability of the subset of the virtual metrology measurements, and / or the subset of the virtual metrology measurements are ranked by an effect of process parameter variation on variability of the virtual metrology measurements.

[0132] Embodiment 23: The non-transitory computer- readable media of embodiment 22, wherein the instructions further cause performance of presenting the rankings.

[0133] Embodiment 24: The non-transitory computer-readable media of any one of embodiments 19-23, wherein the indication of the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is presented in a box plot depicting a current median and range of the at least one physical metrology measurement or the at least one virtual metrology measurement and a target median and range of the at least one physical metrology measurement or the at least one virtual metrology measurement to be achieved.

[0134] Embodiment 25: The non-transitory computer-readable media of any one of embodiments 19-24, wherein the digital twin is configured to generate virtual metrology measurements that match a sensitivity and a variability of physical metrology measurements produced in a physical fabrication environment.

[0135] Embodiment 26: The non-transitory computer-readable media of any one of embodiments 19-25, wherein the set of virtual metrology measurements comprises at least one virtual metrology measurement that does not have a corresponding physical metrology measurement.

[0136] Embodiment 27: The non-transitory computer-readable media of any one of embodiments 19-26, wherein (a) occurs within a user interface, and wherein the indication of the at least one change to be achieved in (d) is presented within the same user interface.

[0137] Embodiment 28: The non-transitory computer-readable media of any one of embodiments 19-27, wherein operations (a) - (d) occur in a period of time of less than two weeks.

[0138] Embodiment 29: The non-transitory computer-readable media of embodiment 28, wherein (b) - (d) occur in an automated sequence.Docket No. LAM1P136WO

[0139] Embodiment 30: The non-transitory computer-readable media of any one of embodiments 19-29, wherein (b) - (d) occur in a period of time of one week or less.

[0140] Embodiment 31: The non-transitory computer- readable media of any one of embodiments 19-30, wherein (b), (c), and (d) comprise transmitting and / or receiving information obtained via a user interface to a backend system via an application programming interface (API).

[0141] Embodiment 32: The non-transitory computer-readable media of embodiment 31, wherein training the digital twin and identifying the change in the at least one physical metrology measurement or at the at least one virtual metrology measurement comprise utilizing compiled source code not accessible via the user interface.

[0142] Embodiment 33: The non-transitory computer-readable media of any one of embodiments 19-32, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement comprise a plurality of changes.

[0143] Embodiment 34: The non-transitory computer-readable media of any one of embodiments 19-33, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is determined using the trained digital twin and based on the set of target wafer specifications.

[0144] Embodiment 35: The non-transitory computer- readable media of embodiment 34, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is determined based on at least one identified failure mode.

[0145] Embodiment 36: The non-transitory computer-readable media of embodiment 35, wherein the at least one identified failure mode corresponds to a virtual metrology measurement that is not within a corresponding specification of the set of target wafer specifications.

[0146] Embodiment 37: A system comprising: one or more processors; and one or more processor-readable media storing instructions which, when executed by one or more processors, cause performance of: (a) receiving indications of a set of process parameters, a set of virtual metrology measurements and a set of physical metrology measurements; (b) pairing physical metrology measurements of the set of physical metrology measurements with corresponding virtual metrology measurements of the set of virtual metrology measurements to form a set of paired metrology measurements; (c) training a digital twin of a semiconductor fabrication apparatus based on the set of process parameters and the paired metrology measurements to generate a trained digital twin; and (d) using the trained digital twin, providing an indication of a change in at least one physical metrology measurement or at least one virtualDocket No. LAM1P136WOmetrology measurement to be achieved to increase a yield in semiconductor wafers, wherein the yield is determined based on a percentage of processed wafers that meet a set of target wafer specifications.

[0147] Embodiment 38: The system of embodiment 37, wherein the digital twin resides on a server device remote from a computing device that provides the indication of the change in the at least one physical metrology measurement or the at least one virtual metrology measurement.

[0148] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

Docket No. LAM1P136WOCLAIMSWhat is claimed is:

1. A method for improving yield of semiconductor wafers, the method comprising: (a) receiving indications of a set of process parameters, a set of virtual metrology measurements and a set of physical metrology measurements;(b) pairing physical metrology measurements of the set of physical metrology measurements with corresponding virtual metrology measurements of the set of virtual metrology measurements to form a set of paired metrology measurements;(c) transmitting instructions for training a digital twin of a semiconductor fabrication apparatus based on the set of process parameters and the paired metrology measurements to generate a trained digital twin; and(d) receiving an indication of a change in at least one physical metrology measurement or at least one virtual metrology measurement to be achieved to increase a yield in semiconductor wafers, wherein the change is determined using the trained digital twin, and wherein the yield is determined based on a percentage of processed wafers that meet a set of target wafer specifications.

2. The method of claim 1, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is identified using a Pareto analysis of at least a subset of the set of process parameters, a subset of the virtual metrology measurements, and / or a subset of the physical metrology measurements.

3. The method of claim 2, wherein the subset of the set of process parameters, the subset of the virtual metrology measurements, and / or the subset of the physical metrology measurements are selected via a user interface.

4. The method of claim 2, wherein the subset of the set of process parameters are ranked based on contribution to variability of the subset of the virtual metrology measurements, and / or the subset of the virtual metrology measurements are ranked by an effect of process parameter variation on variability of the virtual metrology measurements.

5. The method of claim 4, further comprising presenting the rankings.Docket No. LAM1P136WO6. The method of claim 1, wherein the indication of the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is presented in a box plot depicting a current median and range of the at least one physical metrology measurement or the at least one virtual metrology measurement and a target median and range of the at least one physical metrology measurement or the at least one virtual metrology measurement to be achieved.

7. The method of claim 1, wherein the digital twin is configured to generate virtual metrology measurements that match a sensitivity and a variability of physical metrology measurements produced in a physical fabrication environment.

8. The method of claim 1, wherein the set of virtual metrology measurements comprises at least one virtual metrology measurement that does not have a corresponding physical metrology measurement.

9. The method of claim 1, wherein (a) occurs within a user interface, and wherein the indication of the at least one change to be achieved in (d) is presented within the same user interface.

10. The method of claim 1, wherein operations (a) - (d) occur in a period of time of less than two weeks.

11. The method of claim 10, wherein (b) - (d) occur in an automated sequence.

12. The method of claim 11, wherein (b) - (d) occur in a period of time of one week or less.

13. The method of claim 1, wherein (b), (c), and (d) comprise transmitting and / or receiving information obtained via a user interface to a backend system via an application programming interface (API).

14. The method of claim 13, wherein training the digital twin and identifying the change in the at least one physical metrology measurement or at the at least one virtualDocket No. LAM1P136WOmetrology measurement comprise utilizing compiled source code not accessible via the user interface .

15. The method of claim 1, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement comprise a plurality of changes.

16. The method of claim 1, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is determined using the trained digital twin and based on the set of target wafer specifications.

17. The method of claim 16, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is determined based on at least one identified failure mode.

18. The method of claim 17, wherein the at least one identified failure mode corresponds to a virtual metrology measurement that is not within a corresponding specification of the set of target wafer specifications.

19. A non-transitory computer- readable media storing instructions which, when executed by one or more processors, cause performance of:(a) receiving indications of a set of process parameters, a set of virtual metrology measurements and a set of physical metrology measurements;(b) pairing physical metrology measurements of the set of physical metrology measurements with corresponding virtual metrology measurements of the set of virtual metrology measurements to form a set of paired metrology measurements;(c) transmitting instructions for training a digital twin of a semiconductor fabrication apparatus based on the set of process parameters and the paired metrology measurements to generate a trained digital twin; and(d) receiving an indication of a change in at least one physical metrology measurement or at least one virtual metrology measurement to be achieved to increase a yield in semiconductor wafers, wherein the change is determined using the trained digital twin, and wherein the yield is determined based on a percentage of processed wafers that meet a set of target wafer specifications.Docket No. LAM1P136WO20. The non-transitory computer- readable media of claim 19, wherein the change in the at least one physical metrology measurement or the at least one virtual metrology measurement is identified using a Pareto analysis of at least a subset of the set of process parameters, a subset of the virtual metrology measurements, and / or a subset of the physical metrology measurements.

21. A system comprising:one or more processors; andone or more processor- readable media storing instructions which, when executed by one or more processors, cause performance of:(a) receiving indications of a set of process parameters, a set of virtual metrology measurements and a set of physical metrology measurements;(b) pairing physical metrology measurements of the set of physical metrology measurements with corresponding virtual metrology measurements of the set of virtual metrology measurements to form a set of paired metrology measurements;(c) training a digital twin of a semiconductor fabrication apparatus based on the set of process parameters and the paired metrology measurements to generate a trained digital twin; and(d) using the trained digital twin, providing an indication of a change in at least one physical metrology measurement or at least one virtual metrology measurement to be achieved to increase a yield in semiconductor wafers, wherein the yield is determined based on a percentage of processed wafers that meet a set of target wafer specifications.

22. The system of claim 21, wherein the digital twin resides on a server device remote from a computing device that provides the indication of the change in the at least one physical metrology measurement or the at least one virtual metrology measurement.

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