Single-ended to differential converters and co-packaged optical modules containing the same

Abstract

Methods, devices, and systems for circuits that generate differential output. In one aspect, a device includes a first differential pair comprising a first transistor and a second transistor. The device includes a second differential pair comprising a third transistor and a fourth transistor. An input signal is applied to the first transistor and the third transistor. The device includes a feedback network coupled to a gate of the second transistor, the feedback network comprising a resistor and a capacitor. A first current source is coupled to a source of the first transistor and a source of the second transistor. A second current source is coupled to a source of the third transistor and a source of the third transistor. The device includes a first output node coupled to a drain of the first transistor and a second output node coupled to a drain of the fourth transistor.

Description

[0001] Attorney Docket No. 22463-2129WO1

[0002] SINGLE-ENDED TO DIFFERENTIAL CONVERTERS AND CO-PACKAGED OPTICAL MODULES CONTAINING THE SAME

[0003] CROSS REFERENCE TO RELATED APPLICATION

[0004] This application claims the benefit of U. S. Provisional Application No. 63 / 790,023 filed on April 17, 2025, and titled “Single-Ended to Differential Converters,” which is incorporated herein by reference.

[0005] TECHNICAL FIELD

[0006] This specification generally relates to electrical circuits, and more specifically, single- ended to differential converters for high-speed optical receiver applications.

[0007] BACKGROUND

[0008] Demands for artificial intelligence (AI) computing, such as machine learning (ML) and deep learning (DL), are increasing faster than they can be met by increases in available processing capacity. This rising demand and the growing complexity of Al models drive the need to connect many chips into a system where the chips can send data between each other with low latency and at high speed. Performance when processing a workload is often limited by memory and interconnect bandwidth. In many conventional systems, data movement leads to significant power consumption, poor performance, and excessive latency. Co-Packaged Optics (CPO) refers to packaging technology that integrates photonics devices with conventional integrated circuits, such as application-specific integrated circuit (ASIC) devices. CPO solutions are candidates for data interconnects for Al data centers and other high performance computing applications.

[0009] In high-speed communication systems and other digital applications, such as those described above, many devices require accurate precise time, high data rates, and accurate signal representation to ensure reliable data transmission and reception, For example, in optical receiver chains, a transimpedance amplifier (TIA) can convert a current generated by a photodiode into a single-ended voltage signal. However, subsequent processing stages, such as with clocked comparators, limiting amplifiers, or other components, often require the use of differential signals for proper operation. Often converting a single-ended signal into differential signals may introduce performance limitations, such as in high-speed or wideAttorney Docket No. 22463-2129WO1

[0010] bandwidth applications. Such conversions may suffer from distortion, imbalance between outputs, increased power consumption, or increased latency.

[0011] SUMMARY

[0012] Single-ended to differential (S2D) conversion circuits are used in integrated circuits for converting a single-ended signal to a differential signal. Such conversion is often important for proper operation of various circuit components, such as those that operate in high communication data rate environments. In some implementations, the techniques described herein provide for an improved S2D conversion circuit. In particular, the S2D conversion circuit provides for a substantial reduction in differential output balance.

[0013] Conventional S2D converters often exhibit amplitude mismatches between the differential outputs due to asymmetric signal paths, where one side of the circuit sees a swinging input signal and the other side sees a static direct current (DC) level. In contrast, the S2D conversion circuits described herein reduces, e.g., resolves, this mismatch by functioning essentially as two separate single-to-ended differential paths that sum into each other. This S2D converter achieves a symmetrical signal path by providing paths in opposite directions, e.g., both an “up” and “down” path, from the single-ended input to the differential output nodes. Specifically, a first signal path routes the input signal in a first direction (“up”) to a tail node and in a second, opposite direction (“down”) to an output node, while a second signal path routes the input signal in the second direction (“down”) through a diode connected device, across a current mirror, and in the first direction (“up”) to the output node. To prevent doubling the capacitive load on an upstream transimpedance amplifier (TIA), the input stages of the differential pairs can be sized asymmetrically, such as with a two-to-one (2:1) ratio.

[0014] Moreover, the circuit described herein can improve a common-mode rejection.

[0015] Converting the single-ended signal to a differential signal directly at the output of the TIA provides an immediate power supply rejection. This dual path architecture ensures a stronger differential signal with a reduction of a common-mode component. As a resul t, the converter effectively limits the amount of thermal and power supply noise that finds its way to the downstream components.

[0016] In some implementations, the improved S2D converter provides for improved frequency response characteristics. To maximize available bandwidth, the S2D converter can include a center inductor that is coupled to the differential stages to provide bandwidth peaking. This architectural improvement can provide a reduction in output voltage mismatchAttorney Docket No. 22463-2129WO1

[0017] from conventional architectures. For example, simulation results demonstrates that an output voltage mismatch between differential outputs can be reduced from approximately 50 millivolts in conventional architectures to less than approximately 6.5 millivolts.

[0018] Additionally, the differential gain imbalance across the S2D converter’s operating frequency band is reduced to approximately 0.45 decibels, compared to approximately 3.3 decibels in conventional designs.

[0019] The subject matter described in this specification can be implemented in various embodiments and may result in one or more of the following advantages alternatively, or in addition, to those mentioned previously, The disclosed S2D converter allows a system to safely convert single ended signals to differential forms in the circuit path. The S2D converter mitigates linearity and clipping issues that arise when adding multiple single ended stages to a CMOS TIA. Additionally, the S2D converter executes these improvements with high power efficiency, operating within a highly constrained power envelope, such as within 20 milliwatts for the TIA.

[0020] The details of one or more embodiments of the subject matter of this specification are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, the drawings, and the claims.

[0021] BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram schematically illustrating an example of circuit packages for data communication over an optical network.

[0022] FIG. 2A is a diagram illustrating an example bi-directional photonic channel for light with a single wavelength.

[0023] FIG, 2B is a diagram illustrating an example bi-directional photonic channel for light with multiple wavelengths using wavelength-division multiplexing (WDM) technology.

[0024] FIG. 2C is a diagram illustrating an example tile including multiple photonic channels.

[0025] FIG. 2D is a diagram illustrating an example system including multiple tiles.

[0026] FIG. 3A is a diagram schematically illustrating an example structural circuit package. FIG. 3B is a diagram schematically illustrating an example of a circuit package implementing an intra-chip bidirectional photonic channel.Attorney Docket No. 22463-2129WO1

[0027] FIG. 3C is a diagram schematically illustrating an example circuit package implementing an inter-chip bidirectional photonic channel.

[0028] FIG. 3D is a diagram schematically illustrating another example circuit package implementing intra-chip unidirectional lanes for a single wavelength

[0029] FIG. 3E is a diagram schematically illustrating another example circuit package implementing inter-chip unidirectional lanes for multiple wavelengths,

[0030] FIG. 4 is a diagram is a diagram schematically illustrating an example analog-mixed signal (AMS) module including an example interface circuitry coupled between an AMS circuitry' and a flow control unit (FLIT) circuitry.

[0031] FIG. 5 is a diagram schematically illustrating an example of the AMS circuitry' of FIG. 4.

[0032] FIG. 6 is a diagram schematically illustrating an example of a transmitter circuit of the AMS circuitry’ of FIG, 4,

[0033] FIG. 7 is a diagram schematically illustrating an example of a receiver circuit of the AMS circuitry of FIG. 4.

[0034] FIG. 8 is a diagram schematically illustrating an example of a single-ended to differential (S2D) circuit that utilizes a clocked comparator offset cancellation scheme.

[0035] FIG. 9 is a diagram schematically illustrating an example of an S2D circuit for processing signals received from a photodiode.

[0036] FIG. 10 is a diagram schematically illustrating an example of an S2D circuit with differential configurations and current summing.

[0037] FIG. 11 is a plot that depicts a frequency response graph illustrating alternating current (AC) gain characteristics.

[0038] FIG. 12 is a diagram schematically illustrating an electro-photonic network with an S2D circuit coupled to or included within a TIA,

[0039] Like reference numbers and designations in the various drawings indicate like elements. The components shown here, their connections and relationships, and their functions, are meant to be examples only, and are not meant to limit the implementations described and / or claimed in this document.

[0040] DETAILED DESCRIPTION FIG. 1 is a diagram schematically illustrating an example of the circuit packages 140 and 160. Each circuit package can include a corresponding PIC 150, 170. Each PIC can include a number of components, e.g., optical couplers such as grating couplers, optical guiding system, optical modulators such as EAMs, photodetectors such as photodiodes (PDs),Attorney Docket No. 22463-2129WO1

[0041] optical multiplexer(s), and / or optical demultiplexer(s), that can be integrated in the PIC. For illustration, the photodetectors and tire photodiodes may be used interchangeably in the specification. These components can be implemented at least partially as waveguides.

[0042] In some implementations, a circuit package, e.g., 140, 160, can include a photonic integrated circuit (PIC), and an electronic integrated circuit (EIC) such as a digital and mixed-signal application-specific integrated circuit (ASIC). The EIC and PIC can be formed in different layers of the circuit package, which can be referred to as “electronic circuit layer” and “photonic circuit layer,” respectively, one stacked above the other, for example, using copper pillars, bump attachments, or other means to create an electrical interconnect to transmit and receive messages, packets, and / or other data between the EIC and the PIC.

[0043] In some implementations, the EIC includes multiple compute nodes. The compute nodes can communicate with each other over one or more intra-chip bidirectional channels. The intra-chip bidirectional channels can include one or more bidirectional photonic channels, e.g., implemented with optical waveguides in the PIC, and / or one or more electronic channels, e.g., implemented in the circuitry of the EIC. The compute nodes may but need not in all examples be electronic circuits identical or at least substantially similar in design, and as shown, may form “tiles” of the same size arranged in a grid or any other arrangement suitable for performing the computations described herein. Each compute node in the EIC can include one or more circuit blocks serving as processing engines, e.g., a dot product engine, DNN, or a tensor engine.

[0044] In some examples, the compute node can have any combination of processing units (or processing elements or processing devices or processing systems) such as CPUs, GPUs, TPUs, and the like, and the DNN and tensor engine can also be included or omitted depending on the application. Each compute node can include a message router. The message routers interface with channels, e.g., electronic and / or photonic channels to facilitate data flow to and from the compute nodes. Further, the compute node can have a memory system, e.g., including level-one static random-access memory (L1SRAM) and level-two static random access memory (L2SRAM). In some implementations, a compute node includes a compute block which may include various processing, storage, and / or communication functions, and an Analog Mixed Signal (AMS) block that can include analog / mixed signal circuits for interfacing with the PIC. The compute block can include an interface for communicating with the AMS block, or more specifically, with tire componentry of the AMS block.Attorney Docket No. 22463-2129WO1

[0045] A photonic integrated circuit (PIC) can include optical modulators and photodiodes, and an electronic integrated circuit (EIC), e.g., including an AMS block, can include modulator drivers and transimpedance amplifiers (TIAs). An optical modulator and a modulator driver can form an optical transmitter (TX), and a photodiode and a TIA can form an optical receiver (RX). In such a way, the circuit package can have at least one photonic transceiver (TX and RX) whose functionality resides partially in the PIC and / or partially in the EIC, which enables the photonic transceivers to send and receive data packets in the optical domain as modulated electromagnetic waves via photonic channels and / or as digital packets via electrical interconnections.

[0046] A photonic interface can include one or more transmitters and / or one or more receivers. The one or more transmitters can be referred to as an electrical-to-optical (EO) interface, and the one or more receivers can be referred to as an optical-to-electrical (OE) interface. That is, a photonic interface can include at least one of an EO interface or an OE interface. A transmitter in one photonic interface can connect with a receiver in another photonic interface to form a one-to-one unidirectional optical path or an optical lane.

[0047] Unidirectional optical paths formed between the two photonic interfaces can be independent from each other, which can avoid crosstalk between different optical paths and / or avoid path length compensation between different optical paths, e.g., when light is continuous wave - CW light.

[0048] When each of the photonic interfaces includes both an EO interface and OE interface, the photonic interface can provide bi-directional optical paths for optical signals modulated with data. A bi-directional optical path can include two unidirectional optical paths. As discussed with further details below, a photonic channel can include one or more unidirectional optical paths or one or more bidirectional optical paths.

[0049] To provide a large number of optical paths for high bandwidth data communication between photonic interfaces, circuit packages, e.g., 140, 160, and / or systems, wavelength¬ division multiplexing (WDM) or Dense wavelength -division multiplexing (DWDM) technology can be utilized, such that light with multiple wavelengths can be utilized. In some examples, a photonic channel includes multiple bidirectional optical paths, and a number of the multiple bidirectional optical paths is identical to a number of the multiple wavelengths. A number of unidirectional optical paths can be twice of the number of multiple wavelengths.

[0050] To further increase tire number of optical paths, optical splitting or optical dividing technology can be utilized, such that a light beam with a same wavelength can be split into multiple light portions with the same wavelength. In some examples, with the opticalAttorney Docket No. 22463-2129WO1

[0051] splitting technology, a same light source can provide input light for multiple photonic channels and / or multiple tiles each including multiple photonic channels.

[0052] In some implementations, each photonic interface or PIC can receive input light from a corresponding light source 102, 106 via corresponding optical fibers 104, 108, respectively. Each light source 102, 106 can include multiple light elements each providing a corresponding single wavelength of the multiple wavelengths. A number of the multiple light elements can be the number of the multiple wavelengths or multiple times of the number of the multiple wavelengths. A light element can be a laser diode or a laser. In some examples, the light element is configured to emit continuous wave (CW) light. In some examples, the light element is configured to emit pulsed light. In some examples, the multiple wavelengths are in a range from 1,500 nm to 1,600 nm, e.g., in the band of the spectrum referred to as the C-band and / or L-band. In some examples, a difference between adjacent wavelengths is about 10 nm. Light transmitted in a unidirectional optical path can be polarized (e.g., with s polarization) in single mode. An optical fiber, e.g., 104, 108, 130, for transmission can be polarization-maintaining single-mode fibers (PM-SMFs).

[0053] In some implementations, a light source can be implemented into tire PIC or implemented separately from the PIC either within or externally to the circuit package and coupled to the PIC by suitable optical couplers. For example, the light source can be integrated in a chip or a printed circuit board (PCB) coupled to the circuit package or the PIC, e.g., by suitable optical couplers.

[0054] An optical modulator can be an electro-absorption modulator (EAM), which is a semiconductor device that modulates the intensity of an optical signal by varying absorption of the optical signal as it traverses the modulator based on an electric voltage applied to the EAM, An operation of an EAM can be based on the Franz-Keldysh effect, e.g,, a change in the absorption spectrum caused by an applied electric field, which changes the bandgap energy, and thus the photon energy of an absorption edge, but usually does not involve the excitation of carriers by the electric field, EAMs can be made in the form of a waveguide with electrodes for applying an electric field in a direction perpendicular to the modulated optical signal. In some examples, the EAM is implemented in a layer of germanium silicon, e.g., an epitaxially-grown layer of Ge Si. Germanium can stoichiometrically constitute 90% or more of the GeSi material, e.g., 95% or more, 96% or more, 97% or more, 98% or more, or 99% or more.

[0055] As illustrated in FIG. 1, one or more photonic channels (unidirectional optical paths and / or bidirectional optical paths) can be formed between the circuit packages 140, 160, orAttorney Docket No. 22463-2129WO1

[0056] the photonic interfaces 112, 122. For example, light from a first light source 102 can be coupled through optical fibers 104 and grating couplers 151a into a first PIC 150 of the first circuit package 140 and be further guided to optical modulators 153 such as EAMs through an optical guiding system 152a. The optical modulators 153 can modulate the light with data by corresponding modulator drivers in a first EIC of the circuit package 140 to generate modulated light.

[0057] When the light includes multiple light beams each with a single wavelength of multiple wavelengths, modulated light beams with single w avelengths from the optical modulators 153 can be guided or optionally through an optical guiding system 152b to a multiplexer 154. The multiplexer 154 can multiplex the multiple light beams into a multiplexed light beam. The multiplexed light beam can be coupled out of the first PIC 150 through grating couplers 151b into the optical fibers 130, e.g., PM-SMFs, and then to the second circuit package 160. The multiplexed light beam can be coupled into a second PIC 170 in the second circuit package 160 through grating couplers 171c into a demultiplexer 175. The demultiplexer 175 can demultiplex the multiplexed light beam into multiple light portions each with a corresponding single wavelength. The multiple light portions each with the corresponding single wavelength can be guided, or optionally through an optical guiding system 172c, to photodiodes 176. The photodiodes 176 can convert detected light into electrical data that can be transmitted to corresponding TIAs, e.g., TIAs 177, in the second EIC of the second circuit package 160. In some implementations, each of the TIAs 177 can be coupled to a single-ended to differential (S2D) converter 178. In some implementations, each of the TIAs 177 can incorporate a corresponding S2D converter 178. The S2D converter 178 can be configured to convert the single-ended electrical output from a corresponding TIA of the TIAs 177 into a differential signal. In such a way, one or more inter-chip unidirectional optical paths or optical lanes are formed from the optical modulators 153 in the first PIC 150 to the corresponding PDs 176 in the second PIC 170. Accordingly, one or more inter-package unidirectional data paths are formed from the modulator drivers in the first EIC to the TIAs 177 and the S2D converter 178 in the second EIC.

[0058] In some implementations, one or more intra-chip unidirectional optical paths or optical lanes can also be formed from optical modulators to corresponding PDs in a same PIC, and accordingly, one or more intra-package unidirectional data paths can also be formed in a same circuit package.

[0059] In some implementations, the first PIC 150 can include a further optical guiding system 152d, e.g., channel waveguides, that can be coupled with one or more EAMs 153 toAttorney Docket No. 22463-2129WO1

[0060] one or more corresponding PDs 156. Each of the one or more EAM 153 can modulate light with a single wavelength with data from a corresponding modulator driver in a corresponding EIC stacked with the PIC 150 in the same first circuit package 140 and transmit the modulated light through a corresponding channel waveguide of the optical guiding system 152d to a corresponding PD 156 of the one or more corresponding PDs 156 in the same PIC 1 0.

[0061] The corresponding PD 156 can convert detected light into electrical data that can be electrically transmitted to a corresponding TIA 167 in the corresponding EIC of the first circuit package 140. In some implementations, each of the TIAs 167 can be coupled to a single-ended to differential (S2D) converter 168. In some implementations, each of the TIAs 167 can incorporate a corresponding S2D converter 168. The S2D converter 178 can be configured to convert the single-ended electrical output from a corresponding TIA of the TIAs 177 into a differential signal. Thus, an intra-chip unidirectional optical path or optical lane is formed from the EAM 153 to the corresponding PD 156 in the first PIC 150, and accordingly, an intra-package unidirectional data path is formed from the corresponding modulator driver in the corresponding EIC through the EAM 153, the corresponding channel waveguide in the optical guiding system 152d, the corresponding PD 156 to the corresponding TIA 167 and the S2D converter 168 in the corresponding EIC of the first circuit package 140.

[0062] Similarly, light from a second light source 106 can be coupled through optical fibers 108 and grating couplers 171a into the second PIC 170 of the second circuit package 160 and be further guided to optical modulators 173 such as EAMs through an optical guiding system 172a. The optical modulators 173 modulates the light with data by corresponding modulator drivers in the second EIC of the second circuit package 160 to generate modulated light. When the light includes multiple light beams each with a single wavelength of multiple wavelengths, modulated light beams with single wavelengths from tire optical modulators 173 can be guided or optionally through an optical guiding system 172b to a multiplexer 174. The multiplexer 174 can multiplex the multiple light beams into a multiplexed light beam.

[0063] The multiplexed light beam can be coupled out of the second PIC 170 through grating couplers 171b into the optical fibers 130, e.g., PM-SMFs, and then to the first circuit package 140. The multiplexed light beam can be coupled into the first PIC 150 in the first circuit package 140 through grating couplers 151c into a demultiplexer 155. The demultiplexer 155 can demultiplex the multiplexed light beam into multiple light portions each with a corresponding single wavelength. The multiple light portions each with the correspondingAttorney Docket No. 22463-2129WO1

[0064] single wavelength can be guided or optionally through an optical guiding system 152c to photodiodes 156. The photodiodes 156 can convert detected light into electrical data that can be transmitted to corresponding TIAs 167 in the EIC of the first circuit package 140. The electrical data output by the TIAs 167 in the EIC of the first circuit package 140 can be provided to a corresponding S2D converter 168. In such a way, one or more unidirectional optical paths or optical lanes are formed from the optical modulators 173 in the second PIC 170 to the corresponding PDs 156 in the first PIC 150. Accordingly, one or more unidirectional data paths are formed from the modulator drivers in the second EIC to the TIAs 167 and tire S2D converters 168 in the first EIC.

[0065] In some implementations, the second PIC 170 can include a further optical guiding system 172d, e.g., channel waveguides, that can be coupled with one or more EAMs 173 to one or more corresponding PDs 176 in the second PIC 170. Each of the one or more EAM 173 can modulate light with a single wavelength with data from a corresponding modulator driver in a corresponding EIC stacked with the second PIC 170 in the same second circuit package 160 and transmit the modulated light through a corresponding channel waveguide of the optical guiding system 172d to a corresponding PD 176 of the one or more corresponding PDs 176 in the same second PIC 170, The corresponding PD 176 can convert detected light into electrical data that can be electrically transmitted to a corresponding TIA in the corresponding EIC in the second circuit package 160. Thus, an intra-chip unidirectional optical path or optical lane is formed from the EAM 173 to the corresponding PD 176 in the second PIC 170. Accordingly, an intra-package unidirectional data path is formed from the corresponding modulator driver in the corresponding EIC through the EAM 173, the corresponding channel waveguide in the optical guiding system 172d, the corresponding PD 176 to the corresponding TIA in the corresponding EIC of the second circuit package 160.

[0066] In some implementations, the grating couplers 151a, 151b, 151c in the first PIC 150 can be arranged in an array, that can be coupled, e.g., in and out, with the optical fibers 130, 104 together using a first fiber array unit (FAU) or any other suitable coupling method, e.g., using V grooves for edge-coupled fibers. Similarly, the grating couplers 171a, 171b, 171c in the second PIC 170 can be arranged in an array, that can be coupled with the optical fibers 130, 106 together using a second fiber array unit (FAU) or any other suitable coupling method, e.g,, using V grooves for edge-coupled fibers.

[0067] In some implementations, the optical guiding systems 152a, 152b, and 152c in the first PIC 150 can be configured such that light can be guided in or out from corresponding components in the first PIC 150 in an ordered, efficient way and in a miniaturized area. ForAttorney Docket No. 22463-2129WO1

[0068] example, optical modulators 153 and PDs 156 for each photonic channel are positioned in a same corresponding channel area, and light beams with corresponding single wavelengths can be guided as two groups respectively to the optical modulators 153 and the PDs 156 in the corresponding channel area. Channel areas for different photonic channels are arranged adjacent to each other, lire multiplexers 154 and the demultiplexers 155 are arranged further from the channel areas and closer to the grating couplers 15 la, 151b, 1 1c, and can be arranged parallel to one another.

[0069] A multiplexer 154 and a demultiplexer 155 for a same photonic channel can be arranged adjacent to each other. In such a way, light from the optical modulators 1 3 to the multiplexer 154 and light from the demultiplexer 155 to the PDs 156 can be guided in corresponding waveguides adjacent to each other between a corresponding channel area and an area close to the grating couplers. Similarly, the optical guiding systems 172a, 172b, and 172c in the second PIC 170 can be configured such that light can be guided in or out from corresponding components in the second PIC 170 in an ordered, efficient way and in a miniaturized area.

[0070] FIG. 2A is a diagram illustrating an example bi-directional photonic channel 200 for light with a single wavelength, e.g,, Xo. The bi-directional photonic channel 200 includes two unidirectional optical paths or optical lanes 201a, 201b along opposite directions.

[0071] In a first optical path 201a, first light with tire single wavelength Xo from a first light source such as a laser diode 202a is coupled through an optical fiber 203a, e.g,, the optical fiber 104 or 108 of FIG. 1, to a first optical modulator 204a, e.g., the optical modulator 153 or 173 of FIG. 1, of a first transmitter. The first optical modulator 204a modulates the first light with data by a corresponding first modulator driver to provide modulated first light. Ihe modulated first light is transmitted through a first optical fiber 205a, e.g., the optical fiber 130 of FIG. 1, to a first photodetector 206b of a first receiver, e.g., the PD 176 or 156 of FIG. 1. The first photodetector 206b can be connected to a corresponding first TLA, e.g., T1A 167, which is coupled to an S2D converter 168 from FIG. 1. Thus, the first optical path 201a is formed from the optical modulator 204a to the first photodetector 206b.

[0072] In a second optical path 20 lb, second light with the single wavelength Xo from a second light source such as a laser diode 202b is coupled through an optical fiber 203b, e.g., the optical fiber 104 or 108 of FIG. 1, to a second optical modulator 206a, e.g,, the optical modulator 153 or 173 of FIG. 1, of a second transmitter. The second optical modulator 206a modulates the second light with data by a corresponding second modulator driver to provide modulated second light. Ihe modulated second light is transmitted through a second opticalAttorney Docket No. 22463-2129WO1

[0073] fiber 205b, e.g., the optical fiber 130 of FIG. 1, to a second photodetector 204b of a second receiver, e.g., the PD 176 or 156 of FIG. 1. The second photodetector 204b can be connected to a corresponding second TIA, e.g., TIA 177, which is coupled to an S2D converter 178 from FIG. 1. Thus, the second optical path 201b is formed from the second optical modulator 206a to the second photodetector 204b.

[0074] As discussed above and below, the first optical modulator 204a and the second photodetector 204b can be integrated in a first PIC 204, e.g., the PIC 150 or 170 of FIG. 1, or in a first photonic interface and be connected to the first modulator driver and the second TIA that can be integrated in a corresponding first EIC. The second optical modulator 206a and the first photodetector 206b can be integrated in a second PIC 206, e.g., the PIC 150 or 170 of FIG. 1, or in a second photonic interface and be connected to the second modulator driver and the first TIA that can be integrated in a corresponding second EIC.

[0075] FIG, 2B is a diagram illustrating an example bi-directional photonic channel 210 for light with multiple -wavelengths using wavelength-division multiplexing (WDM) technology. The bi-directional photonic channel 200 includes multiple bidirectional optical paths each with a corresponding single wavelength, or multiple pairs of unidirectional optical paths or optical lanes each with a corresponding single wavelength along opposite directions. For illustration, four -wavelengths, e.g., Xo, Xi, X2, X3, are described in the present disclosure. It is understood that a larger or smaller number of wavelengths can also be implemented.

[0076] A first ci rcuit 214 in a first PIC, e, g,, the PIC 150 or 170 of FIG, 1, can includ e multiple modulators 214a, e.g., the optical modulators 153 or 173 of FIG. 1, and multiple photodetectors 214b, e.g., the PDs 156 or 176 of FIG. 1. The first circuit 214 can also include an optical multiplexer 217a, e.g., the multiplexer 154 or 174 of FIG. 1, and an optical demultiplexer 218b, e.g., the demultiplexer 155 or 175 of FIG. 1. Each of the multiple photodetectors 214b are coupled to a corresponding TIA, e.g., TIA 167, which is coupled to an S2D converter 168 from FIG. 1.

[0077] A second circuit 216 in a second PIC, e.g., the PIC 150 or 170 of FIG, 1, can include multiple modulators 216a, e.g., the optical modulators 153 or 173 of FIG. 1, and multiple photodetectors 216b, e.g., the PDs 156 or 176 of FIG. 1. The second circuit 216 can also include an optical multiplexer 217b, e.g., the multiplexer 154 or 174 of FIG. 1, and an optical demultiplexer 218a, e.g,, the demultiplexer 155 or 175 of FIG. 1. Each ofthe multiple photodetectors 216b are coupled to a corresponding TIA, e.g., TIA 177, which is coupled to an S2D converter 169 from FIG. 1.Attorney Docket No. 22463-2129WO1

[0078] Each optical modulator 214a in the first circuit 214 is configured to receive a light beam with a corresponding single wavelength, e.g., Xo, Xi, X2, or Xs, from a corresponding laser diode 212a through a corresponding optical fiber 213a. The optical multiplexer 217a in the first circuit 214 multiplexes the multiple light beams from the multiple optical modulators 214a to obtain a multiplexed light beam that can be transmitted through an optical fiber 215a to the corresponding demultiplexer 218a in the second PIC 216. The demultiplexer 218a demultiplexes the multiplexed light beam into multiple light portions each with a corresponding single wavelength to corresponding photodetectors 216b, e.g., Xo, Xi, X?_, or Xs. Thus, a first group 210a of unidirectional optical paths with the multiple wavelengths is formed between the first circuit 214 and the second circuit 216.

[0079] Similarly, in the second PIC 216, each optical modulator 216a in the second circuit 216 is configured to receive a light beam with a corresponding single wavelength, e.g., Xo, Xi, X2, or X3, from a corresponding laser diode 212b through a corresponding optical fiber 213b. The optical multiplexer 217b in the second circuit 216 multiplexes the multiple light beams from the multiple optical modulators 216a to obtain a multiplexed light beam that can be transmitted through an optical fiber 215b to the corresponding demultiplexer 218b in the first circuit 214, The demultiplexer 218b demultiplexes the multiplexed light beam into multiple light portions each with a corresponding single wavelength to corresponding photodetectors 214b, e.g., Xo, Xi, X2, or X3. Thus, a second group 210b of unidirectional optical paths with the multiple wavelengths is formed between the first circuit 214 and the second circuit 216.

[0080] In some examples, the number of wavelengths is 4. For a photonic channel 210, there can include 4 optical modulators, 4 photodetectors, one optical multiplexer, and one optical demultiplexer in each of the first circuit 214 and the second circuit 216.

[0081] FIG. 2C is a diagram illustrating an example tile 220 including multiple photonic channels. Each photonic channel, e.g., 210-1, 210-2, 210-3, 210-4 (referred to generally as photonic channels 210 and individually as photonic channel 210), can be the same as, or similar to, the photonic channel 210 of FIG, 2B. For each photonic channel, there are multiple modulators, multiple photodetectors, an optical multiplexer and an optical demultiplexer in a first circuit 214, e.g., the first circuit 214 of FIG. 2B, and a second circuit 216, e.g., the second circuit 216 of FIG. 2B. A first PIC 221a can include multiple first circuits 214 for the multiple photonic channels 210, A second PIC 22 lb can include multiple second circuits 216 for the multiple photonic channels 210.

[0082] Different from FIG. 2B, for the tile 220, each PIC includes an optical spliting system configured to split light into multiple portions such that a same laser diode can provide lightAttorney Docket No. 22463-2129WO1

[0083] for multiple optical paths or optical lanes in different photonic channels. For example, a first optical splitting system 222a in the first PIC 221a can split light with a single light beam with a single wavelength, e.g., Xo, Xi, Xc, or la, from each corresponding laser diode 212a into multiple light portions with the same single wavelength for the multiple photonic channels 210-1, 210-2, 210-3, 210-4. lire number of the multiple light portions is identical to the number of the multiple photonic channels 210, e.g., 4. Similarly, a second optical splitting system 222b in the second PIC 221b can split light with a single light beam with a single wavelength, e.g., Xo, Xi, X?„ or X3, from each corresponding laser diode 212b into multiple light portions with the same single wavelength for the multiple photonic channels 210. lire number of the light portions is identical to the number of the photonic channels 210, e.g,, 4.

[0084] In some examples, the number of wavelengths is 4 and the tile 220 includes 4 photonic channels 210 corresponding to 32 optical lanes. For a tile, there can include 16 optical modulators, 16 photodiodes, 4 optical multiplexers, and 4 optical demultiplexers in each of the first PIC 221a and the second PIC 221b. That is, for the tile, there are total 32 optical modulators, 32 photodiodes, 8 optical multipliers, and 8 optical demultiplexers. In this instance, for each tile, each of the 32 photodiodes would be coupled to a respective TIA, and each TIA would be coupled to a corresponding S2D converter, for a total of 32 TIAs.

[0085] FIG. 2D is a diagram illustrating an example system 230 including multiple tiles. Each tile 220-1, 220-2 (referred to generally as tiles 220 and individually as tile 220) can include multiple photonic channels 210, e.g., 4. For each photonic channel, there are multiple modulators, multiple photodetectors, an optical multiplexer and an optical demultiplexer in a first circuit 214, e.g., the first circuit 214 of FIG. 2B, and a second circuit 216, e.g., the second circuit 216 of FIG. 2B. A first PIC 23 la can include multiple first circuits 214 for the multiple photonic channels 210 in the multiple tiles 220, A second PIC 221b can include multiple second circuits 216 for the multiple photonic channels 210 in the multiple tiles 220.

[0086] Similar to FIG. 2C, for the system, each PIC includes an optical splitting system configured to split light into multiple portions such that a same laser diode can provide light for multiple optical paths or optical lanes in different photonic channels. Different from the optical splitting system in FIG. 2C, the optical splitting system in FIG. 2D is configured to split light into more portions such that each lane in the multiple tiles can receive a light portion.

[0087] For example, a first optical splitting system 232a in the first PIC 231a can split light with a single light beam with a single wavelength, e.g., Xo, Xi, X?, or X3, from each corresponding laser diode 212a into multiple light portions, e.g., 8, with the same singleAttorney Docket No. 22463-2129WO1

[0088] wavelength for the total multiple photonic channels 210, e.g., 8 channels, in the multiple tiles 220-1, 220-2, e.g., 2 tiles. Similarly, a second optical splitting system 232b in the second PIC 231b can split light with a single light beam with a single wavelength, e.g., Xo, Xi, X2, or Xs, from each corresponding laser diode 212b into multiple light portions with the same single wavelength for the multiple photonic channels 210.

[0089] In some examples, the number of the multiple wavelengths is 4, and each title 220 includes 4 photonic channels 210, and each channel 210 corresponds to 4 bi-directional optical paths or 8 unidirectional optical paths or optical lanes. If the system 230 includes two tiles 220, which corresponds to 8 photonic channels 210 and 64 unidirectional optical lanes, the system 230 can include 32 optical modulators, 32 photodiodes, 8 optical multiplexers, and 8 optical demultiplexers in each of the first PIC 231a and the second PIC 23 lb. That is, the system 230 include total 64 optical modulators, 64 photodiodes, 16 optical multipliers, and 16 optical demultiplexers. If the system 230 includes four tiles 220, which corresponds to 16 photonic channels 210 and 128 unidirectional optical lanes, the system 230 can include 64 optical modulators, 64 photodiodes, 16 optical multiplexers, and 16 optical demultiplexers in each of the first PIC 231a and tire second PIC 23 lb. That is, the system 230 include total 128 optical modulators, 128 photodiodes, 32 optical multipliers, and 32 optical demultiplexers. In this case, the system 230 can include a similar number of TIAs as the number of photodiodes.

[0090] FIG. 3 A is a diagram schematically illustrating an example circuit package 300 with more details. In this example, an EIC 310 and a PIC 320, e.g,, the PIC 150 or 170 of FIG. 1, are formed in separate semiconductor chips, e.g., silicon chips, although other semiconductor materials may be used. The PIC 320 can be disposed directly on a substrate for subsequent mounting to a printed circuit board (PCB). Ihe EIC 310 and FAUs 302 that connect the PIC 320 to external waveguides 301, e.g., optical fibers, are disposed on top of and optically connected to the PIC 320. Tire EIC 310 can include ASIC that can be a 5 nm system-on-chip (SOC). Optionally, the circuit package 300 can further include an on-chip memory positioned on top of the PIC 320 adjacent to the EIC 310.

[0091] The depicted structure of the circuit package 300 is merely one of several possible ways to assemble and package the various components. In some examples, some or all of the EIC 310 is disposed on the substrate. In some examples, some or all of tire PIC 320 is placed on top of the EIC 310, In some examples, it is also possible to create the EIC 310 and PIC 320 in different layers of a single semiconductor chip. In some examples, the photonic circuit layer includes or is made of multiple PICs 320 in multiple sub-layers. Multiple layers of PICs 320, or a multi-layer PIC 320, may help to reduce waveguide crossings. Moreover,Attorney Docket No. 22463-2129WO1

[0092] the structure may be modified to included multiple EICs 301 connected to a single PIC 320. For example, the multiple EICs 301 may be connected to each other by photonic channels in the PIC 320.

[0093] In some implementations, the EICs and PICs can be manufactured using standard wafer fabrication processes. Further, in some examples, heterogeneous material platforms and integration processes are used. For example, various active photonic components, e.g., the laser light sources and / or optical modulators and photodetectors used in the photonic channels, may be implemented using group III -V semiconductor components.

[0094] The laser light source(s) can be implemented either in the circuit package 300 or externally. When implemented externally, a connection to the circuit package 300 may be made optically using a grating coupler in the PIC 320 underneath an FAU 302 as shown and / or using an edge coupler. In some cases, lasers are implemented in the circuit package 300 by using an interposer containing several lasers that can be co-packaged and edge-coupled with the PIC 320. In some cases, the lasers are integrated directly into the PIC 320 using heterogenous or homogenous integration. Homogenous integration allows lasers to be directly implemented in the silicon substrate in which the waveguides of the PIC 320 are formed, and allows for lasers of different materials, such as indium phosphide (InP), and architectures such as quantum dot lasers. Heterogenous assembly of lasers on the PIC 320 allows for group III-V semiconductors or other materials to be precision-attached onto the PIC 320 and optically coupled to a waveguide implemented on the PIC 320.

[0095] Light from fibers or to fibers can be coupled into and out of a PIC using a number of different ways. In some examples, multiple fibers 301, e.g., in an array, and grating couplers in the PIC 320 can be coupled by a FAU 302 which attaches to a surface of the PIC, e.g., the same surface as the ETC, as illustrated. In some examples, the PIC can include edge couplers with V-grooves and the fibers can be positioned on the V-grooves and coupled with their edges to waveguides in the PIC. In some examples, light is coupled in or out from a side of the PIC 320 or in or out from a top surface of the PIC 320,

[0096] In some implementations, multiple circuit packages 300 may be interconnected to result in a single system providing a large electro-photonic network, e.g., by connecting several chip-level electro-photonic networks. Multiple circuit packages configured as ML processors may be interconnected to form a larger ML accelerator. For example, the photonic channels within the several circuit packages or ML processors, the optical connections, the laser light sources, the passive optical components, and the external optical fibers on the PCB, may be utilized in various combinations and configurations along withAttorney Docket No. 22463-2129WO1

[0097] other photonic elements to form the photonic fabric of a multi -package system or multi -ML-processor accelerator.

[0098] Tire PIC 320 can be included in an interposer, and the EIC 210 can be stacked on the PIC 320. As illustrated in FIG. 3A, the PIC 320 can include an optical guiding system 323, e.g., made of channel waveguides. The optical guiding system 323 can include one or more grating couplers 321 attached to the FAU 302, one or more splitter trees 326, and one or more optical modulators, e.g., EAMs, 322 having contacts 325 with one or more modulator drivers, e.g., EAM drivers, 312 in the EIC 310 via attachments 313. In various embodiments, the attachment 313 is a pillar attachment, such as a 50 um pillar, lire PIC 320 can also include one or more photodiodes 324 that can be electronically connected to one or more corresponding trans-impedance amplifiers (TIAs) 314 in the EIC 210, e.g., by the attachment 215. The TIAs 314 can integrate corresponding S2D converters or may be coupled to the corresponding S2D converters.

[0099] In various embodiments, in a design like the circuit package 300, an EIC is directly- coupled to a PIC, such as shown in FIG. 3A. While FIG. 3A shows a particular configuration of a direct coupling between electronic and photonic elements, many other examples are possible. For example, while a copper pillar attachment connects an EAM driver to an EAM as well as connects a photodiode to a TIA, other embodiments for direct coupling, e.g., chip-to-chip packaging, can be used.

[0100] In various embodiments, the EAM is an optical modulation element that enables light to pass between a cathode and an anode. Additionally, the EAM provides thermal stability at over 30 degrees Centigrade and enables the PIC 320 to be packaged directly with one or more processors of the EIC 310 and / or memory chips. The EAM can provide optical connectivity both within a chip and chip-to-chip. In some examples, the EAM can be about 50 microns in size and / or operate at data rates between 50—115 Gbps, at less than 1.0 volt of power, e.g., but up to 2.0 volts.

[0101] FIG, 3B illustrates an example of a circuit package 330 implementing an intra-clnp bidirectional photonic channel between a first compute node 334-1 and a second compute node 334-2. The circuit package 330 can be same as or similar to the circuit package 140 or 160 of FIG. 1. The circuit package 330 can include various electronic and optical components implemented across an EIC 210 and a PIC 320.

[0102] Tire circuit package 330 includes two compute nodes 334-1 and 334-2, collectively, compute nodes 334, which each include a respective compute block 358-1 and 358-2 which may include various processing, storage, and / or communication functions. The computeAttorney Docket No. 22463-2129WO1

[0103] nodes 334 each include an Analog Mixed Signal (AMS) block 360-1 and 360-2, collectively AMS blocks 360, that includes analog / mixed signal circuits for interfacing with the PIC 320. Tire compute blocks 358 each include an interface 357-1 and 357-2, collectively interfaces 357, for communicating with the AMS blocks 360, or more specifically, with the componentry of the AMS blocks 360. Each compute block 358 including 358-1 and 358-2 can include a flow control unit (FLIT) circuitry’ 359 including 359-1 and 359-2, coupled to the interface 357 including 357-1 and 357-2. The FLIT circuitry' is configured to create flits or segment data from large data packets, which allows for efficient and reliable data transfer across interconnect networks. The AMS block 360-1, 360-2 can receive data from or transmit data to a processing unit or a memory' unit through the FLIT circuitry' 359-1, 359-2 and the interface 357-1, 357-2, e.g., as illustrated with further details in FIG. 4.

[0104] The AMS blocks 360 each include a modulator driver 362-1 and 362-2, collectively drivers 362, and each include a transimpedance amplifier (TIA) 364-1 and 364-2, collectively TIAs 364. Each of the TIAs 364 can include or be coupled to a corresponding S2D converter 168. The PIC 320 includes a pair of modulators 356-1 and 356-2 and a pair of photodetectors 366-1 and 366-2. The PIC 320 also includes a grating coupler 354 or other optical interface (OI) configured to receive and pass on light to one or more components and an optical splitter 326.

[0105] In some implementations, e.g., as illustrated with further details in FIG. 5, the EIC 310 includes a reference clock source 331 configured to provide a reference clock signal, e.g., with a clock frequency 200 MHz, to one or more AMS blocks 360-1, 360-2 in the EIC 310. Each AMS block 360-1, 360-2 can generate an operation clock signal, e.g., with an operation frequency of 14 GHz, using the reference clock signal. Hie operation clock signal can be shared by a plurality of receiver circuits, including the TIAs, and transmitter circuits, including the modulator drivers, to generate TX data signals embedded with clock information to transmit over a photonic network or decode data signals received from a photonic network,

[0106] A light engine 350 can provide light as an optical carrier signal for communication between the first compute node 334-1 and second compute node 334-2. The light engine 350 provides the carrier signal to a FAU 332 of the circuit package 330, such as through an optical fiber. Tire FAU 332 is optically coupled to the grating coupler 354 which directs the optical carrier signal on to other components of the circuit package 330. The splitter 326 receives the optical carrier signal from the grating coupler 354 and splits the optical signal along two optical paths 370 and 372. More generally, the splitter 326 may distribute theAttorney Docket No. 22463-2129WO1

[0107] optical carrier signal over any number of photonic paths. The optical paths 370 and 372 may be implemented as any suitable optical transmission medium and may include a mixture of waveguides and optical fibers, or any other suitable transmission medium. In the present example, the optical paths 370 and 372 can be implemented as waveguides in the PIC 320.

[0108] The optical paths 370 and 372 pass from the splitter 326 to the optical modulators 356-1 and 356-2, respectively. Each optical modulator modulates the optical carrier signal it receives from the splitter 326 based on information from its respective optical driver 362-1 and 362-2 and transmits the modulated signal along the respective optical path. A first photodetector 366-1 receives tire modulated signal from the optical path, e.g., from the associated modulator 356-2. As depicted, the optical path from modulator 356-1 connects to photodetector 366-2 and the optical path from modulator 356-2 connects to photodetector 366-1. The photodetectors 366-1, 366-2 convert the received modulated signal into respective electrical signal and pass the electrical signals to a transimpedance amplifier 364-1, 364-2 through which the compute nodes 334-1 and 334-2 receive the information encoded in the signals, in this way, communication occurs between the compute nodes through the various components just described. Accordingly, the PIC 320 described here includes an intra-chip bidirectional photonic channel, including two unidirectional photonic links for communicating both to and from each compute node.

[0109] Here, the first unidirectional photonic link is defined by the modulator driver 362-1, the optical modulator 356-1, the optical path 370, the photodiode 366-2, and the transimpedance amplifier 364-2. Similarly, the second unidirectional link is defined by tire modulator driver 362-2, the optical modulator 356-2, the optical path 370, the photodiode 366-1, and the transimpedance amplifier 364-1. The first and second unidirectional links operate in opposite directions. Additionally, one or more of the compute nodes 334 may include one or more serializers and / or deserializers for communicating signals between the compute nodes 334. In this way, tlie two unidirectional photonic links form the intra-chip bidirectional photonic channel.

[0110] FIG. 3C illustrates an example circuit package 340a implementing an inter-chip bidirectional photonic channel between a compute node 334a and an additional compute node 334b located on an additional circuit package 340b, such as a memory node on a memory circuit package. Tire circuit package 340a, 340b can be same as or similar to the circuit package 140, 160 of FIG. 1, 300 of FIGS. 3A-3B. The compute node 334a and / or the circuit package 340a may include tlie EIC 310 and tlie PIC 320 including the components described above with reference to FIG. 3B. Further, the PIC 320 can include a multiplexer 374, e.g.,Attorney Docket No. 22463-2129WO1

[0111] the multiplexer 154, 174 of FIG. 1, or 217a, 217b of FIG. 2B, and a demultiplexer 376, e.g., the demultiplexer 155, 175 of FIG. 1, or 218a, 218b of FIG. 2B. A demultiplexer and multiplexer can be used in a PIC for wavelength division multiplexing of optical signals, e.g., as described in FIGS. 1 and 2B-2D.

[0112] In tire inter-chip configuration shown in FIG. 3C, the optical modulator 356 transmits a modulated signal along an optical path 371 to the grating coupler 354. The modulated signal is passed through the multiplexer 374 prior to passing to the grating coupler 354.

[0113] From the grating coupler 354, the modulated signal travels through the FAU 332 and along an optical fiber to another grating coupler of the additional circuit package 340b, where the receiving componentry' of the additional circuit package 340b receives and processes the incoming signal. The receiving componentry may be the same as or similar to the receiving componentry of the circuit package 330 described above or may include any other means for receiving and processing the incoming signal.

[0114] Similarly, the additional circuit package 340b can generate and transmit a signal to the compute node 334a. The additional circuit package 340b may generate and transmit the signal using transmitting componentry7that may include transmitting componentry' similar to or the same as that of the circuit package 300 described above, or any other means. The additional circuit package 340b transmits a signal, for example, along an optical fiber to the FAU 332 and grating coupler 354. The signal travels along an optical path 373 to the photodetector 366 which converts the optical signal to an electrical signal as described herein. The received signal passes through the demultiplexer 376 prior to passing to the photodetector 366. In this way, an inter-chip bidirectional photonic channel is defined by two unidirectional photonic links.

[0115] Here, the first unidirectional photonic link is defined by the modulator driver 362, the optical modulator 356, the optical path 371, the multiplexer 374, the grating coupler 354, the FAU 332, an optical fiber, and recei ving componentry of the additional circuit package 340b. Similarly, the second unidirectional photonic link is defined by the transmiting components of the additional circuit package 340b, the optical fiber, the FAU 332, the grating coupler 354, the demultiplexer 376, the optical path 373, the photodetector 366, and the transimpedance amplifier 364, including or coupled to the S2D converter 168. The first and second unidirectional photonic links operate in opposite directions. In this way, the two unidirectional photonic links forms the inter-chip bidirectional photonic channel.

[0116] FIG. 3D is a diagram schematically illustrating another example circuit package 380 implementing multiple intra-chip unidirectional lanes for a single wavelength. Note that, asAttorney Docket No. 22463-2129WO1

[0117] illustrated in FIG. 1, the intra-chip unidirectional lanes for individual wavelengths can be also formed in circuit packages that can implement inter-chip bidirectional photonic channels.

[0118] As illustrated in FIG. 3D, the PIC 320 receives light from a light source 384 that can include a light element, e.g., a laser diode, configured to emit light with a single wavelength X. The light source 384 can be internally integrated in the circuit package 380 or externally coupled to the circuit package 380. For example, the light source 384 can be integrated in a printed circuit board (PCB) 382 that can be integrated with the circuit package 380, e.g., through PCIe.In some implementations, light with the single wavelength can be split into multiple light portions, e.g., four, as illustrated, with the same single wavelength by a splitter tree 326. Each light portion with the single wavelength can be transmitted through a corresponding channel waveguide 381 to a corresponding EAM 322 in the PIC 320. The corresponding EAM 322 can modulate the light portion with the single wavelength with data from a corresponding EAM driver 312 in the EIC 310 stacked with the PIC 320 in the same circuit package 380, and then transmit the modulated light through another corresponding channel waveguide 383 to a corresponding PD 324 in the same PIC 320. The corresponding PD 324 can convert detected light into electrical data that can be electrically transmitted, e.g., through copper pillar, to a corresponding TIA 314 in the EIC 210 of the circuit package 380. Thus, an intra-chip unidirectional optical path or optical lane is formed from the EAM 322 to the corresponding PD 324 in the PIC 320, and accordingly, an intra-package unidirectional data path is formed from the corresponding EAM driver 312 in the corresponding EIC 310 through the EAM 322, the corresponding channel waveguides 381, 383 in the PIC 320, the corresponding PD 324 to the corresponding TIA 314 in the corresponding EIC 310 of the circuit package 380. Each of the TIAs 314 can be coupled to a corresponding S2D converter 165. For example, multiple S2D converters 168 can be coupled to the TIAs 314. For example, if the TIAs 314 include 4 TIAs, then there are 4 S2D converters, one S2D converter included within or coupled to each TIA,

[0119] For the multiple light portions, e.g., 4, with the same single wavelength, multiple corresponding intra-chip unidirectional optical paths or optical lanes, e.g., 4, can be formed in the PIC 320, and multiple intra-package unidirectional data paths, e.g., 4, can be formed in the circuit package 380. It is noted that the circuit package 380 can also receive multiple light beams each with a corresponding single wavelength of multiple wavelengths, e.g., λ0, λ1, λ2, λ3. For each single wavelength of the multiple wavelengths, one or more intra-chipAttorney Docket No. 22463-2129WO1

[0120] unidirectional optical paths can be formed in the PIC 320 and / or one or more intra-package unidirectional data paths can be formed in the circuit package 380.

[0121] FIG. 3E is a diagram schematically illustrating another example circuit package 390 implementing inter-chip unidirectional lanes for multiple wavelengths. Note that, as illustrated in FIG. 1, FIGS. 2A-2D, and FIGS. 3A-3D, inter-chip bidirectional channels including pairs of inter-chip unidirectional lanes for each of the multiple wavelengths can also be formed in the circuit package 390.

[0122] As illustrated in FIG. 3E, a first PIC 320a can receive light from a light source 394 that can include multiple light elements, e.g., laser diodes, each configured to emit light with a single wavelength of multiple wavelengths, e.g., λ0, λ1, λ2, λ3. The light source 394 can be internally integrated in the circuit package 390 or externally coupled to the circuit package 390. For example, the light source 394 can be integrated in a printed circuit board (PCB) 392 that can be integrated with the circuit package 390, e.g., through PCIe.

[0123] In some implementations, for each light beam with a corresponding single wavelength of the multiple wavelengths, e.g., λ0, λ1, λ2, or λ3, an optical guiding system 396 in the first PIC 320a can guide the light beam to one or more corresponding EAMs 322. lire optical guiding system 396 can split the light beam into one or more light portions with the same corresponding single wavelength, e.g., using a splitter tree 326 of FIG. 3D. Each light portion with the corresponding single wavelength can be transmitted through a corresponding channel waveguide to a corresponding EAM 322 in the first PIC 320a. The corresponding EAM 322 can modulate the light portion with the single wavelength with data from a corresponding EAM driver 312 in a corresponding EIC 310a stacked with the first PIC 320a in the same circuit package 390. Then corresponding EAMs 322 for the multiple wavelengths can transmit the modulated light portions each with a respective single wavelength of the multiple wavelengths to an optical multiplexer 374 to obtain a multiplexed light beam with the multiple wavelengths. The multiplexed light beam with the multiple wavelengths can be transmitted, e.g., through optical fibers 391, to an optical demultiplexer 376 in a second PIC 320b. The optical demultiplexer 376 can demultiplex the multiplexed light beam into multiple light portions each with a corresponding single w avelength that can be transmitted to corresponding PDs 324 in the second PIC 320b. Each corresponding PD 324 can convert detected light into electrical data that can be electrically transmitted, e.g., through copper pillar, to a corresponding TIA 314 in a second EIC 310b stacked with the second PIC 320b. Each of the TIAs 314 can include or be coupled to a corresponding S2D circuit 168, similar to the functionality described with respect to FIG. 3D.Attorney Docket No. 22463-2129WO1

[0124] The second PIC 320b and the second EIC 310b can be in a second circuit package different from the circuit package 390, or in the same circuit package 390 as the first PIC 320a and the first EIC 310a. Thus, multiple inter-chip unidirectional optical paths or optical lanes for the multiple wavelengths, e.g., λ0, λ1, λ2, λ3, can be formed from the EAMs 322 in the first PIC 320a to the corresponding PDs 324 in the second PIC 320b, and accordingly, multiple inter-chip or inter-package unidirectional datapaths for the multiple wavelengths can be formed from the corresponding EAM drivers 312 in the first EIC 310a through the EAMs 322 in the first PIC 320a to the corresponding PDs 324 in the second PIC 320b then to the corresponding TIAs 314 in the second EIC 310b.

[0125] FIGS. 4 to 7 are diagrams schematically illustrating an example analog-mixed signal (AMS) module 400 that can include a flow control unit (FLIT) circuitry 402, an interface circuitry 404, and an AMS circuitry7or AMS block 406. The AMS module 400 can be integrated in an EIC, The EIC can be co-packaged with a PIC in a circuit package. The AMS circuitry 406 can be similar to, or same as, the AMS block 360-1, 360-2 of FIG. 3B. The FLIT circuitry 402 can be similar to, or same as, the FLIT circuitry 359-1 or 359-2 of FIG. 3B. The interface circuitry 304 can be similar to, or same as, the interface 357-1 or 357-2 of FIG. 3B.

[0126] In some implementations, the FLIT circuitry' 402 receives data, e.g., TX data in [255:0], from a processing unit or a memory' unit, e.g., through a transmission bus 401a, and transmit the data to the AMS circuitry' 406 through the interface circuitry' 404. The AMS circuitry 406 can further process the data to be an TX analog signal that can be encoded by an optical signal using an optical modulator in the PIC for optical transmission. In some implementations, the AMS circuitry' 406 receives an RX analog signal from a photodiode in the PIC and process the RX analog signal to be a RX data signal that can be transferred to the FLIT circuitry' 402 through the interface circuitry' 404. The FLIT circuitry' 402 can further transfer data, e.g., RX data out [255:0], to a memory unit or a processing unit, e.g., through a transmission bus 401b, Tire interface circuitry' 404 can be configured for data transmission between the AMS circuitry' 406 and the FLIT circuitry' 402. The FLIT circuitry' 402 can be configured for efficient and reliable data transfer to / from a processing unit or a memory unit.

[0127] With reference to FIG. 4, the FLIT circuitry' 402 includes a FLIT generator 402a coupled to the interface circuitry’ 404 and configured to transmit a data signal, e.g., from a processing unit or a memory' unit, to the interface circuitry' 404. The interface circuitry 404 is coupled betw een the FLIT generator 402a and the AMS circuitry 406. The FLIT generatorAttorney Docket No. 22463-2129WO1

[0128] 402a can be configured to convert input data packets into segmented data in a FLIT format for data transfer.

[0129] Tire segmented data in the FLIT format can include control information for routing and error detection and correction. A flit is the smallest unit of data used in network-on-chip (NoC) and other high-performance computing interconnects, and is a part of a larger packet. Each packet can be divided into multiple flits for efficient data transfer, A structure of the Flits can include a header Flit that contains routing information and sets up the path for the subsequent flits, body Flits: carry the actual payload or data, and a tail Flit that marks the end of the packet and may include error-checking information. In some examples, for data with 256 bits, in the FLIT format, cyclic redundancy check (CRC) codes can be arranged in a middle of the 256 bits, and error correction code (ECC) codes and / or other CRC codes can be arranged at the end of the 256 bits.

[0130] In some implementations, e.g., as illustrated in FIG, 4, the interface circuitry’ 404 includes a medium access control (MAC) sublayer 404a coupled to the FLIT generator 402a, and a plurality of physical coding sublay ers (PCSs) 404b coupled between the MAC sublayer 404a and the AMS circuitry 406. Each of the plurality of PCSs 404b is coupled to a respective second AMS circuit of the plurality of second AMS circuits in the AMS circuitry 406. A number of the plurality of PCSs 404b can be identical to a number of second AMS circuits, e.g., 4. For transferring data with 256 bits, each PCS 404b can transmit 64 bits to the respective second AMS circuit.

[0131] The MAC sublayer 404a and the plurality of PCSs 404b are configured for data transmission from the FLIT generator 402a to the plurality of second AMS circuits. In some implementations, the MAC sublayer 404a is configured to identify and correct transmission errors, acknowledge transmission, and / or retransmit data. Tire MAC sublayer 404a can be coupled to an external memory device 403, e.g., SRAM, that is configured to store data for the MAC sublayer 404a. The external memory device 403 can include a first SRAM for odd bits and a second SRAM for even bits. The PCS 404b can be configured for at least one of data encoding and decoding, scrambling and descrambling, alignment marker insertion and removal, block and symbol redistribution, or lane block synchronization and deskew. For example, the PCS 404b can be configured to encode data to get sufficient rising / falling edges for transmission.

[0132] In some implementations, each of the plurality of PCSs 404b is configured to output a corresponding TX data signal to a corresponding second AMS circuit of the plurality of second AMS circuits. The corresponding second AMS circuit can be configured to generateAttorney Docket No. 22463-2129WO1

[0133] a transmission clock signal, e.g., with 875 Mbps, and send the transmission clock signal to the PCS 404b, and the PCS 404b can be configured to transfer the corresponding TX data signal to the corresponding second AMS circuit using the transmission clock signal. In such a way, the local frequency of the clock signals of the second AMS circuit and the PCS 404b matches, and signals are synchronized between the AMS circuitry' 406 and the interface circuitry’ 404.

[0134] In some implementations, the FLIT circuitry' 402 includes a flow control unit (FLIT) reader 402b coupled to the interface circuitry 404 and configured to convert a data signal from the interface circuitry 404 into segmented data in a FLIT format for data transfer. Ihe interface circuitry' 404 is coupled between the FLIT reader 402b and the AMS circuitry 406. The segmented data in the FLIT format can include control information for routing and error detection and correction.

[0135] As illustrated in FIG. 4, the interface circuitry' 404 can include a medium access control (MAC) sublayer 404d coupled to the FLIT reader 402b and a plurality of physical coding sublayers (PCSs) 404c coupled between the MAC sublayer 404d and the AMS circuitry' 406.

[0136] Each of the plurality' of PCSs 404c is coupled to a respective first AMS circuit or RX circuit of the plurality of first AMS circuits. A number of the PCSs 404c can be identical to a number of the first AMS circuits, e.g., 4. In some examples, each PCS 404c can receive 64 bits from the respective first AMS circuit, and the data from 4 PCSs 404c can be converted into 256 bits data.

[0137] The plurality of PCSs 404c and the MAC sublayer 404d are configured for data transmission from the plurality of first AMS circuits to the FLIT reader 402b. In some implementations, the MAC sublayer 404d is configured to identify and correct transmission errors, acknowledge transmission, and / or retransmit data. Tire MAC sublayer 404d can be coupled to an external memory device 405, e.g., SRAM, that is configured to store data for the MAC sublayer 404d, Tire PCS 404c is configured for at least one of data encoding and decoding, scrambling and descrambling, alignment marker insertion and removal, block and symbol redistribution, or lane block synchronization and deskew'.

[0138] In some implementations, each of the plurality of PCSs 404c is configured to receive a corresponding RX data signal from a corresponding first AMS circuit of the plurality of first AMS circuits, and the MAC sublayer 404d is configured to integrate corresponding RX data signals, e.g., data with 64 bits, from the plurality of PCSs into an integrated data signal, e.g., data with 256 bits.Attorney Docket No. 22463-2129WO1

[0139] In some implementations, the interface circuitry 404 includes one or more other components, e.g., an internipt request controller (IRQ) controller 404e, control / status registers 404f, and / or a finite state machine (FSM) 404g. The IRQ controller 404e can receive hardware interrupt events from various sources and present them to a processing unit, which allows the processing unit to handle real-time events efficiently without constantly polling.

[0140] In some implementations, the FLIT circuitry' 402 and the interface circuitry 404 can be connected through an Advanced extensible Interface (AXI) interface 408. The AXI is a communication bus protocol that connects on-chip peripheral circuits to processor cores. The AXI interface 408 can include a first AXI bus 408a, through which the FLIT generator 402a transfer segmented data to the MAC sublayer 404a, and a second AXI bus 408b, through which the MAC sublayer 404d transfers data to the FLI T reader 402b.

[0141] FIG, 5 is a diagram schematically illustrating an example of the AMS circuitry 406 of FIG. 4. As illustrated in FIG. 5, the AMS circuitry 406 includes a plurality of first AMS circuits 504, e.g., RX circuit, and a plurality of second AMS circuits 506, e.g., TX circuit. Each AMS circuit 504 can be coupled to a respective photodiode in the PIC to form a receiver (RX). Each AMS circuit 506 can be coupled to a respective optical modulator, e.g,, EAM, in the PIC to form a transmitter (RX). FIG. 6 is a diagram schematically illustrating an example of the second AMS circuit or TX circuit 506 of FIG. 5, and FIG. 7 is a diagram schematically illustrating an example of the first AMS circuit or RX circuit 504 of the AMS circuitry 406 of FIG. 5. There may be fewer or additional transmitters (TX) and receivers (RX) in the AMS block 406 than those shown in FIG. 4.

[0142] In some examples, the AMS circuitry 406 is associated with a channel that can include 4 bi-directional optical paths or 8 unidirectional optical paths or optical lanes. For example, a first AMS circuit 504, e.g., RX1, and a second AMS circuit 506, e.g., TX1, can be associated with a bi-directional optical path, e.g., as illustrated in FIG. 3B. Similarly, RX2 and TX2, RX3 and TX3, RX4 and TX4 can be associated with respective bi-directional optical paths.

[0143] In some implementations, each first AMS circuit (or RX circuit) 504 is configured to receive a respective RX analog signal from a corresponding photodiode in the PIC and convert the respective RX analog signal into a corresponding RX data signal, and the interface circuitry' is configured to convert the corresponding RX data signal into a data signal that can be delivered to the FLIT circuitry 402. In some implementations, the interface circuitry 404 is configured to convert the second data signal into a plurality of TX dataAttorney Docket No. 22463-2129WO1

[0144] signals for the plurality of second AMS circuits 506, and each of the plurality of second AMS circuits 506 is configured to convert a respective TX data signal into a corresponding IX analog signal and deliver the corresponding TX analog signal to a corresponding optical modulator in the PIC for modulating an optical signal with the corresponding TX analog signal.

[0145] In some implementations, e.g., as illustrated in FIG, 5, the AMS circuitry 406 includes a clock signal generator 502 configured to receive a reference clock signal from a reference clock source 501, e.g., the reference clock source 331 of FIG. 3B. The reference clock source 501 can be integrated in the EIC and configured to provide the reference clock signal to one or more AMS circuitries 406 in the EIC, e.g., as illustrated in FIG. 3B.

[0146] Tlie clock signal generator 502 is configured to generate an operation clock signal based on the reference clock signal, lire operation clock signal has an operation frequency greater than a clock frequency of the reference clock signal, In some examples, the clock frequency of the reference clock signal is about 200 MHz, and the operation frequency is about 14 GHz. In some examples, the clock signal generator 502 includes an inductorcapacitor phase-locked loop (LCPLL) circuit. The LCPLL circuit can use an LC tank circuit to generate a stable oscillation frequency. The LCPLL circuit includes a closed-loop system that ensures that an output signal remains in phase with an input signal, maintaining a stable and accurate frequency, lire LCPLL circuit can include a single-ended LCPLL, a differential LCPLL, a quadrature LCPLL, an injection -Locked LCPLL, or a fractional-N LCPLL

[0147] In the AMS circuitry 406, each first AMS circuit or RX circuit 504 or second AMS circuit or TX circuit 506 can receive the operation clock signal with the operation frequency, e.g., 14 GHz, and can generate corresponding RX signal or TX signal with a corresponding frequency. For example, the second AMS circuit 506 can generate a high speed TX signal, e.g., with a frequency of 56 GHz, for the PIC, while the first AMS circuit 504 can generate a low speed RX signal, e.g., with a speed of 875 Mbps, for a processing unit or a memory unit.

[0148] In some implementations, e.g., as illustrated in FIG, 6, a second AMS circuit or TX circuit 506 is configured to receive the operation clock signal and a TX data signal, e.g., from a processing unit or a memory unit through the FLIT circuitry 402 and tlie interface circuitry 404, and generate a corresponding TX analog signal using the operation clock signal and the TX data signal. Thus, the corresponding TX analog signal includes both clock information and data information. The operation frequency of the operation clock signal can be greater than a frequency associated with the TX data signal, and smaller than a frequency associated with the corresponding TX analog signal.Attorney Docket No. 22463-2129WO1

[0149] In some examples, the operation clock frequency is 14 GHz, the TX data signal is transferred with 875 Mbps, and the TX analog signal is 56 GHz. As noted above, the corresponding TX analog signal can be delivered to a corresponding optical modulator in the PIC for modulating an optical signal with the corresponding TX analog signal. Thus, the AMS circuitry 406 can combine a low speed data signal from the processing unit or the transmitting unit into a high speed optical signal for the PIC, and the high speed optical signal includes data information embedded clock information. The clock information can be distributed over the photonic network, which can save a lot of power and cost compared to distributing the clock information electronically. Tire photonic network can connect a number of compute nodes. A compute node can be connected to a remote node, and each compute node is connected to the photonic network. Thus, as long as the photonic network has the clock information, every' compute node can have the clock information.

[0150] In some implementations, e.g., as illustrated in FIG, 6, the second AMS circuit or TX circuit 506 includes a first multiplexer 603, an oscillator circuit 601, a second multiplexer 605, and a modulator driver 608. The first multiplexer 603 is configured to convert the TX data signal into a plurality of digital data signals associated with a same transmission speed. Tire first multiplexer 603 can be a 64:4 multiplexer that can, for example, convert 875 Mbps data into 14 Gbps data. The oscillator circuit 601 is configured to convert the operation clock signal into a plurality of clock signals having the operation frequency with different phases, e.g., 4 clock signals having 14 GHz and 4 different phases. Tire oscillator circuit 601 can include an integrated logic oscillator (ILO) circuit.

[0151] The second multiplexer 605 is configured to generate an integrated data signal based on the plurality of digital data signals, e.g., 4 digital data signals with 14 Gbps speed, and tire plurality of clock signals, e.g., 4 clock signals having 14 GHz and 4 different phases. Tire second multiplexer 605 can be a 4: 1 multiplexer, and the integrated data signal can be 56 Gbps data. The modulator driver 608 is configured to generate the corresponding TX analog signal based on the integrated data signal. The modulator driver 608 can be an EAM driver, and the TX analog signal can be delivered to a corresponding optical modulator, e.g., EAM, in the PIC for modulating an optical signal with the TX analog signal.

[0152] In some implementations, as the modulator driver 608 in the second AMS circuit can be in direct electrical connection, e.g., by conductive pillars, with the corresponding optical modulator in the PIC, the modulator driver 608 can directly transfer the corresponding TX analog signal to the corresponding optical modulator in the PIC, without data processing on the corresponding TX analog signal, which can increase the transmission speed. The secondAttorney Docket No. 22463-2129WO1

[0153] AMS circuit can include no data processing unit, e.g., no digital signal processor (DSP). As discussed below with further details, a corresponding RX circuit that receives an RX analog signal generated based on the corresponding TX analog signal without processing can include a Feed-Forward Equalizer (FFE) circuit to process, e.g., correct, equalize, or compensate, the RX analog signal.

[0154] In some implementations, the second AMS circuit 506 further includes a correction circuitry' 602 coupled to the oscillator circuit 601 and configured to correct timing among the plurality of clock signals having the operation frequency with the different phases. The correction circuitry 602 can include one or more duty cycle correction (DCC) circuits, one or more quadrature error correction (QEC) circuits, or a combination thereof. Tire second AMS circuit 506 can further include a retimer 604 that has inputs coupled to the correction circuitry 602 and the first multiplexer 603 and an output coupled to the second multiplexer 605. The retimer 604 is configured to retime the plurality of data signals and the plurality of clock signals and output the retimed data signals and the clock signals to the second multiplexer 605. The retimer 604 can include flip-flop logics. The second AMS circuit 506 can further include a data buffer 606 coupled between the second multiplexer 605 and the modulator driver 608, In some examples, the data buffer 606 includes 4 inverters with a fan out of 2 to allow the 4: 1 multiplexer to drive the EAM driver input.

[0155] The correction circuitry 602 and the retimer 604 are configured to get the clock signals, e.g., 4-phase 14GHz clock signals, and the data signal, e.g., 14 Gbps data signals, to the second multiplexer 605, e.g., 4: 1 multiplexer, with correct timing. The correction circuitry 602 can be a DCC-QEC circuit that includes capacitance based programmable delays, for correcting quadrature error, and programmable loads for skewing a P / N ratio of an inverter for correcting duty cycle error. Tire DCC-QEC circuit can include one or more DCC sub-circuits and one or more QEC sub-circuits that are coupled together. The retimer 604 can include one or more level-shifters for shifting data from the 64:4 p2s and flops for selecting the correct time slot for the data and clocks going to the second multiplexer 605, e.g., 4:1 multiplexer.

[0156] The 4: 1 multiplexer can include 25% duty cycle select clock generator and uses gated inverters to multiplex the data. The second multiplexer 605 can also use a dummy multiplexer to route clocks via a low pass filter (LPF) to a probe point that can be measured at a probe pad. Using this probe point, the average values of all clocks (or Duty Cycle) and the average delay between clocks (or skew) can be measured. Based on this measurement,Attorney Docket No. 22463-2129WO1

[0157] selective delay can be applied to clocks to allow for duty-cycle and quadrature error correction.

[0158] With reference to FIG. 7, a first AMS circuit, e.g., RX circuit, 504 can receive the operation clock signal from the clock signal generator 502, e.g., LCPLL, and a RX analog signal, e.g., from a corresponding photodiode in the PIC, and generate a corresponding RX data signal using the operation clock signal and the RX analog signal. The corresponding RX data signal can be provided to a processing unit or a memory' unit through the interface circuitry 404 and the FLIT circuitry 402, e.g., as illustrated in FIG. 4. The operation frequency of the operation clock signal can be greater than a frequency associated with the corresponding RX data signal and smaller than a frequency associated with the RX analog signal. In some examples, the operation frequency is 14 GHz, the RX analog signal has a transfer speed of 56 Gbps, and the RX data signal has a transfer speed of 875 MHz. The first AMS circuit or RX circuit 504 is configured to convert a high speed optical signal to low speed digital signal for the processing unit or the memory' unit.

[0159] In some implementations, e.g., as illustrated in FIG. 7, the first AMS circuit or RX circuit 504 includes a transimpedance amplifier (TIA) 701, an S2D converter 768, a feed-forward equalizer (FFE) circuit 702, a plurality of samplers 704, and a serial-to-parallel (S2P) interface 707 that are coupled in series along a signal path. Tire S2D converter 768 is similar to the S2D converters 168 and 178 from FIG. 1.

[0160] The TIA 701 is configured to amplify a RX analog signal from the corresponding photodiode in the PIC. Tire S2D converter 768 is coupled to the TIA 701. The FFE circuit 702 is coupled to the S2D converter 768 and configured to convert the differential signal into a plurality' of data signals with different phases. The TIA 701 can include or be coupled to a corresponding S2D converter 768. The functionality and components of the S2D converter 768 will be further described below. The TX analog signal has a higher transfer speed than the plurality of data signals. In some examples, the TX analog signal has a transfer speed of 56 Gbps, while the plurality of data signals has a transfer speed of 14 Gbps. The number of the plurality of data signals can be 4. The 4 data signals can have respective phases, e.g., 0°, 90°, 180°, 270°. The plurality of samplers 704 are coupled to the FFE circuit 702 and each sampler 704 is configured to sample a respective data signal with a corresponding phase.

[0161] A number of the samplers 704 can be identical to a number of the data signals, e.g., for non-retum-to-zero (NRZ) applications, or greater than the number of the data signals, e.g., for duobinary applications. For example, as the first AMS circuit or RX circuit 504 has a quarter rate architecture, each lane needs 4 data path samplers for NRZ applications. ToAttorney Docket No. 22463-2129WO1

[0162] support the duobinary each lane needs 12 samplers. That is, a data signal is sent to 3 samplers 704. A sampler 704 driven by a single phase clock signal can include a double-tail dynamic comparator followed by an SR latch. The comparator determines input differential data either high or low, and generates differential return-to-zero (RZ) shaped output signals. Then, the SR latch converts comparator outputs to the single-ended rail-to-rail non-return-to-zero (NRZ) data.

[0163] The serial-to-parallel (S2P) interface 707 is coupled to the plurality of samplers 704 and configured to generate a corresponding RX data signal based on outputs from the plurality of samplers 704. The S2P interface 707 can include a digital circuit that converts serial data, data sent one bit at a time, into parallel data, e.g., multiple bits sent simultaneously. In some examples, the first AMS circuit 504 further includes a retimer between the samplers 704 and the S2P interface 707. The retimer can align 4-phase output data from the samplers 704 to support synchronized operation. Incoming Data stream can be demultiplexed by either 8 or 16. There can be 12 input streams for 4 phases, each phase having 3 samples. Output words can be retimed on a common word clock and sent to digital. The S2P interface 707 can feature a 1: 16 deserializer core, and the 12 data streams can go into 12 cores to generate 192 parallel bits to the digital, With the 1:16 deserializer core, data with 14 Gbps can be converted into data with 875 Mbps.

[0164] In some implementations, the first AMS circuit, e.g., RX circuit, 504 further includes a reference signal generator 705 configured to generate a reference direct current (DC) signal for the plurality of samplers 704.

[0165] In some implementations, the FFE circuit 702 includes a plurality of thread circuits 703 coupled to the plurality of samplers 704, and each thread circuit 703 is configured to convert the RX analog signal into a respective data signal with a corresponding phase and output the respective data signals with the corresponding phase to one or more corresponding samplers.

[0166] In some implementations, e.g,, as illustrated in FIG. 7, the first AMS circuit or RX circuit 504 includes a first oscillator circuit 710, a phase integrator (PI) 711, and a second oscillator circuit 712. The first oscillator circuit 710 is configured to convert the operation clock signal from the clock signal generator, e.g., LCPLL, 502 into a plurality of first clock signals having the operation frequency with first different phases. The phase integrator (PI) 711 is coupled to the first oscillator circuit 710 and configured to generate a single-phase, adjustable clock signal based on the plurality of first clock signals. The second oscillator circuit 712 is configured to generate a plurality of second clock signals with second different phases basedAttorney Docket No. 22463-2129WO1

[0167] on the single-phase, adjustable clock signal from the phase integrator 711. Each of tlie plurality of thread circuits 703 is configured to generate the respective data signal based on a corresponding second clock signal.

[0168] In some examples, each of the first oscillator circuit 710 and the second oscillator circuit 712 can be an integrated logic oscillator (ILO) circuit, e.g., the oscillator circuit 601 of FIG, 6. In some examples, the first oscillator circuit 710 receives the operation clock signal from LCPLL to create 8 phases 14 GHz clock signal, which are sent to the PI 611. The PI 611 takes in the 8 phases provided by the first oscillator circuit 710, and produces a single-phase, adjustable clock based on interpolation input codes and subsequently transmits it to the second oscillator circuit 712. The second oscillator circuit 712 receive the operation clock signal from the PI 611 and create 4 phases 14 GHz clock and supply for the FFE circuit 702 / samplers 704.

[0169] In some implementations, the first AMS circuit 504 further includes: a first correction circuitry' 714 and a second correction circuitry 716. The first correction circuitry' 714 is coupled between the second oscillator circuit 712 and each of the plurality' of thread circuits 703 in the FFE circuit 702 and configured to perform correction on the corresponding second clock signal. The first correction circuitry’ 714 can include a quadrature clock correction (QCC) circuit that corrects duty' cycle distortion and phase error. The second correction circuitry 716 is coupled to an input of the first correction circuitry 714 and an output of the S2P interface 707 and configured to balance the second difference phases of the plural ity of second clock signals. The second correction circuitry' 716 can include one or more QCC circuits and / or one or more DCC circuits that improve clock signal quality and reduce duty cycle distortion. Each of the plurality of samplers 704 is coupled to the first correction circuitry 714 and configured to receive an output of the first correction circuitry’ 714 based on the corresponding second clock signal.

[0170] In some implementations, e.g., as illustrated in FIG. 7, the thread circuit 703 includes a pulse generator 703a, a track and hold (T& H) circuit 703b, a variable gain amplifier (VGA) 703c, and a summer 703d. The pulse generator 703a is coupled to an output of the first correction circuitry 714 and configured to generate timing pulses based on the corresponding second clock signal. The track and hold (T&H) circuit 703b is coupled to the pulse generator 703a and configured to smooth the RX analog signal using the timing pulses. The variable gain amplifier (VGA) 703c is coupled to the T& H circuit 703b and configured to amplify the respective RX analog signal with a corresponding gain. The summer 703d is coupled to tlieAttorney Docket No. 22463-2129WO1

[0171] VGA 703c and the pulse generator 703a and configured to perform weighted summing on the respective RX analog signal.

[0172] In some implementations, the first AMS circuit 504 further includes a clock data recovery (CDR) circuit 706 configured to receive the corresponding RX data signal and recover a clock signal associated with the corresponding RX data signal. The CDR circuit 706 is coupled to the phase integrator 711 and configured to feed the recovered clock signal back to the phase integrator 711. The plurality of second clock signals can be generated based on the recovered clock signal.

[0173] In some implementations, the first AMS circuit 504 further includes an FFE feedback circuit 708 coupled between an output of the S2P interface 707 and the FFE circuit 702 and configured to feed the corresponding RX data signal back to the FFE circuit 702. The FFE feedback circuit 708 can include an FFE Tap adaption configured for improving a quality of an optical eye diagram from a corresponding optical modulator.

[0174] FIG. 8 is a diagram schematically illustrating an example of a single-ended to differential (S2D) circuit that utilizes a clocked comparator offset cancellation scheme. In some implementations, the S2D circuit or S2D converter is configured to convert an electrical signal into a differential signal.

[0175] In some implementations, the S2D converter is an electric converter that is configured to transform a single-ended input signal into a differential output signal. The single-ended input signal can be a voltage varying signal relative to a fixed ground reference, A differential output signal includes two complementary voltage outputs, e.g., a positive voltage output and a negative voltage output. The differential output signal can be provided across two separate paths.

[0176] In some implementations, the S2D converter can be employed in various communication systems. For example, the S2D converter can be employed in communication systems, high-speed data converters, and analog front-end circuits to interface single-ended sources to differential processing blocks. In an optical receiver chain, for example, the transimpedance amplifier (TIA) typically can convert the current generated by a photodiode into a single-ended voltage signal. However, subsequent high-speed processing stages, such as clocked comparators, limiting amplifiers, or feed-forward equalizers (FFEs), require differential signals for proper operation. The S2D converter can bridge this gap by providing the necessary' signal conditioning for the high-fidelity data transmission.Attorney Docket No. 22463-2129WO1

[0177] There are many challenges associated with converting a single-ended signal to a differential signal. For example, the conversion of single-ended signals to differential signals present challenges in maintaining signal integrity, especially at high frequencies. As data rates continue to rise in modem communication systems, the need for accurate and efficient signal-ended to differential conversions increases. Traditional conversion methods often straggle to provide balanced outputs across wide frequency ranges, leading to signal distortion and degraded performance in subsequent processing stages. One common issue in single-ended to differential converters is the presence of amplitude and phase imbalances between the differential outputs. These imbalances can arise from various factors including, for example, parasitic capacitances, mismatched components, and asymmetric signal paths. Such imbalances can introduce errors in downstream circuitry, potentially leading to increased bit error rates in digital communication systems or reduced accuracy in analog-to- digital conversion process.

[0178] Another challenge in single-ended to differential conversion is maintaining low noise and high linearity across the operating frequency range. As signal frequencies increase, converters may exhibit degraded performance due to bandwidth limitations, increased thermal noise, and non-linear effects in active components. These issues can compromise the overall signal -to-noise ratio and dynamic range of the system, limiting its effectiveness in applications requiring high precision or wide dynamic range. Power consumption is an additional consideration in the design of single-ended to differential converters, particularly for battery-powered or energy-efficient devices. Achieving high-performance conversion while minimizing power consumption often involves trade-offs in circuit complexity, bandwidth, and noise performance. Balancing these factors to meet the requirements of specific applications remains an ongoing challenge for circuit designs. Furthermore, the integration of single-ended to differential converters with other circuit blocks, such as transimpedance amplifiers in optical receivers, presents additional design considerations. Ensuring proper interfacing, maintaining signal integrity, and managing parasitic effects become increasingly complex as system integration levels increase. These challenges can be further compounded in multi-channel systems, where maintaining consistency across multiple conversion paths is important for overall system performance. As the demand for higher data rates and improved signal quality continues to grow across various applications, advancements in single-ended to differential conversion techniques are sought to address these challenges and enable the next generation of high performance analog and mixed signal systems.Attorney Docket No. 22463-2129WO1

[0179] The example of FIG. 8 illustrates one such S2D converter, in particular, the S2D circuit utilizes a clocked comparator offset cancellation scheme. For example, a photodiode 700 D1 may be configured to generate a current in response to receiving incident light. The photodiode 700 D1 may be coupled to a transimpedance amplifier (TIA) 701. As shown in FIG. 8, the photodiode D1 700 can be biased via a biasing network that include a capacitor CF 800 and a resistor RB 804 coupled to a bias voltage VB. The photodiode D1 700 is coupled to the TIA 701 at an input node Y. The coupling between devices illustrated in FIG.

[0180] 8 may be electrically coupled, connected, or in communication with.

[0181] In some cases, tire TIA 701 may include an operational amplifier (OP1) 808 and a feedback resistor (RF1) 806. The operational amplifier 808 may function as a preamplifier, having an input coupled to the photodiode 700 D1 and an output. The feedback resistor 806 may be coupled between the input and the output of the operational amplifier 808. This configuration may allow for the conversion of the current generated by the photodiode 700 D1 into a voltage signal.

[0182] In some implementations, the TIA 701 may include at least one buffer amplifier coupled to the output of the operational amplifier 808. The buffer amplifier may provide additional signal conditioning or amplification. A S2D converter 768 may be coupled to an output of the TIA 701. The S2D converter 768 may be configured to convert the single- ended output of the transimpedance amplifier into a differential signal., e.g., positive output (op) and negative output (on).

[0183] The combination of these components - the photodiode 700 D1, the TIA 701, e.g., comprising the operational amplifier 808, the feedback resistor 806, and potentially one or more buffer amplifiers, and the S2D converter 768, can form a receiver circuit capable of detecting light signals and converting them into differential electrical signals for further processing.

[0184] In some implementations, the S2D converter 768 is configured to receive and convert the single-ended voltage output by the operational amplifier 808 at node X. Specifically, the S2D converter 768 converts the single-ended output voltage at node X into two complementary outputs, denoted as positive output (op) and negative output (on). The differential output may be provided as input to a downstream clocked comparator circuit, such as a strong-arm latch or dual-tail comparator, which can perform a high speed analog-to-digital conversion. By directly integrating the S2D converter 768 at the output of the TIA 701, the circuit illustrated in FIG. 8 ensures that the single-ended analog signal is properlyAttorney Docket No. 22463-2129WO1

[0185] conditioned into a differential format with an improved common-mode noise rejection and preserving signal integrity early in the receiver chain.

[0186] Depending on the implementation, the configuration as illustrated in FIG. 8 is beneficial in high-speed receiver applications, where balanced differential signaling is needed for robust comparator performance and accurate digital conversion. In some implementations, the S2D converter 768 may assist in offset cancellation by facilitating differential amplification paths that inherently suppress common-mode offset voltages. This can contribute to higher sensitivity and precision in low-signal environments, such as optical or sensor-based communication systems.

[0187] FIG. 9 is a diagram schematically illustrating an example of an S2D circuit for processing signals received from a photodiode. The example circuit illustrated in FIG. 9 includes several stages of amplification and signal conditioning before the final conversion to a differential output. As an example, the photodiode 700 may be connected to a cathode bias 902 of approximately 4 vol ts. The current generated by the photodiode 700 in response to incident light can be processed by a series of amplification stages within the TIA 701. The coupling between devices illustrated in FIG. 9 may be electrically coupled, connected, or in communication with.

[0188] The first stage comprises a preamplifier I1 901 with the resistor RF 904 and inductor LF 905 connected between the input and output of the preamplifier I1 901. The feedback resistor RF 904 and the inductor LF 905 provide signal conditioning for high-frequency applications. Specifically, the addition of the inductor LF 905 provides bandwidth peaking to extend the operating bandwidth of the stage and improve impedance matching. The photodiode 700 may be connected to the input of the preamplifier I1 901, which converts the photodiode current into a voltage signal through the negative feedback mechanism provided by the resistor RF 904 and inductor LF 905.

[0189] Following the preamplifier I1 901, the example circuit illustrated in FIG. 9 incorporates two buffer stages implemented by a buffer amplifier I2 902 and output amplifier I3 903. The output of the preamplifier I1 901 may be connected to the input of the buffer amplifier I2 902, which in turn may be connected to the output amplifier I3 903. In some cases, the output amplifier I3 903 may include a resistor Rp 906 and inductor Lp 907 in a feedback configurati on between its input and output. Similar to the feedback path of the preamplifier Ii 901, this configuration can allow for additional signal conditioning, bandwidth peaking, and impedance matching.Attorney Docket No. 22463-2129WO1

[0190] The final stage includes the use of the S2D converter 768, which can receive the output from the output amplifier h. The S2D converter 768 can transform the single-ended signal from the amplifier chain into differential outputs, labeled as “TTA o / p” in the example of FIG. 8.

[0191] In some implementations, the circuit illustrated in FIG. 9 may allow for signal amplification while meeting various requirements. The various requirements may include, for example, bandwidth requirements and the multiple amplification stages providing gain distribution across the signal path. The feedback resistor RF 904, in combination with the preamplifier I1 901, may establish the initial transimpedance gain, while the buffer amplifier I2 902 and the output amplifier I3 903 may provide additional signal conditioning before the differential conversion.

[0192] The configuration described with respect to the example circuit of FIG. 9 may enable efficient conversion of the single-ended signal from the photodiode and amplifier stages into a balanced differential output. This differential output may be suitable for further processing in subsequent stages of the receiver circuit, potentially improving the overall performance of the system in terms of noise rejection and signal integrity'.

[0193] FIG. 10 is a diagram schematically illustrating an example of an S2D circuit 1000 with differential configurations and current summing. The circuit includes multiple transistors arranged in differential pairs to convert a single-ended input signal into highly balanced differential outputs. The S2D circuit 1000 illustrates the circuit components of the S2D converters 168, 178, 327, and 768 from FIGS. 1 through 9. The coupling between devices illustrated in FIG. 10 may be electrically coupled, connected, or in communication with.

[0194] In some implementations, the S2D circuit 1000 includes a first differential pair. The first differential pair includes a third transistor M3 1008 and a fourth transistor Mr 1010. In some implementations, the S2D circuit 1000 includes a second differential pair. The second differential pair includes a first transistor M1 1016 and a second transistor M2 1018. A single ended input signal Inp1006 may be applied to a gate of the third transistor M3 1008 of the first differential pair and to a gate of the first transistor M1 1016.

[0195] In some implementations, the S2D circuit 1000 may include a feedback network. The feedback network can be coupled to a gate of the second transistor M2 1018 and to a gate of the fourth transistor M4 1010 at reference node X 1024. The feedback network can include a resistor RF 1022 and a capacitor CF 1026. The feedback network may be configured toAttorney Docket No. 22463-2129WO1

[0196] generate a common-mode bias for the second transistor M2 1018 and the fourth transistor M4 1010.

[0197] Generally, in differential signaling and amplifier design, the common-mode bias can refer to the average direct current (DC) voltage level that is equally applied to the input terminals (or observed at the output terminals) of a differential circuit. In order for the S2D converter 1000 to process high-speed alternating current (AC) signals without distortion, the active components of the S2D converter 1000, e.g., the MOSFETs shown in each differential pair, need to be maintained at specific DC operating point. This specific DC operating point is often called the quiescent point or the Q-point. The common-mode bias can define the Q-point, and this ensures that the MOSFETs in each differential pair can operate in the saturation region, which is the region in which they can provide linear amplification.

[0198] Alternatively, if the common-mode bias is too high or too low, then the transistors of each differential pair may be driven into their cutoff or linear regions, which can cause signal clipping, distortion, and gain loss, to name a few examples.

[0199] For example, the incoming single-ended signal (Inp) can cany both high speed AC data and a baseline DC voltage from the upstream TIA 701. In order to create balanced differential pairs, both sides of the differential pair need to be biased to the exact same baseline DC voltage. As shown in FIG. 10, this is the job of the low-pass feedback network, with the resistor RF 1022 and a capacitor CF 1026, to extract the average DC voltage or the common mode bias level from the single ended input signal and apply it to the reference node at node X 1024. In this manner, by maintaining an identical common-mode bias across both halves of the differential pairs, e.g., the second transistor M2 1018 and the fourth transistor M4 1010, the S2D circuit 1000 can maintain a symmetric amplification. Moreover the S2D circuit 1000 can maximize the available voltage swing, and ensure that any noise that appears on both sides of the differential pairs is rejected in an equal manner.

[0200] In some implementations, the feedback network, which includes the resistor RF 1022 and the capacitor CF 1026, can establish the operating point and a frequency response of the S2D converter 1000. By coupling this network to the gate of the second transistor M2 1018, the S2D circuit 1000 can achieve several important features.

[0201] First, the S2D circuit 1000 provides a stable common-mode bias, The feedback network creates a direct current (DC) bias voltage at the gate of the second transistor M2 1018. The DC bias voltage is representative of the average (common-mode) level of the input signal Inp. This ensures that the second transistor M2 1018 operates in its intended region, typically the saturation region for linearity and gain.Attorney Docket No. 22463-2129WO1

[0202] Second, the feedback network includes an RC network. The RC network formed by the resistor RF 1022 and the capacitor CF 1026 can act as a low-pass filter. The low-pass filter can attenuate high-frequency components of the input signal Inpat the gate of the second transistor M2 1018. The filtering action can help to stabilize the common-mode level and reduce sensitivity to high-frequency noise or interference.

[0203] Third, by providing a filtered version of the input signal Inp1006 to the gate of the second transistor M21018, while the unfiltered signal of input signal Inp 1006 drives the gate of the first transistor M1 1016, the feedback network can help to create a more symmetrical response between the two halves of the differential pair. This improved balance can contribute to better common-mode rejection and reduced even-order harmonic distortion.

[0204] Fourth, the capacitor CF 1026 allows for alternating current (AC) coupling of the input signal to the gate of the second transistor M21018, while the resistor RF 1022 sets the DC operating point. This configuration enables the circuit to handle input signals with varying DC offsets while maintaining proper biasing of the differential pair.

[0205] Fifth, the values of the capacitor CF 1026 and the resistor RF 1022 can be adjusted to a targeted frequency response of the S2D converter 1000. By tailoring the cutoff frequency of the low-pass filter, designers can balance the trade-off between maintaining signal integrity' at high frequencies and achieving good common-mode rejection.

[0206] For example, the low-pass filter formed by the capacitor CF 1026 and the resistor RF 1022 introduces a pole in the frequency response, with a cutoff frequency given by equation (1):

[0207] f.1(1)Jc2nRFCF

[0208] In some implementations, the cutoff frequency can be adjusted by designers to control how the S2D converter 1000 responds to different frequency components of the input signal, A lower cutoff frequency can provide an improved common-mode rejection and noise suppression at the expense of potentially attenuating high frequency signal content.

[0209] Conversely, a higher cutoff frequency can preserve more of the high-frequency signal components but may reduce the effectiveness of common-mode rejection. In this manner, by leveraging simulation tools, characterization techniques, and modeling, to name some examples, the values of the capacitor CF 1026 and the resistor RF 1022 can be determined iteratively against such factors such as, for example, process variation, temperature effects, and parasitic capacitances to ensure a desired performance of the S2D converter 1000.Attorney Docket No. 22463-2129WO1

[0210] In some implementations, the S2D converter 1000 may include a first current source Itail 1002 coupled to the first differential pair. In particular, the first current source Itail 1002 is coupled to a source of the third transistor M3 1008 and to a source of the fourth transistor M4 1010. In some implementations, the S2D converter 1000 may include a second current source Itail 1004 coupled to the second differential pair. In particular, the second current source Itail 1004 is coupled to a source of the first transistor M1 1016 and to a source of the second transistor M2 1018.

[0211] In some implementations, the first and second current sources I aii 1002, 1004 can be configured to provide equal bias currents to the first and second differential pairs, respectively. By employing two distinct current sources, the S2D converter 1000 can achieve improved isolation between the two differential pairs, allowing for more precise control over their respective operating points. Equal bias currents can promote symmetrical behavior of both differential pairs in terms of gain, bandwidth, and linearity, which ensures the S2D converter 1000’s ability to reject common-mode noise and interference. This balanced operation enhances the S2D converter 1000’s ability to reject common-mode noise and interference, which is relevant in high-speed applications where maintaining signal integrity’ is important. Moreover, by providing equal bias currents, the S2D converter 1000 can maintain consistent transconductance in both differential pairs, which helps to minimize distortion and maintain linearity across the input signal range. Additionally, equal current distribution between the two differential pairs helps to ensure uniform heat dissipation, reducing the likelihood of thermal gradients that can lead to mismatches or performance variations. The use of matched current sources 1002, 1004 can also help mitigate the effects of process variations between transistors, as both differential pairs will be affected similarly by global variations in the manufacturing process. In practice, these current sources may be implemented using various topologies such as, for example, simple current mirrors, cascade current mirrors, or more sophisticated and regulated current sources, depending on the speci fic requirements of the application in terms of accuracy, power consumption, and chip area constraints.

[0212] A first output node, labeled as Outn 1030, can be coupled to a drain of the third transistor M3 1008. Similarly, a second output node, labeled as Outp 1032, can be coupled to a drain of the fourth transistor M4 1010, These outputs Outn 1030 and Outp 1032 provide the differential outputs of the S2D converter 1000.

[0213] To overcome the output imbalances of typical S2D converters, the S2D converter 1000 essentially operates as two separate single-to-differential conversions that are summedAttorney Docket No. 22463-2129WO1

[0214] into one another. The S2D converter 1000 further includes a fifth transistor Ms 1044 that is coupled in parallel with a resistive element Rz 1040 to a first intermediate node A. The S2D converter 1000 further includes a sixth transistor Ms 1042 that is coupled in parallel with a resistive element Rz 1038 to a second intermediate node B. The S2D converter 1000 includes an eighth transistor Ms 1034 cross-coupled to the first intermediate node A (via a current mirror configuration to fifth transistor Ms 1044) and a seventh transistor M? 1036 crosscoupled to the second intermediate node B (via a current mirror configuration to sixth transistor Ms 1042).

[0215] In some implementations, the specific arrangement of transistors Mi through Ms provides an “up” path and a “down” path from the input signal Inp 1006 to the differential output nodes Outn 1030 and Outp. For example, a first signal path extends from the input signal Inp 1006 at the gate of the third transistor M3 1006, up to the shared tail node connecting the sources of the third transistor M3 1006 and the fourth transi stor Mr 1010, and down through the drain of the fourth transistor Mr 1010 to the output node OP1032. The following describes the differential toggling effect that occurs between the third transistor M3 1008 and the fourth transistor Mr 1010.

[0216] The input signal Inp1006 arrives at the gate of the third transistor M3 1008. This signal can dictate how “open” or “closed” the third transistor M3 1008 is, which ultimately affects an amount of current that flows through it. Additionally, the source pins of both the third transistor M3 1008 and the fourth transistor Mr 1010 are tied to the tail node, which is coupled to the first current source ITail1002.

[0217] The current provided by the first current source ITail1002 is a fixed, constant amount of total current, which is shared between the third transistor M3 1008 and the fourth transistor Mr 1010, When the input signal Inp1006 at the gate of the third transistor M3 1008 instructs the third transistor M3 1008 to pull more current, that extra current has to come from somewhere. Because the total current is fixed at the tail node, then the fourth transistor M41010 is forced to take less current. As a result, the influence of the input signal Inp1006 travels from the gate of the third transistor M31008, up to the shared tail node (or the “up” path), and causes the voltage at the tail node to shift. The voltage shift at the tail node then drives the fourth transistor Mr 1010 traveling down through the fourth transistor Mr 1010 to reach the output node Outp 1032. Meanwhile, the current change through the third transistor M3 1008 travels down to Outn 1030.

[0218] Similarly, a second signal path (or the “down” path) extends from the input signal Inp1006 arriving at the gate of the first transistor Mi 1016. This modulates the current flowingAttorney Docket No. 22463-2129WO1

[0219] down into the diode connected reference transistors, e.g., the sixth transistor M61042 and the fifth transistor M5 1044. This signal influence is transferred across the S2D converter 1000 via intermediate nodes A and B to the gates of the mirroring transistors, e.g., the eighth transistor M81034 and the seventh transistor M7 1036, which drive the respective output nodes Outp 1032 and Outn 1030.

[0220] More specifically, the upper transistors of the differential pair, e.g., the first transistor Mi 1016, the second transistor M21018, the third transistor M3 1008, and the fourth transistor Mr 1010 are implemented at p-channel metal oxide semiconductor (PMOS) transistors.

[0221] PMOS transistors can conduct less current when the voltage applied to their respective gates transitions to a higher state. In operation, when the input signal Inp 1006 transitions to a high voltage state, the third transistor M3 1008 conducts less current. As a result, this causes the voltage at the first output node Outn 1030 to transition to a lower state.

[0222] Similarly, when the input signal Inp1006 transitions to a high voltage state, the first transistor Mi 1016 conducts less current, which causes the voltage at the second intermediate node B to drop to a low voltage state. Because Node B is cross-coupled to the gate of the seventh transistor M71036, which is implemented as an n-channel metal oxide semiconductor (NMOS) transistor, the low voltage state at Node B dictates that the seventh transistor M7 1036 pulls less current from the second output node Outp 1032. This reduction in pulled current allows the voltage at the second output node Outp1032 to rise to a high state, which complements the low state at the first output node Outn 1030.

[0223] Concurrently, in some implementations, the second transistor M21018 can conduct an increased amount of current. The increased amount of current can drive the voltage at the first intermediate node A to a high voltage state. The high voltage state at Node A is applied across the S2D converter 1000 to the gate of the eighth transistor M81034. In response, the eighth transistor M81034 can draw more current from the first output node Outn 1030, and actively drive the voltage at the first output node Outn 1030 into the low' voltage state. This cross wired configuration can ensure that the NMOS current mirrors synchronously reinforce the differential signal generated by the top PMOS differential pairs. As a result, this creates a cooperative push and pull action that can balance the overall differential outputs.

[0224] In some implementations, the S2D converter 1000 can include a delay across the first and second signal paths. In particular, the routing of the second signal path, e.g., the “dowai path” through the current mirrors, includes a different delay than the routing of the first signal path, e.g., the “up path” through the tail node. The delay difference between the “up path” and the “down path” can create a phase mismatch between the differential signals arriving atAttorney Docket No. 22463-2129WO1

[0225] the Outp 1032 and the Outn 1030. In order to mitigate the phase mismatch between differential signals, the S2D converter 1000 incorporates the resistive elements Rz 1038 and Rz 1040. These two resistive elements connected to the gate of the sixth transistor M61042 and the gate of the fifth transistor M51044, respectively, can provide a synthetic inductor peaking, The synthetic inductor peaking can compensate for the delay difference and can realign the phase of the summing signals. More specifically, the addition of the two resistive elements Rz 1038 and Rz 1040 introduce a zero in the transfer function and ensure that the summing signals arrive at the Outp 1032 and the Outn 1030 at substantially the same times in order to sum into a clean, undistorted differential output signal. In some examples, the resistive elements Rz 1038 and Rz 1040 can each included resistive values of approximately 15 kilo-ohms.

[0226] In some implementations, the differential pairs can utilize asymmetric transistor sizing. In particular, asymmetric transistor sizing allows for improving the dual-path architecture of the differential pairs without degrading performance of the upstream components. In some examples, the left hand side of the S2D converter 1000, including transistors M31008, M41010, M81034, and M71036, are twice the size of tire transistors on the right hand side of the S2D converter 1000 on the right hand side of the S2D converter 1000, including transistors M11016, M21018, M61042, and M51044. In this case, the transistors on the left hand side of the S2D converter 1000 are sized at a 2: 1 ratio relative to the transistors on the right hand side of the S2D converter 1000. By making the transistors on the right side of the S2D converter 1000 approximately half the size of the transistors on the left hand side of the S2D converter 1000, the S2D converter 1000 achieves a balanced differential performance for offset cancellation without unnecessarily doubling the capacitive load on the preceding TIA 700.

[0227] FIG. 11 is a plot 1100 that depicts a frequency response graph illustrating alternating current (AC) gain characteristics. The plot 1100 displays two closely matched response curves that represent the performance of the single-ended to differential converter described throughout this specification. For example, the plot 1100 can represent the performance characteristics of the S2D converter 1000 illustrated in FIG. 10.

[0228] The plot 1100 includes a response curve 1102 and a response curve 1104. The response curve 1102 represents the AC gain of the positive differential output, e.g., Outp 1032, and the response curve 1104 represents the AC gain of the negative differential output, e.g., Outn 1034. The response curves start at different gain levels around 40 dB at low frequencies, rise with similar slopes through the mid-frequency range, and plateau toAttorney Docket No. 22463-2129WO1

[0229] approximately 70 dB gain from 106Hz through 109Hz. The curves 1102 and 1104 maintain close tracking across the entire frequency range, with only minor deviations between them, particularly in the transition region between 104Hz through 106Hz. The close matching of the response curves 1102 and 1104 indicates an improved amplitude balance between the positive and negative outputs of the differential converter. In some cases, the maximum imbalance between the outputs may be limited to approximately 6.5 mV. This represents a significant improvement over conventional circuits, which typically exhibit imbalances of up to 50 mV.

[0230] The plot 1100 additionally illustrates that the S2D converter 1000 achieves a 0.45 dB imbalance across the frequency band. This performance characteristic sharply contrasts with conventional circuits, which generally exhibit imbalances of around 3.3 dB across the same frequency range. The reduced imbalance across a wide frequency range contributes to improved signal integrity and reduced distortion in subsequent processing stages. At frequency ranges approaching 1010Hz, both curves 1102 and 1104 show a slight downward trend while maintaining their matched characteristics. This behavior suggests that the S2D converter 1000 successfully maintains its balanced performance even at very high frequencies, which is beneficial for applications requiring wide bandwidth operation.

[0231] FIG. 12 is a diagram schematically illustrating an electro-photonic network with an S2D circuit coupled to or included within a TIA. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications.

[0232] As an example, FIG. 12 shows the configuration of an application-specific integrated circuit (ASIC) 1201 situated above a photonic integrated circuit (PIC) 1202. Various tiles 1203 A, 1203B, 1203C, and 1203D within the ASIC are shown, along with the electro-optic (EO) and optoelectronic (OE) interface components that facilitate communication between these tiles through optical links in the PIC. The optical signals in the PIC are coupled to external systems via an optical fiber 1233 connected to the fiber array unit (FAU) 1232, For example, the light is coupled into tire PIC using a grating coupler 1220, which directs the light to the EAMs 1204A, 1204B, 1204C via waveguides 1222.

[0233] The modulator drivers, e.g., 1202A, 1202B, and 1202C, are electronic components situated within the ASIC 1201 in tiles 1203A, 1203B, 1203C, and 1203D, These drivers are responsible for generating the electrical signals that modulate light within the EAMs, e.g., 1204A, 1204B, and 1204C, which are configured directly beneath the drivers in the PIC 1202. For example, the EAMs convert the electrical signals from the modulator drivers intoAttorney Docket No. 22463-2129WO1

[0234] modulated optical signals that can be transmitted through the optical waveguides, e.g., 1200AB, 1200BC, 1200CD, embedded in the PIC. As shown, the waveguides form the optical links between the tiles, enabling high-speed intra-chip communication.

[0235] In FIG. 12, TIAs, e.g., 1206B, 1206C, 1206D, transimpedance amplifiers for converting small current signals generated by the photodetectors, e.g., PDs 1208B, 1208C, 1208D, into amplified voltage signals that can be further processed by the system. For example, the photodetectors first convert incoming optical signals into electrical current. For example, the PDs are located in the PIC directly beneath the TIAs, ensuring that the distance between the optical and electronic components is minimal. In some implementations, one or more S2D circuits are coupled to or integrated within the TIAs 1206A, 1206B, and 1206C. The S2D circuits 1208A, 1208B, and 1208C are configured to generate a differential signal from a single-ended signal provided by the corresponding TIAs. The S2D circuits or S2D converters that are described with respect to FIGs, 1 through 11 may be implemented within the system shown in FIG. 12.

[0236] In some implementations, the integration of the S2D converters described in FIGs. 1 through 11 into the system shown in FIG. 12 can provide an important interface between the analog and digital domains in high-speed optical communication systems. By incorporating the S2D converter into this system, the system can effectively transform the single-ended output from the transimpedance amplifier, e.g., TIAs 1206A, 1206B, and 1206C, into a balanced differential signal suitable for processing by downstream components.

[0237] Moreover, the use of the S2D converter can address challenges related to electromagnetic interference (EMI) and crosstalk, which can be of concern to densely packed optical transceivers. Differential signaling is inherently more resistant to EMI and crosstalk between adjacent channels, helping to maintain signal integrity in multi-channel optical communication systems. By improving signal integrity and noise rejection, the configuration of the S2D converter enables the optical receiver to achieve higher sensitivity and lower bit error rates (BER) at increased data rates. These improvements are useful for meeting the ever-increasing bandwidth demands of modem optical communication networks, including data centers, telecommunications infrastructure, and high-performance computing applications.

[0238] The close alignment between the electronic components, e.g., modulator drivers, TIAs, in the ASIC 1201 and the photonic components, e.g., EAMs, PDs, in the PIC 1202 is important for reducing, e.g., minimizing, the distance over which electrical and optical signals travel. This reduces, e.g., minimizes, latency and reduces the power needed for signalAttorney Docket No. 22463-2129WO1

[0239] conversion. Additionally, the heat generated by the electronic components in the ASIC can help maintain the EAMs and PDs in the PIC at favorable, e.g., optimal, operating temperatures, enhancing the overall thermal stability and performance of the system.

[0240] As described throughout the specification, the terms "‘coupled,” “electrically coupled,” “connected,” and “in communication with” are used interchangeably to encompass both direct and indirect connections. For example, if a first component is electrically coupled to a second component, the relationship encompasses a direct electrical connection, e.g., a physical wire, trace, or conductive path, as well as an indirect electrical connection over one or more intermediary active or passive components, e.g., resistors, capacitors, inductors, buffers, amplifiers, or other, that do not fundamentally alter the nature of the signal being communicated. Further, while some components may be “coupled” the term “electrically coupled” can denote a path that transmits electrical signals, voltage signals, or current between components. Components that are not electrically coupled, by contrast, such as physical, mechanical, optical, or spatial coupling are not considered “electrically coupled.” Although the present invention is defined in the claims, it should be understood that the present invention can also (alternatively) be defined in accordance with the following embodiments:

[0241] 1. A system for generating a differential signal, the system comprising:

[0242] a photodiode configured to generate a current in response to receiving incident light; a transimpedance amplifier coupled to the photodiode, the transimpedance amplifier comprising:

[0243] a preamplifier electrically coupled to the photodiode, the preamplifier configured to receive the generated current from the photodiode;

[0244] a feedback resistor electrically coupled to an output of the preamplifier and an input of the preamplifier;

[0245] at least one buffer amplifier electrically coupled to the output of the preamplifier; and

[0246] a single-ended to differential (S2D) converter electrically coupled to an output of the transimpedance amplifier, the S2D comprising:

[0247] a first differential pair comprising a first transistor and a second transistor; a second differential pair comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are different from the first transistor and the second transistor;Attorney Docket No. 22463-2129WO1

[0248] a feedback network electrically coupled to a gate of the second transistor, the feedback network comprising a resistor and a capacitor;

[0249] a first current source electrically coupled to a source of the first transistor and a source of the second transistor;

[0250] a second current source electrically coupled to a source of the third transistor and a source of the third transistor;

[0251] a first output node electrically coupled to a drain of the first transistor; and a second output node electrically coupled to a drain of the fourth transistor. 2. The system of embodiment 1, wherein the at least one buffer amplifier comprises a first buffer amplifier and a second buffer amplifier connected in series.

[0252] 3. The system of embodiment 2, wherein the second buffer amplifier comprises an inductor and resistance connected in series with an output path of the second buffer amplifier.

[0253] 4. The system of any one of embodiments 1-3, wherein the S2D further comprises: a fifth transistor electrically coupled between the first output node and a first intermediate node; and a sixth transistor electrically coupled between the second output node and a second intermediate node.

[0254] 5. The system of embodiment 4, wherein the S2D further comprises: a seventh transistor electrically coupled between the first intermediate node and a ground; and an eighth transistor electrically coupled between the second intermediate node and the ground.

[0255] 6. The system of any one of embodiments 1-5, wherein the feedback network is configured to generate a common mode bias for the second transistor that is representative of an average level of an input signal received by a gate of the first transistor and a gate of the third transistor.

[0256] 7. The system of any one of embodiments 1 -6, wherein the first current source and the second current source are configured to provide a bias current to the first differential pair and the second differential pair to maintain consistent transconductance.

[0257] 8. The system of any one of embodiments 1-7, further comprising a resistor between the first output node and the second output node to maintain a signal balance between differential outputs.

[0258] 9. The system of any one of embodiments 1-8, wherein tire first differential pair is sized at a two-to-one ratio relative to the second differential pair such that the first transistor and the second transistor are twice the size of the third transistor and the fourth transistor.Attorney Docket No. 22463-2129WO1

[0259] 10. The system of any one of embodiments 1-9. wherein tlie first differential pair and the second differential pair are configured to operate in a complementary manner to perform current summing at the first output node and the second output node.

[0260] 11. The system of any one of embodiments 1-10, w herein the second differential pair is electrically coupled to a current mirror, and wherein the S2D converter is configured to route an input signal to the first output node through a first signal path via a tail node and through a second signal path via the current mirror.

[0261] 12. The system of any one of embodiments 1-11, wherein the first current source and the second current source are configured to provide equal bias currents to the first differential pair and the second differential pair, respectively.

[0262] 13. The system of any one of embodiments 1-12, wherein the transimpedance amplifier is configured to provide an input signal to a gate of the first transistor and a gate of the third transistor.

[0263] 14. A system for generating a differential signal, the system comprising:

[0264] a first differential pair comprising a first transistor and a second transistor;

[0265] a second differential pair comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are different from the first transistor and the second transistor;

[0266] a feedback network electrically coupled to a gate of the second transistor, the feedback network comprising a resistor and a capacitor;

[0267] a first current source electrically coupled to a source of the first transistor and a source of the second transistor;

[0268] a second current source electrically coupled to a source of the third transistor and a source of the third transistor;

[0269] a first output node electrically coupled to a drain of the first transistor; and a second output node electrically coupled to a drain of the fourth transistor.

[0270] 15. The system of embodiment 14, wherein the first transistor and the second transistor of the first differential pair are larger than the third transistor and the fourth transistor of the second differential pair.

[0271] 16. The system of any one of embodiments 14-15, wherein the first, second, third, and fourth transistors comprise PMOS transistors.

[0272] 17. The system of any one of embodiments 14-16, wherein the system further comprises: a fifth transistor electrically coupled between the first output node and a firstAttorney Docket No. 22463-2129WO1

[0273] intermediate node; and a sixth transistor electrically coupled between the second output node and a second intermediate node.

[0274] 18. The system of embodiment 17, wherein the device further comprises: a seventh transistor electrically coupled between the first intermediate node and a ground; and an eighth transistor electrically coupled between the second intermediate node and the ground.

[0275] 19. The system of any one of embodiments 14-18, further comprising a resistor between the first output node and the second output node to maintain a signal balance between differential outputs.

[0276] 20. The system of any one of embodiments 14-19, wherein the first differential pair sized at a two-to-one ratio relative to the second differential pair such that the first transistor and the second transistor are twice the size of the third transistor and the fourth transistor.

[0277] 21. The system of any one of embodiments 14-20, further comprising a clocked comparator circuit electrically coupled to the first output node and the second output node, wherein the clocked comparator circuit is configured to receive the differential output signals for analog-to-digital conversion.

[0278] 22. The system of embodiment 21, wherein the clocked comparator circuit comprises a dual -tail comparator.

[0279] 23. The system of embodiment 21, wherein the clocked comparator circuit comprises a strong-arm latch.

[0280] While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this specification in tire context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination.

[0281] Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0282] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may beAttorney Docket No. 22463-2129WO1

[0283] advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0284] Particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, tire actions recited in the claims can be performed in a different order and still achieve desirable results. As one example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.

[0285] What is claimed is:

Claims

Attorney Docket No. 22463-2129WO1CLAIMS1. A receiver device comprising:a photodiode configured to generate a current in response to receiving incident light; a transimpedance amplifier coupled to the photodiode, the transimpedance amplifier comprising:a preamplifier electrically coupled to the photodiode, the preamplifier configured to receive the generated current from the photodiode;a feedback resistor electrically coupled to an output of the preamplifier and an input of the preamplifier;at least one buffer amplifier electrically coupled to the output of the preamplifier; anda single-ended to differential (S2D) converter electrically coupled to an output of the transimpedance amplifier, the S2D comprising:a first differential pair comprising a first transistor and a second transistor; a second differential pair comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are different from the first transistor and the second transistor;a feedback network electrically coupled to a gate of the second transistor, the feedback network comprising a resistor and a capacitor;a first current source electrically coupled to a source of the first transistor and a source of the second transistor;a second current source electrically coupled to a source of the third transistor and a source of the third transistor;a first output node electrically coupled to a drain of the first transistor; and a second output node electrically coupled to a drain of the fourth transistor.

2. The receiver device of claim 1, wherein the at least one buffer amplifier comprises a first buffer amplifier and a second buffer amplifier connected in series.

3. The receiver device of claim 2, wherein the second buffer amplifier comprises an inductor and resistance connected in series with an output path of the second buffer amplifier.

4. The receiver device of claim 1, wherein the S2D further comprises:Attorney Docket No. 22463-2129WO1a fifth transistor electrically coupled between the first output node and a first intermediate node; anda sixth transistor electrically coupled between the second output node and a second intermediate node.

5. The receiver device of claim 4, wherein the S2D further comprises:a seventh transistor electrically coupled between the first intermediate node and a ground; andan eighth transistor electrically coupled between the second intermediate node and the ground.

6. The receiver device of claim 1, wherein the feedback network is configured to generate a common mode bias for the second transistor that is representative of an average level of an input signal received by a gate of the first transistor and a gate of the third transistor.

7. The receiver device of claim 1, wherein the first current source and the second current source are configured to provide a bias current to the first differential pair and the second differential pair to maintain consistent transconductance.

8. The receiver device of claim 1, further comprising a resistor between the first output node and the second output node to maintain a signal balance between differential outputs.

9. The receiver device of claim 1, wherein the first differential pair is sized at a two-to-one ratio relative to the second differential pair such that the first transistor and the second transistor are twice the size of the third transistor and the fourth transistor.

10. The receiver device of claim 1, wherein the first differential pair and the second differential pair are configured to operate in a complementary manner to perform current summing at the first output node and the second output node.

11. The receiver device of claim 1, wherein the second differential pair is electrically coupled to a current mirror, and wherein the S2D converter is configured to route an inputAttorney Docket No. 22463-2129WO1signal to the first output node through a first signal path via a tail node and through a second signal path via the current mirror.

12. The receiver device of claim 1, wherein the first current source and the second current source are configured to provide equal bias currents to the first differential pair and the second differential pair, respectively.

13. The receiver device of claim 1, wherein the transimpedance amplifier is configured to provide an input signal to a gate of the first transistor and a gate of the third transistor.

14. A device comprising:a first differential pair comprising a first transistor and a second transistor;a second differential pair comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are different from the first transistor and the second transistor;a feedback network electrically coupled to a gate of the second transistor, the feedback network comprising a resistor and a capacitor;a first current source electrically coupled to a source of the first transistor and a source of the second transistor;a second current source electrically coupled to a source of the third transistor and a source of the third transistor;a first output node electrically coupled to a drain of the first transistor; and a second output node electrically coupled to a drain of the fourth transistor.

15. The device of claim 14, wherein the first transistor and the second transistor of the first differential pair are larger than the third transistor and the fourth transistor of the second differential pair.

16. The device of claim 14, wherein the first, second, third, and fourth transistors comprise PMOS transistors.

17. The device of claim 14, wherein the device further comprises:a fifth transistor electrically coupled between the first output node and a first intermediate node; andAttorney Docket No. 22463-2129WO1a sixth transistor electrically coupled between the second output node and a second intermediate node.

18. The device of claim 17, wherein the device further comprises:a seventh transistor electrically coupled between the first intermediate node and a ground; andan eighth transistor electrically coupled between the second intermediate node and the ground.

19. The device of claim 14, further comprising a resistor between the first output node and the second output node to maintain a signal balance between differential outputs.

20. The device of claim 14, wherein the first differential pair sized at a two-to-one ratio relative to the second differential pair such that the first transistor and the second transistor are twice the size of the third transistor and the fourth transistor.

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