ALD operates through sequential, self-limiting surface reactions where alternating precursor pulses each deposit a single atomic monolayer. This yields sub-nanometer thickness control and conformal coverage on topographically complex surfaces — including trenches and vias with aspect ratios of 40:1 or more — at temperatures from room temperature to approximately 400°C. CVD and PVD do not offer the same degree of self-limiting thickness control or conformality on high-aspect-ratio structures.

Plasma-enhanced ALD (PE-ALD) replaces the thermal oxidant pulse with reactive plasma species, extending the process window to lower temperatures, improving film density and reactivity. TSMC's active US patents (2023, 2025) cover plasma-ALD of work function metal layers using reactive-gas plasma treatment cycles for advanced gate stacks in FinFET and gate-all-around transistors. PE-ALD is also used for 2D materials such as WS₂ deposition at 250°C.

Area-selective ALD (AS-ALD) deposits material only on designated surfaces using inhibitor molecules to block deposition on non-target areas, enabling bottom-up self-aligned nanofabrication. This approach directly reduces edge placement errors inherent in EUV lithographic patterning — a fundamental scaling limiter at sub-5 nm nodes. Literature evidence from 2018–2020 shows ABC-type plasma-enhanced AS-ALD of WS₂ at 250°C using acetylacetone inhibitors, with rapid process development reported.

ALD's conformality in high-aspect-ratio structures makes it the enabling deposition technology for 3D NAND flash. The Sungkyunkwan University 2024 US pending patent describes multi-pulse ALD that enables void-free gap-fill in structures with aspect ratios of 40:1 or higher, removing overhangs simultaneously. Conventional single-pulse ALD can create voids or seams in these structures, making multi-pulse approaches a critical process advance for 3D memory architectures.

TSMC filed two US patents (2023 and 2024) on ALD bonding layers deposited on device surfaces and fused by annealing for 3D wafer integration. These patents target die-to-die and wafer-to-wafer bonding for chiplet architectures and high-bandwidth memory — a relatively new application of ALD outside traditional thin-film deposition roles. The 2024 filing is a continuation of the 2023 family, indicating active IP development.

Multiple 2021–2025 CN patents from Chinese semiconductor equipment firms — including Wuxi Yiwen Microelectronics Technology (two CN patents, 2021–2022), Shanghai Jita Semiconductor (2025 pending), and Xin'en (Qingdao) Integrated Circuit Co. (CN, 2024 active) — describe complete ALD system architectures including multi-chamber vacuum platforms, thermal ALD reactors, and matrix-array chamber configurations. This cluster reflects a strategic push toward ALD equipment self-sufficiency within China's semiconductor supply chain.