Processor Loop Buffer Execution Patents: Who Holds the Core Claims

A loop buffer, sometimes called a loop cache, is a small on-chip structure that holds a recently fetched sequence of instructions so a tight loop can re-execute from the buffer instead of re-fetching from the instruction cache or program memory each pass. It saves fetch bandwidth and power on hot loops, which matters for every processor vendor building CPUs, DSPs or accelerators. Because the core mechanics — hit detection against a base fetch address, register-file storage of opcodes, backward-branch triggered loading — are reusable across many processor designs, vendors file dense claim families around small variations, which is why the field shows heavy concentration at the top of the assignee ranking.

The dataset behind this page ranks 57 assignees, with the top five holding 46.4% of all 252 records in scope and the top ten holding 71.8%. That is not an even spread: a small group of processor and semiconductor vendors account for most of the filing activity, while dozens of other assignees appear with only one or a handful of records each. The full ranking, rather than a hand-picked list, is the reliable way to see exactly who sits where.

Filing peaked at 29 records in 2013 and has not returned to that level since. Looking at the last fully-settled window, 2021 to 2024, filings dropped from 8 to 3 records, a -63% change. Figures for 2025 and 2026 are still incomplete because publication typically lags actual filing by around 18 months, so those most recent years should not be read as continued decline — they are simply still filling in.

Almost all of it sits inside G06F, electric digital data processing, which covers 95.2% of the 252 records in scope. Small pockets extend into G01R (electric and magnetic measurement) and G11C (static and digital memories), each at 2.8%, and smaller shares still touch G06N (AI-based computing), antennas, solid-state devices, optical control and image processing. In practice this means loop buffer claims are written almost exclusively as core processor architecture rather than as memory-, AI-, or sensor-specific inventions.

The concentration data points toward the answer indirectly: with 46.4% of the 252 records held by five assignees and heavy filing bunched inside G06F, the core hit-detection and register-file mechanics are well covered by the leaders. Thinner activity in adjacent classes like G11C, G06N and G01R suggests combinations of loop buffering with memory management, AI-workload scheduling or on-chip measurement are less claimed, though that needs confirming against actual claim text rather than class counts alone. A freedom-to-operate search focused on the leading assignees' specific claim language, not just their filing volume, is the necessary next step before committing to a design.