Autonomous Driving Thermal Management for High-Performance Compute

Overview of Technical Issues:

During peak autonomous driving computational loads, the compute modules generate excessive heat that accumulates faster than the heat-conducting and heat-dissipating structures can transfer it away, causing junction temperatures to exceed safe operating thresholds. This thermal accumulation forces the system into thermal throttling mode, reducing processing performance precisely when real-time perception, planning, and control algorithms require maximum computational capacity. The goal is to enhance thermal transfer and dissipation capacity to maintain sustained high-performance computing without thermal throttling, ensuring reliable autonomous driving operation under all environmental conditions.

Solution directions generated for this problem

Problem Direction 1 :

ImproveHeat transfer rate from compute modules
VS
ConstraintThermal management system volume

Inspiration 1 : Cross-domain reference

Application Principle: #2 Taking out (Extraction)
Cross-domain applicability Assess applicability
Refrigerator comprising vacuum space
Innovative Solution Refine solution

Embedded microchannel cold plate directly integrated into compute module substrate

Extract heat at junction source before spreading
How to solve :
  • Fabricate microchannel arrays (200–400 μm width, 0.6 mm depth) directly into the silicon interposer or substrate beneath compute dies, eliminating external heat spreaders and reducing thermal path length to <1 mm
  • Route dielectric coolant (HFE-7100, boiling point 61°C) through channels at 0.3–0.5 L/min flow rate, achieving convective heat transfer coefficient ≥15,000 W/(m²·K) directly at the 85–105°C junction zone
  • Integrate manifold distribution layers within the existing PCB stackup using standard HDI fabrication (laser drilling, copper plating), ensuring uniform flow across all channels with pressure drop <20 kPa
Expected Effect : Junction temp reduction 18–25°C; thermal resistance <0.08 K/W; zero additional volume beyond chip footprint; heat extraction capacity 250–350 W/cm²
Risk Control :
  • microchannel clogging from particulate contamination
  • thermal-mechanical stress at substrate-channel interface during thermal cycling
  • coolant leakage at manifold seals

Problem Direction 2 :

ImproveHeat dissipation capacity to environment
VS
ConstraintThermal management system volume

Inspiration 1 : Cross-domain reference

Application Principle: #2 Taking out (Extraction)
Cross-domain applicability Assess applicability
Power conversion device
Innovative Solution Refine solution

Direct liquid-jet impingement cooling at chip hotspots via embedded microfluidic channels

Extract heat at source before spreading
How to solve :
  • Embed microfluidic jet arrays (0.3–0.6mm diameter nozzles) directly into compute module substrate, targeting hotspot zones where heat flux exceeds 150 W/cm²—eliminates bulky external heat spreaders and radiators
  • Route dielectric coolant (HFE-7100, boiling point 61°C) through substrate channels at 0.5–1.2 L/min flow rate, impinging jets directly onto chip backside within 0.5mm distance to achieve convective heat transfer coefficient ≥20,000 W/(m²·K)
  • Integrate microchannel evaporator (200μm channel width, 400μm pitch) within existing PCB layers using laser micromachining—coolant absorbs latent heat (112 kJ/kg) and exits as two-phase flow to compact external condenser (volume <150 cm³) mounted on vehicle firewall
Expected Effect : Junction temp maintained <85°C under 300W load; system volume 60% smaller than conventional liquid cooling; heat removal capacity 450 W with 180 cm³ total volume
Risk Control :
  • microfluidic channel clogging by particulates
  • coolant leakage at substrate interfaces
  • two-phase flow instability causing temperature oscillation

Problem Direction 3 :

ImproveHeat transfer rate from compute modules
VS
ConstraintCooling system complexity

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Heat sink, heat sink arrangement and module for liquid immersion cooling
Innovative Solution Refine solution

Modular passive heat pipe array with independent thermal zones for compute modules

Divide cooling into independent passive modules to reduce interdependencies
How to solve :
  • Deploy independent heat pipe assemblies for each compute module (CPU, GPU, perception processor) — each unit operates autonomously without shared plumbing or control systems, eliminating pumps, valves, and leak risks
  • Use sintered copper heat pipes (6mm diameter, ≥200 W/(m·K) effective conductivity) with gravity-assisted return — passive two-phase operation transfers 50-80W per pipe without active components
  • Mount each heat pipe directly from chip surface to dedicated finned radiator panel (aluminum, fin pitch 2mm) on vehicle body — modular replacement in under 5 minutes, no system drainage required
Expected Effect : Junction temp maintained ≤95°C; zero pumps/controllers; component count reduced 60% vs liquid loop
Risk Control :
  • heat pipe orientation sensitivity in vehicle tilt
  • vapor chamber dry-out under sustained peak load
  • thermal contact resistance at chip interface

Problem Direction 4 :

ImproveHeat dissipation capacity to environment
VS
ConstraintCooling system complexity

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Heat sink, heat sink arrangement and module for liquid immersion cooling
Innovative Solution Refine solution

Modular passive heat sink array with independent thermal zones for compute modules

Divide cooling into independent passive modules per compute unit
How to solve :
  • Partition the thermal system into separate passive heat sink modules, each dedicated to one compute chip (CPU/GPU/NPU), eliminating shared pumps, valves, and central controllers
  • Each module comprises a direct-contact vapor chamber (0.6mm thick, ≥200 W/(m·K) effective conductivity) bonded to chip surface, coupled to a finned aluminum heat sink (fin pitch 1.2mm, surface area 0.15m²) with natural convection or simple DC fan (12V, PWM-controlled locally)
  • Use thermal diode heat pipes (sintered copper wick, R-134a working fluid) in each module that passively increase conductance from 50 W/K to 180 W/K when junction temperature exceeds 85°C, providing automatic thermal regulation without sensors or logic controllers
Expected Effect : Component count reduced 60%; MTBF increased 3×; peak dissipation 150W per module; no liquid leak risk
Risk Control :
  • vapor chamber manufacturing yield variation
  • fin-to-base thermal contact resistance
  • ambient temperature dependency limiting passive capacity

Problem Direction 5 :

ImproveHeat transfer rate from compute modules
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #3 Local quality
Cross-domain applicability Assess applicability
Electric power conversion apparatus
Innovative Solution Refine solution

Spatially-graded hybrid thermal interface with zone-optimized thickness

Zone-optimized interface balances conductivity and conformability
How to solve :
  • Divide chip contact area into center zone (flat, high-power density) and peripheral zone (non-planar, lower density)
  • apply sintered silver paste (10–15 μm thickness, ≥200 W/(m·K)) to center 60% area via stencil printing, cured at 250°C for 15 min under 5 MPa pressure
  • surround with silicone-based gap filler (80–120 μm thickness, 5 W/(m·K)) dispensed robotically to peripheral 40% area, accommodating ±50 μm surface non-planarity
  • Implement co-planarity inspection using laser profilometry (±5 μm tolerance) before assembly, ensuring center zone flatness <10 μm for sintered silver adhesion
  • peripheral gap filler compressed to 70% original thickness during mounting, verified by pressure-sensitive film (target 0.3–0.5 MPa contact pressure)
  • Integrate thermal test vehicle with embedded thermocouples at 4 quadrants (center and 3 edges) to validate junction-to-case thermal resistance: target <0.15 K/W for center zone, <0.35 K/W overall, measured under 150W steady-state load per module
Expected Effect : Junction temp reduction 18–22°C; thermal resistance 0.28 K/W (vs 0.45 K/W uniform pad); throttling eliminated under peak loads
Risk Control :
  • sintered silver voiding if pressure non-uniform
  • gap filler overflow contaminating center zone
  • co-planarity drift during thermal cycling
Patsnap Eureka Solution