Control Gate Drive Delay in Synchronous Rectifier for LLC

Overview of Technical Issues:

The gate drive signal generator insufficiently synchronizes with the secondary-side voltage and current transitions in the LLC converter, causing delayed or mistimed turn-on/turn-off of the synchronous rectifier FET; this timing misalignment leads to body diode conduction losses, potential reverse recovery losses, and reduced overall rectification efficiency, preventing the system from achieving the target efficiency optimization in low-voltage power supply applications such as USB-PD designs.

Solution directions generated for this problem

Problem Direction 1 :

ImproveGate signal synchronization accuracy
VS
ConstraintControl circuit complexity

Inspiration 1 : Cross-domain reference

Application Principle: #26 Copying
Cross-domain applicability Assess applicability
Updating a local tree for a client synchronization service
Innovative Solution Refine solution

Primary-side resonant current zero-crossing replication for secondary-side synchronous rectifier timing prediction

Replicate timing from primary resonant current
How to solve :
  • Sense primary-side resonant current zero-crossing using a 1:50 current transformer (CT) with 10nH leakage inductance and fast comparator (LT1711, 4.5ns response time)
  • CT secondary feeds into comparator with 5mV threshold to detect zero-crossing within 3ns
  • Apply fixed phase offset calibration derived from LLC transformer phase relationship — measure phase delay between primary current zero-crossing and secondary voltage transition at nominal operating point (typically 25-35ns at resonance), store as digital offset value in controller lookup table indexed by switching frequency
  • Generate secondary-side gate signals by delaying primary zero-crossing trigger by the calibrated offset using a simple digital delay line (74LVC1G123 monostable multivibrator, 1ns resolution) — no secondary-side high-speed sensing required, component count increases by only 3 ICs (CT interface, comparator, delay generator) versus 12+ ICs for direct secondary sensing
Expected Effect : Synchronization accuracy <8ns across 80-130kHz LLC frequency range; component count +15% vs baseline; control power +45mW; efficiency improvement 3.2-4.8%
Risk Control :
  • CT phase accuracy drift with temperature ±3ns over 0-85°C requiring periodic recalibration
  • transformer leakage inductance variation ±8% affecting phase relationship
  • load transient causing frequency jump may introduce 10-15ns timing error for 2-3 cycles until offset table updates

Problem Direction 2 :

ImproveGate signal synchronization accuracy
VS
ConstraintControl circuit power consumption

Inspiration 1 : Cross-domain reference

Application Principle: #19 Periodic action
Cross-domain applicability Assess applicability
Methods and apparatus relating to timing and/or synchronization including the use of wireless terminal beacon signals
Innovative Solution Refine solution

Burst-mode high-speed gate driver with duty-cycled precision timing

Duty-cycled precision timing reduces power
How to solve :
  • Implement burst-mode timing circuit that activates high-speed comparator (response time <3ns, 400mW peak) only during predicted 25ns transition windows, remaining in 8mW standby mode between events — duty cycle <5% at 100-500kHz LLC frequency
  • Use low-power resonant frequency tracker (50mW continuous) based on primary-side zero-crossing detection to predict secondary transition timing within ±15ns, triggering precision circuit wake-up 20ns before expected event
  • Deploy adaptive learning algorithm in microcontroller that corrects prediction offset every 16 cycles by measuring actual vs predicted transition timing via residual body diode conduction detection, maintaining <8ns synchronization accuracy across load variations
Expected Effect : Sync accuracy <8ns; control power 85mW avg (vs 350mW continuous); efficiency gain +3.2%; body diode conduction <4ns
Risk Control :
  • burst timing jitter under transient load
  • prediction algorithm convergence delay
  • comparator wake-up latency variation

Problem Direction 3 :

ImproveSwitching timing precision
VS
ConstraintControl circuit complexity

Inspiration 1 : Cross-domain reference

Application Principle: #10 Preliminary action
Cross-domain applicability Assess applicability
Turn-on procedure for a load control device
Innovative Solution Refine solution

Pre-calibrated lookup table synchronous rectifier timing control

Pre-characterize timing at factory across load and frequency range
How to solve :
  • During manufacturing, measure optimal gate turn-on delay vs. LLC resonant frequency (80-500kHz) and load current (0-100% rated) at 10% intervals, store 121-point lookup table in controller EEPROM occupying 242 bytes
  • Implement bilinear interpolation algorithm in existing microcontroller firmware using resonant frequency (from primary-side zero-crossing detector) and output current (from existing current sense) as inputs, computing gate timing offset in 18 CPU cycles (under 500ns at 36MHz clock)
  • Apply calculated timing offset through standard digital delay line (5 cascaded 1ns-resolution buffers) between LLC controller output and gate driver input, achieving ±3ns timing accuracy without adding high-speed comparators or ADCs
Expected Effect : Body diode conduction <5ns, efficiency +3.2%, zero added ICs
Risk Control :
  • lookup table drift over temperature ±15°C
  • interpolation error at boundary conditions
  • EEPROM data retention below 10 years

Problem Direction 4 :

ImproveSwitching timing precision
VS
ConstraintControl circuit power consumption

Inspiration 1 : Cross-domain reference

Application Principle: #19 Periodic action
Cross-domain applicability Assess applicability
Discharge control circuit and display device
Innovative Solution Refine solution

Event-triggered gate drive with predictive wake-up for LLC synchronous rectification

Predict transition timing using resonant frequency tracking to enable selective circuit activation
How to solve :
  • Implement low-power resonant frequency tracker (10-20mW) that monitors LLC primary-side switching period and predicts secondary-side zero-crossing events 50-100ns in advance
  • activate high-speed comparator and gate driver circuits only during predicted 30ns transition windows, keeping them in shutdown mode (≤5μA quiescent current) for remaining 99.5% of each switching cycle
  • use fast wake-up comparator (LMV7219 or equivalent, 7ns propagation delay, 3ns enable time) that powers up from predicted trigger, captures actual secondary voltage zero-crossing, and generates gate signal with <8ns total delay
Expected Effect : Timing precision <8ns; control power <80mW; net efficiency gain +2.8-4.2%
Risk Control :
  • frequency tracking lag during load transients
  • wake-up timing jitter under line variation
  • comparator supply settling time

Problem Direction 5 :

ImproveRectification energy efficiency
VS
ConstraintControl circuit complexity

Inspiration 1 : Cross-domain reference

Application Principle: #22 Blessing in disguise
Cross-domain applicability Assess applicability
Direct AC power converting apparatus
Innovative Solution Refine solution

Self-powered gate drive using body diode conduction voltage drop feedback

Harvest energy from body diode losses to power timing circuit
How to solve :
  • Install a micro-transformer (turns ratio 10:1, core volume <0.5cm³) across the synchronous rectifier FET drain-source to capture the body diode forward voltage drop (0.7-1.0V) during conduction
  • this generates 50-150mW power that charges a local storage capacitor (10µF ceramic, 16V rating)
  • Use the captured voltage drop as a direct timing feedback signal — when body diode conducts, the voltage spike triggers a simple comparator (propagation delay <8ns, e.g., ADCMP601) to adjust next-cycle gate timing via a passive RC delay network (resistor 100-500Ω, capacitor 10-50pF, tunable in 2ns steps)
  • The self-powered control loop operates only when body diode conduction occurs, consuming zero standby power — as timing improves and body diode conduction decreases, control power naturally drops, creating a self-regulating negative feedback system that converges to optimal <5ns synchronization without external high-speed circuits
Expected Effect : Efficiency +3.2%, control power <80mW, component count +4 parts
Risk Control :
  • micro-transformer coupling tolerance ±15%
  • comparator threshold drift over temperature
  • RC network aging affects delay accuracy

Problem Direction 6 :

ImproveRectification energy efficiency
VS
ConstraintControl circuit power consumption

Inspiration 1 : Cross-domain reference

Application Principle: #15 Dynamics
Cross-domain applicability Assess applicability
Voltage conversion circuits, electronic devices, and control methods for voltage conversion circuits
Innovative Solution Refine solution

Adaptive duty-cycle gate driver with load-responsive power scaling

Scale gate driver power dynamically with load
How to solve :
  • Implement load-sensing circuit using existing LLC output current feedback (via 10mΩ sense resistor) to classify operating zones: heavy load (≥50W), medium (20–50W), light (<20W)
  • At heavy load, activate full-speed comparator (200MHz, 150mW) for <10ns synchronization
  • at medium load, switch to medium-speed mode (100MHz, 80mW) achieving 15ns delay
  • at light load, use predictive timing from stored lookup table (20mW) with 25ns tolerance
  • Transition thresholds set at 45W (heavy↔medium) and 18W (medium↔light) with 2W hysteresis to prevent oscillation, mode switching completed within one LLC switching cycle (10–20μs)
Expected Effect : Control power 60–180mW vs baseline 200–500mW; net efficiency gain 2.8–4.2%; synchronization <10ns at rated load
Risk Control :
  • mode transition glitches during rapid load steps
  • lookup table accuracy across temperature −40 to 125°C
  • current sense resistor tolerance ±1% affecting threshold detection
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