GaN FET Synchronous Rectifier for High-Efficiency AC-DC

Overview of Technical Issues:

The body diode conducts during rectification phases generating harmful voltage drop (0.6-1V) and heat dissipation that significantly reduces AC-DC conversion efficiency, while the driver circuit provides insufficient turn-off timing control allowing excessive diode conduction instead of optimal GaN FET synchronous rectification; the goal is to achieve high-efficiency power conversion by minimizing diode conduction losses through precise switching timing in LLC converter or USB-PD flyback topologies.

Solution directions generated for this problem

Problem Direction 1 :

ImproveDriver turn-off timing precision
VS
ConstraintControl algorithm difficulty

Inspiration 1 : Cross-domain reference

Application Principle: #35 Parameter changes
Cross-domain applicability Assess applicability
Method for controlling, more particularly in a closed-loop manner, a powertrain test bench with real transmission
Innovative Solution Refine solution

Pre-calibrated discrete timing lookup table for GaN synchronous rectification

Factory calibration stores optimal timing for discrete operating points
How to solve :
  • During end-of-line testing, measure optimal turn-off timing at 8-12 discrete operating points covering input voltage range (85-265VAC) and load levels (10%-100%), store in non-volatile EEPROM with ±5ns resolution
  • Runtime controller uses simple 2D lookup table (Vin, Iload) with linear interpolation between calibration points, requiring only 16-bit integer arithmetic and 50ns execution time
  • Calibration procedure: apply each operating point for 100ms, sweep turn-off delay in 2ns steps from -50ns to +50ns around theoretical zero-crossing, record delay yielding minimum drain-source voltage spike (acceptance criterion: Vds_peak < 15V), verify efficiency improvement >2% versus fixed timing
Expected Effect : Timing precision <10ns, algorithm complexity -70%, efficiency >95%
Risk Control :
  • component-to-component timing variation exceeding ±20ns
  • EEPROM data corruption during product lifetime
  • interpolation error at operating points between calibration grid

Problem Direction 2 :

ImproveBody diode forward voltage drop
VS
ConstraintDriver circuit complexity

Inspiration 1 : Cross-domain reference

Application Principle: #2 Taking out
Cross-domain applicability Assess applicability
Luminous assembly
Innovative Solution Refine solution

GaN FET body diode elimination via integrated anti-parallel Schottky barrier structure

Remove body diode conduction path entirely by device redesign
How to solve :
  • Integrate anti-parallel Schottky barrier diode directly into GaN FET die during epitaxial growth — eliminates parasitic body diode conduction by providing lower-barrier path (0.3-0.4V vs 0.6-1V)
  • Fabricate lateral Schottky contact on AlGaN barrier layer adjacent to 2DEG channel using Ni/Au metallization with 0.35-0.45V barrier height, activated during reverse bias without timing control
  • Employ field-plate termination structure extending 2-3μm over Schottky junction to achieve breakdown voltage ≥650V while maintaining forward drop <0.4V at rated current
Expected Effect : Diode loss reduced 50-60%; no timing circuit needed; efficiency gain 2-3%
Risk Control :
  • Schottky barrier height process variation ±0.05V
  • thermal stability above 150°C junction temperature
  • reverse leakage current specification <100μA

Problem Direction 3 :

ImprovePower conversion efficiency
VS
ConstraintControl algorithm difficulty

Inspiration 1 : Cross-domain reference

Application Principle: #35 Parameter changes
Cross-domain applicability Assess applicability
Space curve welding device and welding method
Innovative Solution Refine solution

Discrete operating mode lookup table for GaN synchronous rectification

Pre-calibrate timing for discrete load zones to avoid real-time computation
How to solve :
  • During factory end-of-line testing, measure optimal turn-off timing at 8-12 discrete operating points covering input voltage range (85-265VAC) and load levels (10%, 25%, 50%, 75%, 100%) — store timing offsets in non-volatile EEPROM with ±5ns tolerance
  • Implement runtime zone-based lookup controller that samples input voltage and output current every 50μs, maps to nearest calibrated point using simple comparator logic, applies pre-stored timing offset without calculation
  • Add linear interpolation between adjacent points (max 4 arithmetic operations) to smooth transitions — achieves <10ns timing precision across 90% operating range with algorithm complexity reduced by 75% versus adaptive control
Expected Effect : Efficiency >95%, algorithm steps reduced 75%, development time -60%
Risk Control :
  • calibration point coverage insufficient across temperature range
  • EEPROM data corruption over lifetime
  • interpolation error at boundary conditions

Problem Direction 4 :

ImproveDriver turn-off timing precision
VS
ConstraintDriver circuit complexity

Inspiration 1 : Cross-domain reference

Application Principle: #26 Copying
Cross-domain applicability Assess applicability
Systems For Synchronizing Different Devices To A Cardiac Cycle And For Generating Pulse Waveforms From Synchronized ECG and PPG Systems
Innovative Solution Refine solution

Digital twin predictive timing model for GaN synchronous rectification

Replace analog sensing with digital twin model predicting zero-current transitions
How to solve :
  • Build digital twin model using input voltage, load current, and switching frequency to predict zero-current crossing — eliminates high-speed analog current sensors and comparators
  • Factory-calibrate model parameters during end-of-line testing: measure actual zero-current timing at 8-12 operating points (input 85-265VAC, load 10-100%), store coefficients in EEPROM with ±5ns tolerance
  • Implement lightweight prediction algorithm in existing microcontroller: 2nd-order polynomial interpolation executes in <500ns, outputs turn-off signal with <10ns jitter using hardware timer peripheral
Expected Effect : Timing precision <10ns, circuit complexity -40%, efficiency >95%
Risk Control :
  • model accuracy drift over temperature
  • calibration coverage insufficient for edge cases
  • microcontroller timer resolution limitation
Patsnap Eureka Solution