How to Test Synchronous Rectifier Zero Voltage Switching

Overview of Technical Issues:

The voltage measuring structure provides insufficient detection of the zero-voltage condition at the synchronous rectifying switching element during turn-on transitions, preventing accurate verification of whether drain-source voltage reaches zero before gate activation; the goal is to establish reliable measurement methodology that captures the precise timing relationship between voltage zero-crossing and switching events to confirm ZVS operation and enable turn-off timing optimization for maximum efficiency.

Solution directions generated for this problem

Problem Direction 1 :

ImproveMeasurement bandwidth
VS
ConstraintMeasurement noise immunity

Inspiration 1 : Cross-domain reference

Application Principle: #2 Taking out (Extraction)
Cross-domain applicability Assess applicability
Method for determining reserved tones and transmitter for performing PAPR reduction using tone reservation
Innovative Solution Refine solution

Differential near-field voltage sensing with integrated noise extraction for synchronous rectifier ZVS detection

Extract noise before amplification using differential near-field probes
How to solve :
  • Deploy twisted-pair differential probes positioned 0.6–1.2mm above drain-source terminals, capturing voltage via capacitive coupling (1–3pF coupling capacitance) to achieve >150MHz bandwidth while rejecting common-mode EMI by >40dB through geometric symmetry
  • Integrate a passive LC noise extraction network (series 100nH inductor + shunt 22pF capacitor) at probe output to separate switching noise (10–50MHz fundamental) from zero-crossing transition signal (DC–20MHz), attenuating noise by 25dB before entering measurement chain
  • Route extracted signal through shielded coaxial path (50Ω impedance-matched) to fast comparator (LMH7220, 2.9ns propagation delay) with adaptive threshold set at 80mV during 15ns dead-time window, triggered by gate drive falling edge
  • Implement quality control protocol: verify probe symmetry via network analyzer (S-parameter matching within ±0.5dB up to 200MHz), confirm noise rejection ratio ≥35dB at 25MHz using spectrum analyzer, validate zero-crossing detection timing jitter <3ns RMS across 100 switching cycles at full load
Expected Effect : Bandwidth 180MHz, noise rejection 42dB, timing resolution 4ns, false trigger rate <0.1%
Risk Control :
  • probe positioning tolerance affects coupling symmetry
  • LC filter component variation alters extraction frequency
  • thermal drift changes capacitive coupling

Problem Direction 2 :

ImproveVoltage measurement temporal resolution
VS
ConstraintCircuit implementation complexity

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Apparatus for decoding video accompanied with arithmetic decoding and two dimensional last significant coefficient signaling
Innovative Solution Refine solution

Time-gated dual-path voltage sensing for nanosecond ZVS detection

Divide measurement into timing and amplitude paths to optimize each independently
How to solve :
  • Deploy a fast comparator path (propagation delay <5ns) with fixed 50mV threshold solely for zero-crossing timing capture, using single-stage LVDS comparator IC with built-in hysteresis
  • Implement separate precision amplitude path using 12-bit SAR ADC sampling at 10MHz for voltage magnitude verification, operating independently from timing circuit
  • Synchronize paths via digital timestamp logic in low-cost FPGA that correlates comparator trigger events with ADC samples, requiring only 200 logic cells and eliminating analog synchronization complexity
Expected Effect : Temporal resolution <8ns, circuit adds only 3 ICs versus 12+ for integrated high-speed ADC approach
Risk Control :
  • comparator threshold drift ±15mV over temperature
  • timestamp synchronization jitter >2ns
  • FPGA clock domain crossing metastability

Problem Direction 3 :

ImproveDetection timing accuracy
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #10 Preliminary action
Cross-domain applicability Assess applicability
Method and apparatus of configuring downlink timing and transmitting random access response in mobile communication system using carrier aggregation
Innovative Solution Refine solution

Pre-calibrated adaptive threshold zero-crossing detector with predictive gating

Pre-configure detection thresholds before switching events to optimize sensitivity windows
How to solve :
  • During converter off-state, pre-calibrate comparator offset to ±50mV using on-chip DAC trimming and store baseline noise floor
  • predict turn-on instant from previous cycle timing (±3ns jitter) and pre-arm high-sensitivity detection window 5ns before expected zero-crossing
  • activate dual-threshold comparator (±80mV for zero-detection, ±2V for noise blanking) only during 15ns gated interval, then immediately disable to reject post-switching ringing
Expected Effect : Zero-crossing resolution <5ns; false trigger rate <0.1%; circuit adds only 2 comparators and timing logic
Risk Control :
  • cycle-to-cycle jitter exceeds prediction window
  • calibration drift over temperature
  • gate timing misalignment under load transients
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