Patch Antenna Cross-Coupling Reduction in MIMO Systems

Overview of Technical Issues:

## Natural Language Summary In patch antenna MIMO systems, the electromagnetic field radiated by one patch element harmfully excites and induces currents in adjacent patch elements, causing insufficient isolation between channels (typically below required 20dB threshold), which degrades spatial multiplexing efficiency, distorts radiation patterns, and limits overall MIMO system capacity; the goal is to reduce this cross-coupling to achieve optimized isolation and independent channel operation.

Solution directions generated for this problem

Problem Direction 1 :

ImproveElectromagnetic field confinement capability
VS
ConstraintSubstrate area occupation

Inspiration 1 : Cross-domain reference

Application Principle: #17 Another dimension (Dimensionality change)
Cross-domain applicability Assess applicability
Electrical contact arrangement for microfabricated ultrasonic transducer
Innovative Solution Refine solution

Buried multi-layer via fence with internal EBG ground for vertical field confinement

Vertical via fence blocks surface waves without lateral expansion
How to solve :
  • Implement buried via fences in inner substrate layers (layer 2-3 of 4-layer PCB) with 0.3mm diameter vias spaced 0.15λ (1.5mm at 10GHz) in circular pattern around each patch, depth 2.0–2.5mm penetrating to internal EBG ground plane
  • Etch mushroom-type EBG cells (5×5mm unit, 0.4mm via to ground, 0.2mm gap) on internal layer-2 ground plane across entire shared substrate, creating 8–12GHz bandgap to suppress surface wave propagation vertically
  • Maintain top-layer patch spacing at minimum 0.5λ (15mm) with standard 25×25mm footprint per element, feed via layer-1 microstrip with 50Ω impedance matching network
Expected Effect : Isolation improves from 12–15dB to 22–25dB; field intensity at adjacent elements reduced by 65%; footprint increase <8%; correlation coefficient drops to 0.09
Risk Control :
  • via-to-EBG alignment tolerance ±50μm required
  • internal layer registration accuracy affects bandgap center frequency ±200MHz
  • via plating uniformity must achieve <5% resistance variation

Problem Direction 2 :

ImproveElectromagnetic field confinement capability
VS
ConstraintManufacturing complexity

Inspiration 1 : Cross-domain reference

Application Principle: #27 Cheap short-living objects (Disposable)
Cross-domain applicability Assess applicability
Steel for press hardening and press hardened part manufactured from such steel
Innovative Solution Refine solution

Conductive adhesive via-fence for low-cost field isolation

Replace drilled via isolation with adhesive fence
How to solve :
  • Apply conductive adhesive tape (silver-filled epoxy, σ≥10⁵ S/m) in 0.8mm-wide vertical strips between patch elements to form via-fence equivalent, eliminating precision drilling of 50+ vias per element
  • Position adhesive strips at 0.25λ intervals (7.5mm at 10GHz) along element boundaries, height 1.5mm from ground to top surface, cured at 120°C for 15min using standard pick-and-place dispensing
  • Validate isolation by vector network analyzer S-parameter measurement: target ≥18dB at operating frequency, acceptance tolerance ±1.5dB, inspect adhesive continuity via 4-wire resistance test <0.5Ω end-to-end
Expected Effect : Isolation 18–20dB; fabrication steps reduced from 12 to 6; cost halved; single-layer PCB compatible
Risk Control :
  • adhesive conductivity degradation over thermal cycling
  • dispensing width tolerance causing impedance mismatch
  • adhesive-substrate adhesion failure under mechanical stress

Problem Direction 3 :

ImproveChannel independence
VS
ConstraintSubstrate area occupation

Inspiration 1 : Cross-domain reference

Application Principle: #17 Another dimension (Dimensionality change)
Cross-domain applicability Assess applicability
Codebook generating method and apparatus for generating a codebook for multi-polarized multiple-input multiple-output (MIMO) systems
Innovative Solution Refine solution

Vertical stacked dual-layer patch array with orthogonal polarization for zero-footprint isolation

Stack patches vertically with orthogonal feeds
How to solve :
  • Stack two patch layers vertically separated by 4–6mm foam spacer (εr=1.05–1.15), upper layer fed at 0° azimuth, lower layer fed at 90° azimuth to achieve polarization diversity
  • Use Rogers RO4003C substrate (εr=3.55, tanδ=0.0027) for each patch layer, connect layers via precision coaxial probe feeds (±0.1mm positioning tolerance) through intermediate foam layer to maintain isolation >25dB
  • Implement differential phase feeding where upper and lower elements operate at identical 10GHz center frequency but orthogonal E-field orientations, reducing correlation coefficient from 0.32 to <0.08 while maintaining 25×25mm horizontal footprint per dual-element unit
Expected Effect : Isolation >25dB, correlation <0.08, zero lateral area increase, MIMO capacity +85%
Risk Control :
  • foam layer compression affecting separation distance
  • coaxial probe alignment precision degradation
  • orthogonal feed phase imbalance exceeding ±5°

Problem Direction 4 :

ImproveElectromagnetic field confinement capability
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #3 Local quality
Cross-domain applicability Assess applicability
Systems and methods for coupling parts of an electronic device
Innovative Solution Refine solution

Spatially-graded composite substrate with zone-specific dielectric properties

Composite substrate with high-εr zones under patches and low-εr zones between elements
How to solve :
  • Fabricate substrate with high-εr ceramic tiles (εr=9.8–10.2, 18×18mm) embedded at patch locations to miniaturize resonators by 55–60%, bonded into low-εr PTFE matrix (εr=2.1–2.4) filling inter-element gaps to suppress surface wave coupling by 14–18dB
  • Use co-fired lamination process: stack pre-cut Rogers TMM10i tiles (0.635mm thick, εr=9.8±0.25) with RT/duroid 5880 sheets (2.5mm, εr=2.2±0.02), bond at 180°C under 2.5MPa for 45min, achieving <0.1mm interface tolerance
  • Implement impedance-matched transition zones (3mm wide) with intermediate εr=5.5 material around tile perimeters to minimize reflection coefficient below −20dB across 8–12GHz band
Expected Effect : Patch size reduced 58%, isolation improved to 21–24dB, footprint penalty <8%
Risk Control :
  • ceramic-PTFE interface delamination under thermal cycling
  • dielectric constant gradient causing impedance mismatch
  • tile positioning accuracy ±0.15mm affecting resonance frequency
Patsnap Eureka Solution