Patch Antenna Miniaturization Methods for Mobile Devices

Overview of Technical Issues:

The radiating patch element cannot sufficiently reduce its physical dimensions below the conventional half-wavelength requirement while maintaining resonance at the target frequency, resulting in antennas that either exceed the severely constrained space available in modern mobile device housings or suffer from degraded radiation efficiency and bandwidth when forcibly miniaturized; the goal is to achieve substantial size reduction while preserving acceptable antenna performance metrics including gain, bandwidth, and radiation efficiency.

Solution directions generated for this problem

Problem Direction 1 :

ImproveEffective electrical length
VS
ConstraintStructural design complexity

Inspiration 1 : Cross-domain reference

Application Principle: #17 Another dimension (Dimensionality change)
Cross-domain applicability Assess applicability
Multiple contact tulip
Innovative Solution Refine solution

Vertical via-stitched multi-layer patch antenna for electrical length extension

Distribute current path across vertical dimension using multi-layer substrate stack
How to solve :
  • Stack 3-layer substrate configuration (each 0.4–0.6mm thick Rogers RO4003C, εr=3.55) with vertical via arrays connecting patch segments — total height ≤2mm, footprint reduced to 18mm×18mm (64% area reduction from 37.5mm baseline)
  • Route current path through top patch → via-1 → middle layer meander (single 90° turn) → via-2 → bottom ground, achieving equivalent electrical length 72–78mm (λ/2 at 2GHz) within compact vertical stack
  • Via diameter 0.3mm, spacing 2mm, positioned at current maxima locations identified by EM simulation — eliminates complex planar fractal geometry while maintaining resonant frequency 1.95–2.05GHz and efficiency ≥68%
Expected Effect : Electrical length 75mm in 18mm footprint; efficiency 68–72%; design iterations reduced 60% vs planar meandering
Risk Control :
  • via-to-layer misalignment exceeding ±0.15mm
  • interlayer adhesive thickness variation affecting εr_effective
  • via inductance causing resonance shift beyond ±50MHz

Problem Direction 2 :

ImprovePatch physical area
VS
ConstraintManufacturing precision requirement

Inspiration 1 : Cross-domain reference

Application Principle: #28 Mechanics substitution (Replace mechanical system)
Cross-domain applicability Assess applicability
Exposure methods and exposure apparatus, and component manufacturing methods
Innovative Solution Refine solution

High-permittivity ceramic substrate patch antenna with optical alignment fabrication

Replace geometric miniaturization with material-driven size reduction
How to solve :
  • Adopt high-permittivity ceramic substrate (εr=20-30, e.g., barium titanate composite) to compress wavelength by factor √εr, shrinking patch from 37.5mm×37.5mm to 16.7mm×16.7mm (55% reduction) without complex geometry
  • Implement optical vision-based alignment system during substrate-conductor lamination: CCD cameras capture fiducial marks on substrate and copper layer, software calculates offset in real-time, piezo actuators correct positioning to ±0.05mm before bonding at 180°C, 2MPa for 15min
  • Design patch with ±0.4mm tolerance margin: simulate frequency shift vs dimensional variance, set acceptance band 1.95-2.05GHz to absorb ±0.3mm fabrication error while maintaining target 2GHz resonance, eliminating need for ±0.1mm precision
Expected Effect : Area reduction 55%, tolerance relaxed to ±0.3mm, yield >92%, efficiency >68%
Risk Control :
  • ceramic substrate cost 3-5× standard FR4
  • CCD alignment system adds $15k capital investment
  • dielectric loss tangent (tan δ<0.002) must be verified per batch

Problem Direction 3 :

ImproveRadiation efficiency
VS
ConstraintStructural design complexity

Inspiration 1 : Cross-domain reference

Application Principle: #3 Local quality
Cross-domain applicability Assess applicability
Coating systems and articles made therefrom
Innovative Solution Refine solution

Spatially-graded substrate with selective high-conductivity zones for efficiency recovery

Graded substrate with selective zones
How to solve :
  • Partition the miniaturized patch into three functional zones: high-current-density feed region (±5mm from feed point) uses silver-plated copper (conductivity ≥6.0×10⁷ S/m) to minimize ohmic loss
  • radiating edge region (outer 3mm perimeter) employs ultra-thin substrate (0.4mm, εr=2.2, tanδ<0.0009) to maximize radiation coupling
  • central transition zone uses standard FR-4 (εr=4.4, 0.8mm) for mechanical stability and cost control
  • Apply spatially-graded material deposition via selective electroplating for conductor zones and laminated substrate bonding with ±0.2mm alignment tolerance, avoiding full-structure redesign or complex fractal geometry
  • Implement zone-specific quality control: measure feed zone sheet resistance ≤2mΩ/sq via four-point probe
  • verify edge substrate thickness 0.4±0.05mm by micrometer
  • confirm transition zone adhesion strength ≥1.2N/mm via peel test
  • validate overall efficiency ≥68% at target frequency through anechoic chamber measurement with gain tolerance ±0.5dB
Expected Effect : Efficiency 50%→68%, no geometric complexity increase, cost +15% vs uniform design
Risk Control :
  • electroplating uniformity deviation in feed zone
  • substrate layer misalignment exceeding 0.2mm
  • interface delamination under thermal cycling

Problem Direction 4 :

ImproveEffective electrical length
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #17 Another dimension (Dimensionality change)
Cross-domain applicability Assess applicability
Multiple contact tulip
Innovative Solution Refine solution

Vertical via-stitched multi-layer patch for electrical length extension

Stack patch into vertical layers with vias
How to solve :
  • Stack three substrate layers (Rogers RO4003C, εr=3.55, h=0.5mm each) vertically with plated through-hole vias (diameter 0.3mm, spacing 2mm) connecting serpentine traces on each layer — total footprint 18mm×18mm (60% reduction), electrical path length 78mm via vertical current routing
  • Etch meandering microstrip traces (width 0.6mm, spacing 1.2mm) on each layer with 120° phase-shifted patterns — layer-1 feeds from center, via transitions to layer-2 at edge, returns via layer-3 to ground, achieving λ/2 resonance at 2.0GHz ±50MHz
  • Use laser-drilled via registration (positional accuracy ±0.05mm) and automated optical inspection (AOI) to verify inter-layer alignment — press-fit lamination at 3MPa, 180°C for 90min ensures via resistance <5mΩ and layer bonding strength >15MPa
Expected Effect : Footprint 18×18mm (64% reduction from 37.5×37.5mm); electrical length 78mm (λ/2 at 2GHz); radiation efficiency >68%; bandwidth 120MHz; gain 3.2dBi
Risk Control :
  • via-to-trace misalignment exceeding ±0.1mm
  • inter-layer dielectric delamination under thermal cycling
  • via plating thickness variation affecting impedance matching
Patsnap Eureka Solution