Patch Antenna Scan Blindness Mitigation in Phased Array

Overview of Technical Issues:

When the phased array scans to certain angles, the substrate material excessively guides surface waves that trap electromagnetic energy, and mutual coupling between adjacent patch elements intensifies harmfully, causing the radiating patches to insufficiently convert electrical signals to radiated waves at these blind angles, resulting in sharp drops in radiation efficiency and beam steering failure; the goal is to eliminate or mitigate scan blindness across the operational angular range.

Solution directions generated for this problem

Problem Direction 1 :

ImproveSubstrate surface wave suppression capability
VS
ConstraintAntenna operational bandwidth

Inspiration 1 : Cross-domain reference

Application Principle: #15 Dynamics
Cross-domain applicability Assess applicability
Audio encoder and decoder using a frequency domain processor, a time domain processor, and a cross processor for continuous initialization
Innovative Solution Refine solution

Frequency-adaptive substrate with voltage-tunable dielectric constant for scan-angle-dependent surface wave suppression

Voltage-tunable substrate adapts dielectric constant dynamically across operating band
How to solve :
  • Integrate ferroelectric thin-film layer (Ba₀.₆Sr₀.₄TiO₃, 50–80μm thick) between patch and ground plane, applying DC bias voltage 0–200V to tune εr from 10.2 (0V) to 5.8 (200V) with response time <10μs
  • Implement scan-angle-sensing feedback circuit that monitors beam steering angle via phase shifter state readout and dynamically adjusts bias voltage — maintain εr=10±0.3 at broadside (0–40° scan) for 15% bandwidth preservation, reduce to εr=6.5±0.4 at 50–70° scan angles where surface waves dominate
  • Apply segmented bias electrode grid (0.3λ×0.3λ cells) beneath substrate with independent voltage control per 4-element cluster, enabling spatial tuning zones that suppress surface waves in high-coupling regions while preserving bandwidth in low-risk areas — bias voltage tolerance ±5V, uniformity ≥95% within each cell verified by capacitance measurement
Expected Effect : Trapped energy <12% at 65° scan; bandwidth maintained at 14.2%; efficiency >72% across 0–70° scan
Risk Control :
  • ferroelectric hysteresis causing tuning lag
  • bias voltage stability under RF power
  • dielectric loss tangent increase at high bias

Problem Direction 2 :

ImproveInter-element electromagnetic isolation level
VS
ConstraintArray aperture size

Inspiration 1 : Cross-domain reference

Application Principle: #1 Segmentation
Cross-domain applicability Assess applicability
Systems and methods of sectioned bit line memory arrays, some including hierarchical and/or other features
Innovative Solution Refine solution

Vertical metallic via fence isolation walls between array elements

Insert vertical isolation barriers to block coupling paths without expanding footprint
How to solve :
  • Fabricate vertical metallic via fences between adjacent patches at existing 0.5λ spacing — drill via arrays (diameter 0.3–0.5mm, pitch 0.15λ) forming continuous walls from ground plane to substrate top surface, blocking substrate-guided coupling paths
  • Position via fences along E-plane and H-plane boundaries between elements — fence height equals substrate thickness (typically 1.5–3mm for X-band), fence length spans 0.4λ centered between patch edges, creating isolated electromagnetic cells
  • Use standard PCB via plating process with copper thickness ≥25μm — ensure via-to-via spacing tolerance ±0.05mm, wall continuity verified by time-domain reflectometry showing <-20dB transmission at operating frequency, maintaining substrate εr=10 for 15% bandwidth preservation
Expected Effect : Isolation improved from -8dB to -18dB; aperture unchanged; efficiency >72% at 65° scan; bandwidth maintained at 14%
Risk Control :
  • via drilling precision affecting fence continuity
  • plating thickness uniformity causing impedance variation
  • thermal expansion mismatch between vias and substrate

Problem Direction 3 :

ImproveSubstrate surface wave suppression capability
VS
ConstraintMust not deteriorate

Inspiration 1 : Cross-domain reference

Application Principle: #3 Local quality
Cross-domain applicability Assess applicability
Reconstituted substrate for radio frequency applications
Innovative Solution Refine solution

Spatially-graded composite substrate with functional dielectric zoning

Spatially grade substrate dielectric properties
How to solve :
  • Fabricate high-εr ceramic islands (εr=9.8±0.3, diameter 0.55λ) centered under each patch using LTCC co-fired ceramic (DuPont 951 Green Tape), ensuring radiation efficiency ≥72% at 65° scan
  • Embed islands in low-εr polymer matrix (Rogers RO3003, εr=2.2±0.02) filling inter-element regions with 0.25λ minimum barrier width, blocking surface wave propagation and reducing trapped energy to 8%
  • Bond layers at 180°C, 2.5 MPa for 90 min, with impedance transition zones (graded εr=6.5 over 0.1λ width) at island boundaries to minimize reflection coefficient below -20dB
Expected Effect : Radiation efficiency 72% at 65° scan; trapped energy 8%; bandwidth maintained 14.2%
Risk Control :
  • ceramic-polymer interface delamination under thermal cycling
  • dielectric constant tolerance accumulation in graded zones
  • impedance mismatch at material boundaries
Patsnap Eureka Solution