Synchronous Rectifier Efficiency Optimization for USB-PD
Overview of Technical Issues:
When the gate drive circuit's turn-off timing is not optimized for the synchronous rectification FET in the LLC converter, body diode conduction occurs as a harmful effect, generating excessive heat and conduction losses that directly degrade the power conversion efficiency below the target performance expected from GaN FET implementation; the goal is to optimize turn-off timing to eliminate body diode conduction and achieve maximum efficiency improvement in the USB-PD secondary-side rectification stage.
Solution directions generated for this problem
Problem Direction 1 :
ImproveGate drive turn-off timing precision
VSConstraintTiming control circuit complexity
Inspiration 1 : Cross-domain reference
Application Principle: #35 Parameter changes
Cross-domain applicability
I/O circuit with phase mixer for slew rate control
Innovative Solution Refine solution
Self-adaptive delay line driven by resonant tank voltage for timing precision
Resonant tank voltage drives delay line directly
How to solve :
- Extract resonant tank voltage via resistive divider (100kΩ:1kΩ ratio) and feed into voltage-controlled delay line (VCDL) IC such as HMC910LP4E
- VCDL propagation delay auto-tracks resonant frequency variations (50-150kHz range) with 8-12ps/mV sensitivity, eliminating separate sensing circuits
- Calibrate VCDL transfer function at three operating points (light/medium/heavy load) during production: measure resonant voltage amplitude and corresponding optimal turn-off delay, program lookup table into microcontroller with ±5ns tolerance verification
- Gate driver receives VCDL output directly as turn-off trigger—resonant voltage zero-crossing inherently coincides with current zero-crossing in LLC topology, achieving ±10ns timing precision with only 4 added components (divider resistors, VCDL IC, bypass capacitor) versus 15-20 components in adaptive feedback systems
- Quality control: verify VCDL delay linearity across 2.5-5V input range (±3% max deviation), test timing precision under load transients (0-65W step in <2ms), temperature cycling (-20°C to +85°C, timing drift <±8ns)
- Implementation: mount VCDL within 15mm of resonant capacitor to minimize parasitic delay, use 50Ω controlled impedance trace, shield with ground plane
- Performance benchmark: mainstream adaptive solutions add 40-60% component count and require 12-bit ADC plus DSP for real-time calculation
- this approach adds <15% component count, reduces BOM cost by $1.20, achieves body diode conduction <20ns (vs 80-150ns baseline), raising efficiency from 94.2% to 96.3% at 45W load
Expected Effect : Timing precision ±10ns; efficiency 96.3%; component count +15%
Risk Control :
- VCDL linearity deviation under temperature
- resonant voltage noise coupling
- calibration drift over product lifetime
Problem Direction 2 :
ImproveGate drive turn-off timing precision
VSConstraintDetection and measurement precision requirement
Inspiration 1 : Cross-domain reference
Application Principle: #28 Mechanics substitution
Cross-domain applicability
Synchronous voltage-controlled adjustable pulse generator circuit and fiber laser
Innovative Solution Refine solution
Magnetically sensed zero-cross timing for LLC SR turn-off
Sense field not current
How to solve :
- Mount a TMR sensor 1.5-2.5mm from resonant inductor gap, detect field zero-cross and feed a 3ns comparator
- Add a blanking RC 8-12ns and fixed lead trim 5-15ns, then drive SR turn-off through a low-skew gate path under 6ns
- Calibrate at 10%, 50%, 100% load and -20 to 85C, store one offset table, accept timing error within ±8ns by oscilloscope and ATE check
Expected Effect : Turn-off error ±8ns;body diode time under 10ns;efficiency 96.4-96.8%;sensor path jitter under 3ns;parts increase under 15%
Risk Control :
- sensor offset drift
- dvdt magnetic pickup
- inductor placement tolerance
Problem Direction 3 :
ImproveBody diode conduction duration
VSConstraintDetection and measurement precision requirement
