Synchronous Rectifier Turn-Off Timing Control for LLC

Overview of Technical Issues:

The turn-off timing control circuit insufficiently detects the optimal switching moment for the synchronous rectifier element in the LLC converter's secondary side, causing either premature turn-off that forces body diode conduction with reverse recovery losses, or delayed turn-off that allows harmful reverse current circulation; the goal is to achieve precise adaptive timing control that maximizes synchronous rectification efficiency across varying load and frequency conditions.

Solution directions generated for this problem

Problem Direction 1 :

ImproveSwitching moment detection precision
VS
ConstraintControl algorithm difficulty

Inspiration 1 : Cross-domain reference

Application Principle: #32 Color changes
Cross-domain applicability Assess applicability
Method of determining calibration parameter for three-dimensional (3D) display device
Innovative Solution Refine solution

Frequency-domain phase-locked timing control for synchronous rectifier turn-off

Transform time-domain zero-crossing detection to frequency-domain phase control
How to solve :
  • Implement phase-locked loop (PLL) tracking LLC resonant frequency (100–500kHz), generating reference clock synchronized to primary-side switching with ±2ns jitter
  • Derive turn-off command at fixed phase offset 185°±3° from primary turn-on edge using digital phase accumulator, eliminating real-time zero-crossing calculation
  • Embed automatic phase calibration every 500 cycles by monitoring body diode conduction via voltage spike detection, adjusting offset by ±1° increments to maintain optimal timing across load variations
Expected Effect : Detection precision ±8ns across full range; algorithm uses single phase counter; calibration converges within 50ms; efficiency >98.5% at 10–100% load
Risk Control :
  • PLL lock time during startup transient
  • phase noise from EMI coupling
  • temperature drift of phase offset

Problem Direction 2 :

ImproveDetection response speed
VS
ConstraintControl algorithm difficulty

Inspiration 1 : Cross-domain reference

Application Principle: #10 Preliminary action
Cross-domain applicability Assess applicability
Content addressable memory
Innovative Solution Refine solution

Predictive timer-based synchronous rectifier control with cycle-ahead computation

Compute turn-off timing during previous cycle to eliminate real-time processing delay
How to solve :
  • Use the previous resonant cycle to measure frequency and predict next zero-crossing time, pre-load turn-off command into hardware timer before critical moment arrives — eliminates algorithmic processing in <30ns window
  • Implement dual-phase control architecture: background MCU updates timing parameters at 10kHz based on load/frequency, foreground timer executes pre-computed commands with <5ns jitter
  • Deploy self-correcting prediction algorithm that compares actual vs predicted zero-crossing every 50 cycles, auto-adjusts timing offset by ±2ns increments to maintain ±10ns precision across 100–500kHz and 10–100% load
Expected Effect : Response latency <20ns; algorithm complexity reduced 60%; efficiency >98% across full range
Risk Control :
  • prediction error accumulation under rapid load transients
  • timer resolution limiting precision to ±8ns
  • temperature drift affecting cycle-to-cycle stability

Problem Direction 3 :

ImproveControl circuit adaptability
VS
ConstraintCircuit implementation complexity

Inspiration 1 : Cross-domain reference

Application Principle: #6 Universality
Cross-domain applicability Assess applicability
Three-dimensional sonar imaging system based on graph processor and three-dimensional image method thereof
Innovative Solution Refine solution

Multi-function gate drive transformer with integrated timing detection for adaptive synchronous rectification

Integrate timing detection into existing gate drive transformer structure
How to solve :
  • Add a tertiary sensing winding (5 turns, 0.2mm wire) to the gate drive transformer — this winding simultaneously provides gate power and captures resonant current zero-crossing timing through mutual inductance, eliminating separate high-speed current sensors
  • Implement adaptive turns-ratio switching using two parallel secondary windings (8:1 and 16:1 ratios) with back-to-back MOSFETs as selectors — digitally switch between windings based on load zone (10–50% uses 16:1, 50–100% uses 8:1) to maintain optimal gate drive strength and timing sensitivity across full operating range
  • Use the tertiary winding voltage zero-crossing as direct turn-off trigger through a single fast comparator (LT1711, 4.5ns propagation delay) with digitally-programmable threshold (±50mV adjustment via 8-bit DAC) — the magnetic coupling inherently tracks resonant frequency variations without external frequency measurement circuits
Expected Effect : Component count 18 (vs 40+), timing precision ±12ns across 100–500kHz, adaptability 10–100% load, board area +15% only, detection power 0.15W
Risk Control :
  • transformer leakage inductance variation affecting timing accuracy ±3ns
  • turns-ratio switching transient causing 20ns timing glitch
  • tertiary winding coupling coefficient <0.85 reducing signal amplitude

Problem Direction 4 :

ImproveSwitching moment detection precision
VS
ConstraintCircuit implementation complexity

Inspiration 1 : Cross-domain reference

Application Principle: #26 Copying
Cross-domain applicability Assess applicability
Delay orthogonal digital intermediate-frequency phase discrimination method for detecting phase difference accurately
Innovative Solution Refine solution

Phase-domain waveform reconstruction for zero-crossing prediction without added sensors

Extract zero-crossing timing from existing drain-source voltage waveform using digital phase reconstruction
How to solve :
  • Digitize existing drain-source voltage (Vds) waveform at 2 GSa/s using single ADC already present for protection — voltage transition at synchronous rectifier inherently encodes current zero-crossing timing with ~8ns phase offset
  • Apply digital phase-locked loop (DPLL) algorithm to track resonant frequency (100–500kHz) and reconstruct phase angle — calculate zero-crossing prediction as phase reference +185° with <±10ns accuracy across load variations
  • Implement predictive gate timing using low-cost MCU (STM32G4 at 170MHz) — pre-compute turn-off command 200ns ahead based on phase trajectory, trigger via hardware timer with <5ns jitter, eliminating need for separate high-speed current sensors or comparator arrays
Expected Effect : Precision ±10ns achieved; component count remains 15; board area unchanged; detection latency <25ns
Risk Control :
  • ADC sampling jitter accumulation
  • DPLL lock time during transients
  • phase offset calibration drift

Problem Direction 5 :

ImproveDetection response speed
VS
ConstraintEnergy consumption of detection circuit

Inspiration 1 : Cross-domain reference

Application Principle: #19 Periodic action
Cross-domain applicability Assess applicability
Electronic instrument and display screen control method of electronic instrument
Innovative Solution Refine solution

Event-triggered burst-mode detection for LLC synchronous rectifier timing

Predictive wake-up reduces detection power
How to solve :
  • Implement dual-state detection architecture: low-power monitoring mode (5mW) tracks resonant voltage slope to predict zero-crossing 150ns ahead, then triggers high-speed comparator burst (80mW) active only during 100ns critical window
  • Use analog slope detector with RC differentiator (R=10kΩ, C=22pF) on drain-source voltage to generate wake-up pulse when dV/dt exceeds threshold (±2V/ns), activating fast comparator (LT1711 or equivalent, 4.5ns propagation delay) from shutdown mode
  • Synchronize burst timing with LLC resonant frequency via phase-locked prediction loop: measure previous cycle period (T), activate high-speed path at 0.85T to cover zero-crossing window, achieving <30ns response with 92% duty-cycled power reduction
  • Quality control: verify wake-up timing jitter <±20ns across 100–500kHz via oscilloscope sampling (≥1000 cycles), confirm comparator output delay <30ns at 25°C and 85°C, measure average detection circuit power <0.25W at 50% load using precision power analyzer (±1% accuracy)
Expected Effect : Detection power reduced to 0.22W (73% reduction); response time maintained at 25ns; efficiency gain 1.8% vs continuous sampling
Risk Control :
  • slope detector threshold drift with temperature
  • comparator wake-up latency variation
  • prediction error accumulation over frequency range

Problem Direction 6 :

ImproveControl circuit adaptability
VS
ConstraintControl algorithm difficulty

Inspiration 1 : Cross-domain reference

Application Principle: #35 Parameter changes
Cross-domain applicability Assess applicability
Pressure Closed-Loop Control Method and System for Superchargers in Two-Stroke Piston Engines of Aerospace
Innovative Solution Refine solution

Phase-angle referenced adaptive turn-off control for LLC synchronous rectifier

Control turn-off as normalized phase angle relative to resonant cycle instead of absolute time
How to solve :
  • Measure primary-side switching event as phase reference (0°), set turn-off at fixed phase angle 185°±3° from reference — naturally adapts across 100–500kHz without frequency-dependent tables
  • Implement simple zero-crossing detector on primary transformer voltage (existing signal) to capture reference edge, feed to digital counter clocked at 16× resonant frequency for phase quantization
  • Divide load into 3 zones (10–40%, 40–70%, 70–100%) detected by output current moving average, apply pre-calibrated phase offsets (+8°, +3°, 0°) — eliminates real-time resonant parameter extraction
Expected Effect : Adaptability 10–100% load maintained; algorithm complexity reduced 60%; efficiency >98% across range; timing precision ±12ns equivalent
Risk Control :
  • phase quantization jitter at frequency extremes
  • zone transition hysteresis tuning
  • temperature drift of counter clock
Patsnap Eureka Solution